232
1, JANUARY 2000
On the Performance Limits for Si MOSFETs:
A Theoretical Study
Farzin Assad, Zhibin Ren, Dragica Vasileska, Member, IEEE, Supriyo Datta, Fellow, IEEE, and
Mark Lundstrom, Fellow, IEEE
AbstractPerformance limits of silicon MOSFETs are exam-
ined by a simple analytical theory augmented by self-consistent
SchrdingerPoisson simulations. The on-current, transconduc-
tance, and drain-to-source resistance in the ballistic limit (which
corresponds to the channel length approaching zero) are exam-
ined. The ballistic transconductance in the limit that the oxide
thickness approaches zero is also examined. The results show that
as the channel length approaches zero (which corresponds to the
ballistic limit), the on-current and transconductance approach
finite limiting values and the channel resistance approaches a
finite minimum value. The source velocity can be as high as about
1.5 107 cm/s. The limiting on-current and transconductance
are considerably higher than those deduced experimentally by a
previous study of MOSFETs with channel lengths greater than
0.2 m. At the same time, the transconductance to current ratio is
substantially lower than that of a bipolar transistor.
Index TermsCharge carrier processes, MOSFETs, nanotech-
nology, semiconductor device modeling, semiconductor devices.
I. INTRODUCTION
A S silicon technology advances, questions about ultimate
performance limits arise. Toriumi et al. estimated perfor-
mance limits by extrapolating measured results to the limits of
zero channel length and zero oxide thickness [1]. Their results
suggested that the electron saturation velocity and finite inver-
sion layer capacitance set a limiting transconductance of about
3000 mS/mm. In this paper, we reexamine MOSFET limits by
calculating the theoretical performance limits for an idealized,
ballistic MOSFET using an approach similar to that of Natori
[2] and our own recent work [3], [4]. For this study, we make
use of self-consistent SchrdingerPoisson simulations [5] to
examine the validity of several simplifying assumptions made
in earlier work. The results should be useful for assessing the
performance potential of different transistors designs, for com-
paring measured device characteristics against ultimate limits,
and for identifying important technological and theoretical is-
sues for silicon transistors at the end of the roadmap [6].
Manuscript received January 11, 1999; revised June 2, 1999. This work
was supported by the Semiconductor Research Corporation under Contract
98-SJ-089, the Defense Advanced Research Projects Administration Advanced
Microelectronics Program, and by the National Science Foundation Distributed
Center for Advanced Microelectronics Simulations (DesCArtES). The review
of this paper was arranged by Editor J. N. Hollenhorst.
F. Assad, Z. Ren, S. Datta, and M. Lundstrom are with the School of Electrical
and Computer Engineering, Purdue University, West Lafayette, IN 47907-1285
USA (e-mail: lundstro@ecn.purdue.edu).
D. Vasileska is with the Department of Electrical Engineering, Arizona State
University, Tempe, AZ 85287-5706 USA.
Publisher Item Identifier S 0018-9383(00)00169-6.
00189383/00$10.00 2000 IEEE
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO.
Before we begin, we should ask whether the ballistic
limits discussed here are of concern for present-day devices.
Hot electrons near the drain have a mean-free-path of only
a few Angstroms, much shorter than the channel length
of present-day MOSFETs. But when the performance of
present-day MOSFETs is compared to the corresponding
ballistic limits presented in this paper, we find that they operate
at roughly 3040% of the ballistic limit. The reason is that the
steady-state on-current is controlled by a very short region near
the source [3]. Once the mean-free-path (which is longer near
the source) is comparable to the length of this critical region,
quasi-ballistic transport occurs. This is analogous to transport
in metal-semiconductor diodes, where the thermionic emission
(ballistic) theory applies if the mean-free-path is longer than the
distance over which the first of potential drop occurs
(the so-called Bethe condition). Current levels that approach
the ballistic limit occur when the mean-free-path is comparable
to the length of the critical region of the device; it does not have
to be longer than the channel length itself.
In this paper, we examine the limiting performance of a
device corresponding to the nm node in the 1997
national technology roadmap for semiconductors (NTRS) [6].
The device on-current, transconductance, and source-to-drain
resistance will be examined in two limits, the ballistic limit
(corresponding to the channel length approaching zero or
the mean-free-path approaching infinity) and the zero oxide
thickness limit. Although there are simplifying assumptions in
the theoretical model, the results will indicate that the ultimate
MOSFET limits are considerably higher than previously esti-
mated and well above those currently achieved. On the other
hand, the transconductance limit is well below that projected
by Johnson, who argued that as the channel length and oxide
thickness approach zero, the transconductance of a MOSFET
should approach that of a bipolar transistor [7]. If projections
like those to be described in this paper are done for devices at
the end of the NTRS, they show that to achieve the performance
targets called for, devices will have to operate significantly
closer to their ultimate limits than todays devices. Parasitic
resistances and scattering at the oxide-silicon interface tend
to increase as devices are scaled and will make it difficult to
operate closer to the ballistic limits. New device designs are
likely to be necessary to achieve device performance targets at
the end of the NTRS.
II. THEORY
The ballistic current for a MOSFET is readily evaluated as
described by Natori [2] and Datta [4]. A sketch of the derivation
ASSAD et al.: ON THE PERFORMANCE LIMITS FOR Si MOSFETS
Fig. 1. Assumed geometry of the ballistic MOSFET. Current flow is along the
x-direction, the confinement potential varies in the y -direction, and the width
of the device is along the z -direction.
is presented in the Appendix; the important results are summa-
rized here. Fig. 1 shows the geometry. Current flow is in the
-direction, the confining potential is in the -direction, and the
width of the transistor is in the -direction. The drain current
is sum of the contributions from each subband. The positive
states are populated by injection from the source, and the neg-
ative states by injection from the drain. The drain current
contributed by subband, , is
(1)
where is the conductivity effective mass of subband, , and
is the subband energy and is the FermiDirac integral
of order one-half as defined by Blakemore [8]. Similarly, the
electron density in subband, , is
(2)
where is the density of states effective mass for the sub-
band. Under high drain bias, injection from the drain is sup-
pressed, and the on-current can be written as
(3)
where
(4)
is the product of the nondegenerate thermal velocity,
, and a correction factor for FermiDirac
233
statistics. For small drain biases, we find the drain-to-source
conductance as
(5)
The transconductance contributed by the th subband,
(6)
is obtained by differentiating the drain current. In the limit that
the oxide thickness approaches zero or its dielectric constant,
infinity, there is no voltage drop across the oxide, and the lim-
iting transconductance is
(7)
where is the surface potential.
Equations (1)(7) summarize the important formulas, which
are essentially those of Natori [2]. (A sketch of their derivation
is contained in the Appendix.) Our work extends that of
Natori by: 1) using self-consistent, one-dimensional (1-D)
SchrdingerPoisson simulations to treat all relevant subbands,
2) examining the limit in addition to the ballistic
limit, and 3) making specific predictions for devices on the
NTRS [6]. The analysis procedure begins with a self-consistent
SchrdingerPoisson simulation that determines the equilib-
rium Fermi energy and the subband energies for a given gate
bias. The channel conductance can then be evaluated from (5).
To sweep out a common source characteristic, the inversion
layer density is fixed at its equilibrium value for the given gate
voltage, and (2) is solved for the Fermi energy at each drain
bias. At each drain bias, the corresponding current is evaluated
from (1). Finally, by perturbing the gate bias, we also obtain
the transconductances by numerical differentiation.
The SchrdingerPoisson solver used in this work has been
described previously [5]; we summarize the essentials here.
The one-electron Schrdinger equation is solved self-con-
sistently with Poissons equation with an effective potential
included to treat exchange and correlation. We use the density
functional theory of Hohenberg and Kohn [9], and Kohn and
Sham [10], and the interpolation formula developed by Hedin
and Lundqvist, which is accurate over a large density range
[11]. We assume that the wavefunction goes to zero at the
oxide-silicon interface. This assumption can be questioned for
very thin oxides, but does not appear to significantly affect the
results presented here. The poly-silicon gates are modeled as
heavily-doped single-crystal silicon. Electrons in the poly-sil-
icon and holes in the substrate are treated classically assuming
general FermiDirac statistics.
Our 1-D treatment of MOS electrostatics implies a gradual
channel approximation at the source and drain ends of the
channel. The source end is at the top of a potential energy
barrier, so the lateral electric field is zero and a 1-D treatment
is reasonable. (The second derivative is nonzero, however, so
two-dimensional (2-D) effects such as drain-induced barrier
lowering (DIBL) need to be accounted for separately.) At the
234
drain end, the 1-D treatment can only be justified at low drain
voltages, but when the voltage exceeds a few , carrier
injection from the drain is small, so the assumption has little
effect on the drain current.
III. RESULTS
The device examined was taken from the nm node
of the national technology roadmap for semiconductors [6]. The
oxide thickness is 1.5 nm, and the substrate is uniformly doped
at cm-3. This substrate doping results in a
threshold voltage of about 0.4 V, which is much too high for the
assumed 1.0 V power supply. In practice, however, this value
would be lowered by 2-D, short-channel effects which are not
considered here. Results are quoted, therefore, at a gate over-
drive of V, which would result for a more appro-
priate of 0.2 V. [Note that the uniform channel doping was
assumed only to provide a baseline against which more sophis-
ticated channel doping profiles can be compared. For example,
it would be interesting to compare the ultimate performance of a
super steep retrograde (SSR) channel profile [12] against a uni-
form profile.] Unless otherwise stated, all simulations are for
K. In the remainder of this section, we present several
results and discuss some issues. At the end of the section, we
summarize the ultimate performance parameters for this model
device.
In equilibrium, the positive and negative states in the
carrier distribution function are both occupied. In a ballistic
MOSFET, however, positive states are populated by injec-
tion from the source, and the negative states by injection
from the drain. If the drain bias exceeds several , 1-D electrostatics as the distribution function is distorted by the
therefore, the carrier distribution function at the source will
consist of only positive states. The effects of this strongly
off-equilibrium distribution on MOS electrostatics will be
examined next.
Fig. 2 shows the computed inversion layer density versus gate
voltage as obtained by self-consistent, SchrdingerPoisson
simulations [5]. Results for both a metal gate and a polysilicon
gate are shown. The metal gate is taken to be aluminum (with
a workfunction difference of eV) while the
polysilicon gate is doped to 1 1020 cm-3. As expected, the
equilibrium versus characteristics (solid lines) are well
fit by
(8)
where is the total gate capacitance. For the metal gate re-
sults, the capacitance extracted from the slope of versus
gives a capacitance about 25% less than the oxide capacitance
due to well-known carrier degeneracy and quantum mechanical
confinement effects [5]. Polysilicon depletion further reduces
the gate capacitance.
To examine the effect of having only the states occu-
pied, which will occur in a ballistic MOSFET under a drain
bias of a few or greater, we reduced the 2-D density of
states by a factor of two and performed the simulation again
(dashed lines in Fig. 2). The results show that even when only
one-half of the states are occupied, the inversion layer density is
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 1, JANUARY 2000
Fig. 2. Inversion layer density versus the gate voltage as obtained by a
self-consistent solution to the Schrdinger and Poisson equations. Two cases
+
are shown: 1) the equilibrium solution when both k and k states 0
+
occupied, solid lines and 2) the ballistic solution for which only the k states
are occupied, dashed lines. Solutions for both a metal gate and for a polysilicon
gate are shown. For comparison, a classical calculation for a metal gate
+ 0
transistor with both k and k states occupied is also shown (dotted line).
very nearly the same. This occurs because of charge balance in
the MOS system. As the negative half is suppressed by the in-
creasing drain bias, the surface potential increases, pushing the
Fermi level deeper into the conduction band, which increases
and maintains charge balance. This is a kind of DIBL effect
(drain induced barrier lowering) but it is not due to 2-D electro-
statics but, rather, to the need to maintain charge balance in the
drain bias. There is only a small decrease in , which can be
interpreted as a small reduction in the effective gate capacitance
for the ballistic MOSFET. We conclude that when computing a
common source characteristic, fixing the value of at its equi-
librium value as varies, is a good approximation.
Fig. 3(a) shows the common source characteristics of the
MOSFET as computed using (1). For this computation, we eval-
uated in equilibrium for a given gate voltage, then fixed at
the equilibrium value as was swept from zero to the supply
voltage. The ballistic drain current is seen to saturate at a drain
bias of a few , which is much lower than the saturation
voltage of a typical MOSFET. Beyond the saturation voltage,
the drain current is constant when 2-D electrostatics, which pro-
duces DIBL in a real device, are not treated. (Also shown in
Fig. 3(b) is a common source characteristic showing the effects
of DIBL, which effectively lowers , or raises , as
increases.) Finally, the characteristics clearly shows
the detrimental effect of the polysilicon depletion on the drive
current.
In Fig. 4, we plot the ballistic characteristic for the
metal gate device at a supply voltage of
V. The drain current is proportional to inversion layer density
times the thermal injection velocity. The inversion layer density
is proportional to ( ) as given by (8). The thermal in-
jection velocity (4) is constant for nondegenerate conditions and
proportional to when fully degenerate. Conse-
quently, we expect to vary linearly with ( ) under
ASSAD et al.: ON THE PERFORMANCE LIMITS FOR Si MOSFETS 235

(a)
Fig. 4. I versus V for the ballistic MOSFET at a drain voltage of 1.0 V.

(b)

Fig. 3. (a) Common source characteristics of metal gate (dotted lines) and
Fig. 5. The ratios, n =n and I =I versus V for the metal gate,
polysilicon gate (dashed lines) ballistic MOSFETs. (b) Common source
ballistic MOSFET.
characteristics of a metal gate ballistic MOSFET showing the effect of DIBL.
Without DIBL (solid line) and with an assumed DIBL of 100 mV/V (dashed
line).
If one describes the on-current by

nondegenerate conditions and as under degen-
erate conditions. Fig. 4 indicates that the device is operating be-
tween these two limits.
Natoris analytical treatment assumed that only one subband
was occupied [2]. Fig. 5 shows that about 90% of the inver-
sion layer density and drain current arises from electrons in the
first subband. The fraction increases slightly as the gate voltage
increases, because quantum confinement increases the energy
spacing to the second subband, then decreases for high gate volt-
ages as the first subband becomes degenerate. For this device,
the one-subband approximation is adequate. Fig. 6(a) shows the
thermal injection velocity versus gate voltage as obtained from
the SchrdingerPoisson simulation and (4). The thermal in-
jection velocity is constant only in the nondegenerate regime,
which occurs below threshold. Note that under on-current con-
ditions, the thermal injection velocity approaches 2 107 cm/s,
as has been noted by Natori [2]. In Fig. 6(b), we compare the
thermal injection velocity to its degenerate limit. For this de-
vice, fully degenerate conditions do not occur.
(9)
then the upper limit for the average velocity at the source,
, is the thermal injection velocity. In practice, scattering
will reduce below the thermal injection velocity [3]. In
small transistors, strong velocity overshoot occurs within the
channel. Through its influence on the self-consistent channel
potential, velocity overshoot affects the electric field at the
source, and therefore carrier backscattering and consequently
[3]. But velocity overshoot does not change the upper
limit for .
The transconductance of the ballistic MOSFET is
(10)
If the second term is small, then the transconductance is a mea-
sure of the thermal injection velocity. Fig. 7 compares the com-
puted transconductance with that obtained from the first term on
the right-hand side of (10). In the subthreshold region, where the
236 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 1, JANUARY 2000

(a) (a)

(b) (b)

Fig. 6. (a) Ballistic injection velocity at the source versus gate voltage, V , Fig. 8. (a) Ratio of transconductance divided by drain current, versus
for the metal gate, ballistic MOSFET. Also shown is the injection velocity for V for the metal gate, ballistic MOSFET. (b) The ratio of the intrinsic
the first subband alone. (b) Ratio of the degenerate limit velocity to the actual transconductance, g^ , to the drain current versus surface potential.
injection velocity for electrons in the lowest subband versus V .

velocity from the transconductance by ignoring the second term,

as is common practice, the result would be higher than the ac-
tual thermal injection velocity.
A useful way to assess the transconductance is to ex-
amine the ratio, . For a bipolar transistor, this ratio is
. It has been argued that for a MOSFET with the
oxide thickness approaching zero, should approach
the bipolar limit [7]. Fig. 8(a) plots versus for
the model transistor. Below threshold, the transconductance
does approach the bipolar limit. (It is a little lower than the
bipolar limit because the subthreshold slope of the MOSFET is
higher than the theoretical minimum of 60 mV/decade.) Above
threshold, however, is only about 5% of the bipolar
limiteven for the assumed oxide thickness of 1.5 nm. In the
limit that approaches zero, we can evaluate the limiting
Fig. 7. Transconductance versus V for the ballistic MOSFETs
transconductance, from (7). The result is shown in Fig. 8(b).
(solid lines). Also shown is the product of C V (dashed lines). The Below threshold, is even closer to the bipolar limit. (It
transconductance is seen to be higher than C V for V > 0:6 V. is a little lower because of the finite inversion layer thickness.)
Above threshold, the ratio drops, but it is a sizable fraction
thermal injection velocity is constant, the second term in (10) is of the bipolar limit. The limiting transconductance increases
negligible, but above threshold it is not. If one were to deduce a with surface potential; its maximum value will be set by the
ASSAD et al.: ON THE PERFORMANCE LIMITS FOR Si MOSFETS 237

TABLE I
COMPUTED PERFORMANCE OF THE MODEL BALLISTIC

DEVICE AT 300K. THE THRESHOLD VOLTAGE WAS 0:4 V, THE GATE
OVERDRIVE WAS (V 0 V ) 0:8 V, AND THE DRAIN VOLTAGE WAS 1.0 V

TABLE II
COMPUTED PERFORMANCE OF THE MODEL BALLISTIC DEVICE AT 77K. THE

THRESHOLD VOLTAGE WAS 0:5 V AND THE GATE OVERDRIVE WAS
(V 0
V ) 
0 :8 V

Fig. 9. Intrinsic drain to source resistance, R , versus V for the metal gate,
ballistic MOSFET.

maximum surface potential that can be achieved. Finally, note

that these results show that a hypothetical MOSFET with a
gate insulator having an infinite dielectric constant (so that its
times higher than the on-current target. Current-day devices op-
electrical thickness is zero) and an infinite bandgap (so that
erate at about the same percentage of the ballistic limit, so it ap-
there is no penetration of the wavefunction into the insulator),
pears that scaling current devices to the 100 nm node should be
still delivers a lower transconductance than a corresponding
capable of producing the required on-current. If one looks fur-
bipolar transistor. In practice, tunneling through the gate
ther ahead, however, the gap between the ballistic limit and the
insulator would further reduce performance, so that MOSFETs
performance target narrows. For example, for a model
will always deliver considerably lower transconductance that
nm devices with a 1.0 nm gate oxide and a power supply of 0.6
bipolar transistors.
V, the ballistic current is only 1.5 times the target on-current.
Finally, we examine the intrinsic drain to source resistance of
This suggests that to meet the on-current targets with low power
the ballistic MOSFET. Conventional MOSFET theory predicts
supply voltages, new device architectures might be needed.
a channel resistance that goes as the length of the channel, so
Operation at liquid nitrogen temperatures improves the per-
in the ballistic limit, where L approaches zero, there should be
formance of MOSFETs; typically, the on-current increases by
no channel resistance. Equation (5), however, shows that the
about 30% [14]. In the ballistic MOSFET, the on-current is de-
ballistic MOSFET has a finite resistance. This resistance, due
termined by the thermal injection velocity, which may be ex-
to the finite number of transverse modes available to conduct
pected to decrease at low temperatures. Table II shows the com-
current, is analogous to the quantum contact resistance
puted device performance parameters at K. Note that
of a mesoscopic device [13]. It sets a lower limit for the resis-
the on-current improves at low temperatures. The reason may
tance of a MOSFET, independent of contact technology. Fig. 9
be seen from Fig. 10, which compares the thermal injection ve-
is a plot of the intrinsic resistance of the ballistic MOSFET.
locity versus gate voltage at K and 77K. At low gate
This gate-voltage dependent intrinsic resistance is large enough
voltages, the inversion layer is nondegenerate, and the carrier
that it may have to be accounted for in analyzing experiments.
velocity is considerably lower at 77K. Above threshold, how-
A simple physical explanation for the finite resistance of the
ever, carrier degeneracy, which raises , is stronger at low
ballistic channel is that the net drain to source current is the
temperatures, so the injection velocity under maximum gate bias
difference between the current thermionically injected from
is actually higher at 77K than at 300K. Real devices dont op-
the source and that thermionically injected from the drain.
erate at the ballistic limit, so the reduction in scattering at low
The current injected from the drain is lower by a factor of
temperatures further boosts the on-current. A quantitative anal-
in the nondegenerate limit. At small drain
ysis of the magnitude of the effect would also have to consider
biases, the exponential can be expanded, and we find that the
possible changes in the saturation drain voltage and in the par-
net current is proportional to the drain voltage, which gives a
asitic resistances.
finite resistance.
In practice, device performance will fall well below the bal-
The computed performance limits for the nm bal-
listic limits projected here. Series resistance will become in-
listic MOSFET are summarized in Table I.
creasingly important as the channel resistance decreases. Scat-
tering by phonons and at the oxide-silicon interface needs to
IV. DISCUSSION
be accommodated in a realistic theory. We have also neglected
The performance limits for the ballistic MOSFET presented quantum mechanical reflections within the channel and from
in Table I are comfortably above the performance targets in the the drain and source, which may become significant as devices
NTRS [6]. For example, the ballistic on-current is almost four shrink. Our use of 1-D SchrdingerPossion simulations for
238
Fig. 10. The injection velocity versus gate voltage for the model device. Solid
line, T = 300K. Dashed line, T = 77 .K
MOS electrostatics needs to be examined by 2-D simulations
of the same problem. Serious comparisons of the ballistic limit
results with measured nanoscale device characteristics such as
those reported in [14] may also help us understand the signif-
icance of such effects. This work is a prelude to that kind of
serious comparison with experiment. It provides a clear, simple
procedure to estimating upper limits, so that the performance
of current devices and potential replacements can be gauged
against performance limits.
The theoretical results reported here should be compared to
those of Toriumi et al.[1] who conducted a careful experimental
study to establish performance limits by extrapolating measured
results to zero channel length (which corresponds to our ballistic
assumption) and zero oxide thickness. Toriumi et al. examined
the transconductance,
(11)
where is the transconductance in the limit of zero oxide
thickness as defined by (7). Using
(12)
where is the semiconductor capacitance, (11) can be expressed
as
(13)
We have defined the effective thickness of the inversion layer
by . According to (13), a plot of inverse transcon-
ductance versus oxide thickness is linear if the effective thick-
ness of the inversion layer is constant. Toriumi et al.observed
this linear dependence experimentally [1]. They found a lim-
iting transconductance of mS/mm, which is significantly
lower than the value we obtained. From the intercept of their
plot, an effective inversion layer thickness of nm can
also be inferred. The effective inversion layer thickness obtained
from our self-consistent, SchrdingerPoisson simulation was
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 1, JANUARY 2000
much smaller, about 1.1 nm. Note that the limiting transcon-
ductance, , and the effective inversion layer thickness, , both
depend on the surface potential. The lower and larger ob-
served by Toriumi et al.suggest that the experimental data were
taken at lower surface potentials than assumed in the theoret-
ical calculations. Series resistance causes the transconductance
to peak at lower surface potentials and may explain the discrep-
ancy between the theory and experiment.
V. SUMMARY
We presented a simple procedure for estimating the per-
formance limits of silicon MOSFETs as channel lengths and
oxide thicknesses approach zero. In addition to the ballistic
limit current, the procedure also gives the ballistic limit
transconductance and the channel resistance. The procedure
assumed a gradual channel approximation at the source end of
the channel and then made use of 1-D SchrdingerPoisson
simulations of the MOS problem. (This approach misses
important 2-D effects such as DIBL, which have to be added
in separately.) We also treated the channel and drain as perfect
absorbers for electrons injected from the source, which neglects
quantum mechanical reflections that might occur in very small
transistors. These issues should be addressed by more sophisti-
cated simulations, but the approach presented here provides a
clear conceptual way to think about transistor limits, and the
simplifying assumptions are physically based and will provide,
we believe, reasonable upper limits for device performance.
In agreement with a previous experimental study, we found
that as the channel length approaches zero (or as the device
becomes ballistic) the drain current and transconductance have
a finite limit. We also found a finite channel resistance, even
when the channel is ballistic. We found that the carrier velocity
at the source end of the channel [ in (9)] can be as high
as cm/s in the ballistic limit. The MOSFET perfor-
mance limits established here are well above those of current
day devices and considerably higher than those deduced by To-
riumi et al. [1]. For example, the drive current targeted for the
nm node of the NTRS is only about one fourth of the
ballistic limit current. Even for a 1.5-nm thin oxide, however,
the transconductance to current ratio is only about 5% of the
value for a bipolar transistor. As one looks further ahead, how-
ever, it appears that devices will have to operate significantly
closer to the ballistic limit if the NTRS targets are to be met.
The approach presented here should be useful in assessing new
device designs as well as in understanding the performance lim-
iting factors of present-day devices.
APPENDIX
When the SiO2/Si interface is parallel to the [100] plane, the
six equivalent minima of the bulk silicon conduction band split
into two sets of subbands [16]. The first set consists of the two
equivalent valleys with in-plane effective density-of-states mass
(where a factor of two accounts for the valley de-
generacy) and perpendicular effective mass of . The second
set ( -band) consists of the four equivalent valleys with
(again, factor of four accounts for valley degeneracy)
and the perpendicular effective mass is . The energy levels
ASSAD et al.: ON THE PERFORMANCE LIMITS FOR Si MOSFETS 239

associated with the first set comprise the so-called unprimed The results of our study show that this assumption is, for the
ladder of subbands, whereas those associated with the second most part acceptable. In this case, the total carrier concentration
set comprise the primed ladder of subbands. is the first subband population, so
The drain current of a MOSFET is the sum of the contri-
butions from the unprimed and primed subbands. The ballistic (10)
limit current contribution from each subband is computed from
and we may, therefore, solve (2) for and, therefore
(A1) perform the entire analysis analytically. A SchrdingerPoisson
simulation may be needed to specify and .
It is useful to examine the one-subband analytical results in
where is a normalization area, the degenerate limit. In this case

(A2)
(A11)
the Fermi function for electrons injected from the left contact,
Notice that (A11) is the standard, equilibrium result for single
and
spherical valley; it is actually a factor of two smaller because
(A3) only states are occupied, but then it is multiplied by two to
account for valley degeneracy. Using the degenerate limit of the
for electrons injected from the right contact. Parabolic energy FermiDirac integral
bands were assumed, and we assumed that the MOSFET width,
, was large so that the sum over could be replaced by an (12)
integral (see [17], Sections 1.2.3 and 3.1) for a discussion of how
such integrals are worked out). The result of evaluating (A1) in the degenerate thermal injection velocity becomes
this manner gives the drain current carried by each subband, (1).
In the drain current expressions, one must use the proper (13)
density of states and conductivity effective masses. For the un-
primed ladder Note that in the one-subband approximation, the thermal injec-
(A4) tion velocity is independent of temperature, if a fixed gate over-
drive is maintained. Fig. 10 shows that the injection velocity at
and for the primed ladder high gate voltages is higher at 77K than at 300K. This occurs
because at 300K, upper subbands are partially occupied, which
(A5) lowers the average injection velocity somewhat.
The on-current is now readily evaluated from the product of
Also
and to find
(A6)
on
for the unprimed ladder and

(A7) (A14)

for the primed ladder. The carrier density for each subband is Finally, we can find the one-subband, channel conductance in
given by (2), and the total inversion layer density per unit area the degenerate limit as
is the sum of the carrier densities of each subband. Note that
the factor of two in the denominator of (2) arises because in (A15)
the ballistic limit, only the states are occupied when is
greater than a few . Equation (A15) can be expressed in a more familiar form if we
To evaluate the source to drain resistance in the ballistic limit, write it in terms of the number of transverse modes at the Fermi
note that for small drain-to-source voltages energy

(A8) (A16)

and the source to drain channel conductance becomes In (A16), the factor of two comes from valley degeneracy. Using
(A16) in (A15), we find
(A9)
(A17)
which can be evaluated to find (5).
A common assumption in the analysis of MOS problems is to where , etc., because of the valley degeneracy.
assume that only a single subband is occupied (e.g., Natori [2]). Equation (A17) is a familiar result in mesoscopic physics [9]. In
240
the degenerate limit, each transverse mode contributes to
the ballistic conductance.
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[1] A. Toriumi, M. Iwase, and M. Yoshimi, On the performance limit for
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[2] K. Natori, Ballistic metal-oxide-semiconductor field effect transistor,
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[3] M. S. Lundstrom, Elementary scattering theory of the MOSFET, IEEE
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[4] S. Datta, F. Assad, and M. S. Lundstrom, The Si MOSFET from a
transmission viewpoint, Superlattices and Microstructures, vol. 23, pp.
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[5] D. Vasileska, D. K. Schroder, and D. K. Ferry, Scaled silicon
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[7] E. O. Johnson, The insulated-gate field-effect transistorA bipolar
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[8] J. S. Blakemore, Approximations for the FermiDirac integrals, espe-
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[10] W. Kohn and L. J. Sham, Self-consistent equations including exchange
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Addison-Wesley, 1990.
Farzin Assad was born in Tehran, Iran. He was
received the B.S.E.E. degree with honors and the
M.S.E.E. degree in 1990 and 1991, both from the
University of Minnesota, Minneapolis. In 1995,
he joined the device simulation team at Purdue
University, West Lafayette, IN, where he is currently
pursuing the Ph.D. degree. His research interests are
in the area of transport in ultra-small devices and
electromagnetics.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 1, JANUARY 2000
Zhibin Ren was born on October 2, 1969 in
Zhengzhou, China. He received the B.S. degree
from Zhejiang University, China, and the M.S.
degree from the University of Massachusetts,
Dartmouth, in 1991 and 1997, respectively, all in
physics. Currently, he is a Ph.D. candidate in the
Department of Electrical Computer Engineering,
Purdue University, West Lafayette, IN. His work
includes research on deep submircon device physics
and bipolar and MOS transistor design. He has been
engaged in 25-nm generation transistor research on
at Purdue since 1997.
Dragica Vasileska (M97) received the B.S.E.E.
(diploma) and the M.S.E.E. degrees from the
University of Cyril and Methodius, Skopje, Republic
of Macedonia, in 1985 and 1992, respectively, and
the Ph.D. degree from Arizona State University
(ASU), Tempe, in 1995.
From 1995 until 1997, she held a faculty research
position within the Center of Solid State Electronics
Research at ASU. In the fall of 1997, she joined
the faculty of Electrical Engineering at ASU. Her
research interests include semiconductor device
physics and semiconductor device modeling, with strong emphasis on quantum
transport and Monte Carlo particle-based simulations. She has published 34
journal publications, 16 conference proceedings refereed papers, and has given
several invited talks.
Dr. Vasileska is a member of the APS.
Supriyo Datta (M82SM93F96) received
the B.Tech degree from the Indian Institute of
Technology, Kharagpu, in 1975 and the Ph.D. degree
from the University of Illinois at Urbana-Champaign
in 1979.
In 1981, he joined Purdue University, where he is
currently a Distinguished Professor in the School of
Electrical and Computer Engineering. He has written
three books: Surface Acoustic Wave Devices (En-
glewood Cliffs, NJ: Prentice-Hall, 1986), Quantum
Phenomena (Boston, MA: AddisonWesley, 1989),
and Electronic Transport in Mesoscopic Systems (Cambridge, U.K.: Cambridge
Univ. Press, 1995), and has coauthored more than 100 journal articles. His
current research interests are generally centered around the physics of nanos-
tructures and includes molecular electronics, spin electronics, and mesoscopic
superconductiveity in addition to nanoscal device physics.
Dr. Datta received a Presidential Young Investigator Award and an IEEE Cen-
tennial Key to the Future Award in 1984 and the Frederick Emmons Terman
Award from the ASEE in 1994. He is a fellow of the APS.
Mark Lundstrom (SM80F94) received the
B.E.E. and M.S.E.E. degrees from the University of
Minnesota, Minneapolis, and the Ph.D. degree from
Purdue University, West Lafayette, IN, in 1973,
1974, and 1980, respectively.
From 1974 to 1977, he was with Hewlett Packard,
where he worked on the development of second-gen-
eration NMOS integrated circuit process. He is cur-
rently a Professor of electrical engineering at Purdue
University, where he has also served as the Director
of the Optoelectronics Research Center and as an As-
sistant Dean of Engineering. His research interests center on the physics of semi-
conductor devices and include carrier transport, ultrasmall transistors, and com-
putational electronics. He is the author of a textbook, Fundamentals of Carrier
Transport (Boston, MA: Addison-Wesley).
Dr. Lundstrom is the 1993 recipient of the ASEE Frederick Emmons Terman
Award.