Signal Simulation

Dr DC Hendry

January 2006

1 Signals

Signals in VHDL are intended to represent data that we might send on wires or through logic
gates. Signals may therefore be subject to delays. Such delays may be explicitly included
within a concurrent assignment statement. Here is an example:

x <= a and b after 1.5 nS;

If either of the signals a or b changes value then the signal x may change 1.5 nS later (note
that the space between the 1.5 and nS is required). This is illustrated in figure 1. Whenever
any input signal changes to a value that causes the output x to change, then there is a delay
of 1.5 nS before the output changes. This delay of 1.5 nS is modelling the delay of the AND
gate.

1.5 nS

Figure 1:

It was said in a previous lecture that the statements within an architecture body are con-
current statements, and that they execute in parallel. We can now explore that this means.
The VHDL concurrent assignment statement above is evaluated whenever any of the signals
on the right hand side of the statement changes. So whenever in that example the signals
a or b change value, then x is scheduled to be updated 1.5 nS later if the AND function
requires this.

The next statement is often used in testbenches to generate a clock waveform.

clk <= not clk after 5 nS;

This statement generates a clock waveform with a 50% duty cycle and a period of 10 nS.
Whenever clk changes the statement is evaluated, since clk appears on the right hand
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side of the statement. This results in clk changing 5 nS later, but then the statement is
evaluated again, and so on and so on.

This explains why the order of statements within an architecture body is immaterial, the
statements are executed when a signal on their right hand side changes value, we say the
statements are sensitive to the signals appearing in the expression on the right hand side.

Suppose that an architecture body contains the statements shown in figure 2, and that a, b
and c are inputs to the design.

y <= x after 1.5 nS;

x <= (a or b) after 2.0 nS;

Figure 2:

Suppose that the signals in figure 2 initially have the values a = 1, b = 0 and c =
1, so that the initial value of x is 1, and that of y is also 1. Suppose then that the
signal a changes value to 0 at time 5 nS, this causes the assignment to x to be evaluated.
Evaluation of the statement schedules x to be updated to 0 at time 7 nS, but note that
the scheduling takes place at time 5 nS. At 7 nS x changes, causing the second statement
to be evaluated. This in turn schedules, at time 7 nS, y to be updated at 8.5 nS. Then at
8.5 nS, y changes to 0. This behaviour is shown in figure 3.

y
2.0 nS
1.5 nS

Figure 3: Behaviour of figure 2 when a changes

2 Delta Delays

Let us return to the simpler statements previously used, where no explicit delays were shown.
Consider a statement such as:

x <= y;
w <= x;

When is x updated if y changes value at time 10 nS? The answer is that x is scheduled
to be updated at time 10 nS + . The signal w is updated at time 10 nS + 2. Thus if

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0 1 2 3 4 5

x_t

x_i

Figure 4:

we do not supply an explicit delay in a concurrent assignment statement, then a delay of

is assumed. Note that the value of is assumed to be so small that no matter how many
delays we sum, that delay is always smaller than any real delay. Implementing this is a
relatively simple task in a simulation program. During the laboratory you will be able to
observe this aspect of VHDL.

3 Transport and Inertial Delays

Consider the following concurrent assignment statement:

x <= a after 2 nS;

Suppose that a is at logic 0. Suppose further that at time 1 nS signal a changes to logic 1,
so that x is scheduled to be updated to logic 1 at time 3 nS. Now suppose that signal at
time 2 nS changes to logic 0 again. How does x behave? Do we schedule a further change
to x back to 0 at time 4 nS, leaving the previously scheduled change to take effect, or do
we throw away the previously scheduled change to logic 1 at 3 nS and simply leave x at
logic 0 ?

VHDL supports both behaviours. The two behaviours are referred to as transport delays,
and inertial delays. A transport delay models the physical situation of a transmission line
for example, where the delay is due to the time the signal takes to propagate down the line
(very roughly think of this as being like the effect of shaking a long string at one end, and
observing the eventual behavour at the other end). This is illustrated by x t in figure 4.
Thus all changes at the input are faithfully seen at the output, but after a delay.

An inertial delay models delays typified by an RC charge or discharge curve. With an

inertial delay when we multiple transitions during the charge or discharge time, only the
effect of the last transition is seen. This is illustrated by x i in figure 4.

The assignment statements we have used so far have used inertial delay, as this is the default
assignment. If we wish to have a transport delay we denote this with the keyword transport
after the assignment operator, as in:
y <= transport a or b after 5.0 nS;

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4 Waveforms in an Assignment

It is often useful, especially in testbenches (to be discussed later) to specify a waveform to

a signal, this may be done with:

x <= 0, 1 after 1.0 nS,

0, after 3.0 nS,
1, after 5.0 nS,
0, after 6.0 nS;

The signal x then behaves as follows:

0 1 2 3 4 5 6 7 8 nS

5 Selected Assignment Statement

A selected signal assignment statement allows a choice of expression as the right hand side
of an assignment. Which expression is used is determined by the value of an expression
within a WITH clause. The next example describes a 4-to-1 multiplexor.

mux4to1 example for course EG3560.

Dr DC Hendry

library ieee;
use ieee.std logic 1164.all;

entity mx4to1 is 10

port (
i0, i1, i2, i3 : in std logic;
s0, s1 : in std logic;
y : out std logic);

end mx4to1;

architecture rtl of mx4to1 is

20
begin rtl

with s0 & s1 select

y <= i0 when "00",

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i1 when "01",
i2 when "10",
i3 when "11",
i0 when others;

end rtl; 30

The basic structure of the selected signal assignment statement is a WITH clause follows a
number of selections. The expression within the WITH clause must have only a finite number
of possible values (so for example, real numbers may not be used here). In the example
given, the expression consists of the concatenation of two bits 1 .

The set of choices must then cater for all possible values of the WITH expression. It is
possible however to use an OTHERS clause for those values which have not been previously
listed. Note that in the example above, that since an object of type std logic can take on
more values than just 0 or 1, it may for example takes values such as U for Unassigned,
or X for not known, we do need an OTHERS clause.

1 The operator & in VHDL concatenates its two operands, it may be used with single bits, bit strings,

and character strings

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