SRM University

Faculty of Engineering and Technology

Department of Electronics and Communication Engineering
15EC212L Electronic Circuits Laboratory
Fourth Semester, 2016-17 (even semester)

LABORATORY REPORT COVER SHEET

Name :

Register Number :

Semester / Section :

Batch :

Venue :

Title of the Experiment :

Date of Performance :

Date of Submission :

Particulars Max. Marks Marks Obtained

Pre lab Questions 05
Design 10
Lab Performance 10
Post Lab 05
Questions
Lab Report 10
Record 05
Total 45

REPORT VERIFICATION
Staff Name :

Staff Signature :
 1. DESIGN AND ANALYSIS OF BJT COMMON EMITTER
AMPLIFIER CONFIGURATION

1.1 OBJECTIVE

1. To design a single stage CE amplifier Circuit for the given specifications.

2. To perform the transient analysis and determine the phase difference between input and
output signals.
3. To measure the voltage gain of the amplifier over a range of frequencies and plot the
frequency response curve.
4. To determine the values of lower and upper 3-dB frequencies and 3-dB bandwidth.

1.2 HARDWARE REQUIRED

a. Power supply : Variable regulated low voltage DC source(0-30V, 0-

2A)
b. Equipments : AFO(0.3Hz-3MHz), CRO(0-30MHz)
c. Resistors : To be calculated.
d. Capacitors : To be calculated.
e. Semiconductors : BC 107 (or equivalent)
f. Miscellaneous : Breadboard and wires.

1.3 THEORY

Amplifier is an electronic circuit that is used to raise the strength of a weak signal. The
process of raising the strength of a weak signal is known as amplification. One importance
requirement during amplification is that only the magnitude of the signal should increase and
there should be no change in signal shape. The transistor is used for amplification. When a
transistor is used as an amplifier, the first step is to choose a proper configuration in which
device is to be used. Then the transistor is biased to get the desired Q-point. The signal is
applied to the amplifier input and gain is achieved.
1.3.1 CE amplifier operation
Consider a CE amplifier circuit as shown in fig. 1-1

Fig 1.1 CE Amplifier

When the capacitors are regarded as ac short circuits, it is seen that the circuit input
terminals are the transistor base and emitter, and the output terminals are the collector and the
emitter. So, the emitter terminal is common to both input and output, and the circuit
configuration is termed Common Emitter (CE).

1.3.2 Transient Analysis

Transient analysis is nothing but taking voltages and current at different instants. It is
seen that there is a 180o phase shift between the input and output waveforms (Figure
2.4(a&b)). This can be understood by considering the effect of a positive going input signal.
When VS increases in a positive direction, it increases the transistor VBE. The increase in VBE
raises the level of IC, thereby increasing the drop across Rc, and thus reducing the level of the
VC. The changing level of VC is capacitor-coupled to the circuit output to produce the ac
output voltage, VO. As VS increases in a positive direction, VO goes in a negative direction.
Similarly, When VS changes in a negative direction, the resultant decrease in VBE reduces the
IC level, thereby reducing VRC, and producing a positive going output.
1.3.3 CE amplifier circuit elements and their functions
(i) Biasing circuit: The resistances R1, R2 and RE form the biasing and stabilization circuit.
The biasing circuit must establish a proper operating point, otherwise a part of the
negative half-cycle of the signal may be cut-off in the output.
(ii) Input capacitor, C1: An electrolyte capacitor C1 is used to couple the signal to the base
of the transistor. If it is not used, the signal source resistance, Rs will come across R2
and thus change the bias. C1 allows only ac signal to flow but isolates the signal source
from R2.
(iii) Emitter bypass capacitor, Ce: An Emitter bypass capacitor, Ce is used parallel with RE
to provide low reactance path to the amplified ac signal. If it is not used, then amplified
ac signal flowing through RE will cause a voltage drop across it, thereby reducing the
output voltage.
(iv) Coupling capacitor, Cc: The coupling capacitor, Cc couples one stage of amplification
to the next stage. If it is not used, the bias conditions of the next stage will be drastically
changed due to the shunting effect of RC. This is because RC will come in parallel with
the upper resistance R1 of the biasing network of the next stage, thereby altering the
biasing conditions of the latter. In short, the coupling capacitor C2 isolates the dc of one
stage from the next stage, but allows the passage of ac signal.
1.3.4 CE amplifier circuit currents
(i) Base current
iB = IB +ib
Where IB = dc base current when no signal is applied
ib = ac base when as signal is applied
and iB = total base current
(ii) Collector current
iC = IC+ic
Where IC = zero signal collector current
ic = ac collector current when ac signal is applied
and iC = total collector current

(iii) Emitter Current

iE = IE + ie
 Where IE = Zero signal emitter current
Ie = ac emitter current when ac signal is applied
and iE = total emitter current
It is useful to keep in mind that
IE = IB + IC
and ie = ib +ic
Also, IE IC and ie ic

1.3.5 CE amplifier frequency response

The voltage gain of an amplifier varies with signal frequency. It is because reactances
of the capacitors in the circuit changes with signal frequency and hence affects the output
voltage. The curve between voltage gain and signal frequency of an amplifier is known a
frequency response. Figure 2.5
It is clear that the voltage gain drops off at low (< fL) and high (> fH) frequencies
whereas it is uniform over mid-frequency range (fL to fH).
(i) At low frequencies (< fL), the reactance of coupling capacitor is quite high and hence
very small part of signal will pass from amplifier stage to the load. Moreover, CE cannot shunt
the RE effectively because of its large reactance at low frequencies. These two factors cause
a falling of voltage gain at low frequencies.
(ii) At high frequencies (> fH), the reactance of Cc is very small and it behaves as a short
circuit. This increases the loading effect of amplifier stage and serves to reduce the voltage
gain. Moreover, at high frequency, capacitive reactance of base-emitters junction is low
which increases the base current. These reduce the current amplification factor. Due to these
two reasons, the voltage gain drops off at high frequency.
(iii) At mid frequencies (fL to fH), the voltage gain of the amplifier is constant. The effect of
coupling capacitor Cc in this frequency range is such as to maintain a uniform voltage gain.
Thus, as the frequency increases in this range, reactance of CC decreases which tend to
increase the gain.
1.3.6 CE amplifier analysis
The first step in AC analysis of CE amplifier circuit is to draw ac equivalent circuit by
reducing all dc sources to zero and shorting all the capacitors. Fig 2.2 shows the ac equivalent
circuit.

Fig 1.2 Equivalent Circuit

The next step in the ac analysis is to draw h-parameter circuit by replacing the transistor
in the ac equivalent circuit with its h-parameter model. Fig. 2.3 shows the h-parameter
equivalent circuit for CE circuit.

Fig 1.3 h- Parameter Equivalent Circuit

The typical CE circuit performance is summarized below:
Device input impedance, Zb = hie
Circuit input impedance, Zi = R1|| R2|| Zb
1
Device output impedance, Z C
hoe

Circuit output impedance, Z O RC Z C RC

h fe
Circuit voltage gain, AV ( RC RL )
hie
 h fe RC RB
Circuit current gain, Ai
( RC RL )( RC hie )

Circuit power gain, AP = AV x Ai

1.4 MODEL GRAPH

1.4.1 Transient Analysis

Fig 1.4(a) Input Voltage Waveform

Fig 1.4(b) Output Voltage Waveform

1.4.2 Frequency Response

Fig 1.5 Frequency Response

1.5 CE AMPLIFIER CIRCUIT DESIGN

Design of CE circuit normally commences with a specification of supply voltage,

minimum voltage gain, frequency response, signal source impedance load impedance,
stability factor and the Q-point.
Selection of IC, RC and RE
h fe
AV ( RC RL )
hie

For satisfactory transistor operation, Ic should not be less than 500A. A good
minimum Ic to aim for is 1mA.
The VCE should typically be around 3v to ensure that the transistor operates linearly and
to allow a collector voltage swing of 1v which is usually adequate for small-signal amplifier
o Note: RC should normally be very much larger than R L, so that RL has little effect on
voltage gain.
Select VE = 5v for good bias stability in most circumstances.
o Note: When VE>>VBE, VE will be only slightly affected by any variation in VBE (due
to temperature change or other effects)
Once VE, VCE and Ic are selected, VRC is determined as VRC = VCC VCE VE
VRC V
Then, RC and RE are calculated as RC and RE E
IC IC

Selection of bias resistors

As discussed in lab-1, experiment-1.1, section-1.1, selection of voltage divider current
(I2) as IC/10 gives good bias stability and reasonably high input resistance. The bias resistors
are calculated as
VB V VB
R2 and R1 CC
I2 I2

Selecting R2 = 10RE gives I2 = IC/10 the precise level of I2 can be calculated as I2 = VB/R2 and
this can be used in the equation for R1.
Selection of bypass capacitor, CE
Basically the capacitor values are calculated at the lowest signal frequency that the
circuit is required to amplify. This frequency is the lower cut-off frequency, fL.
 hie
Choose X CE at fL for CE calculation to give the smallest value for the bypass
1 h fe
capacitor.
Selection of coupling capacitors, C1 and C2
The coupling capacitors C1 and C2 should have a negligible effect on the frequency
response of the circuit. To minimize the effects of C1 and C2, the reactance of each coupling
capacitor is selected to be approximately equal to one-tenth of the impedance in series with it
at the lowest operating frequency of the circuit (fL).
Z i rs
X C1
10
Z O RL
X C3
10
Usually, RL >> ZO and often Zi >> rS, so that ZO and rS can be omitted in the above equations.

1.6 DESIGN PROBLEM

(i) Design a single stage CE transistor amplifier using BC107 transistor with Vcc = 15V,
VCEQ = 5V, VE = 3V, RL = 47K and fL = 100Hz.
(ii) Determine Zi, ZO, AV, Ai and AP for the CE circuit designed in problem (i).

Procedure
Given VCC = 15V, VCE = 5V, VE = 3V, RL = 47k and fL = 100Hz.
The data sheet of BC107 transistor shows:
hie = 3k and hFE=190
Selection of RC
RC << RL so that RL will have little effect on the circuit voltage gain.
RL 47 K
Select RC 4.7 K (Standard value)
10 10
Selection of RE
VE VE
RE
IE IC

VRC VCC VCE VE (15 5 3)V

Where I C 1.4mA
RC RC 4.7K
 3V
RE 2.14K (use a standard 2.2 k)
1.4mA
Selection of R1 and R2
Selection of voltage divider current I2 as IC/10 gives good bias stability and reasonably high
input resistance
Selecting R2 = 10 RE gives I2 = IC/10
i.e., R2 10 2K 22K (standard value)

I C 1.4mA
and I 2 1404
10 10
VCC VB 15 (VBE VE ) 15 (0.7 5)
R1 66.43K (use standard 68k)
I2 1404 1404

Selection of C1 and C2
The coupling capacitors C1 and C2 should have negligible effect on the frequency response of
the circuit. So, the reactance of each coupling capacitor is selected to be approximately equal
to 1/10th of the impedance in series with it at the lowest operating frequency for the circuit.

Z i R 1 R 2 h ie 68K 22K 3K
X C1 254
10 10 10
1 1
C1 6F
2L X C1 2 100 254 (Standard value 10F)
R L 47K 1 1
X C2 4.7K C2 0.34F
10 10 2L X C2 2 100 4.7K

(use a standard 0.47f)

C1 = CC in Input Side
C2 = CC in Output Side
Selection of CE
h ie 3K
X CE 15.71
1 h fe 1 190

1 1
CE 101.360 (use a standard 100f)
2L X CE 2 100 15.71

Neglect source resistance RS and feedback resistor Rf

 Calculation of Zi, ZO, AV, Ai and AP
Input impedance, Zi = R1||R2|| hie = 68k||22k||3K
= 2.54K
Output impedance, ZO = RC = 4.7k
h fe 190
Voltage gain, AV (R C R L ) (4.7K 47K) 270.61
h ie 3K

h fe R C R B 190 4.7K (68K 22K )

Current gain, A i 37.23
(R C R L )(R C h ie ) (4.7K 47K)(4.7K 3K)

Power gain, AP = AV x Ai = 270.61 X 37.23 = 10K

1.6.1 Design Constraints

If IC> VCC/2(RE+RC) and VCE < VCC/2 is not satisfied, then thermal runaway will occur.

15V

4.7K
68K

0.33F
6F

47K
22K
100mV, 100F
1KHz
2.2K

Fig 1.6 Designed Circuits

1.7 PROCEDURE
Transient and Frequency response curve measurements

a. Feed 100mV (peak-to-peak) sinusoidal signal at 1KHz frequency as the input signal (Vs)
to the CE circuit.
 b. Observe the input and output voltages simultaneously on a CRO. Note down the amplitude,
frequency and phase difference between the two voltages in the table.
c. In the above assembled circuit, keep the magnitude of the source same, ie., 100mv and
vary the frequency from 50 Hz to 10 MHz and measure the voltage gain of the amplifier
at each frequency across RL. Take atleast 10 readings and tabulate the reading in Table.
Plot on a semi log graph sheet the frequency response (voltage gain Vs frequency) curve
using the above measurements.
d. From the plot, determine the values of (a) Mid band voltage gain, Av(mid), (b) Lower
Cut-off frequency,(c) upper cut-off frequency and (d) Bandwidth.

1.8 TABULATION
Transient Analysis
Amplitude Frequency Phase difference
Input signal

Output signal
(a)
Frequency Response Vi = 100mV
Frequency Output Voltage Gain Gain in db
(Vo) Av = 20
log(Vo/Vi)

(b)
1.9 PRELAB QUESTIONS
1. Define Biasing.
2. Identify the type of biasing circuit used in the amplifier and justify its selection over
other biasing circuits.
3. How the bypass and coupling capacitances affect the low frequency response of the
amplifier?
4. What are the different h-parameters of CE amplifier.
5. What are the main applications of CE amplifier.
1.10 POSTLAB QUESTIONS
1. How do coupling capacitors C1 and C2 affect the frequency response? Why?
2. What is the effect on the amplifier performance of omitting RE?
3. What is the effect on input impedance of removing bypass capacitor CE?
4. (a) What is the phase relationship between the input and output signals of a CE
amplifier?
(b) Was this relationship confirmed by the results of your experiments? Explain how.
5. Is the output impedance of a Common emitter amplifier a fixed quantity? Confirm your
answer by referring specifically to any substantiating data in this experiment.
6. From a measurement of the rise time of the output pulse of an amplifier, whose input is
a small amplitude square wave, one can estimate the ________ parameter of the
amplifier.
7. What is the effect found when VCE>VCC/2?

1.11 RESULT
a. The phase difference between the input and output voltage waveform is _________
b. The Mid-band voltage gain =
c. The Lower cutoff frequency =
d. The Upper cutoff frequency =
e. Bandwidth =