Documentation

Implementation and Establishment of Gigabit Serial Rocket IO Communication using Virtex - 5 FPGA
TABLE OF CONTENTS
1. INTRODUCTION.............................................................................................................. 7
1.1 INTRODUCTION TO GIGABIT SERIAL IO ........................................................................... 7
1.2 MGT - MEANS TO GIGABIT SERIAL IO ............................................................................ 8
1.2.1 MGTs are Faster..................................................................................................... 9
1.3 GIGABIT SERIAL IO ADVANTAGES ............................................................................... 10
1.4 APPLICATIONS OF GIGABIT SERIAL IO .......................................................................... 10
1.5 INTRODUCTION TO SYSTEM DESIGN USING FPGA ......................................................... 11
1.5.1 Embedded System Design in an FPGA ................................................................. 11
1.5.2 Field Programmable Gate Array (FPGA).............................................................. 11
1.5.3 Technical Reasons to Use FPGAs in System Design ............................................ 11
1.5.4 Applications of FPGAs ........................................................................................ 11
1.5.5 FPGA Manufacturers ........................................................................................... 12
1.5.6 Advantages of XILINX ........................................................................................ 12
1.5.7 XILINX Families ................................................................................................. 12
1.6 COMMUNICATION BETWEEN ICS ................................................................................... 12
1.6.1 System-Synchronous ............................................................................................ 13
1.6.2 Source-Synchronous............................................................................................. 13
1.6.3 Self-Synchronous ................................................................................................. 13
1.7 SUMMARY ................................................................................................................... 14
2. PROJECT DESCRIPTION .............................................................................................. 15

2.1 AIM OF THE PROJECT .................................................................................................... 15
2.2 INTRODUCTION TO ELECTRONIC WARFARE................................................................... 15
2.2.1 Electronic Support Measures (ESM)..................................................................... 15
2.2.2 Electronic Counter Measures (ECM) .................................................................... 16
2.2.3 Electronic Counter to Counter Measures (ECCM) ................................................ 16
2.3 PRESENT SYSTEM ........................................................................................................ 16
2.4 PROPOSED SYSTEM ...................................................................................................... 16
2.5 OBJECTIVE OF THE PROJECT ......................................................................................... 16
2.6 OVERVIEW OF THE PROJECT ......................................................................................... 17
2.6.1 Block diagram of the Project ................................................................................ 17
2.6.1.1 Xilinx ............................................................................................................. 17
Electronics and Communication Engineering, TKRCET 1

2.6.1.2 VHDL ............................................................................................................ 17

2.6.1.3 Aurora Protocol .............................................................................................. 17
2.6.1.4 Multi Gigabit Transceiver (MGT) ................................................................... 18
2.6.1.5 SFP Transceiver ............................................................................................. 18
2.6.1.6 Optical Fiber Cable (OFC).............................................................................. 18
2.6.2 SOFTWARE AND HARDWARE RESOURCES .................................................................. 18
3. HARDWARE DESCRIPTION ........................................................................................ 19

3.1 XILINX VIRTEX5 FPGA ............................................................................................... 19
3.1.1 Virtex-5 FPGA logic ............................................................................................ 20
3.1.2 Virtex-5 FPGA Features ....................................................................................... 20
3.2 ROCKET IO MULTI GIGABIT TRANSCEIVER................................................................... 22
3.2.1 Generic Block Diagram of SERDES .................................................................... 23
3.2.2 Functions of SERDES .......................................................................................... 24
3.2.3 Rocket IO Transceiver Block Diagram and FPGA interface signals ...................... 28
3.2.4 Rocket IO features................................................................................................ 29
3.3 OPTICAL FIBER CABLE (OFC) ...................................................................................... 29
3.3.1 Why only Optical ................................................................................................. 30
3.4 SFP TRANSCEIVER....................................................................................................... 30
3.5 JTAG CABLE ............................................................................................................... 31
4. SOFTWARE DESCRIPTION .......................................................................................... 32

4.1 XILINX ISE 12.4 .......................................................................................................... 32
4.1.1 Software Overview............................................................................................... 32
4.1.2 Project Navigator interface ................................................................................... 32
4.1.3 Design Summary/Report Viewer .......................................................................... 36
4.1.4 VHDL or Verilog ................................................................................................. 36
4.1.5 ISim ..................................................................................................................... 36
4.2 INTRODUCTION TO AURORA PROTOCOL ........................................................................ 37
4.2.1 Protocol................................................................................................................ 37
4.2.2 Standard Protocols ............................................................................................... 37
4.2.3 Overview of Aurora ............................................................................................. 38
4.2.4 Functional Description of Aurora ......................................................................... 39
4.2.7 User Interface ....................................................................................................... 40

4.2.8 Status, Control, and the GTP/GTX Block Interface .............................................. 43

4.2.9 Applications of Aurora ......................................................................................... 47
4.3 CHIP SCOPE PRO ANALYZER ........................................................................................ 48
4.3.1 Introduction.......................................................................................................... 48
4.3.2 Chip Scope Pro Analyzer Features ....................................................................... 48
5. PROJECT IMPLEMENTATION ..................................................................................... 50

5.1 SOFTWARE IMPLEMENTATION ........................................................................... 50
5.1.1 GENERATION OF AURORA CORE BY USING CORE GENERATOR ............................... 50
5.1.2 PROJECT IMPLEMENTATION ................................................................................... 52
5.1.3 SYNTHESIS ............................................................................................................ 54
5.1.4 USER CONSTRAINT FILE (UCF) GENERATION ........................................................ 54
5.2 HARDWARE IMPLEMENTATION .......................................................................... 55
5.2.1 IMPLEMENTING DESIGN USING IMPACT TOOL ...................................................... 57
5.2.2 CHIPSCOPE PRO ANALYZER .......................................................................... 57
6. RESULT .......................................................................................................................... 58
6.1 SPECIFICATIONS ........................................................................................................... 58
6.1.1 Project Specifications ........................................................................................... 58
6.1.2 Timing Specifications........................................................................................... 58
6.1.3 Inputs and Outputs ............................................................................................... 58
6.2 SIMULATION RESULTS ................................................................................................. 59
6.2.1 Top Level Module ................................................................................................ 59
6.3 SIMULATION WAVEFORMS ........................................................................................... 59
6.4 CHIPSCOPE PRO RESULTS ............................................................................................. 61
6.5 SYNTHESIS REPORT...................................................................................................... 64
6.6 RTL SCHEMATIC ......................................................................................................... 67
7. ADVANTAGES AND LIMITATIONS ........................................................................... 68

7.1 ADVANTAGES .............................................................................................................. 68
7.2 LIMITATIONS ............................................................................................................... 68
8. APPLICATIONS ............................................................................................................. 69
9. CONCLUSION AND FUTURE SCOPE .......................................................................... 70
9.1 CONCLUSION ............................................................................................................... 70

9.2 FUTURE SCOPE ............................................................................................................ 70
10. REFERENCES............................................................................................................... 71
APPENDIX ......................................................................................................................... 72
List of Figures
Figure 1 Multiphase data extraction circuit ............................................................................. 9
Figure 2 Example waveform of Multiphase extraction circuit ................................................. 9
Figure 3 System-Synchronous Diagram ............................................................................... 13
Figure 4 Source-Synchronous Diagram ................................................................................ 13
Figure 5 Self-Synchronous Diagram..................................................................................... 14
Figure 6 Clock Data Recovery Waveform ............................................................................ 14
Figure 7 Block Diagram of Electrical Warfare ..................................................................... 15
Figure 8 Electronic Support Measures System...................................................................... 16
Figure 9 Block Diagram of the Project ................................................................................. 17
Figure 10 SERDES Block Diagram ...................................................................................... 23
Figure 11 CRC Packet Format .............................................................................................. 24
Figure 12 10-Bit TX Data Map with 8B/10B Bypassed ........................................................ 25
Figure 13 10-Bit RX Data Map with 8B/10B Bypassed ........................................................ 26
Figure 14 Rocket IO Transceiver Block Diagram ................................................................. 28
Figure 15 Basic Optical Fiber system ................................................................................... 30
Figure 16 Xilinx Project Navigator....................................................................................... 32
Figure 17 Aurora simplex channels over view ...................................................................... 38
Figure 18 Functional Block diagram of Aurora .................................................................... 39
Figure 19 Aurora module with single example design .......................................................... 39
Figure 20 Aurora Block Diagram ......................................................................................... 39

Figure 21 Aurora 8b/10b core Streaming user interface ........................................................ 41
Figure 22 Typical Tx Streaming Data Transfer ..................................................................... 42
Figure 23 Typical RX Streaming Data Transfer.................................................................... 42
Figure 24 Top-Level GTP/GTX Block Interface .................................................................. 43
Figure 25 Status and Control Interface for Full-Duplex Cores .............................................. 44
Figure 26 Xilinx Core Generator .......................................................................................... 50
Figure 27 Aurora 8b/10b IP Customizer ............................................................................... 50
Figure 28 Second GUI Page for Virtex-5 FPGA Rocket I/O GTP Transceivers .................... 51
Figure 29 8b/10b component and interface selection window ............................................... 51
Figure 30 Aurora core Generated window ........................................................................... 52
Figure 31 Aurora core with two example designs ................................................................. 52
Figure 32 Aurora core with one example design and removed frame gen and frame check ... 53
Figure 33 State machine program ......................................................................................... 53
Figure 34 Simulation behavioral windows ............................................................................ 54
Figure 35 Power Supply for Virtex-5 FPGA ......................................................................... 55
Figure 36 JTAG Connection ................................................................................................ 55
Figure 37 Virtex-5 FPGA Board .......................................................................................... 56
Figure 38 Implementation of Project using Hardware resources ........................................... 56
Figure 39 iMPACT Programming Operation ........................................................................ 57
Figure 40 Top Level module ................................................................................................ 59
Figure 41 Channel_up and Lane_up signal ........................................................................... 59
Figure 42 Transmission signals ............................................................................................ 60
Figure 43 Reception Signals ................................................................................................. 60
Figure 44 Byte Data Transmission using State Machine ....................................................... 61

Figure 45 Chipscope Pro results showing Count & TX_DATA ............................................ 62
Figure 46 Chipscope Pro results showing RX_DATA .......................................................... 62
Figure 47 Chipscope Pro result in listing format showing COUNT & TX_DATA ................ 63
Figure 48 Chipscope Pro results in listing format showing RX_DATA ................................ 63
Figure 49 RTL schematic diagram ...................................................................................... 67
List of Tables
Table 1 Software and Hardware resources ............................................................................ 18
Table 2 List of Family of Virtex 5 FPGA ............................................................................. 19
Table 3 Number of Rocket IO cores per Device type ............................................................ 22
Table 4 Communication standards followed by Rocket IO transceiver ................................. 23
Table 5 Streaming User I/O Ports (TX) ................................................................................ 42
Table 6 Streaming User I/O Ports (RX) ................................................................................ 42
Table 7 Status and Control Ports for Full-Duplex Cores ....................................................... 44
Table 8 Error Signals in Full-Duplex Cores .......................................................................... 46

1. INTRODUCTION
1.1 Introduction to Gigabit Serial IO
In present day world, communication has become very important role in every aspect
of life including warfare. In warfare, communication plays a vital role in knowing the
information about the enemies and receiving the commands from the control room. Mainly in
submarines as they will be in under seas, they require information about what is happening
and services that it has to provide. Here high speed long distance communication without
transmission losses is the main criteria. The data usage & maintenance has become an
important aspect for usage. This data transfer technique helps to transfer the data in large
amounts.
We had been using parallel transmission technology to achieve high speeds.
In parallel transmission, binary data consisting of 1s and 0s may be organized into groups of n
bits each. By grouping, we can send data n bits at a time instead of one. We use n wires to
send n bits at one time. That way each bit has its own wire, and all n bits of one group can be
transmitted with each clock pulse from one device to another. For n = 8, typically, eight wires
are bundled in a cable with a connector at each end. The advantage of parallel transmission is
speed. All else being equal, parallel transmission can increase the transfer speed by a factor of
n over serial transmission. A significant disadvantage of parallel transmission is cost. Parallel
transmission requires n communication lines (wires in the example) just to transmit the data
stream. Because this is expensive, parallel transmission is usually limited to short distances.
In serial transmission one bit follows another, so we need only one communication
channel rather than n to transmit data between two communicating devices. The advantage of
serial over parallel transmission is that communication is possible with only one channel.
Serial transmission reduces the cost of transmission over parallel by roughly a factor or n.
Since communication within devices is parallel, conversion devices are required at the
interface between the sender and the line (parallel-to-serial) and between the line and the
receiver (serial-to-parallel). Serial transmission occurs in one of two ways; asynchronous or
synchronous.
Asynchronous transmission uses start and stop bits to signify the beginning bit. ASCII
character would actually be transmitted using 10 bits. For example, "0100 0001" would
become "10100 00010". The extra one (or zero, depending on parity bit) at the start and end of
the transmission tells the receiver first that a character is coming and secondly that the

character has ended. This method of transmission is used when data are sent intermittently as
opposed to in a solid stream.
Synchronous transmission uses no start and stop bits, but instead synchronizes
transmission speeds at both the receiving and sending end of the transmission using clock
signals built into each component. A continual stream of data is then sent between the two
nodes.
Multi-Gigabit transceivers (MGTs) are used increasingly for data communications
because they can run over longer distances. The main function of these MGTs is to convert
the parallel data into serial data and vice-versa and this action is performed by configuring the
MGTs using aurora core. These MGTs are present in the FPGA as hard IPs and we have to
interface to our application by configuring hard IPs using soft IPs such as aurora core in order
to achieve the high speed serial data transmission. The MGTs are configured as
either transmitter or receiver to perform the data transmission.
The Rocket IO GTX transceiver is a power-efficient transceiver for Virtex-5 FPGAs.
The GTX transceiver is highly configurable and tightly integrated with the programmable
logic resources of the FPGA. GTX transceivers are placed as dual transceiver GTX_DUAL
tiles in Virtex-5 FXT devices. This configuration allows two transceivers to share a single
PLL with the TX and RX functions of both, reducing size and power consumption. Multi-
Gigabit Transceiver (MGT) is a Serializer/Deserializer (SERDES) capable of operating at
serial bit rates above 1 Gigabit/second to perform the data transmission. The Rocket I0 GTX
transceiver is power-efficient transceiver for Virtex-5 FPGAs.
1.2 MGT - means to Gigabit Serial IO

Multi-Gigabit transceivers (MGTs) are the way to go when we need to move lots of
data fast. Multi-Gigabit Transceiver (MGT) is a Serializer/Deserializer (SERDES) capable of
operating at serial bit rates above 1 Gigabit/second. MGTs are used increasingly for data
communications because they can run over longer distances, use fewer wires, and thus have
lower costs than parallel interfaces with equivalent data throughput. They are hard silicon
present inside the FPGA. They use different new technologies to operate at high line rates
besides serialization and deserialization such as differential signaling, MOS current mode
logic (MCML), emphasis, phase locked loops (PLLs), error detection, channel bonding and
Electrical Idle/Out-of-Band Signaling.

1.2.1 MGTs are Faster

An unsettling aspect of the Gigabit SERDES is that they appear to be almost magical.
They work with 3, 5, and even 10+ gigabits. There are several techniques that provide this
speed. A common element of most of these techniques is multiple phases. We can get an idea
of how multiple phases can help us by looking at a multiphase data extraction circuit (Figure-
1). If we have an incoming serial stream with a bit rate of x, we can recover the stream with a
clock of x/4 by using multiple phases of the slow clock (Figure-2). The incoming stream is
directed into four flip-flops, each running off a different phase of the clock (0, 90, 180 & 270).
270
0 90
180
Figure 1 Multiphase data extraction circuit
in
clk 0
clk 90
clk 180
clk 270
a
b
c
d
out
Figure 2 Example waveform of Multiphase extraction circuit

1.3 Gigabit Serial IO Advantages

The chief advantage of gigabit serial IO is its Speed. For getting data on and off of
the chips, boards, or boxes nothing beats a high-speed serial link. And with fewer pins, no
massive Simultaneous Switching Output (SSO) problems, lower EMI, and lower cost high-
speed serial is the clear choice. Multi-Gigabit transceivers (MGTs) are the way to go when
we need to move lots of data fast.
(A) Pin count

Pin count is the first problem encountered when trying to move a lot of data in and out
of a chip or a board. The number of input and output pins is always limited. Although pin
count tends to increase over time, it is never enough to keep up.
(B) Simultaneous Switching Output

A designer should consider SSO when using single ended parallel buses. However,
some of those outputs are going to toggle at the same time. When too many switch
simultaneously, ground bounce creates a lot of noise.
(C) Electro Magnetic Immersions (EMI)

Experience has shown that as clocks get faster, emission testing gets more difficult.
Hence, gigabit design may seem nearly impossible. But a high-speed serial link will usually
exhibit less radiated emissions than a large bus that moves at a slower rate. This is because
functioning of gigabit link requires excellent signal integrity.
(D) Cost
Using MGTs will often result in lower overall system costs. With a smaller, cheaper
package, the connectors can have fewer pins and the board design may be simpler as well.
(E) Predefined Protocols

Another benefit of using MGTs is the availability of predefined protocols and interface
standards. From Aurora to XAUI, designs already exist for many different needs.
1.4 Applications of Gigabit Serial IO

Initially, gigabit SERDES was confined to the telecommunication industry and to a
few niche markets such as broadcast video. Today, MGT applications appear in every section

of the electronic industry military, medical, networking, video, communications etc. They
are also being used on Printed Circuit Board (PCB) assemblies.
1.5 Introduction to System Design using FPGA

1.5.1 Embedded System Design in an FPGA
A typical digital system design involves a significant amount of custom logic circuitry,
but also includes pre-design major components, such as processors, memory units and various
types of input/output interfaces. A different approach for realizing digital systems called, the
embedded system design is used which leverages the advanced capability of today's IC
technology by implementing many of the components of the system within a single chip,
such as an FPGA (Field Programmable Gate Array).
1.5.2 Field Programmable Gate Array (FPGA)

A Field Programmable Gate Array (FPGA) is a semiconductor device containing
programmable logic components and programmable interconnects. The programmable logic
components can be programmed to duplicate the functionality of basic logic gates such as
AND, OR, XOR, NOT or more complex combinational functions such as decoders or simple
math functions. In most FPGAs, these programmable logic components also include memory
elements which may be simple flip-flop or more complete blocks of memories.
1.5.3 Technical Reasons to Use FPGAs in System Design

FPGAs are generally slower than their Application Specific Integrated Circuit (ASIC)
counterparts, can't handle as complex design, and draw more power. However, they have
several advantages, which make them a good choice for implementing digital systems such as
Offer large logic capacity, exceeding several million equivalent logic gate, and include
memory resources.
Support a wide range of interconnection standards, such as PCI and high speed serial
protocols.
Shorter time to market.
Ability to re-program.
1.5.4 Applications of FPGAs

Applications of FPGAs including DSP, software-defined radio, aerospace and defense
system, medical imaging, computer vision, speech recognition and a growing range of other

areas. FPGAs especially find applications in any area or algorithm that can make use of the
massive parallelism offered by their architecture.
1.5.5 FPGA Manufacturers

As of late 2005, the FPGA market has mostly settled into a state where there are two
major "general-purpose" FPGA manufactures and a number of other players who differentiate
themselves by offering unique capabilities.
Xilinx and Altera are the current FPGA market lenders.
Lattice Semiconductor provides both SRAM and non-volatile, flash-based FPGAs.
Actel has anti-fuse and reprogrammable flash-based FPGAs, and also offers mixed
signal flash-based FPGAs.
1.5.6 Advantages of XILINX

Xilinx leads the Programmable logic device (PLD) market-one of the fastest growing
segments of the semiconductor industry. This programmability provides a revolutionary
alternative to fixed or custom logic devices that typically required many months to design,
test, and manufacture. Xilinx customer enjoys the benefit of faster time-to-market and
increased product design flexibility as a result.
Xilinx chip can be found in a wide variety of digital electronic applications ranging
from wireless base station to DVD players.
1.5.7 XILINX Families

Xilinx extensive product line includes silicon solution like the
Virtex series FPGAs (high performance FPGAs for networking communications and
video/imaging applications at the lowest cost).

Spartan FPGAs (ideal for high volume applications).
1.6 Communication between ICs

There are three basic timing models used for communication between two ICs. They are,
A. System-Synchronous.
B. Source-Synchronous.
C. Self-Synchronous.

1.6.1 System-Synchronous
System-Synchronous is communication between two ICs where a common clock is
applied to both ICs and is used for data transmission and reception. This method is as shown
in the Figure-3.
Data
Source
Destination
IC
IC
OSC
Figure 3 System-Synchronous Diagram
1.6.2 Source-Synchronous
Source-Synchronous is communication between two ICs where the transmitting IC
generates a clock that accompanies the data. The receiving IC uses this forwarded clock for
data reception and to manage any delays. This model is as shown in Figure-4.
DATA
Source CLK
Destination
IC
IC
Figure 4 Source-Synchronous Diagram
1.6.3 Self-Synchronous
Self-Synchronous is communication between two ICs where the transmitting IC
generates a data stream that contains both the data and the clock. The three main blocks of a
self-synchronous interface are parallel-to-serial conversion, serial-to-parallel conversion, and
Clock Data Recovery (CDR). This model is as shown in the Figure-5.

CLK &
Source DATA
IC Destination
IC
Figure 5 Self-Synchronous Diagram
1.6.3.1 Clock Data Recovery

The clock recovery process does not provide a common clock or send the clock with
the data. Instead, a phased locked loop (PLL) is used to synthesize a clock that matches the
frequency of the clock that generates the incoming serial data stream.
Where a phased locked loop (PLL) is a circuit that takes a reference clock and an
incoming signal and creates a new clock that is locked to the incoming signal.
Rx_pin
RCLK
Rx_internal
Figure 6 Clock Data Recovery Waveform
1.7 Summary
To increase the speed in chip-to-chip communication design methods such as signal-,
source- and self-synchronization are used. In self-synchronization, data can be converted from
parallel to serial and serial to parallel, which is performed by MGT on FPGA. MGTs are the
way to go when we need to move lots of data fast, hence the name Rocket IO.

2. PROJECT DESCRIPTION
2.1 Aim of the project
The aim of the project is to transmit data serially at a high speed in Gbps using the
Aurora protocol software transmission module and the hardware features of Rocket IO
transceiver in Virtex-5 FPGA.
2.2 Introduction to Electronic Warfare

Any military action involving the use of electromagnetic and directed energy to
control the electromagnetic spectrum or to attack the enemy is called Electronic Warfare. The
basic concept of Electronic warfare is to exploit the energys electromagnetic emissions in all
parts of the electromagnetic spectrum in order to provide intelligence on the enemy's order of
battle intentions and capabilities, and to use countermeasures to deny effective use of
communications and weapon systems while protecting one's own effective use of the same
spectrum.
Electronic Warfare is organized into three major categories:
ELECTRONIC WARFARE
ESM ECM ECCM
Figure 7 Block Diagram of Electrical Warfare
2.2.1 Electronic Support Measures (ESM)

The term Electronic Support Measures (ESM) is the division of Electronic Warfare
involving actions taken under direct control of an operational commander to search for,
intercept, identify and locate sources of radiated electromagnetic energy for the purpose of
immediate threat recognition. Thus, ESM provides a source of information required for
immediate decisions involving Electronic Counter Measures (ECM), Electronic Counter to
Counter Measures (ECCM), avoidance, targeting, and other tactical employment of forces.
ESM units include both interception and direction finding capabilities.
An ESM system as shown below receives the RADAR pulses emitted by the various
RADARS and measures the parameters of these pulses and then uses these parameters to sort

out from which of the RADARs the pulses are emitted. Finally, emitter is identified and
information is presented to the operator.
RECEIVER ESM PROCESSOR DISPLAY
Figure 8 Electronic Support Measures System
2.2.2 Electronic Counter Measures (ECM)

ECM is defined as actions taken to prevent or reduce the enemys effective use of the
electromagnetic spectrum.
2.2.3 Electronic Counter to Counter Measures (ECCM)

ECCM is defined as actions taken to ensure friendly use of the electromagnetic
spectrum against Electronic Warfare.
2.3 Present System

In the Parallel transmission technology used currently, parallel lines are used for
transmitting and receiving the data which consume resources and time and meet physical
limitations when data rates exceed just 1Gb/s and no longer reliable.
2.4 Proposed System

The Proposed Project we are dealing with is applicable in the ESM system of
Electronic Warfare to meet the requirement of high speed data transmission above 1Gbps.
In this proposed project, serial Rocket IO based design offers many advantages over
parallel implementation which includes fewer device pins, reduced board space requirements,
few printed circuit board (PCB) layers, smaller connectors and better noise immunity. By
using the Aurora protocol software transmission module and Rocket IO (MGT), a SERDES
block on Virtex5 FPGA, serial bit rates above 1Gbps can be achieved.
2.5 Objective of the Project

The main objectives of the Project are:
To transfer the data with a speed more than 1Gbps.
To decrease the number of wires, time and power.

To design Aurora protocol, used to configure the Multi Gigabit Transceiver.

To analyze the results and to give the synthesis report of the schematic using Xilinx
12.1 tool.
To dump the program into Virtex5 FPGA kit and verify the result.
2.6 Overview of the Project

2.6.1 Block diagram of the Project
Parallel Serial
AURORA MODULE Tx
Tx MGT Tx SFP O
128 BIT DATA (SERDES) F
TRANSCEIVER
(COUNTER OR C
ROCKET IO
FSM) Rx Rx
Rx
Serial
Parallel
Figure 9 Block Diagram of the Project
2.6.1.1 Xilinx
Xilinx ISE (Integrated Synthesis Environment) is a software tool produced by Xilinx
for synthesis and analysis of HDL designs, enabling the developer to synthesize ("compile")
their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to
different stimuli, and configure the target device with the programmer. It is also called as
project navigator. By using VHDL/Verilog we can execute the programs in Xilinx software.
2.6.1.2 VHDL
Very High Speed Integrated Circuit Hardware Description Language is a hardware
description language used in electronic design automation to describe digital and mixed-signal
systems such as field-programmable gate arrays and integrated circuits. VHDL can also be
used as a general purpose parallel programming language.
2.6.1.3 Aurora Protocol

Aurora is an area-efficient, scalable data transfer protocol for high speed serial links.
There are two types of aurora protocol depending on the type of encoding and decoding. The
Aurora 8B/10B protocol is primarily targeted for chip-to-chip and board-to-board applications
and it can also be used for box-to-box applications with the addition of standard optical

interface components. It is an open standard and is available for implementation by anyone

without restriction.
2.6.1.4 Multi Gigabit Transceiver (MGT)

Multi-Gigabit Transceiver (MGT) is a Serializer / Deserializer (SERDES) capable of
operating at serial bit rates above 1Gb/s. MGTs are used increasingly for data
communications because they can run over longer distances, using fewer wires, and thus have
lower costs than parallel interfaces with equivalent data throughput. MGTs are the way to go
when we need to move lots of data fast, hence the name Rocket IO.
2.6.1.5 SFP Transceiver

Small Form factor Pluggable transceiver (SFP) is a compact, hot-pluggable transceiver
used for both telecommunication and data communications applications. It interfaces a
network device mother board (for a switch, router, media converter or similar device) to a
fiber optic or copper networking cable.
2.6.1.6 Optical Fiber Cable (OFC)

An optical fiber is a flexible, transparent fiber made of high quality extruded glass
or plastic, slightly thicker than a human hair. It can function as a waveguide, or "Light
pipe", to transmit light between the two ends of the fiber.
2.6.2 Software and Hardware Resources

The Software and Hardware resources required to implement the project are:
Table 1 Software and Hardware resources
SOFTWARE RESOURCES HARDWARE RESOURCES
1. Xilinx 12.4 ISE tool. 1. Virtex-5 RocketIO development board (FPGA).

2. Xilinx core generator. 2. Optical Fiber Cable (OFC).
3. Xilinx aurora protocol. 3. JTAG (Joint Test Action Group) cable.
4. Xilinx Chip Scope Pro 4. SFP (Small Form factor Pluggable) Transceiver.
analyser. 5. SMPS.

3. HARDWARE DESCRIPTION
3.1 Xilinx Virtex5 FPGA
Virtex-5 FPGAs with integrated high-speed selection technology and Multi-Gigabit
serial transceivers (MGTs) support the widest range of broadcast video and audio connectivity
standards, including: standard video interfaces for sD-sDi, HD-sDi, Dual link HD-sDi, 3g-sDi
and DVb-asi; as well as aEs3 digital audio interfaces, audio embedding and de-embedding.
Table 2 List of Family of Virtex 5 FPGA

3.1.1 Virtex-5 FPGA logic

On an average, Virtex-5 FPGA has one to two speed grade improvements over
Virtex-4 devices.
It has cascadable 32-bit variable shift registers or 64-bit distributed memory
capability.
Virtex-5 provides superior routing architecture with enhanced diagonal routing
supports block-to-to block connectivity with minimal hops.
It has up to 330,000 logic cells including:
- Up to 207,360 internal fabric flip-flops with clock enable (XC5VLX330).
- Up to 207,360 real 6-input look-up tables (LUTs) with greater than 13 million
total LUT bits.
- Two outputs for dual 5-LUT mode gives enhanced utilization.
- Logic expanding multiplexers and I/O registers.
3.1.2 Virtex-5 FPGA Features

Four platforms LX, LXT, SXT, and FXT
- Virtex-5 LX: High-performance general logic applications.
- Virtex-5 LXT: High-performance logic with advanced serial connectivity.
- Virtex-5 SXT: High-performance signal processing applications.
- Virtex-5 FXT: High-performance embedded systems.
Cross-platform compatibility
- LXT, SXT, and FXT devices are footprint compatible in the same package.
Most advanced, high-performance, optimal-utilization, FPGA fabric
- Real 6-input look-up table (LUT) technology.
- Dual 5-LUT option.
- Improved reduced-hop routing.
- 64-bit distributed RAM option.
- SRL32/Dual SRL16 option.
Powerful clock management tile (CMT) clocking
- Digital Clock Manager (DCM) blocks for zero delay buffering, frequency
synthesis, and clock phase shifting.

- PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and
phase-matched clock division.
36-Kbit block RAM/FIFOs
- True dual-port RAM blocks.
- Enhanced optional programmable FIFO logic.
- Programmable
o True dual-port widths up to x36.
o Simple dual-port widths up to x72.
- Built-in optional error-correction circuitry.
- Optionally program each block as two independent 18-Kbit blocks.
65-nm copper CMOS process technology.
1.0V core voltage.
High signal-integrity flip-chip packaging available in standard or Pb-free package
options.
High-performance parallel Select IO technology
- 1.2 To 3.3V I/O operation.
- Source-synchronous interfacing using Chip Sync technology.
- Digitally-controlled impedance (DCI) active termination.
- Flexible fine-grained I/O banking.
- High-speed memory interface support.
Advanced DSP48E slices
- 25 x 18, twos complement multiplication.
- Optional adder, subtracter, and accumulator.
- Optional pipelining.
- Optional bitwise logical functionality.
- Dedicated cascade connections.
Flexible configuration options
- SPI and Parallel FLASH interface.
- Multi-bit stream support with dedicated fallback reconfiguration logic.
- Auto bus width detection capability.
Integrated Endpoint blocks for PCI Express (LXT/SXT)

- Compliant with the PCI Express Base Specification 1.1

- x1, x2, x4, or x8 lane support per block.
- Works in conjunction with Rocket IO transceivers.
Tri-mode 10/100/1000 Mb/s Ethernet MACs (LXT/SXT)
- Rocket IO transceivers can be used as PHY or connect to external PHY using
many soft MII (Media Independent Interface) options.
Rocket IO GTP transceivers 100 Mb/s to 3.2 Gb/s (LXT/SXT).
System Monitoring capability on all devices
- On-chip/Off-chip thermal monitoring.
- On-chip/Off-chip power supply monitoring.
- JTAG access to all monitored quantities.
3.2 Rocket IO Multi Gigabit Transceiver

Rocket IO is used to transfer the data at faster rate over distances. Up to 48 transceiver
modules are available on a single Virtex-5 FPGA, depending on the part being used. These
Rocket IOs are also called as MGTs, SERDES.
Table 3 Number of Rocket IO cores per Device type
DEVICE ROCKET IO CORES

GTP GTX
XC5VLX20T 4 NA
XC5VLX30T 8 NA
XC5VLX50T 12 NA
XC5VLX85T 12 NA
XC5VLX110T 16 NA
XC5VLX155T 16 NA
XC5VLX220T 16 NA
XC5VLX330T 24 NA
XC5VSX35T 8 NA
XC5VSX50T 12 NA
XC5VSX95T 16 NA
XC5VSX240T 24 NA
XC5VTX150T NA 40
XC5VTX240T NA 48
XC5VFX30T NA 8
XC5VFX70T NA 16
XC5VFX100T NA 16
XC5VFX130T NA 20
XC5VFX200T NA 24

The Transceiver module is designed to operate at any serial bit range in the range of
600 Mbps to 3.125 Gbps per channel, including the specific bit rates used by the
communications standard list in Table 4.
Table 4 Communication standards followed by Rocket IO transceiver
Channels I/O Bit Rate

Mode
(Lanes)(1) (Gb/s)
Fibre Channel 1 1.06
Gbit Ethernet 1 1.25
PCI Express (2) 1 2.5
XAUI (10-Gbit Ethernet) 4 3.125

XAUI (10-Gbit Fibre 4 3.1875(4)
Channel)(3)
Infiniband 1,4,12 2.5
Aurora (Xilinx protocol) 1,2,3,4,. 0.600 3.125
Custom Mode 1,2,3,4,. 0.600 3.125
3.2.1 Generic Block Diagram of SERDES
Figure 10 SERDES Block Diagram

3.2.2 Functions of SERDES

Functions of SERDES include Serializing, Deserializing, Cyclic Redundancy Check
(CRC) generators, CRC checkers, multiple encoding and decoding 4b/5b, 8b/10b & 64b/66b.
3.2.2.1 Serializer
The Multi-Gigabit transceiver multiplies the reference frequency provided on the
reference clock input (REFCLK) by 20 or by 10 if half-rate operation is selected. Data is
converted from parallel to serial format and transmitted on the TXP and TXN differential
outputs.
Serializing the data makes greater use of the available resources (pins). A system
processing 64 bits of data at 80 MHz can use a 64-bit data link (with control signals) to
another device.
3.2.2.2 Deserializer
The Rocket IO transceiver core accepts serial differential data on its RXP and RXN
inputs. The clock/data recovery circuit extracts clock phase and frequency from the incoming
data stream and re-times incoming data to this clock. The recovered clock is presented on
output RXRECCLK at 1/20 of the received serial data.
3.2.2.3 Cyclic Redundancy Check (CRC) generation

Cyclic Redundancy Check is a procedure to detect errors in the receiving data.
Rocket IO transceivers support the 32-bit invariant CRC used by Infiniband, Fiber
channel, Gigabit Ethernet. The CRC recognizes the SOP (Start Of Packet), EOP (End Of
Packet), and other packet features to identify the beginning and end of data.
The Transmitter computes 4-byte CRC on the packet data between the SOP and EOP.
The transmitter inserts the computed CRC just before the EOP.
The Receiver re-computes CRC and verifies it against the inserted CRC.
SOP . DATA CRC . EOP . IDLE
Figure 11 CRC Packet Format

3.2.2.4 8b/10b Encoding and Decoding

The Rocket IO transceiver has the ability to encode eight bits into a 10-bit serial
stream using standard 8B/10B encoding. This guarantees a DC-balanced, edge-rich serial
stream, facilitating DC- or AC-coupling and Clock recovery.
8b/10b Encoding
- A bypassable 8B/10B encoder is included in the transmitter. The encoder uses
the same 256 data characters and 12 control characters (shown in Appendix A,
8B/10B Valid Characters) that are used for Gigabit Ethernet, XAUI, Fiber Channel,
and Infiniband.
- The encoder accepts 8 bits of data along with a K-character signal for a total of
9 bits per character applied. If the K-character signal is High, the data is encoded into
one of the twelve possible K-characters available in the 8B/10B code. (See Table A-2
of Appendix A).
- When 8B/10B encoding is bypassed, the TXCHARDISPVAL and
TXCHARDISPMODE bits become bits b and a, respectively, of the 10-bit
encoded data that the transceiver must transmit to the receiving terminal. Figure
illustrates the TX data map during 8B/10B bypass.
Figure 12 10-Bit TX Data Map with 8B/10B Bypassed
8b/10b Decoding
- An optional 8B/10B decoder is included in the receiver. A programmable
option allows the decoder to be bypassed. When it is bypassed, the 10-bit character
order is as shown in Figure 13.

Figure 13 10-Bit RX Data Map with 8B/10B Bypassed
- The decoder uses the same table that is used for Gigabit Ethernet, Fiber
Channel, and Infini-Band. The decoder separately detects both disparity errors and
out-of-band errors.
- A disparity error occurs when a 10-bit character is received that exists within
the 8B/10B table (Table A-1 of Appendix A), but has an incorrect disparity.
- An out-of-band error occurs when a 10- bit character is received that does not
exist within the 8B/10B table.
- It is possible to obtain an out-of-band error without having a disparity error.
The proper disparity is always computed for both legal and illegal characters. The
current running disparity is available at the RXRUNDISP signal.
- The 8B/10B decoder performs a unique operation if out-of-band data is
detected. When this occurs, the decoder signals the error, passes the illegal 10 bits
through, and places them on the outputs. The decoder also signals reception of one of
the twelve valid K-characters (Table A-2) by way of the RXCHARISK port. In
addition, a programmable comma detect is included. The comma detect signal
RXCOMMADET registers a comma on the receipt of any plus-comma, minus-
comma, or both. Since the comma is defined as a 7-bit character, this includes several
out-of-band characters. RXCHARISCOMMA allows the decoder to detect only the
three defined commas (K28.1, K28.5, and K28.7) as plus-comma, minus-comma, or
both. In total, there are six possible options, three for valid commas and three for any
comma.
Running disparity
DC balance is achieved in the 8b/10b through a method called running
disparity. The primary use of running disparity is to keep track of whether the encoder

has output either more ones or more zeros. The 8b/10b encoding and decoding
functions use a binary variable called running disparity. The variable can have a value
of either positive (RD+) or a negative (RD-).

3.2.3 Rocket IO Transceiver Block Diagram and FPGA interface signals
Figure 14 Rocket IO Transceiver Block Diagram

3.2.3.1 PCS & PMA Layers

The Rocket IO MGT consists of Physical Media Attachment (PMA) and Physical
Coding Sub layer (PCS).
Physical Media Attachment (PMA)
- The PMA contains the 3.125 Gbps Serializer/Deserializer (SERDES) Tx/Rx
buffers, clock generator, and Clock Recovery Circuitry (CRC).
- The PMA function is responsible for serializing 10-bit parallel code groups to/from
a serial bit stream on a lane-by-lane basis.
Physical Coding Sub layer (PCS)
- The PCS contains the bypassable 8b/10b Encoder/Decoder, elastic buffers, and
Cyclic Redundancy Check (CRC) units.
- The PCS function is responsible for the idle sequence generation, lane stripping,
and encoding for transmission.
3.2.4 Rocket IO features

Full-Duplex Serial Transceiver (SERDES) Capable Baud Rates from 600 Mbps to
3.125 Gbps Terminations.
Fiber Channel, 10G Fiber Channel, Gigabit Ethernet, 10 Gb Attachment Unit interface
(XAUI), and Infiniband-Compliant Transceivers.
8B/10B Encoder and Decoder (optional).
Channel Bonding Support (from 2 to 20 Channels)
2.5V Transceiver Supply Voltage.
3.3 Optical Fiber Cable (OFC)

An optical fiber is a flexible, transparent fiber made of high quality extruded glass
or plastic, slightly thicker than a human hair. It can function as a waveguide, or "Light
pipe", to transmit light between the two ends of the fiber, Power over Fiber (POF) optic
cables can also work to deliver an Electric current for low power electric devices. The field of
applied science and engineering concerned with the design and application or optical fiber is
known as fiber optics.
Optical fibers are widely used in Fiber-optic communications, where they permit
transmission over longer distances and at higher bandwidths (data rates) than wire cables.
Fibers are used instead of metal wires because signals travel along them with less loss and are

also immune to electromagnetic interference. Fibers are also used for illumination, and are
wrapped in bundles so that they may be used to carry images, thus allowing viewing in
confined spaces specially designed fibers are used for a variety of other applications,
including sensors and fiber lasers.
Figure 15 Basic Optical Fiber system
3.3.1 Why only Optical

Optical is having broad bandwidth. But present communication systems are not using
the complete bandwidth. Why because we don't have any system that can use at that speed,
i.e., we continue to handle the data at high speed (>10 GB) in order to use the complete
bandwidth we can use this system.
The information carrying capacity of an optical fiber is far greater than it is for its
competitors: wires, coaxial cables, and microwave links. In addition, optical fibers are
inexpensive to produce, do not conduct electricity (which makes them immune to disturbance
by lightning storms, and other electromagnetic signals except nuclear radiation), do not
corrode, and are of small size. The primary reason that optical fibers have very much larger
information carrying capacity than other media is that they carry light: this might seem a
trivially obvious observation but it has fundamental significance. The frequency of the light
beams that travel along optical fibers is in the vicinity of two hundred trillion cycles per
second (Hz). Compare this with the frequency of the latest generation of personal
communication service (PCS) cellular wireless systems-approximately two billion cycles per
second (2 GHz). Consider the frequencies that must be transmitted for voice communications,
which cover the range (bandwidth) from about 50Hz to 20,000Hz (20 kHz). It is possible, in
principle, to carry about 50 billion voice conversations on a single laser beam in an optical
fiber.
3.4 SFP Transceiver

Small Form factor Pluggable transceiver (SFP) is a compact, hot-pluggable transceiver
used for both telecommunication and data communications applications. It interfaces a

network device mother board (for a switch, router, media converter or similar device) to a
fiber optic or copper networking cable. SFP transceivers are designed to support SONET,
Gigabit Ethernet, and Fiber Channel. Completely passive modules have a minimal effect on
serial data traffic.
SFP transceivers are available with a variety of different transmitter and receiver
types, allowing users to select the appropriate transceiver for each link to provide the required
optical reach over the available optical fiber type (e.g. multimode fiber or single-mode fiber).
Optical SFP modules are commonly available in four different categories: 850 nm, 1310nm,
1550nm, and DWDM. SFP transceivers are also available with a "copper" cable interface,
allowing a host device designed primarily for optical fiber communications to also
communicate over unshielded twisted pair networking cable. The optical transceiver which is
used supports high speed serial links over multimode optical fiber at signaling rates up to 4.25
Gbps. SFP transceivers converts the electrical signal to light signal and vice versa.
3.5 JTAG Cable

JTAG cable is used for boundary scanning of the FPGA device and communication
link between the computer and FPGA board. The full form of JTAG is Joint Test Action
Group because it is developed by Joint Test Action Group and Sanctioned by IEEE as STD
1149.1 test access port and Boundary Scan Architecture in 1990.

4. SOFTWARE DESCRIPTION
4.1 Xilinx ISE 12.4
4.1.1 Software Overview
The ISE software controls all aspects of the design flow. Through the
Project Navigator interface, you can access all of the design entry and design
implementation tools. You can also access the files and documents associated with the
project.
4.1.2 Project Navigator interface

By default, the Project Navigator interface divided into five panel sub windows.
Figure 16 Xilinx Project Navigator
1. Toolbar.
2. Sources window.
3. Processes window.
4. Workspace.
5. Transcript window

On the top left are the Start, Design, Files, and Libraries panels, which include display
and access to the source files in the project as well as access to running processes for the
currently selected source. The Start panel provides quick access to opening projects as well as
frequently access reference material (Documentation and tutorials). At the bottom of the
Project Navigator are the Console, Errors, and Warnings panels, which display status
messages, errors, and warnings. To the right is a Multi Document interface (MDI) window
referred to as the Workspace. The Workspace enables you to view design reports, text tiles,
schematics, and simulation waveforms. Each window can be resized, undocked from Project
Navigator, moved to a new location within the main Project Navigator window, tiled, layered,
or closed.
You can use the View > Panels menu commands to open or close panels.
You call use the Layout > Load Default Layout to restore the default window layout.
These windows are discussed in more detail in the following sections.
Design Panel
The Design panel provides access to the View, Hierarchy, and Processes panes.
View Pane
The View pane radio buttons enable you to view the source modules associated with
the implementation or Simulation Design View in the Hierarchy pane. If you select
Simulation, you must select a simulation phase from the drop-down list.
Hierarchy Panel
The Hierarchy pane displays the project name, the target device, user documents, and
design source flies associated with the selected Design View. The View pane at the top or the
Design panel allows you to view only those source files associated with the selected Design
View, such as Implementation or Simulation. Each file in the Hierarchy pane has an
associated icon. The icon indicates the file type (HDL file, schematic, core, or text file, for
(Example). From Project Navigator, select Help > Help Topics to view the ISE Help. If a file
contains lower levels of hierarchy, the icon has, plus symbol (+) to the left of the name. You
can expand the hierarchy by clicking the plus symbol (+). You can open a file for editing by
double-clicking on the filename.

Processes Panel
The Processes pane is context sensitive, and it changes based upon the source
type selected in the Sources pane and the top-level source m your project. From the
Processes pane, you can run the functions necessary to define, run, and analyze your design.
The Processes pane provides access to the following functions:
Design Summary/Reports
Xilinx ISE provides access to design reports, messages, and summary of results data.
Message Filtering can also be performed.
Design Utilities
Xilinx ISE provides access to symbol generation. Instantiation templates, viewing
command line History, and simulation library compilation.
User Constraints
Provides access to editing location and timing constraints
Synthesis
Xilinx ISE provides access to Check Syntax, Synthesis, view RTL or Technology
Schematic, and synthesis reports. Available processes vary depending on the synthesis tools
you use.
Implement Design
Xilinx ISE provides access to implementation tools and post-implementation analysis
tools.
Generate Programming File

Xilinx ISE provides access to bit stream generation.
Configure Target Device

Xilinx ISE provides access to configuration tools for creating programming flies and
programming the device.
Files Panel
The Files panel provides a flat, sortable list of all the source files in the project. Files
can be sorted by any of the columns in the view. Properties for each file can be viewed and
modified by right-clicking on the file and selecting Source Properties.

Libraries Panel
The Libraries panel enables you to manage HDL libraries and their associated HDL
source files. You can create, view, and edit libraries and their associated sources.
Console Panel
The Console provides all standard output from processes run from Project Navigator.
It displays errors, warnings, and information messages. Errors are signified by a red X next to
the message; while warnings have a yellow exclamation mark (!).
Errors Panel
The Errors panel displays only error messages. Other console messages are filtered
out.
Warnings Panel
The Warnings panel displays only warning messages. Other console messages are
filtered out.
Error Navigation to Source

You can navigate from a synthesis error or warning message in the Console, Errors, or
Warnings panel to the location of the error in a source HDL file. To do so, select the error or
warning message, right-click the mouse, and select Go to Source from the right-click menu.
The HDL source file opens, and the cursor moves to the line with the error.
Error Navigation to Answer Record

You can navigate front an error or warning message in the Console, Errors.
Or Warnings panel to relevant Answer Records on the Support page of the Xilinx website. To
navigate to the Answer Record, select the error or warning message, right-click the mouse,
and select Go to Answer Record from the right-click menu. The default Web browser opens
and displays all Answer Records applicable to this message.
Workspace
The Workspace is where design editors, viewers, and analysis tools open.
These include ISE Text Editor, Schematic Editor, Constraint Editor, Design
Summary/report Viewer, RTL and Technology Viewers, and Timing Analyzer.

Other tools such as the Plan Ahead software for I/O planning and floor planning, ISim, third-
party text editors, XPower Analyzer, and IMPACT open in separate windows outside the
main Project Navigator environment when invoked.
4.1.3 Design Summary/Report Viewer

The Design Summary provides a summary of key design data as well as access to all
of the messages and detailed reports from the synthesis and implementation tools,
The summary lists high-level information about your project, including overview
information, device utilization summary, performance data gathered from the Place and Route
(PAR) report, constraints information, and summary information from all reports with links
to the individual reports. A link to the System Settings report provides information
on environment variables and tool settings used during the design implementation. ISE In-
Depth Messaging features such as message filtering, tagging, and incremental messaging are
also available from this view.
4.1.4 VHDL or Verilog

This (Xilinx ISE 12.4) tutorial supports both VHDL and Verilog designs and applies
to both designs simultaneously, noting differences where applicable. You will need to decide
which HDL language you would like to work through for the tutorial and download the
appropriate files for that language. XST can synthesize a mixed-language design.
4.1.5 ISim
Xilinx ISim is a Hardware Description Language (HDL) simulator that enables you to
perform functional and timing simulations for VHDL, Verilog and mixed VHDL/Verilog
designs.
4.1.5.1 Simulation Libraries

The Xilinx simulation device libraries are precompiled, and are updated automatically
when updates arc installed. Do not run the Simulation Library Compilation Wizard
(Compxlib) to compile libraries for use with ISim.
4.1.5.2 Steps in a Simulation

The basics steps for simulating your design in ISim are as follows:
Step 1: Gathering Files and Mapping Libraries
Step 2: Parsing and Elaborating the Design

Step 3: Simulating the Design

Step 4: Examining the Design
Step 5: Debugging the Design
4.2 Introduction to Aurora Protocol

4.2.1 Protocol
Serializer/Deserializer (SERDES) by themselves are relatively flexible devices. To set
them up, we must define an alignment sequence, a clock correction sequence. The line
encoding method, and the physical connection, and data will How between the
two transceivers. But the meaning of that data requires more definition, and that is the purpose
of the protocol. What data is transmitted to where, what the data means, what is inserted in
data, what can be discarded, are defied by protocols.
4.2.2 Standard Protocols
XAUI: A 4-channel interface (2.5 Gbps payload, 3.125 Gbps wire speed) for 10-Gigabit
Ethernet.
PIC Express: Takes the old parallel PIC structure and updates it to a high speed serial
structure. Upper levels of the protocol remain compatible, providing an easy adaptation into
legacy PIC system.
Serial Rapid IO: Serial rapid IO is quite flexible and sometimes used as a method of
interfacing to multiple protocols such as P1C and infini-band.
Fiber Channel: Fiber channel has always been a serial standard, but its speed has increased
over the year. As copper interconnects have advanced, it has also become available on copper
as well as fiber optics.
Infiniband: a box-to-box protocol runs over either copper or fiber. Infiniband style cable has
become highly popular for multi-gigabit links of few meters range. Die specification allows
for a variety of devices and complexity, and includes specifications for repeaters, and switches
or hubs to expand the number of connected devices. Infiniband can also be used for complex
system configurations.
Aurora: Aurora is a relatively simple protocol that handles only link layer and physical
issues. It has been designed to allow other protocol such as TCP/IP or Ethernet to ride easily
on top of it. It uses one or more high speed serial lanes.

4.2.3 Overview of Aurora

The Aurora 8B/10B core is a scalable, lightweight, link-layer protocol for high-speed
serial communication. The protocol is open and can be implemented using Xilinx FPGA
technology. The protocol is typically used in applications requiring simple, low-cost, high-
rate, data channels. It is used to transfer data between devices using one or many transceivers.
Connections can be full-duplex (data in both directions) or simplex.
Figure 17 Aurora simplex channels over view
Aurora 8B/10B cores automatically initialize a channel when they are connected to an
Aurora channel partner. After initialization, applications can pass data freely across the
channel as frames or streams of data. Aurora frames can be any size, and can be interrupted at
any time. Gaps between valid data bytes are automatically filled with idle to maintain lock
and prevent excessive electromagnetic interference. Flow control is optional in Aurora. It can
be used to reduce the rate of incoming data or to send brief, high-priority messages through
the channel.
Each GTP/GTX/GTH transceiver is driven by an instance of the lane logic module,
which initializes each individual GTP/GTX/GTH transceiver and handles the encoding and
decoding of control characters and error detection. Streams are implemented in the Aurora
8B/10B core as a single, unending frame. Whenever data is not being transmitted, idles are
transmitted to keep the link alive. The Aurora 8B/IOB core detects single-bit and most multi-
bit errors using 8B/10B coding rules. Excessive bit errors, disconnections, or equipment
failures cause the core to reset and attempt to re-initialize a new channel.

4.2.3.1 Functional Block diagram of Aurora
Figure 18 Functional Block diagram of Aurora
Figure-18 shows the Functioning of Aurora when two example designs are
implemented in which one of the example designs receives data when the other transmits.
For simplicity, in the current project only one example design is used where the same
example design transmits as well as receives data. The Figure-19 below demonstrates the
same.
Figure 19 Aurora module with single example design
4.2.4 Functional Description of Aurora
Figure 20 Aurora Block Diagram

The major functional modules of the Aurora 8B/10B core are:
Lane logic: Each GTP/GTX/GTH transceiver is driven by an instance of the lane logic
module, which initializes each individual GTP/GTX/GTH transceiver and handles the
encoding and decoding of control characters and error detection.
Global logic: The global logic module in each Aurora 8B/10B core performs
the bonding and verification phases of channel initialization. While the channel
is operating, the module generates the random idle characters required by the
Aurora protocol and monitors all the lane logic modules for errors.
RX user interface: The RX user interface moves data from the channel to
the application. Streaming data is presented using a simple stream interface
equipped with a data bus and a data valid signal. Frames are presented using a
standard AX14-Stream interface. This module also performs now control functions.
TX user interface: The TX user interface moves data from the application to
the channel. A stream interface with a data valid and a ready signal is used
for streaming data. A standard AX14-Stream interface is used for data frames.
The module also performs flow control TX functions. The module has an interface
for controlling clock compensation (the periodic transmission of special characters
to prevent errors due to small clock frequency differences between connected Aurora
8B/10B cores). This interface is normally driven by a standard clock compensation
manager module provided with the Aurora 8B/10B core, but it can be turned off, or
driven by custom logic to accommodate special needs.
Channel bonding: Channel bonding is the technique of tying several
channels together to create one aggregate channel. Several channel are fed on the
transmit side by one parallel bus and reproduced on the receive side as the
identical parallel bus. The maximum number of serial number of serial differential
pairs that can be bonded is 24.
4.2.7 User Interface

An aurora core can be generated with either of the two user data interfaces, which are
shown below.
1. Framing user interface
2. Streaming user interface

The framing user interface complies with a local link interface specification.
It comprises the signals are available for designs for designs with framing interfaces.
The streaming interface allows sending data without special frame delimiters.
The Project deals with streaming user interface, which is very simple to operate, and also
user fewer resources than framing.
4.2.7.1 Streaming Interfacing
Figure 21 Aurora 8b/10b core Streaming user interface
Streaming TX Ports
The streaming interface allows the Aurora 8B/10B channel to be used as a
pipe. Words written into the TX side of the channel are delivered, in order after some
latency, to the RX side. After initialization, the channel is always available for writing,
except when the DO_CC signal is asserted to send clock compensation sequences.
Applications transmit data through the TX_D port, and use the TX_SRC_RDY_N port
to indicate when the data is valid (asserted Low). The Aurora 8B/10B core will
insert TX_DST_RDY_N (High) when the channel is not ready to receive data.
Otherwise, TX_DST_RDY_N will remain asserted.
When TX_SRC_RDY_N is deserted, gaps are created between words.
These gaps are reserved, except when clock compensation sequences are being
transmitted. Clock compensation sequences are replicated or deleted by the GTP/GTX
transceiver to make up for frequency differences between the two sides of the Aurora
8B/10B channel. As a result, gaps created when DO-CC is asserted can shrink and
grow.

Figure 22 Typical Tx Streaming Data Transfer
Table 5 Streaming User I/O Ports (TX)
Name Direction Description

TX_D[0:(wn-1)] Input Outgoing data (Ascending bit order).
Asserted (Low) during clock edges when signals from the source
will be accepted (if TX_SRC_RDY_N is also asserted).
TX_DST_RDY_N Output
Deasserted (High) on clock edges when signals from the source
will be ignored.
Asserted (Low) when Local Link signals from the source are valid.
TX_SRC_RDY_N Input Deasserted (High) when Local Link control signals and/or data
from the source should be ignored (active-Low).
Streaming Rx Ports
When data arrives at the RX side of the Aurora 8B/10B channel it is presented
on the RX_D bus and RX_SRC_RDY is asserted. The data must be read immediately
or it is lost. If this is unacceptable, a buffer must be connected to the RX interface to
hold the data until it can be used.
Figure 23 Typical RX Streaming Data Transfer
Table 6 Streaming User I/O Ports (RX)

Incoming data from channel partner (Ascending bit
RX_D[0:(wn-1)] Output
order).

Asserted (Low) when data and control signals from an

Aurora 8B/10B core are valid.
Deasserted (High) when data and/or control signals
RX_SRC_RDY_N Output
from an Aurora 8B/10B core should be ignored (active-
Low).
4.2.8 Status, Control, and the GTP/GTX Block Interface
Figure 24 Top-Level GTP/GTX Block Interface
4.2.8.1 Full-Duplex Status and Control Ports

Full-duplex cores provide a TX and an RX Aurora 8B/10B channel connection. Figure
shows the status and control interface for a full-duplex Aurora 8B/10B core.

Figure 25 Status and Control Interface for Full-Duplex Cores
Table 7 Status and Control Ports for Full-Duplex Cores

Asserted when Aurora 8B/10B channel initialization is
complete and channel is ready to send data. The Aurora
CHANNEL_UP Output
8B/10B core cannot receive data before
CHANNEL_UP.
Asserted for each lane upon successful lane
LANE_UP[0:m- initialization, with each bit representing one lane
Output
1] (active-High). The Aurora 8B/10B core can only
receive data after all LANE_UP signals are High.
Channel frame/protocol error detected. This port is
FRAME_ERROR Output
active-High and is asserted for a single clock.
Hard error detected. (Active-High, asserted until
HARD_ERROR Output
Aurora 8B/10B core resets).
The LOOP BACK[2:0] port selects between the normal
operation mode and the different loopback modes. See
the Virtex-5 FPGA Rocket IO GTP Transceiver User
LOOPBACK[2:0] Input Guide, Virtex-5 FPGA Rocket IO GTX Transceiver
User Guide, Virtex-6 FPGA GTX Transceivers User
Guide, and Spartan-6 FPGA GTP Transceivers User
Guide for details about loopback.
Input Drives the power-down input of the GTP/GTX
POWER_DOWN Input
transceiver (active-High).
RESET Output Resets the Aurora 8B/10B core (active-High). This

signal must be synchronous to USER_CLK and must

be asserted for at least one USER_CLK cycle.
Soft error detected in the incoming serial stream
SOFT_ERROR Input
(Active-High, asserted for a single clock).
RXP[0:m-1] Input Positive differential serial data input pin.
RXN[0:m-1] Output Negative differential serial data input pin.
TXP[0:m-1] Output Positive differential serial data output pin.
TXN[0:m-1] Input Negative differential serial data output pin.
The reset signal for the PMA modules in the
transceivers is connected to the top level through a
debouncer. The GT_RESET should be asserted (active-
GT_RESET Input High) when the module is first powered up in
hardware. This systematically resets all PCS and PMA
subcomponents of the transceiver.
The signal is debounced using the INIT_CLK.
INIT_CLK is used to register and debounce the
GT_RESET signal in cores targeted for the Virtex- 5
device. INIT_CLK is required since USER_CLK stops
when GT_RESET is asserted. INIT_CLK should be set
to a slow rate, preferably slower than the reference
INIT_CLK Input clock. INIT_CLK is a board clock. For example, the
ML523 board has a 50 MHz crystal oscillator and it is
constrained for this frequency by default in the
<component_name>_example_design.ucf file. Users
needs to update this clock constraint with respect to
their board clock frequency.
4.2.8.2 Error Signals in Full-Duplex Cores

Equipment problems and channel noise can cause errors during Aurora 8B/10B
channel operation. 8B/10B encoding allows the Aurora 8B/10B core to detect all single bit
errors and most multi-bit errors that occur in the channel. The core reports these errors by
asserting the SOFT_ERR signal on every cycle they are detected. The core also monitors each
GTP/GTX transceiver for hardware errors such as buffer overflow and loss of lock. The core

reports hardware errors by asserting the HARD_ERR signal. Catastrophic hardware errors can
also manifest themselves as burst of soft errors. The core uses the leaky bucket algorithm
described in the Aurora 8B/10B Protocol Specification to detect large numbers of soft errors
occurring in a short period of time, and will assert the HARD_ERR signal when it detects
them.
Aurora 8B/10B cores with a Local Link data interface can also detect errors in Aurora
8B/10B frames. Errors of this type include frames with no data, consecutive Start of Frame
symbols, and consecutive End of Frame symbols. When the core detects a frame problem, it
asserts the FRAME_ERR signal. This signal is usually asserted close to a SOFT_ERR
assertion, with soft errors being the main cause of frame errors.
Table 8 Error Signals in Full-Duplex Cores
Signal Description
TX Overflow/Underflow: The elastic buffer for TX data overflows or
underflows. This can occur when the user clock and the reference clock
sources are not running at the same frequency.
RX Overflow/Underflow: The elastic buffer for RX data overflows or
underflows. This can occur when the clock source frequencies for the two
channel partners are not within 200 ppm.
Bad Control Character: The protocol engine attempts to send a bad
HARD_ERROR control character. This is an indication of design corruption or
catastrophic failure.
Soft Errors: There are too many soft errors within a short period of time.
The Aurora 8B/10B protocol defines a leaky bucket algorithm for
determining the acceptable number of soft errors within a given time
period. When this number is exceeded, the physical connection may be
too poor for communication using the current voltage swing and
preemphasis settings.
Invalid Code: The 10-bit code received from the channel partner was not
a valid code in the 8B/10B table. This usually means a bit was corrupted
SOFT_ERROR in transit, causing a good code to become unrecognizable.
Typically, this will also result in a frame error or corruption of the current
channel frame.

Disparity Error: The 10-bit code received from the channel partner did
not have the correct disparity. This error is also usually caused by
corruption of a good code in transit, and can result in a frame error or bad
data if it occurs while a frame is being sent.
Truncated Frame: A channel frame is started without ending the previous
channel frame, or a channel frame is ended without being started.
FRAME_ERROR Invalid Control Character: The protocol engine receives a control
character that it does not recognize.
No Data in Frame: A channel frame is received with no data
4.2.8.3 Full-Duplex Initialization

Full-duplex cores initialize automatically after power up, reset, or hard error. Full-
duplex modules on each side of the channel perform the Aurora 8B/10B
initialization procedure until the channel is ready for use. The LANE_UP bus indicates which
lanes in the channel have finished the lane initialization portion of the initialization
procedure. This signal can be used to help debug equipment problems in a multi-lane
channel. CHANNEL_UP is asserted only after the core completes the entire
initialization procedure.
Aurora 8B/10B cores cannot receive data before CHANNEL_UP is asserted. Only the
RX_SRC_RDY_N signal on the user interface should be used to qualify incoming data.
CHANNEL_UP can be inverted and used to reset modules that drive the TX side of a full-
duplex channel, since no transmission can occur until after CHANNJEL_UP. If user
application modules need to be reset before data reception, one of the LANE_UP signals can
be inverted and used. Data cannot be received until after all the LANE_UP signals are
asserted.
4.2.9 Applications of Aurora

Aurora cores can be used in a wide variety of applications because of their low
resource cost, scalable throughput, and flexible data interface. Examples of Aurora core
applications include:
Chip to Chip links

Replacing parallel connections between chips with high speed serial connections can
significantly reduce the number of traces and layers required on a PCB. The Aurora core
provides the logic needed to use MGTs with minimal FPGA resource cost.
Board to Board/Backplane links
Aurora uses standard 8b/10b encoding, making it compatible with many existing
hardware standards for cables and backplanes. Aurora can be scaled, both in line rate
and channel width to allow inexpensive legacy hardware to be used in new, high
performance systems.
4.3 Chip Scope Pro Analyzer

4.3.1 Introduction
The Chip Scope Pro Serial I/O Toolkit provides features and capabilities specific to
the exploration and debug of designs that use the high sped serial transceiver I/O capability of
FPGAs. The IBERT (Internal Bit Error Ratio Tester) core and related software provides
access to the high-speed serial transceivers and perform bit error ratio analysis on channels
composed of these transceivers. In this document, the transceivers are called MGTs (Multi-
Gigabit Transceivers). The IBERT core supports the high-speed serial transceivers found in
the Xilinx Virtex-7, Kintcx-7, Virtex-6, Spartan-6, and Virtex-5 FPGA devices.
As the density of FPGA devices increases, so does the impracticality of attaching test
equipment probes to these devices under test. The Chip Scope Pro tools integrate key logic
analyzer and other test and measurement hardware components with the target design inside
the supported Xilinx FPGA devices listed in the JSE Design Suite Product. The tools
communicate with these components and provide the designer with a robust logic analyzer
solution.
4.3.2 Chip Scope Pro Analyzer Features

4.3.2.1 Working with Projects
Projects hold important information about the Chip Scope Pro Analyzer program state,
such as signal naming, signal ordering, bus configurations, and trigger conditions. They allow
you to conveniently store and retrieve this information between Chip Scope Pro Analyzer
sessions.
When you first run the Chip Scope Pro Analyzer tool, a new project is automatically
created and is titled new project.

To open an existing project, select File > Open Project, or Select one of the recently
used projects in the File menu.
The title bar of the Chip Scope Pro Analyzer and the project tree displays the project
name. If the new project is not saved during the course of the session, a dialog box appears
when the Chip Scope Pro Analyzer tool is about to exit, asking you if you wish to save the
project.
4.3.2.2 Creating and Saving a New Project

To create a new project, select File > New Project.
A new project called new project is created and made active in the chip Scope Pro
Analyzer tool.
To save the new project under a different name, select File > Save Project.
The project file has a .cpj extension.
4.3.2.3 Saving Projects

To rename the current project, or to save a copy to another filename, select
File > Save Project As,
Type the new name in the File name dialog box, and click Save.
4.3.2.4 Printing Waveforms

One of the features of Chip Scope Pro is the ability to print a captured data waveform
by using the File > Print menu option.
Selecting the File Print menu option starts the Print Wizard.

5. PROJECT IMPLEMENTATION
5.1 SOFTWARE IMPLEMENTATION
5.1.1 Generation of Aurora Core by Using Core Generator
Step by step procedure for generating aurora core:
1. Select Xilinx ISE from all programs and select tools and click on it.
2. Select core generator and click on it and core generator window opens.
Figure 26 Xilinx Core Generator
3. Then select new project and save the coregen in required folder and below window opens.
Figure 27 Aurora 8b/10b IP Customizer

4. Then select family as Virtex 5, device xc5vfx200t, package ff1738 and speed grade as -1
and click apply ok.
5.Then expand communication and networking which is in left side of window then select
serial interfaces and in that select aurora 8b/10b 5.2 and click on it.
Figure 28 Second GUI Page for Virtex-5 FPGA Rocket I/O GTP Transceivers
6. Aurora 8b 10b window select streaming for interface and for 16 bits select lane width as
2,for 32 select lane width as 4as shown in below figure and click generate.
Figure 29 8b/10b component and interface selection window
7. Such that aurora core is generated and this core will be saved in required folder mentioned
by the user.

Figure 30 Aurora core Generated window
5.1.2 Project implementation

Step by step procedure for implementing the project:
1. Select the Xilinx ISE project from the folder where the core is saved.
2. Then open the Xilinx file and the aurora core opens where we can see the different modules
of aurora.
3. This window has two example aurora design modules as shown below.
Figure 31 Aurora core with two example designs

4. One example design module is removed such that only one aurora module is used for
implementation.
5. In the next process frame gen and frame check is removed and our own logic is attached.
Figure 32 Aurora core with one example design and removed frame gen and frame check
6. By using state machine our own data is passed so, the logic is attached to the program.
Figure 33 State machine program

7. After saving the program click check syntax for checking errors and after debugging select
simulation and enter the required test bench program.
8. Save the program and click on behavioral check syntax and after select simulate behavioral
model for obtaining the result.
Figure 34 Simulation behavioral windows
5.1.3 Synthesis
The code is written and checked for any errors by running the Synthesize-XST tool in
the processor window of the Project Navigator in the ISE development tool.
5.1.4 User Constraint File (UCF) Generation

The UCF provides a mechanism for constraining a logical design without returning to
the design entry tools. However, without design entry tools, the exact syntax needed to define
constraints must be understood.
Syntax to define a constraint in UCF is
NET <pin> LOC = <pin location>;
Example:
NET TXP_T (0) LOC = AP20;
The Constraints Editor and Pin out Area Constraints Editor (PACE) are the graphical
tools that enable you to enter timing and pin location constraints. The constraints editor can be
opened using Create Timing Constraints option.

5.2 HARDWARE IMPLEMENTATION

The power that is to be supplied to the FPGA should be very strictly regulated and it
should be a constant supply because if any power disturbances occur in the process of the
execution that will affect the memory of the FPGA as the memory in Virtex- 5 is a volatile
memory. So here we use a power supply which is programmed to give regulated voltage and
current that is required for the board.
Figure 35 Power Supply for Virtex-5 FPGA
JTAG which acts as interface between the FPGA board and computer
Figure 36 JTAG Connection
Typical Virtex-5 FPGA board used for implementation of the project,

Figure 37 Virtex-5 FPGA Board
The Virtex-5 FPGA board is dumped with the program using the JTAG and Xilinx
iMPACT Tool. This transmission and reception of data in the FPGA board is observed using
the chipscope probe analyzer.
Implementation of Project using Hardware resources,
Figure 38 Implementation of Project using Hardware resources

5.2.1 Implementing Design using iMPACT Tool

Once the UCF file is generated, the next step is to download the bit file into FPGA
using the parallel JTAG cable which connects PC and FPGA. The bit file is used to configure
the device using the iMPACT Tool of Xilinx.
xc5vfx200t
main.bit
Program Succeeded
Figure 39 iMPACT Programming Operation
5.2.2 CHIPSCOPE PRO ANALYZER

After configuring the FPGA, Chipscope Pro Analyzer of Xilinx tool kit is used to
verify the data at required pins of FPGA. To do so, after generating UCF file, Chipscope Pro
analyzer must be intialized resulting in the genration of a bit file and a cdc file. Adding these
files to the Chipscope Pro tool gives the simulation waveforms/data at the required pins (Pins
that are added during the intialization of Chipscope Pro tool).

6. RESULT
6.1 Specifications
6.1.1 Project Specifications
Software : Xilinx 12.4 ISE
Family : Virtex-5
Device : xc5vfx200t
Package : ff1738
Speed Grade : -1
Preferred language : VHDL
Simulator : ISE Simulator (VHDL)
Top- Level Source Type : HDL
6.1.2 Timing Specifications

Minimum period : 2.729ns
Minimum input arrival time before clock : 1.154ns
Maximum output required time after clock : 3.314ns
Clock Period : 8ns
Total REAL time to Xst completion : 12.00 sec
Total CPU time to Xst completion : 11.56 sec
6.1.3 Inputs and Outputs

Inputs : Reset, data_rdy , new_data , GTXD0_P, GTXD0_N,RXP,RXN
Outputs : Lane_up, Channel_up, hard_error, soft error, TXP, TXN, Tx_dst_rdy_n.

6.2 Simulation Results

6.2.1 Top Level Module
Figure 40 Top Level module
6.3 Simulation Waveforms
Figure 41 Channel_up and Lane_up signal
From the above figure we can see that channel_up and lane_ up signals becomes high so that
the data passes through the channel and lane.

Figure 42 Transmission signals
In the above figure tx_src_rdy_n and tx_dst_rdy_n becomes low so that the data starts
transmitting in Tx_d .
Figure 43 Reception Signals
In the above figure, when Rx_src_rdy_n becomes low such that the receiver rx_d receives the
data.

Figure 44 Byte Data Transmission using State Machine
The above figure shows the transmission of data by using State Machine where Present state
and Next state show the state of the data being transmitted.
6.4 Chipscope Pro results

Schematic Waveforms showing TX_DATA & RX_DATA

Figure 45 Chipscope Pro results showing Count & TX_DATA
Figure 46 Chipscope Pro results showing RX_DATA
Result in listing format,

Figure 47 Chipscope Pro result in listing format showing COUNT & TX_DATA
Figure 48 Chipscope Pro results in listing format showing RX_DATA

6.5 Synthesis Report

----- Source Parameters
Input File Name : "aurora_8b10b_v5_3_example_design.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
----- Target Parameters
Output File Name : "aurora_8b10b_v5_3_example_design"
Output Format : NGC
Target Device : xc5vfx200t-1-ff1738
----- Source Options
Top Module Name : aurora_8b10b_v5_3_example_design
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Use DSP Block : Auto
Automatic Register Balancing : No
----- Target Options
LUT Combining : Auto

Reduce Control Sets : Auto

Add IO Buffers : YES
Global Maximum Fan-out : 100000
Add Generic Clock Buffer (BUFG) : 32
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
----- General Options
Optimization Goal : Speed
Optimization Effort :1
Power Reduction : NO
Keep Hierarchy : No
Net-list Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5
----- Other Options

Cores Search Directories : {"aurora_8b10b_v5_3/implement" }

Advanced HDL Synthesis Report
Macro Statistics :2
# Counters :3
4-bit down counter :1
8-bit up counter :2
# Registers : 434
Flip-Flops : 434
# Latches :2
16-bit latch :1
5-bit latch :1
# Xors :4
1-bit xor2 :4

6.6 RTL Schematic
Figure 49 RTL schematic diagram

7. ADVANTAGES AND LIMITATIONS

7.1 Advantages
1. The most important advantage is the speed of transmission of data. As we are using
OFC cable that data travels in the speed of light.
2. As the data is transmitted in the form of light there is no interference of noise during
the transmission and hence the loss of data is negligible almost zero.
3. Complexity is reduced due to practical application of OFC a single cable where data is
transmitted serially and in single cable.
4. This technology is used in long distance communication channels.
5. This technology is used in long distance communication channels where installation of
cables in the path of transmission is almost considered.
7.2 Limitations
1. This type of communication is only possible for point-point communication.

2. Aurora protocol supports only error detection but not error correction.

8. APPLICATIONS
1. This type of communication is used in war fare as the information about the enemies
should be known quickly and without any loses.
2. This communication is mainly applicable in Board-to-Board/Backplane and Chip-to-
Chip communication.
3. This technology is applicable in long distance radar communication without data loss.

9. CONCLUSION AND FUTURE SCOPE

9.1 Conclusion
The high speed serial data is transmitted through optical fiber cable at the rate of 3.125
Gbps using multi-gigabit transceiver and received by other multi-gigabit transceivers. Both
the transmitted and received data are monitored in the chip-scope pro analyzer.
9.2 Future Scope

The present project is implemented using aurora protocol for serial data transmission
at the rate of 3.125Gbps. The next level protocol is Serial Rapid I/O (SRIO) which works on
the principle of data packets switching is more efficient for error free transmission and speed
can be increased to higher level.

10. REFERENCES
1. Chip-scope pro integrated bit error ratio test (IBERT) for virtex-5 FPGA GTX(v2.01a),
DS774 October 19, 2011.
2. Circuit Design with VHDL text book by Volnei A. Pedroni.
3. Logic core IP aurora 8b/10 v5.2 user guide July 23, 2010 by Xilinx.
4. Logic ORE IP FIFO Generator v8.1, DS 317.
5. Data Sheet -850 nm, SFP (Small Form Pluggable), RoHS Compliant, Low Voltage
(3.3V) Digital Diagnostic Optical Transceiver by AVAGO Technologies.
http://www.avagotech.com/docs/AV02-0881EN.
6. High speed serial I/O made simple- A designers guide with FPGA applications book by
Abhijit Athavale and Carl Christensen of Xilinx
7. RocketIO Transceiver User Guide by Xilinx
8. http://www.xilinx.com/publications/archives/books/serialio.pdf
9. ISim User Guide user guide 660 (version 13.1) march 18 , 2011
http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1 /plugin_ism.pdf
10. Aurora 8b/10b protocol specification, 2010 by Xilinx.
http://www.xilinx.com/support/documentation/ip_documentation
Aurora_8b10b_protocol_spec_sp002.pdf.

APPENDIX
APPENDIX-A
8b/10b Valid Data Characters




APPENDIX B
VALID CONTROL CHARACTERS ( K- CHARACTERS )
Special Bits Current RD Current RD +

Code Name HGF EDCBA abcdei fghj abcdei fghj
K28.0 000 11100 001111 0100 110000 1011
K28.1 001 11100 001111 1001 110000 0110
K28.2 010 11100 001111 0101 110000 1010
K28.3 011 11100 001111 0011 110000 1100
K28.4 100 11100 001111 0010 110000 1101
K28.5 101 11100 001111 1010 110000 0101
K28.6 110 11100 001111 0110 110000 1001
K28.7(1) 111 11100 001111 1000 110000 0111
K23.7 111 10111 111010 1000 000101 0111
K27.7 111 11011 110110 1000 001001 0111
K29.7 111 11101 101110 1000 010001 0111
K30.7 111 11110 011110 1000 100001 0111

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Implementation and Establishment of Gigabit Serial Rocket IO Communication using Virtex - 5 FPGA

2. PROJECT DESCRIPTION .............................................................................................. 15

Electronics and Communication Engineering, TKRCET 1

2.6.1.2 VHDL ............................................................................................................ 17

3. HARDWARE DESCRIPTION ........................................................................................ 19

4. SOFTWARE DESCRIPTION .......................................................................................... 32

Electronics and Communication Engineering, TKRCET 2

4.2.8 Status, Control, and the GTP/GTX Block Interface .............................................. 43

5. PROJECT IMPLEMENTATION ..................................................................................... 50

7. ADVANTAGES AND LIMITATIONS ........................................................................... 68

Electronics and Communication Engineering, TKRCET 3

9.2 FUTURE SCOPE ............................................................................................................ 70

Figure 2 Example waveform of Multiphase extraction circuit ................................................. 9

Figure 3 System-Synchronous Diagram ............................................................................... 13

Figure 4 Source-Synchronous Diagram ................................................................................ 13

Figure 5 Self-Synchronous Diagram..................................................................................... 14

Figure 6 Clock Data Recovery Waveform ............................................................................ 14

Figure 7 Block Diagram of Electrical Warfare ..................................................................... 15

Figure 8 Electronic Support Measures System...................................................................... 16

Figure 9 Block Diagram of the Project ................................................................................. 17

Figure 10 SERDES Block Diagram ...................................................................................... 23

Figure 11 CRC Packet Format .............................................................................................. 24

Figure 12 10-Bit TX Data Map with 8B/10B Bypassed ........................................................ 25

Figure 13 10-Bit RX Data Map with 8B/10B Bypassed ........................................................ 26

Figure 14 Rocket IO Transceiver Block Diagram ................................................................. 28

Figure 15 Basic Optical Fiber system ................................................................................... 30

Figure 16 Xilinx Project Navigator....................................................................................... 32

Figure 17 Aurora simplex channels over view ...................................................................... 38

Figure 18 Functional Block diagram of Aurora .................................................................... 39

Figure 19 Aurora module with single example design .......................................................... 39

Figure 20 Aurora Block Diagram ......................................................................................... 39

Electronics and Communication Engineering, TKRCET 4

Figure 21 Aurora 8b/10b core Streaming user interface ........................................................ 41

Figure 22 Typical Tx Streaming Data Transfer ..................................................................... 42

Figure 23 Typical RX Streaming Data Transfer.................................................................... 42

Figure 24 Top-Level GTP/GTX Block Interface .................................................................. 43

Figure 25 Status and Control Interface for Full-Duplex Cores .............................................. 44

Figure 26 Xilinx Core Generator .......................................................................................... 50

Figure 27 Aurora 8b/10b IP Customizer ............................................................................... 50

Figure 29 8b/10b component and interface selection window ............................................... 51

Figure 30 Aurora core Generated window ........................................................................... 52

Figure 31 Aurora core with two example designs ................................................................. 52

Figure 33 State machine program ......................................................................................... 53

Figure 34 Simulation behavioral windows ............................................................................ 54

Figure 35 Power Supply for Virtex-5 FPGA ......................................................................... 55

Figure 36 JTAG Connection ................................................................................................ 55

Figure 37 Virtex-5 FPGA Board .......................................................................................... 56

Figure 38 Implementation of Project using Hardware resources ........................................... 56

Figure 39 iMPACT Programming Operation ........................................................................ 57

Figure 40 Top Level module ................................................................................................ 59

Figure 41 Channel_up and Lane_up signal ........................................................................... 59

Figure 42 Transmission signals ............................................................................................ 60

Figure 43 Reception Signals ................................................................................................. 60

Figure 44 Byte Data Transmission using State Machine ....................................................... 61

Electronics and Communication Engineering, TKRCET 5

Figure 45 Chipscope Pro results showing Count & TX_DATA ............................................ 62

Figure 46 Chipscope Pro results showing RX_DATA .......................................................... 62

Figure 48 Chipscope Pro results in listing format showing RX_DATA ................................ 63

Figure 49 RTL schematic diagram ...................................................................................... 67

Table 1 Software and Hardware resources ............................................................................ 18

Table 2 List of Family of Virtex 5 FPGA ............................................................................. 19

Table 3 Number of Rocket IO cores per Device type ............................................................ 22

Table 4 Communication standards followed by Rocket IO transceiver ................................. 23

Table 5 Streaming User I/O Ports (TX) ................................................................................ 42