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ESE 2018 : Prelims Exam ELECTRICAL

CLASSROOM TEST SERIES ENGINEERING
Answer Key & Solutions of Section A : Electrical Circuits (All Topics)
Test No. 1 Section B : Digital Electronics + Microprocessors (All Topics)

1. (c) 16. (a) 31. (b) 46. (b) 61. (b)

2. (c) 17. (c) 32. (c) 47. (b) 62. (d)

3. (b) 18. (b) 33. (b) 48. (a) 63. (c)

4. (d) 19. (a) 34. (c) 49. (c) 64. (c)

5. (b) 20. (d) 35. (a) 50. (c) 65. (c)

6. (d) 21. (c) 36. (a) 51. (a) 66. (b)

7. (d) 22. (c) 37. (c) 52. (b) 67. (b)

8. (c) 23. (b) 38. (c) 53. (d) 68. (a)

9. (c) 24. (a) 39. (d) 54. (b) 69. (b)

10. (b) 25. (b) 40. (d) 55. (d) 70. (d)

11. (c) 26. (d) 41. (d) 56. (c) 71. (a)

12. (c) 27. (c) 42. (c) 57. (c) 72. (a)

13. (d) 28. (b) 43. (d) 58. (d) 73. (d)

14. (c) 29. (c) 44. (d) 59. (c) 74. (d)

15. (c) 30. (a) 45. (c) 60. (b) 75. (b)
12 ESE 2018 Prelims Exam Classroom Test Series

DETAILED EXPLANATIONS : Section A (Electrical Circuits)

1. (c)
t
Energy, E = v (t ) i(t ) dt

dq
But, i(t) =
dt
or i(t) dt = dq
t 3
2
E = v (t ) dq = (1 + 2q + 3q ) dq
1

3
2q 2 3q 3
= q + + = [(3 1) + (32 12) + (33 13)]
2 3 1
= 2 + (9 1) + (27 1)
= 2 + 8 + 26 = 36 J

2. (c)
A A

Vs R Vs

B B

R
A A

Is Is

B B

3. (b)
Rs I
The internal resistance will be in series with the load.
Circuit current will be 5 +

21 Voc 21 V VT RL 2
I = =3A
7
Terminal voltage = I RL
= 32=6V

4. (d)
By inspection,

15
i = = 3.75 A
4
and the current through 3 resistor is,

15
i = =5A
3

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 Electrical Engineering | Test 1 13

is 1

i i

15 V + 4 i 3

Applying KCL at node (1), we get,

is + i = i + i

i is
= 1+
i i
As is cant be determined with the given data, also cant be determined.

5. (b)
The given circuit can be reduced as
R1 = 2

+ v
+ Req = [(5 + 1) 4 2]
6v + 20 V
= 1.09

By applying KVL, we get,

6v + v + 20 = 0
or, 5v = 20
or, v = 4V
Power loss in 2 resistance is
v2 42
PR = = W=8W
1 R1 2

6. (d)
Given, I = 25 mA
Isc = 50 mA
V = 0.5 V

Isc Req V R

Req
I = R + R Isc
eq

Req
25 = 50
R + Req
50
or 1 = R
25 Req

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14 ESE 2018 Prelims Exam Classroom Test Series

or Req = R
V = IR
0.5 V = 25 mA R

0.5
or R = k = 20
25
Req = 20

7. (d)
Let 1 = primary coil flux
12 = mutual flux
where 12 = K 1 = 0.5 1 = 0.7

0.7 7
1 = = = 1.4 Wb
0.5 5
The primary coil inductance,
7
250
L1 =
N 1
= 5 = 25 = 5 H
I1 70 5

8. (c)
A

3
1A 2 6 4A
+ 6V

2 2

+
4V 2V

B
The given circuit can be reduced as,
A
A
A

2A 3 6 3A 1
1A 2 4A 1 A

3V 2

1 2V
2A 2 2 1A B
1 1A 1V

B
B B

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 Electrical Engineering | Test 1 15

1A 2

9. (c)
Redrawing the circuit, we get,
R
R

R R R/2
R R

A B R/2 R R/2
R/2 R R/2
R R R
A B
A B

R 3
Req = 3 R = R
2 5
3
For R = 20 , Req = (20) = 12
5

10. (b)

1
0 =
LeqC

Here, Leq = L1 + L2 2M
= 1+54=2H
C = 2F
1 1
0 = = = 0.5 rad/sec
22 2
11. (c)
Under resonance
XL = XC
The current flowing through the inductor is equal to the current flowing through the capacitor.
V V
I = =
X L 2fL
1
where, f =
2 LC
V 2 LC
I = =V C
2L L

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16 ESE 2018 Prelims Exam Classroom Test Series

12. (c)
According to the question,
Vs = I (Rs + RL )
Vs = 4(Rs + 5) ...(i)
Vs = 2(Rs + 20) ...(ii)
By solving equation (i) and (ii), we get,
Vs = 60 V
and Rs = 10
For maximum power transfer,
Rs = RL
Vs2 602
Pmax = = = 90 W
4RL 4 10

13. (d)

Resonant frequency
Bandwidth =
Quality factor
For parallel RLC circuit,
C
Q = R
L
1
and 0 =
LC
1 L
BW =
R LC C
1
BW = BW is independent of L
RC

14. (c)
The impedance matrix is given by,

V1 j L1 j M I1
V = j M j L2 I2
2
Here L1 = 3 H, L2 = 8 H, and M = 2 H
From figure (B),
Leq = L1 + L2 + 2M
= 3+8+4
= 15 H

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 Electrical Engineering | Test 1 17

15. (c)

Condition Condition
Parameters for for
symmetrical reciprocal
Z-parameter Z11 = Z22 Z12 = Z21

Y-parameter Y11 = Y22 Y12 = Y21

h-parameter h = 1 h12 = h21

ABCD parameter A=D A = 1

16. (a)
Let, v be the reference vector, it is clearly observed from the question that, i lags v by 30.

Vm 18
Also, = =9
Im 2

Z = R 2 + (L)2
9 2 = R 2 + (L ) 2 ...(i)
L 1
= tan30 =
R 3
R = 3 (L) ...(ii)

( )
2
From equation (i) and (ii), 92 = 3 L + (L)2
2(L) = 9
9 9
L = = = 0.5 H = 9 rad/sec
2 29

17. (c)
V 2 100 100
R = = = 1k
P 10
V 100
IR = = = 0.1 A
R 1000

I = IR2 + IC2

0.3 = (0.1)2 + ( IC )2

1 1
or, IC = (0.3)2 (0.1)2 = 32 12 = 2 2
10 10
IC = 0.2828

IC 0.2828
C = =
2f V 2 50 100

0.2828
= 9 F
314 100

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18 ESE 2018 Prelims Exam Classroom Test Series

18. (b)
VA

I
2
4 3A
12 V +
24 V
+

By applying KCL at node A,

12 VA 24 VA
+3+ = 0
4 2
12 VA + 12 + 48 2VA = 0
3VA = 72
VA = 24 V
12 VA 12
I = = = 3 A
4 4
19. (a)
The absence of any independent source leads to VTh = 0 V
Now, to calculate RTh a dc source Vdc is applied across the terminal A and B.
2i
1 2 A Idc

+
V 4 2 +
Vdc

i

V V
Here, Vdc V = 2i = 2 =
4 2

3
or Vdc = V
2
By applying KCL at node (2), we get,
Vdc V
+ = Idc
2 4
Vdc 2/3 Vdc
or Idc = +
2 4
2
Idc = Vdc
3
Vdc 3
or =
Idc 2

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 Electrical Engineering | Test 1 19

20. (d)
Given graph is a complete graph
the maximum number of possible trees = nn 2
where n = total number of nodes
n=4
Total number of trees = 4(4 2)
= 42 = 16

21. (c)
The connected graph is
1
a
5

c d
3
2
6
b
4

22. (c)
The internal impedance of the circuit is
Zin = 3 + j4 8 j = (3 4 j )
The open circuit voltage across RL
Voc = 500 Volts
As per the maximum power transfer theorem, for maximum power transfer,
or, RL = (3 4 j ) = 9 + 16 = 5
500 500
I = =
(3 j 4 + 5) 8 j4
500 500
I = = A
64 + 16 4 5
2
2 500
Pmax = I RL = 5
4 5
50 50 2500
= 5 = = 156.25 W
16 5 16

23. (b)
Considering the second node equation
i2 i4 + i5 i6 = 0
2 4 + 4 i6 = 0
i6 = 2 A

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20 ESE 2018 Prelims Exam Classroom Test Series

24. (a)
When the switch was opened

2 F 2 F
Ceq

2 F 2 F

Ceq = 2
22 8
= = 2 F
+ 2 4
2
When the switch get closed
A

2 F 2 F
Ceq

2 F 2 F

4 F 4 F 16
=
C eq = = 2 F
8 F 8

25. (b)
The time constant for an RC circuit is
= Ceq Req
2 4 8 4
Here, Req = (2 4 ) =
6
=
6
=
3
3 1 3
and Ceq = F= F
4 4
4 3
= = 1sec
3 4

26. (d)
The number of links = Total number of independent loops
Bn+1 = 3
B8+1 = 3
B = 10

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 Electrical Engineering | Test 1 21

27. (c)
2 2

i(t)
+
4t v(t) 2t
e 1H e

The current flowing through the inductor is

i(t) = e 4t + e 2t
Voltage across the inductor is
di d
v (t ) = L = 1 (e 4t + e 2t )
dt dt
= [4e 4t + 2e 2t ] V

28. (b)
By applying source transformation, we come to known that the circuit act as a parallel RLC circuit.

8 40 F 16 mH Is

C 40 1 8
Q = R =8 103 = 8 =
L 16 20 20
1 20 1
The damping factor, = = = = 1.25
2Q 8 16
2
20
> 1 Overdamped

29. (c)
The charging current equation for RL circuit is
V
i(t ) =
R
(
1 e t / u (t ) )
L
where, = = time constant
R
2
= = 0.1sec
20
100
i = (1 e t /0.1)u(t ) = 5(1 e 10 t )u (t ) A
20
di
= 50e 10 t u (t) A/s
dt
The rate of change of current at the instant just after closing the switch (t = 0+) is
di
(t = 0 + ) = 50 A/s
dt

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22 ESE 2018 Prelims Exam Classroom Test Series

30. (a)
Taking the circuit in Laplace domain, we get,
I(s)

2 2
s

1
+
s
s

1
s 1 1
I(s) = = 2 =
2 2
2 + + s s + 2s + 2 (s + 1) + 1
s
By taking inverse Laplace transform,
t
i(t ) = e sint u(t ) A

31. (b)
5I0
I1 2 I0 I2
+ +

V1 I1 I2 V2

By applying KVL in the first loop, we get,

V1 = I1 2 + 0 (I1 + I2)
V1 = 2I1 = 2I0
V1
I1 = ...(i)
2
5
Also, I2 = 5I0 = V1 ...(ii)
2
From equations (i) and (ii),
1
0
Y11 Y12 2 1 1 0
[Y ] = = J = J
Y21 Y22 5 0 2 5 0
2

32. (c)
V1
1 2
I1 +

+
V1 1
I1 2 V2
(1 + )I1

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 Electrical Engineering | Test 1 23

In loop (1), by applying KVL, we get,

V1 = I1 + 2(1 + )I1 + V1 + 2(1 + )I1
or (1 )V1 = (5 + 4)I1

(5 + 4)
or V1 = I
(1 ) 1
Also, V2 = (1 + )I1 2 = 2(1 + )I1
V2 2(1 + )(1 )
=
V1 (5 + 4)
3
= 4 = 6
2
3
2 1
V2 2 (1 ) = (1 )
So, =
V1 (5 6)

1
(1 ) =
2
1 3
or = +1=
2 2
33. (b)
I1 j I2
+ +

V1 1 V2

Using KVL,
V1 = I1 + I2
V2 = (1 j )I2 + I1
Finding transmission parameters, we get,
V1
A = =1
V2 I2 = 0

V1
B = = j
I2 V
2 =0

I1
C = = 1S
V2 I2 = 0

I1
D = = (1 j )
I2 V
2 =0

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24 ESE 2018 Prelims Exam Classroom Test Series

Using parameter conversion, we get,

1 1 1
h21 = = = = (1 + j )1
D (1 j ) 1 + j
1
Z12 = = =1
C 1
D (1 j )
Y11 = = = (1 + j )
B j

34. (c)
Elements should be also bilateral to satisfy the reciprocity.

37. (c)

di
v = L
dt
Thus, the potential drop across the inductor is proportional to the rate of change of the current.

Section B : Digital Electronics + Microprocessors

38. (c)
(64)8 = 6 8 + 4 = (52)10
(64)10 + (52)10 = (12)10
thus X = 12

39. (d)
AND-NOT NAND (Universal gate)
NOTOR NOR (Universal gate)

40. (d)
The circuit can be redrawn as,

B
F

C
A
which can be redrawn as,
A+B

B B+C A +B+C
A+ B+C = A B C

C
A C+A

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 Electrical Engineering | Test 1 25

41. (d)
An n-bit ring counter can count only n-pulses whereas an n-bit ripple counter can count 2n pulses. In a ring
counter we do not require a decoder circuit because we can read the count by simply noting which flip-flop
is set.

42. (c)
(45)16 = 4 16 + 5 = (69)10
(45)10 (69)10 = (24)10
Now, (+24)10 = (011000)2
Thus, (24)10 = (101000)2

43. (d)
(110011)2 = (51)10
= (63)8 = (33)16 = (303)4

44. (d)

F = ABCD + ABCD + ABCD + ABCD

= ABC (D + D ) + ABC (D + D )

= AB(C + C )
= AB

45. (c)
CD
AB 00 01 11 10

00 1 0 1 0

01 1 0 1 1

11 1 0 0 0

10 1 0 0 0

thus, F = ABC + ACD + CD

but F can also be expressed as
F = ABC + ACD + CD (A + A)

= ABC + ACD + ACD + ACD

46. (b)
MOD 78 = MOD(13) MOD (6)

47. (b)
f = w + w x + x yz
By solving,
f = w + x yz
So there is no need of Gate-2.

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26 ESE 2018 Prelims Exam Classroom Test Series

48. (a)
1 x = x
So, to complement the higher significant nibble of the accumulator, we can use XRI F0H.

49. (c)
F ( A,B,C) = m(0, 4, 6, 7)
BC
A 00 01 11 10

0 1 0 0 0

1 1 0 1 1

F ( A,B,C) = AB + BC
Thus logic circuit 2 and 3 can be used to implement this function.

50. (c)
The circuit can be redrawn as,
C B+C A(B + C)
B

A F

BC AB C

Thus, F = A(B + C ) + ABC

= AB + AC + ABC
= B(A + AC ) + AC
= B(A + C) + AC
= AB + AC + BC

51. (a)
F = x1 y1( x0 y 0 ) + x1 y1( x0 y 0 ) + x1 y1(x0 y 0 ) + x1 y1( x0 y 0 )
= x0 y 0 ( x1 y 1 + x1 y 1) + ( x0 y 0 )( x1 y 1 + x1 y 1)
= x0 y 0 ( x1 e y 1) + x0 y 0 ( x1 y1)
= x0 y 0 ( x1 y1) + ( x0 y 0 )( x1 y1)
= x1 y 1 x0 y 0

52. (b)
The Master-Slave configuration is used to eliminate Race-around condition.

53. (d)
A MUX is used as a data selector. It can also be used in data acquisition devices where the input data is
to be received from many sources. It is also used as parallel to serial converter.

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 Electrical Engineering | Test 1 27

54. (b)
Given the initial state to be zero, thus the state sequence table can be given as

Qn J = (1) K = (Qn ) Qn +1
0 1 1 1
1 1 0 1
1 1 0 1
M M M M

55. (d)
T Qn Qn + 1
0 0 0
0 1 1
1 0 1
1 1 0

Qn + 1 = TQn + T Qn

56. (c)
MVI B, 10H 2 Byte instruction (1000H, 1001H)
DCR B 1 Byte instruction (1002H)
JNZ 1000H 3 Byte instruction (1003H, 1004H, 1005H)
RET 1 Byte instruction (1006H)
So, the machine code of RET will be stored at 1006H.

57. (c)
STAX Rp, LDAX Rp instructions should be used only with BC and DE register pairs.
In option (c), LDAX is used with HL pair, which is invalid.

59. (c)
MVI H, 5DH ; H = 5DH
MVI L, 6BH ; L = 6BH
MOV A, H ; A = 5DH
ADD L ; A = 0101 1101
L = 0110 1011
1111 111
A = 1100 1000 AC = 1 and CY = 0

60. (b)
Y = A + AB + ABC
= A + AB
= A +B
= AB

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28 ESE 2018 Prelims Exam Classroom Test Series

61. (b)
TRAP Both Level and Edge - sensitive
RST 7.5 Edge - sensitive
RST 6.5 Level - sensitive
RST 5.5 Level - sensitive

62. (d)

63. (c)
ORI 00H does not alter the content of accumulator.
After execution of ORA, ORI instructions, CY and AC flags will be cleared automatically.

64. (c)
x y xy = x (y x y )
(
= x y ( xy ) + y ( xy ) )
= x ( y ( x + y ) + y ( xy ))
= x xy
= x ( x y ) + x( x + y )
= x + xy + x y
= x + xy = x + y

65. (c)
The given circuit can work as a 1-bit Johnson counter with MOD = 2n = 2(1) = 2.
fclock 50 103
So, fout = =
2 2
= 25 kHz

67. (b)
F = (A + C )(B + C )(A + B)

= (A + C )(A + B) (By consensus theorem)

68. (a)
16 5 16 address location with 5 bits in each location

69. (b)
CD
AB 00 01 11 10

00 1 1

01 1

11 1

10 1

Y = AB + CD

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 Electrical Engineering | Test 1 29

70. (d)
XTHL is used to exchange the contents of HL pair with Top of stack, it needs 16 T-states.

71. (a)
VFS
100 < (0.4) VFS
2n 1
1
n < 0.004
2 1
2n 1 > 250
n (minimum) = 8

72. (a)
X1 = Y1
X2 = Y1 Y2

73. (d)
A universal gate is a gate which can implement all Boolean functions without need to use any other type of
gate. The NAND and NOR gates are universal gates and XOR is not a universal gate because it is not
possible to implement all Boolean functions using XOR gates only.

74. (d)
For RLC and RRC instructions, final result does not depend on initial state of CY.
For RAL and RAR instructions, final result depends on initial state of CY.
RLC, RRC, RAL, RAR all these instructions will affect CY.

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