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3, MARCH 1998
I. INTRODUCTION
(2)
Fig. 5. The proposed voltage doubler. where is the energy delivered to load
(3)
(10)
where
period of the clock;
total switching time including nonoverlaping interval.
is directly linked with the RC constant of the circuit
Fig. 8. Power efficiency versus VOUT for f =1 MHz, C = 100 pF, and
so a first-order low-pass term must be added to [5] VIN = 1:5 V showing the importance of capacitors to obtain a small VOUT
drop with good efficiency.
(11)
(12)
If
(13)
Fig. 12. Normal high efficiency voltage doubler (M5 and M6 are not
represented to simplify the schematic).
B. Nonoverlapping Switching
At high frequency (above 1 MHz), the dynamic losses
become important, and to make things work properly we must
avoid overlap in the clock signals of the two series switches
M3 and M4 (Fig. 10). This is done by adding asynchronous
delays between the two gate signals (Fig. 11). The same can
be applied to the transistors M1, M2.
C. Conductance Improvement
Up to now the gate signals of the two series switches (M3,
M4) were between and 2 (Fig. 10). The conductance
Fig. 14. Low-voltage scheme of the high efficiency voltage doubler (M5 and
is greatly improved if these signals can range between 0 and M6 are not represented to simplify the schematic).
2 (Fig. 11). This is very important for under 1.5 V.
Assuming a of 1.5 V and a of 1 V, the ON voltage
is 0.5 V in the proposed schematic. Driving these switches 3 , this last technique must be restricted to input voltage
between 0 and 2 boosts the ON voltage to 2 V, thus below one third of the maximum voltage specified in the
dividing by four the ON resistance. The entire charge-pump process.
circuit is represented by a block schematic in Fig. 12.
A simple and well-known circuit that can be used to
implement the function above is shown in Fig. 13. Its principle V. SIMULATED RESULTS
is based on the voltage mirror (M3, M4). They generate a To illustrate the improvement achievable with bulk switch-
command signal to an inverter (M5, M6). The whole circuit ing, we show two simulations beginning at start up. Once the
is supplied by the output voltage of the charge pump. final voltage is reached (twice 1.5 V), the addition and removal
For low input voltages ( mV), M1 and of a capacitive load occurs twice. First, the charge-pump circuit
M2 also have a low ON voltage. The efficiency and the is simulated without M5, M6 (Fig. 15) and compared with
overall functionality may be significantly reduced by this. To the bulk-switched version (Fig. 16). The high current peaks
overcome this limitation, the gates of M1 and M2 (Fig. 12) observed may reduce the power efficiency for capacitive load
should be driven between and 3 . This could be and also reduce the circuits charge-up speed. Of course, if
achieved by driving the gates of M1 and M2 from an auxiliary a capacitor big enough to handle the load were added at the
charge pump (Fig. 1) with 02 clock signals. These clock output, the problem would not appear, but then the charge-up
signals could come from the level shifters used to drive M3 speed would be greatly reduced. The cost in complexity and
and M4. In practice, the cross coupling of M1 and M2 shown the added area of two minimum-sized transistors like M5, M6
in Fig. 12 is necessary to start up the charge pump. A simple is very small for all the advantages they bring.
scheme which improves the efficiency and guarantees the start- For measurement access reasons, we were not able to
up is shown in Fig. 14. Important remark: since we generate provide the measured versions of Figs. 15 and 16.
414 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 3, MARCH 1998
Fig. 15. Simulation of the step-up without bulk switching showing the very
high current peaks flowing to the substrate due to the vertical bipolars.
Fig. 21. Power efficiency versus frequency showing the practical range of
the charge pump.
Fig. 19. Microphotograph of the voltage doubler in a 0.7-m CMOS digital
technology.
Fig. 22. Measured and theoretical source resistance versus frequency. Above
Fig. 20. Measured and theoretical power efficiency of the fully integrated
the cutoff frequency of the system, the source resistance reaches a minimum.
voltage doubler at 10 MHz.