What is VHDL

VHDL Example
Design Capture
VHDL Standards

Introduction to VHDL

Dr DC Hendry

January 2006

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

1 What is VHDL

2 VHDL Example

3 Design Capture

Level of Abstraction

Synthesis

4 VHDL Standards

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

What is VHDL

1 VHDL is similar to a programming language such as C or

Matlab.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

What is VHDL

1 VHDL is similar to a programming language such as C or

Matlab.
2 It describes digital logic rather than computer programs.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

What is VHDL

1 VHDL is similar to a programming language such as C or

Matlab.
2 It describes digital logic rather than computer programs.
3 A simulator can show the expected behaviour of the design
before building the real hardware.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

What is VHDL

1 VHDL is similar to a programming language such as C or

Matlab.
2 It describes digital logic rather than computer programs.
3 A simulator can show the expected behaviour of the design
before building the real hardware.
4 A computer program (called a synthesis tool) converts the
VHDL into a netlist (logic gates plus the interconnections
between).

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

What is VHDL

1 VHDL is similar to a programming language such as C or

Matlab.
2 It describes digital logic rather than computer programs.
3 A simulator can show the expected behaviour of the design
before building the real hardware.
4 A computer program (called a synthesis tool) converts the
VHDL into a netlist (logic gates plus the interconnections
between).
5 The VHDL program is entered into the computer with an
editor and stored in a file.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

History of VHDL

1 VHDL stands for Very high speed integrated circuit Hardware

Description Language.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

History of VHDL

1 VHDL stands for Very high speed integrated circuit Hardware

Description Language.
2 Original proposal for a standard arose from the US Star
Wars defense program.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

History of VHDL

1 VHDL stands for Very high speed integrated circuit Hardware

Description Language.
2 Original proposal for a standard arose from the US Star
Wars defense program.
3 Based on both US and European research efforts to produce
such a design language.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

History of VHDL

1 VHDL stands for Very high speed integrated circuit Hardware

Description Language.
2 Original proposal for a standard arose from the US Star
Wars defense program.
3 Based on both US and European research efforts to produce
such a design language.
4 Main competitor is Verilog, although new languages to replace
both VHDL and Verilog are now being considered.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Why do we need a standard?

1 Experience of real time programming languages in the DOD

and MOD.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Why do we need a standard?

1 Experience of real time programming languages in the DOD

and MOD.
2 Lack of standards led to nearly 1000 different languages in use,
with at times, new languages being invented for each project.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Why do we need a standard?

1 Experience of real time programming languages in the DOD

and MOD.
2 Lack of standards led to nearly 1000 different languages in use,
with at times, new languages being invented for each project.
3 Staff training was costly and time consuming.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Why do we need a standard?

1 Experience of real time programming languages in the DOD

and MOD.
2 Lack of standards led to nearly 1000 different languages in use,
with at times, new languages being invented for each project.
3 Staff training was costly and time consuming.
4 Code maintenance was very expensive. Estimated at $10 per
line of code at one time.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Why do we need a standard?

1 Experience of real time programming languages in the DOD

and MOD.
2 Lack of standards led to nearly 1000 different languages in use,
with at times, new languages being invented for each project.
3 Staff training was costly and time consuming.
4 Code maintenance was very expensive. Estimated at $10 per
line of code at one time.
5 VHDL syntax along similar lines to the defense industry
language ADA.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Advantages of a Standard.

1 Supported by a number of vendors, leading to competition in

price and features.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Advantages of a Standard.

1 Supported by a number of vendors, leading to competition in

price and features.
2 Additional tools from new companies become feasible.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Advantages of a Standard.

1 Supported by a number of vendors, leading to competition in

price and features.
2 Additional tools from new companies become feasible.
3 Pool of experienced staff (and inexperienced graduates)
available.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Advantages of a Standard.

1 Supported by a number of vendors, leading to competition in

price and features.
2 Additional tools from new companies become feasible.
3 Pool of experienced staff (and inexperienced graduates)
available.
4 New features are added by agreement in a standards
committee with world wide membership.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Advantages of a Standard.

1 Supported by a number of vendors, leading to competition in

price and features.
2 Additional tools from new companies become feasible.
3 Pool of experienced staff (and inexperienced graduates)
available.
4 New features are added by agreement in a standards
committee with world wide membership.
5 Experienced VHDL writers have wide range of opportunities.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Why use an HDL?

1 As the complexity of digital systems increased, it was clear

that design cost and time was a major limiting factor.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Why use an HDL?

1 As the complexity of digital systems increased, it was clear

that design cost and time was a major limiting factor.
2 Text based design, as opposed to schematics, had shown
promise in earlier languages.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Why use an HDL?

1 As the complexity of digital systems increased, it was clear

that design cost and time was a major limiting factor.
2 Text based design, as opposed to schematics, had shown
promise in earlier languages.
3 Using a text language with a synthesis tool promised very
efficient design, and process independence.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Why use an HDL?

1 As the complexity of digital systems increased, it was clear

that design cost and time was a major limiting factor.
2 Text based design, as opposed to schematics, had shown
promise in earlier languages.
3 Using a text language with a synthesis tool promised very
efficient design, and process independence.
4 Text based design is also to an extent self documenting.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Why use an HDL?

1 As the complexity of digital systems increased, it was clear

that design cost and time was a major limiting factor.
2 Text based design, as opposed to schematics, had shown
promise in earlier languages.
3 Using a text language with a synthesis tool promised very
efficient design, and process independence.
4 Text based design is also to an extent self documenting.
5 Allows design at a higher level of abstraction than design at
gate level.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

Example VHDL Design

The following code could be stored into a single file:

--*-VHDL-*--------
-- An example VHDL design.
entity example1 is
port(
a, b, c : in bit;
x, y : out bit);
end example1;

architecture rtl of example1 is

begin -- rtl
x <= (a and b) or c;
y <= a xor b xor c;
end rtl;
Dr DC Hendry Introduction to VHDL
 What is VHDL
VHDL Example
Design Capture
VHDL Standards

VHDL Comments

1 Comments in VHDL start with -- and continue to the end of

the line.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

VHDL Comments

1 Comments in VHDL start with -- and continue to the end of

the line.
2 Comments can start anywhere on a line.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

VHDL Comments

1 Comments in VHDL start with -- and continue to the end of

the line.
2 Comments can start anywhere on a line.
3 Comments can be placed within statements, as long as the
statement covers multiple lines.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

VHDL Comments

1 Comments in VHDL start with -- and continue to the end of

the line.
2 Comments can start anywhere on a line.
3 Comments can be placed within statements, as long as the
statement covers multiple lines.
4 The line with -*-VHDL-*- indicates to the text editor xemacs
that the file contains VHDL.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

The Entity Declaration

entity example1 is
port(
a, b, c : in bit;
x, y : out bit);
end example1;

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

The Entity Declaration

entity example1 is
port(
a, b, c : in bit;
x, y : out bit);
end example1;

1 The entity clause gives the design name, in this case,

example1.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

The Entity Declaration

entity example1 is
port(
a, b, c : in bit;
x, y : out bit);
end example1;

1 The entity clause gives the design name, in this case,

example1.
2 The port list gives the list of input and output pins, in this
case a, b and c are inputs, but x and y are outputs.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

The Entity Declaration

entity example1 is
port(
a, b, c : in bit;
x, y : out bit);
end example1;

1 The entity clause gives the design name, in this case,

example1.
2 The port list gives the list of input and output pins, in this
case a, b and c are inputs, but x and y are outputs.
3 The entity declaration must then end with the design name
repeated again.
Dr DC Hendry Introduction to VHDL
 What is VHDL
VHDL Example
Design Capture
VHDL Standards

An Architecture Body

architecture rtl of example1 is

begin -- rtl
x <= (a and b) or c;
y <= a xor b xor c;
end rtl;

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

An Architecture Body

architecture rtl of example1 is

begin -- rtl
x <= (a and b) or c;
y <= a xor b xor c;
end rtl;

1 For each design, such as example1, there may be more than

one architecture body, each with its own name, such as rtl
above.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

An Architecture Body

architecture rtl of example1 is

begin -- rtl
x <= (a and b) or c;
y <= a xor b xor c;
end rtl;

1 For each design, such as example1, there may be more than

one architecture body, each with its own name, such as rtl
above.
2 The architecture could be in a separate file to the entity
header.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

An Architecture Body

architecture rtl of example1 is

begin -- rtl
x <= (a and b) or c;
y <= a xor b xor c;
end rtl;

1 For each design, such as example1, there may be more than

one architecture body, each with its own name, such as rtl
above.
2 The architecture could be in a separate file to the entity
header.
3 The example above then contains two concurrent assignment
statements.
Dr DC Hendry Introduction to VHDL
 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

Design Capture

1 Design capture refers to the method used to enter a design

into the CAD tools.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

Design Capture

1 Design capture refers to the method used to enter a design

into the CAD tools.
2 The earliest tools required the designer to manually convert a
paper design into a text file describing the netlist.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

Design Capture

1 Design capture refers to the method used to enter a design

into the CAD tools.
2 The earliest tools required the designer to manually convert a
paper design into a text file describing the netlist.
3 Graphics programs permitting construction and modification
of schematics on a computer screen were then used.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

Design Capture

1 Design capture refers to the method used to enter a design

into the CAD tools.
2 The earliest tools required the designer to manually convert a
paper design into a text file describing the netlist.
3 Graphics programs permitting construction and modification
of schematics on a computer screen were then used.
4 Current logic designs easily exceed one million logic gates.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

Design Capture

1 Design capture refers to the method used to enter a design

into the CAD tools.
2 The earliest tools required the designer to manually convert a
paper design into a text file describing the netlist.
3 Graphics programs permitting construction and modification
of schematics on a computer screen were then used.
4 Current logic designs easily exceed one million logic gates.
5 To meet market demands (time to market especially) faster
design methods are needed.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

Abstraction
1 We use language such as low level design and high level
design.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

Abstraction
1 We use language such as low level design and high level
design.
2 High level design generally hides low level detail, eases
understanding, and is more efficient.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

Abstraction
1 We use language such as low level design and high level
design.
2 High level design generally hides low level detail, eases
understanding, and is more efficient.
3 An example of high level design is the statement: x + y
where x and y refer to say 16 bit numbers.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

Abstraction
1 We use language such as low level design and high level
design.
2 High level design generally hides low level detail, eases
understanding, and is more efficient.
3 An example of high level design is the statement: x + y
where x and y refer to say 16 bit numbers.
4 At low level we might describe the same operation at bit level
with statements such as:

ci = (xi ANDyi )OR(xi ANDci1 )OR(yi ANDci1 )

s i = xi yi c i

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

Abstraction
1 We use language such as low level design and high level
design.
2 High level design generally hides low level detail, eases
understanding, and is more efficient.
3 An example of high level design is the statement: x + y
where x and y refer to say 16 bit numbers.
4 At low level we might describe the same operation at bit level
with statements such as:

ci = (xi ANDyi )OR(xi ANDci1 )OR(yi ANDci1 )

s i = xi yi c i
5 The high level statement is easier to read, and most
importantly, faster and less error prone to write.
Dr DC Hendry Introduction to VHDL
 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

A Simple Design Flow:

A simple synthesis based design flow then consist of the following
steps:

1 Enter the high level VHDL source code using an editor such
as Xemacs with VHDL-mode.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

A Simple Design Flow:

A simple synthesis based design flow then consist of the following
steps:

1 Enter the high level VHDL source code using an editor such
as Xemacs with VHDL-mode.
2 Simulate the high level VHDL and correct any errors. This is
actually one of the more difficult and time consuming steps
for a large design.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

A Simple Design Flow:

A simple synthesis based design flow then consist of the following
steps:

1 Enter the high level VHDL source code using an editor such
as Xemacs with VHDL-mode.
2 Simulate the high level VHDL and correct any errors. This is
actually one of the more difficult and time consuming steps
for a large design.
3 Synthesise the high level VHDL to give a VHDL (or Verilog)
netlist.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

A Simple Design Flow:

A simple synthesis based design flow then consist of the following
steps:

1 Enter the high level VHDL source code using an editor such
as Xemacs with VHDL-mode.
2 Simulate the high level VHDL and correct any errors. This is
actually one of the more difficult and time consuming steps
for a large design.
3 Synthesise the high level VHDL to give a VHDL (or Verilog)
netlist.
4 Simulate the netlist. This simulation may include logic delays
which are more typical of the actual circuit, although there are
other means of verifying timing closure.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

A Simple Design Flow:

A simple synthesis based design flow then consist of the following
steps:

1 Enter the high level VHDL source code using an editor such
as Xemacs with VHDL-mode.
2 Simulate the high level VHDL and correct any errors. This is
actually one of the more difficult and time consuming steps
for a large design.
3 Synthesise the high level VHDL to give a VHDL (or Verilog)
netlist.
4 Simulate the netlist. This simulation may include logic delays
which are more typical of the actual circuit, although there are
other means of verifying timing closure.
5 Build it!
Dr DC Hendry Introduction to VHDL
 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

Relationship to Software Engineering

1 Given the similarity of VHDL to languages such as C or C++,

much of software engineering theory is applicable to VHDL.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

Relationship to Software Engineering

1 Given the similarity of VHDL to languages such as C or C++,

much of software engineering theory is applicable to VHDL.
2 Use techniques such a version management using systems
such as CVS (I use CVS to maintain these lectures).

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

Relationship to Software Engineering

1 Given the similarity of VHDL to languages such as C or C++,

much of software engineering theory is applicable to VHDL.
2 Use techniques such a version management using systems
such as CVS (I use CVS to maintain these lectures).
3 VHDL systems generate a plethora of files, use a file naming
system to track files (youll see an example in the laboratory).

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

Relationship to Software Engineering

1 Given the similarity of VHDL to languages such as C or C++,

much of software engineering theory is applicable to VHDL.
2 Use techniques such a version management using systems
such as CVS (I use CVS to maintain these lectures).
3 VHDL systems generate a plethora of files, use a file naming
system to track files (youll see an example in the laboratory).
4 Specification ....

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example Level of Abstraction
Design Capture Synthesis
VHDL Standards

Relationship to Software Engineering

1 Given the similarity of VHDL to languages such as C or C++,

much of software engineering theory is applicable to VHDL.
2 Use techniques such a version management using systems
such as CVS (I use CVS to maintain these lectures).
3 VHDL systems generate a plethora of files, use a file naming
system to track files (youll see an example in the laboratory).
4 Specification ....
5 Write your code to be maintainable, use the style that I use,
or in a company, a style may be imposed.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

VHDL Standards

1 The original specification of the VHDL language was further

developed before becoming a standard.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

VHDL Standards

1 The original specification of the VHDL language was further

developed before becoming a standard.
2 The first standard was accepted in 1987 by IEEE, and that
standard is generally referred to as VHDL-87.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

VHDL Standards

1 The original specification of the VHDL language was further

developed before becoming a standard.
2 The first standard was accepted in 1987 by IEEE, and that
standard is generally referred to as VHDL-87.
3 This standard was upgraded and accepted by IEEE in 1993,
now generally referred to as VHDL-93.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

VHDL Standards

1 The original specification of the VHDL language was further

developed before becoming a standard.
2 The first standard was accepted in 1987 by IEEE, and that
standard is generally referred to as VHDL-87.
3 This standard was upgraded and accepted by IEEE in 1993,
now generally referred to as VHDL-93.
4 Further updates to the standard are imminent.

Dr DC Hendry Introduction to VHDL

 What is VHDL
VHDL Example
Design Capture
VHDL Standards

VHDL Standards

1 The original specification of the VHDL language was further

developed before becoming a standard.
2 The first standard was accepted in 1987 by IEEE, and that
standard is generally referred to as VHDL-87.
3 This standard was upgraded and accepted by IEEE in 1993,
now generally referred to as VHDL-93.
4 Further updates to the standard are imminent.
5 The majority of tools assume one standard (often VHDL-87)
and need an option to accept another standard.

Dr DC Hendry Introduction to VHDL