Proprietary

& Confidential C

65nm Signoff

2009 TSMC, Ltd

Design and Technology Platform

2009 TSMC, Ltd.
 Contents
Proprietary
& Confidential C

z Signal EM Flow
z Power Grid Sign-off
z Timing Closure & Sign-off
z Dummy filling flow & Timing fixing
z Others

2009 TSMC, Ltd

DTP/ P. 2
2009 TSMC, Ltd.
 Signal EM Analysis
Proprietary
& Confidential C

z Peak/Avg./RMS current
z AstroRail or TSMC utility (Ref. Flow 4.0/5.0)

2009 TSMC, Ltd

DTP/ P. 3
2009 TSMC, Ltd.
 Proprietary
& Confidential C

Signal EM Analysis Procedure

1. The temperature for the signal EM analysis: 125C.

2. The RC corner for the RC extraction: Cworst in
125C.
3. The power consumption is calculated in the LT
corner, or the ML corner.
4. Set the reasonable switching activity in the signal
EM analysis.

2009 TSMC, Ltd

DTP/ P. 4
2009 TSMC, Ltd.
 Power Integrity
Proprietary
& Confidential C

z Power grid signed-off in three modes

Static IR drop
Average power IR drop < 5% VDD+VSS (wire-bond) 3% ( Flip chip)
Dynamic IR drop
4-5X Static IR < 15% VDD + VSS
Dcap insertion
Scan Peak IR around clock-edge < 30% VDD
Peak power usually around clock-edge
Seen many chips failing even in scan-mode
Analyzing IR drop during small timing window when flops are
switching

z Power reductions
Leakage: Multi-Vt by default
Dynamic: RTL clock gating is highly recommended
Comprehensive power approaches for portable device
2009 TSMC, Ltd

DTP/ P. 5
2009 TSMC, Ltd.
 Proprietary
& Confidential C

Power Integrity Procedure

1. The temperature for the power EM analysis: 125C.

2. The RC corner for the RC extraction: CWorst in
125C.
3. The power consumption is calculated in the LT
corner, -40C/110% VDD/FF, or the ML corner.
4. Set the reasonable toggle rate to calculate the
average power consumption.
5. The EM spec is tight in 125C, the current is large
in the LT or ML corner, and the power EM
criterion in such condition should be most robust.

2009 TSMC, Ltd

DTP/ P. 6
2009 TSMC, Ltd.
 Proprietary
& Confidential C

Scan Peak Power

z The most of flops are switching at almost the same

time Current

CLK
Many flops switching

Timing window (t)

2009 TSMC, Ltd

Clock skew + Average CK-Q delay + Average Transition/2
DTP/ P. 7
2009 TSMC, Ltd.
 Scan Power Analysis
Proprietary
& Confidential C

ATPG Test Patterns

Peak Switching Cycle
Search
IR Sensitivity of Each Flop
Flop Transition at
Peak Switching Cycle

Peak Power Calculation

SDF & SDC

Dynamic IR Analysis

Peak IR Report &

Hot Spot Colormap
2009 TSMC, Ltd

DTP/ P. 8
2009 TSMC, Ltd.
 Static vs. Dynamic IR-drop Proprietary
& Confidential C

Current envelope

Average current
Peak current

nT (n+1)T (n+2)T

Wire sizing can be used to control static IR-drop

Critical de-cap provides immediate spike filtering

2009 TSMC, Ltd

DTP/ P. 9
2009 TSMC, Ltd.
 65nm PI sign off criteria Proprietary
& Confidential C

Technology node: 65nm PI sign off criteria

recommended
Package Corner

Wirebond Flipchip

w/o w/ w/o w/
pkg pkg pkg pkg

FF/SS
Static 5% 5% 3% 3%
VDD: TT

FF/SS
VCD 10% 15-18% 8-10% 13-15%
VDD: TT
Function
FF/SS
Vectorless 10% 15-18% 8-10% 13-15%
VDD: TT
Dynamic
FF, TT
VCD 10% 15-18% 8-10% 13-15%
VDD: TT
Scan
FF, TT
Vectorless 10% 15-18% 15-18% 13-15%
VDD: TT

2009 TSMC, Ltd IR limit : VDD+GND

DTP/ P. 10
2009 TSMC, Ltd.
 Timing Closure Proprietary
& Confidential C

Synthesis
Synthesis
(By
(Bycustomer
customerwith
with10% CTS/CTO Signal
setup
10% CTS/CTO SignalEM
EM
setuptime
timemargin
margin&& (Double
(Doublewidth
width++spacing
CWLM)
CWLM) ++via)
spacing Fixing
Fixing
via)

TD
TDPlacement Detail
Placement
(Netlist Detailrouting
routing Decap
Decap
(Netlistw/w/hold
holdaware
aware (Decap pre-insert, Xtalk
buffer insertion +setup (Decap pre-insert, Xtalk
prevention, Insertion
Insertion
buffer insertion +setup
time prevention,Ant.
Ant.fixing)
fixing)
timedriven)
driven)

Trial RC
RCExtraction Double
DoubleVia
TrialCTS
CTS Extraction Via
(setup/hold
(Derive
(Derivesetup
setuptime
time (setup/holdfixing)
fixing)
requirement for ICG)
requirement for ICG)

Setup/Hold Dummy
Setup/Hold DummyFill
Fill
Setup
Setuptime
timeOpt.
Opt. fixing
fixing (setup/hold
(setup/holdfixing)
fixing)
(All
(Allsign-off
sign-offmodes)
modes)

Xtalk
XtalkFixing
Fixing STA
STASign-off
Sign-off
Power
PowerOpt.
Opt. (Glitch
(Glitch&&setup/hold
setup/hold
(Multi-Vt
(Multi-Vtswap)
swap) fixing)
fixing)
2009 TSMC, Ltd

DTP/ P. 11
2009 TSMC, Ltd.
 Proprietary
& Confidential C

Timing Sign-off

z Timing closure taking all kinds of following

effects into account
Multi-mode STA
Multiple Device & RC Corners
WC, WCL, BC or LT (-40C)
Cworst, Cbest (RCworst, RCbest, RCtypical)

OCV, Hold margin

Crosstalk
DFM Dummy metals, Dummy Vias

2009 TSMC, Ltd

DTP/ P. 12
2009 TSMC, Ltd.
 Proprietary
& Confidential C

OCV

z OCV On Chip Variation

2009 TSMC, Ltd

DTP/ P. 13
2009 TSMC, Ltd.
 Proprietary
& Confidential C

Timing Sign-off Recommendation

z Clock jitter is not included

WC + WCL + BC or LT + Max. Setup Hold

OCV
Cworst Cworst Cbest/Cworst transition margin margin

Setup/ Setup/ WC: 5%

65nm hold 0.6ns* 0 50ps
hold hold BC:10%

*Max transition applied at WC corner.

*Over constraint is recommended at APR stage.
**Typical number showed here:
- OCV and Hold margin design dependant: transition, cell types, IR-drop
**Corner shown here:
- It is the basis. Customer should add more corners based on product application.
2009 TSMC, Ltd

DTP/ P. 14
2009 TSMC, Ltd.
 Proprietary
& Confidential C

Dummy filling flow & Timing Fixing

APR RC
APR RCextraction
extraction

Add
AddExclusive
Exclusivelayer
layer
atatclock nets
clock nets
STA
STA

GDS
Timing
violations
Calibre
Calibre

ECO
ECO
Dummy
GDS
2009 TSMC, Ltd

DTP/ P. 15
2009 TSMC, Ltd.

(Fi i
 Proprietary
& Confidential C

Dummy Fill Guidelines

z In a cell-based design area, its recommended to use

filler cell with DPO/DOD for empty area (please refer
TSMC N90 standard cell library).
z Its recommended to use TSMC fill utility for macro block
and chip top level for final GDSII to guarantee global
uniformity.
z If using TSMC fill utility for DM and DOD, low densities
violations could be waived by TSMC PE. Otherwise, all
densities rules should be met.
z Do dummy fill in a bottom-up approach.
Macro block meet rules and timing first, then chip level.

2009 TSMC, Ltd

DTP/ P. 16
2009 TSMC, Ltd.
 Proprietary

Macro IP Dummy Fill Timing Flow & Confidential C

N90 Dummy Mx DMx Make dummy top cell name

utility GDSII the same as
Dummy IP top cell for StarRC-XT
GDS Merge
GDSII
N90 Dummy DPO, DOD
PO,OD utility GDSII

Original IP Final IP
GDS Merge
GDSII GDSII

Milkyway Database

LVS/LPE by LPE RCX by RCX Post-layout

Hercules Netlist Star-RCXT Netlist Simulation
(device) (device+RC) *mky.gds.map
OD 6 1
poly 17 1
* Star-RCXT command file
metal1 31 1
METAL_FILL_GDS_FILE: dummy.gds
metal2 32 1
GDS_LAYER_MAP_FILE: mky.gds.map

METAL_FILL_POLYGON_HANDLING: FLOAT
metal1 31 7
2009 TSMC, Ltd metal2 32 7
DTP/ P. 17
2009 TSMC, Ltd.
 Proprietary

Top (Digital) Dummy Fill Timing Flow & Confidential C

N90 Dummy
Mx DMx Make dummy top cell name
utility GDSII the same as
Dummy chip top cell for StarRC-XT
Chip GDS Merge
GDSII GDSII
N90 Dummy DPO, DOD
PO,OD utility GDSII

Final chip
GDS Merge
GDSII

P&R RCX by SPEF w/

Sign-off STA
Milkyway Star-RCXT dummy
Database impact
*mky.gds.map

ECO OD 6 1
poly 17 1
metal1 31 1
metal2 32 1
* Star-RCXT command file

METAL_FILL_GDS_FILE: dummy.gds
metal1 31 7
GDS_LAYER_MAP_FILE: mky.gds.map
metal2 32 7
2009 TSMC, Ltd METAL_FILL_POLYGON_HANDLING: FLOAT

DTP/ P. 18
2009 TSMC, Ltd.
 Others: High-Speed Clocks
Proprietary
& Confidential C

Top-view

M3/M5

M2/M4
M4

End-view

VIA34 Clock net

M3 M3
Clock Net

2009 TSMC, Ltd

Shielding Net
DTP/ P. 19
2009 TSMC, Ltd.
 Signoff Task vs. EDA Tool Proprietary

Task EDA Tool Major Role & Confidential C

ATPG Tmax/fastscan Vector generation/simulation

Floor plan Astro/SOC encounter Floor plan environment

Placement/CTS/Route Astro/SOC encounter Placement/CTS/Route tool

Design tool SI Celtic Xtalk analysis
RC extraction StarRC RC extraction

Netlist Handoff Spyglass & Prime Time Sanity Check

LEC ( Verplex ) LEC formal validation

Static IR Voltage Storm Static IR drop analysis

Dynamic IR RedHawk Dynamic IR drop analysis

Power EM Voltage Storm Power Ring reliability issue

Signal EM Astro/CISD utility Signal wire reliability issue

Signoff
STA w/ Incr. SDF Prime Time Static timing analysis
Redundant via insertion Calibre/Laker/Virtuoso Yield improvement
Dummy metal insertion Calibre/Laker/Virtuoso Yield improvement
Antenna Calibre/Hermcules Antenna effect check
2009 TSMC, Ltd DRC/LVS/ERC Calibre/Hercules TSMC design rule checks
DTP/ P. 20
2009 TSMC, Ltd.