DIRECTIONAL RELAYING ALGORITHM FOR SERIES

COMPENSATED LINE

Report submitted to
National Institute of Technology, Agartala
for the award of the degree of
Bachelor of Technology

By
BIRRU JEEVAN KUMAR
(13UEE019)

Under the Guidance of

Dr. Biman Saha Roy

Associate Professor, EE Department, NIT Agartala, India

ELECTRICAL ENGINEERING DEPARTMENT

NATIONAL INSTITUTE OF TECHNOLOGY AGARTALA
April , 2017

1
 REPORT APPROVAL FOR B.TECH
This report entitled Directional Relaying Algorithm for Series Compensated Line,
by Birru Jeevan Kumar (13UEE019), is approved for the award of Bachelor of
Technology in Electrical Engineering.

Examiners
________________________

________________________

________________________

Supervisor(s)

Dr. Ajoy Kumar Chakraborty

(Head of the Department) Assosiate Professor

Dr. Biman Kumar Saha Roy

(Project Supervisor)
Assistant Professor

Date:
Place: NIT, Agartala

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 CERTIFICATE

It is certified that the work contained in the report titled Directional Relaying Algorithm for Series
Compensated Line, by Birru Jeevan Kumar (13UEE019), has been carried out under my supervision and
this work has not been submitted elsewhere for a degree.

Dr. Biman Saha Roy Dr. Ajay Kumar Chakraborty

(Project Supervisor) (Head of the Department)
Assistant Professor Assistant Professor
Electrical Engineering Department Electrical Engineering Department
NIT Agartala NIT Agartala

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 Acknowledgement

I would like to take this opportunity to express my deep sense of gratitude to all who helped me directly
or indirectly during this project work.
Firstly, I would like to thank my supervisor, Dr. Biman Saha Roy, for being a great mentor and the best
advisor I could ever have. His advice, encouragement and critics are source of innovative ideas,
inspiration and causes behind the successful completion of this report. The confidence shown in me by
him was the biggest source of inspiration for me. It has been a privilege working with him from last
semester.
I am highly obliged to thank our B.Tech Project Coordinator Mr. Diptanu Das and all other faculty
members of Electrical Engineering Department for their support and encouragement. I also thank
Prof.(Dr.) Gopal Mugeraya, Director, NIT Agartala and Dr. Ajay Kumar Chakraborty, H.O.D, EE
Department for providing excellent facilities without which this work could have not achieve its quality
goal.

-BIRRU JEEVAN KUMAR

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 Contents

Acknowledgement -------------------------------------------------------------------------------------------------- 4

1 Introduction

1.1 Overview ------------------------------------------------------------------------------------------- 7

2 Theory

2.1 Series Compensation---------------------------------------------------------------------------- 8

2.2 Advantages of Series Compensation--------------------------------------------------------- 8

2.2.1 Increase in Power Transfer Capability------------------------------------------------ 9

2.2.2 Improvement in System Stability------------------------------------------------------ 10

2.2.3 Load Division Among Parallel Lines--------------------------------------------------- 11

2.2.4 Control of Voltage------------------------------------------------------------------------- 11

2.3 Problems Arising due to Series Compensation

2.3.1 Voltage Inversion------------------------------------------------------------------------- 11

2.3.2 Current Inversion------------------------------------------------------------------------- 12

3 Voltage and Current Inversion Problems

3.1 Voltage Inversion Condition------------------------------------------------------------------ 13

3.2 Current Inversion Condition------------------------------------------------------------------ 15

4 Proposed Technique

4.1 Proposed Technique--------------------------------------------------------------------------- 16

5
5 Case Study

5.1 PSCAD Simulation Model--------------------------------------------------------------------- 22

5.2 Simulation Results----------------------------------------------------------------------------- 23

6 Conclusion and Future Work

6.1 Conclusion---------------------------------------------------------------------------------------- 26

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 CHAPTER 1

Introduction

1.1 Overview

Series capacitor imposes problems to line production and other online decisions. The
directional relaying issues during voltage and current inversions in a series compensated line
are addressed in this project. Conventional directional relaying algorithm uses fault voltage and
current phases to derive the decisions and thus, finds its limitations at voltage or current
inversions. The project proposes fault direction estimation technique for series compensated
line using phase change in positive sequence voltage at fault. The technique is evaluated using
data simulated with EMTDC/PSCAD for series compensated line and the dynamic performance
of the algorithm is studied.

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 CHAPTER 2

Theory

2.1 Series Compensation

Series Compensation is the method of improving the system voltage by connecting a capacitor
in series with the transmission line. In other words, in series compensation, reactive power is
inserted in series with the transmission line for improving the impedance of the system. It
improves the power transfer capability of the line. It is mostly used in extra and ultra high
voltage line.

2.2 Advantages of Series Compensation

Series compensation has several advantages like it increases transmission capacity, improve
system stability, control voltage regulation and ensure proper load division among parallel
feeders. These advantages are discussed below,

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2.2.1 Increase in Power Transfer Capability
The power transfer over a line is given by

Where,
P1 power transferred per phase (W)
Vs sending end phase voltage (V)
Vr receiving end phase voltage

XL series inductive reactance

of the line phase angle
between Vs and Vr

If a capacitor having capacitance reactance Xc is connected in series with the line, the
reactance of the line is reduced from XL to (XL Xc). The power transfer is given by

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Where,

The factor k is known as a degree of compensation or compensation factor. Thus, per unit
compensation is given by the equation percentage

compensation is given by the equation

Where,
XL = total series inductive reactance of the line per phase
XC = capacitive reactance of the capacitor bank per phase
In practice, k lies between 0.4 and 0.7. For k = 0.5,

Thus, the power transfer is doubled by 50 % compensation.

2.2.2 Improvement in System Stability

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 For same power transfer and for the same value of sending and receiving end voltage, the
phase angle in the case of the series impedance line is less that for the uncompensated
line. The reduced value of gives higher stability.

2.2.3 Load Division among Parallel Line

Series capacitors are used in transmission systems for improving the load division between
parallel lines. When the new line with large power transfer capability is paralleled with an
already existing line, then it is difficult to load the new line without overloading the old line.
In such case the series compensation reduces the series reactance and proper load division
among parallel circuit can be done easily. Load division increases the power transfer
capability of the system and reduced losses.

2.2.4 Control of Voltage

In series capacitor, there is an automatic change in Var (reactive power) with the change in
load current. Thus, the drops in voltage levels due to sudden load variations are corrected
instantly.

2.3 Problems arising due to Series Compensation

Series Compensation imposes protection problems which depends on level of compensation,

its location and air gap arrangements. The different issues that are associated with protection
include voltage inversion and current inversion. For a Series Compensated system direction,
distance and fault location estimation algorithms are affected significantly leading to
malfunction of relays a different situation.

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 2.3.1 Voltage Inversion

Voltage inversion is a common problem in series-compensated lines. If a fault occurs beyond

the capacitor, the loop impedance may still be inductive, resulting in an inductive current (as
usually found for a line). The relay voltage, as the voltage across the capacitor and line segment,
may lag the current by nearly 90 . This is in contrast to the ordinary lines where fault current
lags the voltage by nearly 90 Thus, voltage inversion causes the relay to see a fault in the
protected line to be in a reverse direction. This directional relaying problem can be overcome
by detecting the inversion state and modifying the algorithm accordingly.

2.3.2 Current Inversion

The other problem with series-compensated line arises when the overall impedance of the fault
loop is capacitive. The fault current leads the system voltage by 90 but the relay voltage
(including the memory voltage) remains close in phase with system voltage. This current
inversion situation leads to improper decisions by the conventional directional relaying
algorithm. Practically, current inversion is difficult to obtain as at this point, the fault current
becomes substantially high. One solution to this problem can be obtained by using the
incremental voltage to current ratio technique, employing a current inversion detector.

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 CHAPTER 3

Voltage and Current Inversion Problems

3.1 Voltage Inversion Condition

Voltage inversion at a relay bus occurs when the total impedance between the voltage source
and the fault is inductive, but simultaneously, the impedance between the bus and the fault
point is capacitive. Voltage inversion causes the relay to see a fault on the protected line to be
in a reverse direction. For a mathematical formulation of voltage inversion, Fig. 1, which shows
the reactances of a series-compensated system, is considered (neglecting resistances)., Xs , Xc
and Xl and represent the source, series capacitor, and line reactances.

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 Figure 1: Reactance diagram of a series compensated network.

Assuming Xs and Xl to be inductive reactances, the fault current through the relay bus will be

(1)

(2)

The relay voltage in (2) will be inverted when the following conditions are satisfied

And
(3)

Figure 2(a)

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The phasor diagram for the voltage inversion case is shown in Fig. 2(a), where VRnor and VRinv are
the voltages at the forward fault situations in case they are without and with voltage inversion,
respectively. Thus, the directional relay will see the fault as if it is in the back of the relay
resulting in an incorrect decision.

3.2 Current Inversion Condition

For the forward fault in the line, if the current at the relay location leads the source voltage by
90 due to the large capacitive reactance in the fault loop and simultaneously the relay voltage
is in phase with the source voltage, current inversion occurs. At this condition, the conventional
directional relaying algorithm also fails to provide the correct decision.
The condition for current inversion is

Xc > Xl + Xs (4)

Figure 2(b)

The corresponding phasor diagram is shown in Fig. 2(b), where IRnor and IRinv are relay currents
without and with current inversion, respectively. The chance of current inversion is rare, as at
the above condition the fault current becomes so high. From (3) and (4), it is inferred that
voltage and current inversion do not occur for the same system configuration.

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 CHAPTER 4

Proposed Technique

4.1 Proposed Technique

There are several techniques available for directional relaying using current-voltage phasors
[15], [16] for the conventional transmission line. In case of series-compensated line, the
presence of capacitor changes the fault path impedance and, thus, the conventional directional
relaying algorithm finds limitation. A three-phase power system as shown in Fig. 4 is considered
with the relay located at bus-M. For any type of fault at point Fx in the system, the sequence
diagram can be represented as showninFig.5[17]. ZF, in this case, includes all other sequence
components (if any) which depend on the type of fault and the fault resistance part. It is to be
noted that fault current in this paper is considered as current observed during fault (i.e.,
including load current).

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 Figure 3: The Three phase power system.

Figure 4: Sequence diagram for fault at Fx.

The prefault steady current in the line can be expressed as

Ipre = (EL - EN )/Z1 (5)

where and are the source voltages and is the total line impedance between two sides.
For fault at Fx (upstream), the positive-sequence fault current (including load current) through
bus will be . For the left loop in the figure, the voltage equation becomes,

EL I1FL (ZSL1 + ZLF1 + ZF) + I1FN ZF = 0 (6)

For the other loop in Fig. 3 the relation will be.

-IFN ZX EN + I1FL ZF = 0
Where,
ZX = ZSN1 + ZMN1 + ZC + ZFM1 + ZF

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 Substituting the value of IFL from (7) in (6), the positive sequence current at bus M will be

Note that a and a1 are greater than 1 always for the system. For the fault at Fy, the
corresponding sequence diagram is shown in Fig. 4. For the fault at Fy (downstream), the
positive sequence fault current through bus M will be. IFL . For the left loop in the figure, the
voltage relation becomes,

EL IFL ZY + I1FN ZF = 0 (9)

Where, ZY = ZSL1 + ZLM1 + ZC + ZMF1 + ZF.

For the other loop in Fig. 6, the relation will be,

I1FL ZF I1FN (ZF + ZFN1 + ZSN1) EN = 0 (10)

Substituting the value of IFN from (9) in (10), the positive sequence current at bus M will be,

Where,

It is to be noted that b and b1 are greater than 1 always for the system.

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 Figure 5. Sequence diagram for fault at Fy.

Depending on the compensation level and other impedances in the system, the situation of
voltage or current inversion arises. Using the aforementioned relations and the discussion on
voltage/current inversion in Section II, phasor diagrams are obtained. The diagrams show
positive-sequence components of voltages and currents which are being applied in the
direction estimation technique and the diagrams are valid for any type of fault. When the series
capacitor is bypassed, the phasor diagram becomes similar to any ordinary line. For the two
fault situations (at Fx and Fy in Fig. 5), the phasor diagrams are shown in Fig. 2(a) and 2(b),
respectively, where the latter one is for the voltage inversion case. The voltage phasors VMpre
and VMfault refer to relay bus voltages at prefault and fault conditions, respectively. These
phasors are included in the diagram to see the relative position of current phasors. It is to be
noted that Fig. 5(a) is drawn using (8) where I1 is greater than IS, in general, as. Similarly, Fig.
5(b) is obtained by using (11) where is greater than in general as. It is observed that fault
currents in Fig. 5(a) and Fig. 5(b) remain in different regions with respect to the prefault current
Ipre. Thus, the direction of fault can be identified from the fault current phasor position with
respect to the prefault phasor regardless of whether the former lags or leads the latter. The
angle difference of fault and prefault positive-sequence current phasors for the upstream case
(Fx) is positive and for downstream (Fy), it is negative as observed from the phasor
diagrams. Thus, the algorithm does not require any detector for voltage inversion as necessary
in (13).

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 Figure 6. Phasor diagram showing different currents and voltages.

For the current inversion case, the phasor diagram is provided in Fig. 8 (for the fault at Fy). It is
found that at current inversion, the angle is also positive. Thus, a detection process is
required to identify the situation of current inversion. Normally, for a simple transmission line,
there is a drop in relay bus voltage during the fault. But at the current inversion case, due to the
different position of the fault current phasor, there is a rise in voltage which is evident from the
phasor diagram and corresponding waveforms of Fig. 3.

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 Figure 7. Phasor diagram showing currents and voltages only during inversion.

A change in the positive-sequence voltage magnitude-based feature (|V| magnitude

difference of the fault and prefault voltage) is used in the discrimination process. Voltage and
current inversions do not occur for the same system configuration as can be noticed from (3)
and (4). For all situations of series-compensated systems related to directional relaying, the
decision rule for relay at M can be framed as follows.
1) If is positive and |V| is negative, the fault is in upstream.
2) If is positive and |V| is positive, the fault is in downstream (current inversion).
3) If is negative the fault is in downstream.
is the phase angle difference between fault and prefault positive-sequence
current phasors set within - to and |V| is the relay bus positive-sequence voltage
magnitude difference for any fault and corresponding prefault situation. Thus, the decision
process needs to compute and if it is positive, then it checks whether |V is positive or
not. This check is required in case of current inversion otherwise, there is no need to
compute |V|. Thus, in a series-compensated line with only the voltage inversion problem,
the algorithm will not need the fault voltage component. After estimating the current and
voltage phasors, the algorithm computes the positive-sequence components followed by the
angle difference and change in voltage magnitude. That decision on fault direction is derived
using the rule as stated above.

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 CHAPTER 5

Case Study

5.1 PSCAD Simulation Model

As a case study, simulation is modeled on a 400KV, 50 Hz three phase system as shown in fig
6. In the system line 1 and line 2 segments are 250kms and 285km respectively.
The power system specications of gure 4.1 are:
The parameters of each line are:
Positive sequence impedance = 0.03293 + j 0.3184 /km.
Positive sequence capacitance = 0.00768 farad/km.

Zero sequence impedance = 0.2587 + j 1.1740 /km.

Zero sequence capacitance = 0.00768 farad/km.
For voltage inversion: Line 1 255km, Line 2 285km,
For current inversion Line 1 40km, Line 2 285 km.
The parameters of each source are:
Positive sequence impedance = 0.06979 + j1.99878 .
Zero Sequence impedance = 0.2094 + j0.59963 .

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Figure 8: A 400KV single line transmission using PSCAD Simulation

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 5.2 Simulation Results

We apply different types faults on both sides of the relay bus M with and without capacitor and
tabulate the positive sequence voltage and current magnitudes and phase angles.

Figure 9: Simulation result for three phase fault at Fx

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 Table 1: Results for three phase fault Voltage Inversion Case.

Table 2 Results for line to ground (AG) fault , Voltage inversion case

RESULTS FOR THREE PHASE FAULT , CURRENT INVERSION CASE.

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 CHAPTER 6

Conclusion and Future Work

6.1 Conclusion

The problem of voltage and current inversions on directional relaying in a series-compensated

line is addressed. A new solution is proposed using the phase change in positive-sequence
current and magnitude change in positive-sequence voltage. The method does not require a
voltage inversion detector. The current inversion problem is solved by detecting the condition
using the voltage magnitude change at that situation. With current inversion unlikely to occur,
the proposed directional relaying technique for the voltage inversion problem will be an
attractive option since it does not require the fault voltage component. The method is tested
for series-compensated lines with and without the presence of capacitor, variation in source
capacity, fault resistance, fault inception angle and other system conditions. The dynamic
performance of the algorithm is also evaluated.

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