JAIN UNIVERSITY

Declared as Deemed-to-be University u/s 3 of the UGC Act,1956

JU/HR/REC/002
Recent passport
APPLICATION NO. size color photograph

Note : Form must be complete in all respects. Use BLOCK LETTERS only. Attach your CV to this form with recent passport size color photograph.

INSTITUTION APPLIED School of Engineering & Technology

POST APPLIED Associate Professor

PERSONAL DETAILS

NAME OF THE APPLICANT

R A J E E V K A M A L

DATE OF BIRTH GENDER (TICK) NATIONALITY MOTHER TONGUE

0 2 0 2 1 9 8 5 INDIAN HINDI

DAY MONTH YEAR FEMALE MALE

RELIGION CASTE CATEGORY (TICK)
HINDU BRAHMIN

GENERAL SC ST OBC

FATHERS NAME FATHERS QUALIFICATION FATHERS OCCUPATION

SHEO KUMAR PATHAK BA HONS Retired Bank Manger

MOTHERS NAME MOTHERS QUALIFICATION MOTHERS OCCUPATION

SHAIL KUMARI DEVI HIGH SCHOOL HOUSE WIFE

MARITAL STATUS (TICK) NUMBER OF CHILDREN

1

SINGLE MARRIED WIDOWED DIVORCED

SPOUSE NAME SPOUSE QUALIFICATION SPOUSE OCCUPATION

AARTI MBA HR Manger in IBM India Pvt.ltd.

PERMANENT ADDRESS (DO NOT REPEAT NAME)

H No. 357, Near Kaali Mandir, Behind Pakri Police Chowkey, Pakri, ARRAH, BHOJPUR, Bihar, Pin -802301

ADDRESS FOR CORRESPONDENCE (DO NOT REPEAT NAME)

Flat -7, Chaithram Apartment, Sree Krishna Garden, Katteganhalli, Yelahanka PO, Near BSF Bus Stop and Reva College. Bangalore,
Pin-560064, Karnataka, India
JU/HR/REC/002

TELEPHONE NUMBER (RESIDENCE / LANDLINE) MOBILE NUMBER

8 0 9 5 2 6 3 5 6 1

APPLICANTS E-MAIL ID
rajeevkamal062@gmail.com
 ACADEMIC QUALIFICATION

SUBJECT / MODE OF STUDY

(FULL TIME / PART BOARD / INSTITUTION YEAR OF AGGREGATE % /
QUALIFICATION SPECIALIZATION /
TIME / DISTANCE) / UNIVERSITY PASSING GRADE
NAME OF THE COURSE

JU/HR/REC/002
10TH CLASS / Hindi, English, Social Science, Full Time Bihar School Examination Board Patna, 2000 75
EQUIVALENT Mathes-2, and Science-2 (Bihar) India
10+2 / Hindi, English, Mathematics, Full Time Bihar Intermediate Education Council- 2002 62
EQUIVALENT Physics, and Chemistry Bihar, Patna, India
BACHELORS Electronics & Communication Full Time Uttar Pradesh Technical University, 2006 74.5
DEGREE Engineering (UP), India
MASTERS VLSI Design Full Time CDAC Noida/Guru Gobind Singh 2008 77
DEGREE Indraprastha University, Delhi, India
M.PHIL. /
EQUIVALENT
Electronics Engineering Full Time Technical University of Catalonia 2017 NA
Ph.D
(UPC), Barcelona SPAIN

INDICATE SPECIFICALLY WHETHER Ph.D. DEGREE HAS BEEN AWARDED: Network-on-Chip YES / NO YES

Course work is there but exempted from course YES

WHETHER Ph.D DEGREE WAS WITH COURSE WORK OR NOT YES / NO
work on recommandation of superviser
POST DOCTORAL
FELLOW

NET / SLET / KSET

GATE 2006 and 2011

OTHERS

Ph.D REGISTRATION DATE Ph.D CONVOCATION DATE

0 2 1 2 2 0 1 4 2 2 0 9 2 0 1 7

DAY MONTH YEAR DAY MONTH YEAR

PUBLISHED ACCEPTED /
PUBLICATIONS [ISBN / ISSN] (NOS.) IN PRINT (Nos.) COMMUNICATED

PAPER INTERNATIONAL JOURNAL

INDEXED & PEER REVIEWED EXTRA SHEET ATTACHED
PAPER / BOOK CHAPTER NATIONAL
JOURNAL INDEXED & PEER REVIEWED

BOOKS PUBLISHED

OTHER PUBLICATIONS

TOTAL No. OF CITATIONS

h-INDEX (EXCLUDING SELF-CITATIONS)
RESEARCH QUALITY

NATIONAL INTERNATIONAL TOTAL

FULL PAPERS IN CONFERENCE PROCEEDINGS (No.) (No.) (No.)

EXTRA SHEET ATTACHED

SEMINARS / CONFERENCES / WORKSHOPS / TRAINING NATIONAL INTERNATIONAL TOTAL

PROGRAMMES, ATTENED (No.) (No.) (No.)

EXTRA SHEET ATTACHED

No. OF M.PHIL STUDENTS No. OF Ph.D STUDENTS

RESEARCH GUIDANCE
JU/HR/REC/002

TOTAL IMPACT FACTOR AS PER SCI / SCOPUS

TOTAL IMPACT FACTOR AS PER GOOGLE SEARCH

h-INDEX FACTOR AS PER SCOPUS

h-INDEX FACTOR AS PER GOOGLE SEARCH

i-10 INDEX FACTOR AS PER GOOGLE SEARCH

 SEMINARS / CONFERENCES / WORKSHOPS / TRAINING NATIONAL INTERNATIONAL TOTAL
PROGRAMMES, ORGANIZED (No.) (No.) (No.)

3 3

JU/HR/REC/002
RESEARCH PROJECTS (ONLY EXTERNALLY FUNDED)
As PI/CO-PI or AMOUNT OF GRANT
TITLE OF PROJECTS COMPLETED FUNDING AGENCY INVESTIGATOR AND DURATION

TITLE OF ONGOING PROJECTS

PEER RECOGNITIONS

AWARD / HONOURS AGENCY YEAR

RECENT PUBLICATION DATE No. OF PATENTS

DAY MONTH YEAR

PROFESSIONAL MEMBERSHIP (IF ANY)

EMPLOYMENT DETAILS

CURRENT EMPLOYMENT
PART TIME /
GROSS
FULL TIME / FROM TO REASON FOR
ORGANIZATION DESIGNATION (DD/MM/YY) (DD/MM/YY) SALARY
CONTRACT / LEAVING
PER MONTH
CONSULTANT
Technical University of Catalonia Research Scholar in Advance 01/07/2014 22/09/2017 1340 EURO Work Finished
(UPC), Barcelona SPAIN Hardware Architecture (AHA) Full Time
Group

ADDRESS OF THE ORGANIZATION : Campus Nord, Building C4, c/Jordi Girona 1-3, 08034 - Barcelona - Spain

REPORTING TO :
(Name of the person and designation) J. Manuel Moreno Arostegui, Associate Professor

CONTACT NUMBER : +34 93 401 56 95

E - MAIL ID : juan.manuel.moreno@upc.edu

PREVIOUS EMPLOYMENT DETAILS

PART TIME /
GROSS
FULL TIME / FROM TO REASON FOR
JU/HR/REC/002

ORGANIZATION & LOCATION DESIGNATION (DD/MM/YY) (DD/MM/YY) SALARY PER

CONTRACT / LEAVING
MONTH
CONSULTANT
1) Dronacharya College of Assistant Professor Full Time 17/01/2013 30/06/2014 65000 Personal
Engineering, Khentawas, Far- +
rukhnagar, Gurgaon Haryana Perks

2) NCU University, Gurgaon, Assistant Professor Full Time 01/07/2009 04/12/2012 55000 Personal
(NCR-Delhi) India +
Perks
REFERENCE DETAILS (Professional reference only)

REFERENCE 1 REFERENCE 2

NAME Dr. Arti Noor Vikas Nehra

JU/HR/REC/002
DESIGNATION Scientist-E, Head School of Electronics Assistant Professor

Centre for Development of Advanced Computing (CDAC) Deenbandhu Chhotu Ram University of Science and Technology
ORGANIZATION Department of Electronics and Communication

LOCATION
B -30 & C-56/1, Institutional Area, Sector-62, Noida-UP 50th K.M. Stone, NH-1, Murthal, Sonipat, Haryana 131039

CONTACT NUMBER
+91-20-25503100 91-130- 248 4003

E - MAIL ID
artinoor@cdac.in vikasnehra.ece@dcrustm.org

YOUR AREA OF TEACHING / RESEARCH / INDUSTRY EXPERIENCE

SUBJECT/S TAUGHT

UG LEVEL PG LEVEL OTHERS

Digital design Digital systems engineering VLSI Training Consultant

Analog circuit design System on Chip SystemVerilog as HDL

17 - 1378
Digital circuit design Network on Chip
Introduction to electronics Principle of Interconnects
Computer architecture Advance Digital System
Digital System Design with Verilog HDL Advanced VLSI design
Digital System Design with VHDL

Prepared by Office of Strategic Communications and Human Resources, JGI Group

RESEARCH
During my PhD, I developed a novel Multi-Synchronous Buffer architecture for routers interface and I want to enhance this buffer with spin-transfer torque magnetic
random-access memory (STT-RAM) using behavioural modelling (Verilog-AMS). The emerging STT-RAM has attracted a lot of interest from both academia and
industry in recent years. It has been considered as a promising replacement of SRAM and DRAM in the cache and memory system design thanks to many advantages,
including non-volatility, low leakage power, SRAM comparable read performance and read energy consumption, higher density than SRAM, better scalability than
conventional CMOS technologies, and good CMOS compatibility. However, the disadvantages of STT-RAM, such as higher write energy and longer write latency than
SRAM, also bring design challenges. I wish to develop buffer architecture design using STT-RAM for NoCs Interface.

INDUSTRY
At MentorGraphics I gave a series of seminars on topics like design for testability, SystemVerilog, UVM, future of CMOS VLSI, and ASIC management. I had to
research the related material before giving a seminar to the group. It required a lot of multitasking as I was working as an ASIC design engineer on time-critical
projects like
PCI-Express Verification IP.
To deliver SUPERMAC IP core (4XSGig Ethernet (SGMII/STBI) interfaces).

NA
Have you applied / worked at JU earlier, if yes, when________________for which institution?

How did you hear about us?

Newspaper Friends JU Employee JU Website Social Media Job portal Others

DECLARATION

I acknowledge that all the information provided in this employment application form is true and correct.

Signature of the Applicant

Date :
JU/HR/REC/002

FOR OFFICE OF STRATEGIC COMMUNICATIONS & HUMAN RESOURCES USE ONLY