Program

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity muxfinalju is

Port ( a21 : in STD_LOGIC_VECTOR (7 downto 0);

s21 : in STD_LOGIC_VECTOR (2 downto 0);

en21 : in STD_LOGIC;

y21 : out STD_LOGIC);

end muxfinalju;

architecture Behavioral of muxfinalju is

begin

process(s21,en21,a21)

begin

if en21='1' then

case s21 is

when "000"=> y21 <=a21(0);

when "001"=> y21 <=a21(1);

when "010"=> y21 <=a21(2);

when "011"=> y21 <=a21(3);

when "100"=> y21 <=a21(4);

when "101"=> y21 <=a21(5);

when "110"=> y21 <=a21(6);

when others=> y21 <=a21(7);

end case;
end if;

end process;

end Behavioral;

test bench

--------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 09:50:37 06/13/2014

-- Design Name:

-- Module Name: D:/5334/anil/mux12.vhd

-- Project Name: anil

-- Target Device:

-- Tool versions:

-- Description:

--

-- VHDL Test Bench Created by ISE for module: muxfinalju

--

-- Dependencies:

--
-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

-- Notes:

-- This testbench has been automatically generated using types std_logic and

-- std_logic_vector for the ports of the unit under test. Xilinx recommends

-- that these types always be used for the top-level I/O of a design in order

-- to guarantee that the testbench will bind correctly to the post-implementation

-- simulation model.

--------------------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY mux12 IS

END mux12;

ARCHITECTURE behavior OF mux12 IS

-- Component Declaration for the Unit Under Test (UUT)

 COMPONENT muxfinalju

PORT(

a21 : IN std_logic_vector(7 downto 0);

s21 : IN std_logic_vector(2 downto 0);

en21 : IN std_logic;

y21 : OUT std_logic

);

END COMPONENT;

--Inputs

signal a21 : std_logic_vector(7 downto 0) := (others => '0');

signal s21 : std_logic_vector(2 downto 0) := (others => '0');

signal en21 : std_logic := '0';

--Outputs

signal y21 : std_logic;

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

-- constant <clock>_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

 uut: muxfinalju PORT MAP (

a21 => a21,

s21 => s21,

en21 => en21,

y21 => y21

);

-- Clock process definitions

-- <clock>_process :process

-- begin

-- <clock> <= '0';

-- wait for <clock>_period/2;

-- <clock> <= '1';

-- wait for <clock>_period/2;

-- end process;

-- Stimulus process

stim_proc: process

begin

a21(0)<='0';

wait for 700 ns;

a21(0)<='1';

wait for 100 ns;

end process;
 stim_proc1: process

begin

a21(1)<='0';

wait for 600 ns;

a21(1)<='1';

wait for 100 ns;

a21(1)<='0';

wait for 100 ns;

end process;

stim_proc2: process

begin

a21(2)<='0';

wait for 500 ns;

a21(2)<='1';

wait for 100 ns;

a21(2)<='0';

wait for 200 ns;

end process;

stim_proc3: process

begin

a21(3)<='0';

wait for 400 ns;

a21(3)<='1';

wait for 100 ns;

a21(3)<='0';
wait for 300 ns;

end process;

stim_proc4: process

begin

a21(4)<='0';

wait for 300 ns;

a21(4)<='1';

wait for 100 ns;

a21(4)<='0';

wait for 400 ns;

end process;

stim_proc5: process

begin

a21(5)<='0';

wait for 200 ns;

a21(5)<='1';

wait for 100 ns;

a21(5)<='0';

wait for 500 ns;

end process;

stim_proc6: process

begin

a21(6)<='0';

wait for 100 ns;

a21(6)<='1';
 wait for 100 ns;

a21(6)<='0';

wait for 600 ns;

end process;

stim_proc7: process

begin

a21(7)<='0';

wait for 0 ns;

a21(7)<='1';

wait for 100 ns;

a21(7)<='0';

wait for 700 ns;

end process;

stim_proc8: process

begin

s21(0)<=not s21(0);

wait for 100 ns;

end process;

stim_proc9: process

begin

s21(1)<=not s21(1);

wait for 200 ns;

end process;

stim_proc10: process

begin
 s21(2)<=not s21(2);

wait for 400 ns;

end process;

stim_proc11: process

begin

en21<=not en21;

wait for 800 ns;

end process;

END;
Technology schematic

Jk flip

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity jkflip is

Port ( j,k,c : in STD_LOGIC;

q12 : inout STD_LOGIC);

end jkflip;

architecture Behavioral of jkflip is

begin

process(c,j,k)

begin

if(c'event and c='1')then

if(j='0' and k='1')then

q12<='0';

elsif(j='1' and k='1')then

q12<= not q12;

elsif(j='1' and k='0')then

q12<='1';

elsif(j='0' and k='0')then

q12<= q12;

end if;

end if;

end process;

end Behavioral;

jk test bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY jktest IS

END jktest;

ARCHITECTURE behavior OF jktest IS

 COMPONENT jkflip

PORT(

j : IN std_logic;

k : IN std_logic;

c : IN std_logic;

q12 : INOUT std_logic

);

END COMPONENT;

signal j : std_logic := '0';

signal k : std_logic := '0';

signal c : std_logic := '0';

signal q12 : std_logic;

BEGIN

uut: jkflip PORT MAP (

j => j,

k => k,

c => c,

q12 => q12

);

c_process :process

begin

c <= '0';

wait for 10 ns;

c <= '1';

wait for 10 ns;

 end process;

stim_proc: process

begin

wait for 100 ns;

j<= not j;

end process;

stim_proc1: process

begin

wait for 50 ns;

k<= not k;

end process;

END;
Rtl schematic