Department of Electrical Engineering

Faculty Member:_________________ Dated: ________________

Semester:_____________ Section: ________________

EE-241: Digital Logic Design

Lab 07

Design a display system of a rolling dice

Name Reg. No. Report Evaluation Total/10

Marks / 25 Marks / 10

Lab7: Design a system that display from 1 to 6. It displays the result on a

dice. The dice has seven lights

This Lab Activity has been designed to practice the use of basic gates for designing a
system
 Simplification of Combinational Circuits
 Design and Implementation of a design a system to display dice values.
 Values-Segment Decoder for Selected Digit Display
 There are related questions at the end of this activity. Give complete answers.
Use diagrams if needed for clarity.
Lab Task 01
Design a system that display from 1 to 6. It displays the result on a dice. The dice has
seven lights ( as shown on the diagram below)

a d e
b f
c g

A 1 for each segment ( a, b, c, d, e, f, g) indicates that it is lit; a 0 that is not. The

arrangement is the six numbers on a dice are shown below; where the darken circles are
to lit.

1 2 3 4 5 6

 Design a decoder/driver that produces the seven signal (a, b, c, d, e, f, g) to drive the
display.
1. Complete the following table.
(5 Mark)

Inputs (Binary) Number Outputs(7 LEDs on Dice Display)

A B C a b c d e f g

0 0 1 1 0 0 0 1 0 0 0

0 1 0 2 1 0 0 0 0 0 1

0 1 1 3 1 0 0 1 0 0 1

41 0 0 4 1 0 1 0 1 0 1

1 0 1 5 1 0 1 1 1 0 1

1 1 0 6 1 1 1 0 1 1 1
 Write minimum possible functions to realize outputs. Show and get verified the
minimized Boolean Function expressions to Lab Engineer before implementation.
(5 Marks}
 Draw the complete logic circuit diagram of the system. Use ‘don’t care’ conditions in
your advantage to realize minimum number of gates. (5 marks)
 Design the above circuit using only NAND gates and implement on hardware (5+5e)

// Design of dice display

module MyModule(A,B,C,a,b,c,d,e,f,g);

input A,B,C;

output a,b,c,d,e,f,g;

wire nA,nB,nC,nAB;

// not A

nand g1(nA,A,A);

// not B

nand g2(nB,B,B);

// not C

nand g3(nC,C,C);

// a

nand g4(a,nA,nB);

// b

nand g5(nAB,A,B);

nand g6(b,nAB,nAB);

// c

nand g7(c,nA,nA);
// d

nand g8(d,nC,nC);

// e

nand g9(e,nA,nA);

// f

nand g10(f,nAB,nAB);

// g

nand g11(g,nA,nB);

endmodule

module TestBench();

reg A,B,C;

wire a,b,c,d,e,f,g;

MyModule mod(A,B,C,a,b,c,d,e,f,g);

initial

begin

A=0;

B=0;

C=1;
#5

A=0;

B=1;

C=0;

#5

A=0;

B=1;

C=1;

#5

A=1;

B=0;

C=0;

#5

A=1;

B=0;

C=1;

#5

A=1;

B=1;

C=0;

#5

A=1;

B=1;

C=0;

end

endmodule
Lab Task 02

Write Verilog code to realize the design. Design also test bench to check the valid outputs.
Include all the timing diagram snap shots and Verilog code in the report. (5+5e)