Intel 440lx r1.4 Schematics

A B C D E
440LX CUSTOMER REFERENCE DESIGN

THESE SCHEMATICS ARE PROVIDED "AS IS" WITH NO
4 WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY 4
TITLE PAGE OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR

PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT
OF PROPOSAL, SCHEMATIC OR SAMPLE.
COVER SHEET 1
BLOCK DIAGRAM 2
SLOT1 CONN. 3,4 No license, express or implied, by
CLK SYNTHESIZER 5 estoppel or otherwise, to any
intellectual property rights is granted
PAC 6,7,8 herein.
DIMM SOCKETS 9,10,11
Intel disclaims all liability, including
3 PIIX4 12,13 liability for infringement of any 3
ULTRA I/O 14 proprietary rights, relating to use of
AGP CONN. 15 information in this specification. Intel
PCI CONN. 16,17 does not warrant or represent that such
use will not infringe such rights.
ISA CONN. 18
I2C is a two-wire communications
IDE CONN. 19 bus/protocol developed by Philips. SMBus
USB CONN 20 is a subset of the I2C bus/protocol and
FLASH BIOS 21 was developed by Intel. Implementations
PARALLEL of the I2C bus/protocol or the SMBus
22
bus/protocol may require licenses from
SERIAL/FLOPPY 23 various entities, including Philips
2 KEYBD/MOUSE 24 Electronics N.V. and North American 2
VRM 25 Philips Corporation.

PWR CONN 26 *Third-party brands and names are the property of their
respective owners.
GTL TERMINATION 27 Copyright * Intel Corporation 1996
PCI/AGP PULLUPS 28
ISA PULLUPS 29
PAC DECOUP 30
BULK DECOUP 31
INTEL CORPORATION
VREF PAGE 32
PCI COMPONENTS DIVISION
REVISION HISTORY 33 1900 PRAIRIE CITY RD. FM5-62
1 FOLSOM, CA 95630 1
Title
Size Document Number Rev

A Intel 440LX PCIset 1.4
Date: Sheet 1 of 33
A B C D E
1 2 3 4 5 6 7 8
THIS DRAWING CONTAINS INFORMATION

WHICH HAS NOT BEEN VERIFIED FOR
MANUFACTURING AN END USER PR ODUCT.
INTEL IS NOT RESPONSIBLE FOR THE
MISUSE OF THIS INFORMATION.
KLAMATH ’SLOT 1’
VRM CONNECTOR CLOCK
VTT GEN. ITP CON.
PG. 25 PG. 5
PG. 3,4
A A
ADDR
CNTL
DATA
HOST BUS GTL
TERM.
PG. 27
ADDR
CNTL
DATA
CNTL MEMORY
ADDR/DATA 3 DIMM
AGP PAC 82443LX
ADDR MODULES
CONN. 492 BGA

PGS. 9-11
CNTL
AGP SIDEBAND
PG. 15 PG. 6-8 DATA
B B
ADD/DATA
CNTL
PCI BUS
ADD/DATA
PG. 20
CNTL
2 USB CONN. PGS. 16,17

2 PCI IDE
USB
USB
CONNECTORS
PCI CONN
PCI CONN
PCI CONN
PCI CONN
PG. 19
CNTL
IDE
SECONDARY
IDE
PRIMARY
CNTL
PIIX4
82371AB
324 BGA
ADDR/DATA
PGS. 12,13 ADDR/DATA
C C
CONTROL
ADDR
CNTL
DATA
ISA BUS
PG 18
ADDR
CNTL
DATA
ADDR
ADDR
X-BUS
CONN
ISA
CONN
ISA
FLASH DATA
BIOS ULTRA
PG. 21
KEYBOARD
I/O
PG.14 CNTL
PG. 24
MOUSE DATA
PG.24
D D
SER.
FLOPPY PARA. CONN. INTEL CORPORATION
CONN. CONN. RESET, POWER CONNECTORS PG. 26
PG. 23 PG. 22 PG .23 PCI COMPONENTS DIVISION
1900 PRAIRIE CITY RD. FM5-62
SER. PG. 28,29 FOLSOM, CA 95630
ISA, PCI RESISTORS
CONN.
Title
DECOUPLING CAPACITORS PGS. 30-32 Intel 440LX PCIset Block Diagram

Custom Intel 440LX PCISET 1.4
Date: Thursday, May 07, 1998 Sheet 2 of 33

1 2 3 4 5 6 7 8
A B C D E
VCCVID VTT VTT

J1A
B01 EMI VCC_VTT A01

4 B02 FLUSH# GND A02 4
28 FLUSH# B03 SMI# VCC_VTT A03
13,28 SMI# B04 INIT# IERR# A04
6,13,28 HINIT# IERR_PU 28
B05 VCC_VTT A20M# A05 A20M# 25,28
B06 STPCLK# GND A06
13,28 STPCLK# B07 TCK FERR# A07
5 TCK FERR# 13,28
B08 SLP# IGNNE# A08 IGNNE# 25,28
13,28 SLP# B09 VCC_VTT TDI A09 TDI 5
B10 TMS GND A10
5 TMS B11 TRST# TDO A11
5 TRST# TDO 5
B12 RESERVED PWRGOOD A12 POWERGOOD 26
B13 VCC_VID TESTHI1 A13 TESTHI_PU 28
B14 THRMDA GND A14
B15 THRMDC THERMTRIP# A15 THERMTRIP# 28
B16 LINT[1] RESERVED A16
25,28 LINT1 B17 VCC_VID LINT[0] A17 LINT0 25,28
B18 PICCLK GND A18
5 PICCLK B19 BP#[2] PICD[0] A19 PICD0 28
B20 RESERVED PREQ# A20 PREQ#0 5
B21 100/66# BP#[3] A21
B22 PICD[1] GND A22
28 PICD1
B23 PRDY# BPM#[0] A23
5,27 PRDY#0
B24 BPM#[1] BINIT# A24
B25 VCC_VID DEP#[0] A25
B26 DEP#[2] GND A26
B27 DEP#[4] DEP#[1] A27
B28 DEP#[7] DEP#[3] A28
3 B29 VCC_VID DEP#[5] A29 3
HD#62 B30 D#[62] GND A30
HD#58 B31 D#[58] DEP#[6] A31
HD#63 B32 D#[63] D#[61] A32 HD#61
B33 VCC_VID D#[55] A33 HD#55
HD#56 B34 D#[56] GND A34
HD#50 B35 D#[50] D#[60] A35 HD#60
HD#54 B36 D#[54] D#[53] A36 HD#53
B37 VCC_VID D#[57] A37 HD#57
HD#59 B38 D#[59] GND A38
HD#48 B39 D#[48] D#[46] A39 HD#46
HD#52 B40 D#[52] D#[49] A40 HD#49
B41 EMI D#[51] A41 HD#51
HD#41 B42 D#[41] GND A42
HD#47 B43 D#[47] D#[42] A43 HD#42
HD#44 B44 D#[44] D#[45] A44 HD#45
B45 VCC_VID D#[39] A45 HD#39
HD#36 B46 D#[36] GND A46
HD#40 B47 D#[40] RESERVED A47
HD#34 B48 D#[34] D#[43] A48 HD#43
B49 VCC_VID D#[37] A49 HD#37
HD#38 B50 D#[38] GND A50
HD#32 B51 D#[32] D#[33] A51 HD#33
HD#28 B52 D#[28] D#[35] A52 HD#35
B53 VCC_VID D#[31] A53 HD#31
HD#29 B54 D#[29] GND A54
HD#26 B55 D#[26] D#[30] A55 HD#30
2 HD#25 B56 D#[25] D#[27] A56 HD#27 2
B57 VCC_VID D#[24] A57 HD#24
HD#22 B58 D#[22] GND A58
HD#19 B59 D#[19] D#[23] A59 HD#23
HD#18 B60 D#[18] D#[21] A60 HD#21
B61 EMI D#[16] A61 HD#16
HD#20 B62 D#[20] GND A62
HD#17 B63 D#[17] D#[13] A63 HD#13
HD#15 B64 D#[15] D#[11] A64 HD#11
B65 VCC_VID D#[10] A65 HD#10
HD#12 B66 D#[12] GND A66
HD#7 B67 D#[7] D#[14] A67 HD#14
HD#6 B68 D#[6] D#[9] A68 HD#9
B69 VCC_VID D#[8] A69 HD#8
HD#4 B70 D#[4] GND A70
HD#2 B71 D#[2] D#[5] A71 HD#5
HD#0 B72 D#[0] D#[3] A72 HD#3
B73 VCC_VID D#[1] A73 HD#1
EMI_PD3
EMI_PD2
EMI_PD1
SLOT1_0.7
SLOT 1a
8,27 HD#[63:0]
1 1
R3 R4 R5 INTEL CORPORATION
0 0 0 PCI COMPONENTS DIVISION

FOLSOM, CA 95630
Title
SLOT 1 (PART I)


A B C D E
A B C D E
VCCVID
VCC VCC3
4 4
J1B
5,6,27 HRESET# B74 RESET# GND A74

B75 BREQ1# BCLK A75 CPUHCLK 5
B76 FRCERR# BREQ0# A76 BREQ#0 6,27
B77 VCC_VID BERR# A77
B78 A#[35] GND A78
B79 A#[32] A#[33] A79
HA#29 B80 A#[29] A#[34] A80
B81 EMI A#[30] A81 HA#30
HA#26 B82 A#[26] GND A82
HA#24 B83 A#[24] A#[31] A83 HA#31
HA#28 B84 A#[28] A#[27] A84 HA#27
B85 VCC_VID A#[22] A85 HA#22
HA#20 B86 A#[20] GND A86
HA#21 B87 A#[21] A#[23] A87 HA#23
HA#25 B88 A#[25] RESERVED A88
B89 VCC_VID A#[19] A89 HA#19
HA#15 B90 A#[15] GND A90
HA#17 B91 A#[17] A#[18] A91 HA#18
HA#11 B92 A#[11] A#[16] A92 HA#16
B93 VCC_VID A#[13] A93 HA#13
HA#12 B94 A#[12] GND A94
HA#8 B95 A#[8] A#[14] A95 HA#14
HA#7 B96 A#[7] A#[10] A96 HA#10
B97 VCC_VID A#[5] A97 HA#5
3 HA#3 B98 A#[3] GND A98 3
HA#6 B99 A#[6] A#[9] A99 HA#9
B100 EMI A#[4] A100 HA#4
B101 S_O# BNR# A101
BNR# 6,27
HREQ#0 B102 REQ#[0] GND A102
HREQ#1 B103 REQ#[1] BPRI# A103 BPRI# 6,27
HREQ#4 B104 REQ#[4] TRDY# A104 HTRDY# 6,27
B105 VCC_VID DEFER# A105 DEFER# 6,27
B106 LOCK# GND A106
6,27 HLOCK#
B107 DRDY# REQ#[2] A107 HREQ#2
6,27 DRDY#
B108 RS#[0] REQ#[3] A108 HREQ#3
6,27 RS#0
B109 VCC_5 HITM# A109 HITM# 6,27
B110 HIT# GND A110
6,27 HIT#
B111 RS#[2] DBSY# A111 DBSY# 6,27
6,27 RS#2
B112 RESERVED RS#[1] A112 RS#1 6,27
B113 VCC_3 RESERVED A113
B114 RP# GND A114
B115 RSP# ADS# A115 ADS# 6,27
B116 AP#[1] RESERVED A116
B117 VCC_3 AP#[0] A117
0 B118 AERR# GND A118
VID3 R220 RV3 B119 VID[3] VID[2] A119 RV2 R221 VID2
VID0 RV0 B120 VID[0] VID[1] A120 RV1 0
B121 VCC_3 VID[4] A121 RV4 R223 VID1
R222 0
R224 0
VID4 NOTE :
SLOT1_0.7 0
2 SLOT 1b U25 IS DEFAULT NO STUFF DEVICE. 2
LM75 IS 3.3 VOLT THERMAL SENSOR.

6,27 HA#[31:3] LOCATE NEAR THE CPU AND PAC.
6,27 HREQ#[4:0]
SLAVE ADDRESS = 1001100b
25 VID[4:0]
EMI_PD5
EMI_PD4
VCC VCC3 VCC3
JP14 1 SEL_VID0 R207 U25

VID0 2 8.2K
3 5,9,10,11,13,28 SMBDATA 1 8 R208
SDAT VCC3
R6 R7 8.2K
5,9,10,11,13,28 SMBCLK 2 7
0 0 JP15 1 R209 SCLK SA0
SEL_VID1
VID1 2 8.2K 13,28 THERM# 3 6
OTS SA1
3
4 5 TW_PU1
GND SA2
JP16 1 SEL_VID2 R210
VID2 2 8.2K NOTE : LM75_0.1
3
JP14 - JP18 , R207 AND R209 - R212
JP17 1 SEL_VID3 R211 ARE DEFAULT NO-STUFF
1 1
VID3 2 INTEL CORPORATION
8.2K
3
JP18 1 SEL_VID4 R212 FOLSOM, CA 95630
VID4 2 8.2K
3 Title
SLOT 1 (PART II)


A B C D E
A B C D E F G H I J
VCC3 VCC3 VCC2.5 VCC3
VCC3 VCC3
10 10
R10 R11
14
19
30
36
42
48
10K 10K
U1
13
18
U20
1
8
VDD
C1
VDDQ3
VDDQ3
VDDQ3
VDDQ3
VDDQ3
VDDQ2
VDDQ2
XTLI1 4 2 R_IO_XTALIN R198 22 IO_XTALIN 2
VDD
VDD
VDD
VDD
XTALIN REFOUT XTALIN
9
SEL0
RS0
10pF Y1
9 C3 14.318 IOAPIC0
47 R_ACLK0 R170 33
PICCLK 3
SEL1
10 RS1
9
XTLO1 5 46 3
XTALOUT IOAPIC1 XTALOUT
7
10pF 0.5X AUDIO VCC3
6
R171 33 22 C1 1X AUDIO
13 PX4PCLK R_PCLKF 7 13 OSC0 R194 17
R172 33 PCI_F 22 22 C2 SREF0
R_PCLK0 8 38 R_DCLK0 R173 R195 19
16
16
PCONNCLK1
PCONNCLK2 R174 33 R_PCLK1 10
PCI0
PCI1
SDRAM0
SDRAM1
37 R_DCLK1 R175 22
DIMMHCLK0 9 18 OSC1
DIMMHCLK1 9 14 OSC3 R196 22 C3 20
REF1
REF2
20 SSOP
R176 33 R_PCLK2 11 35 R_DCLK2 R177 22
17 PCONNCLK3 DIMMHCLK2 9
17
7
PCONNCLK4
PACPCLK
R178
R180
33
33
R_PCLK3
R_PCLK4
12
13
PCI2
PCI3 48 SSOP SDRAM2
SDRAM3
34
32
R_DCLK3
R_DCLK4
R179
R181
22
22
DIMMHCLK3 9
DIMMHCLK4 10 13 48MHz R197 22 C4 14
R14
10K
PCI4 SDRAM4 22 48MHz
15 31 R_DCLK5 R182 15
8 PCI5 SDRAM5/PWR_DWN# DIMMHCLK5 10 48MHz
8
GND
GND
GND
29 R_DCLK6 R183 22 12 5 RO1
SDRAM6/CPU_STOP# DIMMHCLK6 10 24MHz OE
28 R_DCLK7 R184 22
SDRAM7/PCI_STOP# DIMMHCLK7 10
R185 33 R_CCLK0 44 21 R_DCLK8 R186 22
4 CPUHCLK CPU0 SDRAM8 DIMMHCLK8 11
R187 33 R_CCLK1 43 20 R_DCLK9 R188 22
4
6 PACHCLK DIMMHCLK9 11
11
16
CPU1 SDRAM9 22 CKIO
41 18 R_DCLK10 R189 DIMMHCLK10 11
R190 33 CPU2 SDRAM10 22
15 AGPHCLK R_CCLK3 40 17 R_DCLK11 R191 DIMMHCLK11 11 VCC3
CPU3 SDRAM11
R15
4,9,10,11,13,28 SMBDATA 23 26 FSEL1
SDATA SEL_66/60# VCC3
R16 8.2K
4,9,10,11,13,28 SMBCLK 24 25 MPU
7 SCLOCK MODE
7
GND
GND
GND
GND
GND
GND
GND
GND
10K
R_CCLK2
NOTE :
3
9
16
22
27
33
39
45
CK3D_0.9
SLAVE ADDR. = 1101010b
6 6
R192
33 VCC2.5
VCC2.5
ITP_CLK
R18 R19
5 100 150 OPTIONAL
R20 R21 R22 R23
5
ITP TEST 330 150 330 330
R27
4,6,27 HRESET# CONNECTOR
J2
240
ITP_RST
1 2
26 DBRESET# 3 4
3 TCK 5 6
3 TMS 7 8 TDI 3
ITP_PON
4 9
11
10
12
BSEN_PU1
TDO 3
TRST# 3 4
13 14
15 16 PREQ#0 3
R_PRDY#0 PRDY#0 3,27
R29 17 18
R28 240
VTT 1K 19 20
5% 21 22
23 24
25 26 R30
27 28 470
29 30
3 ITP CONN 3
2 2
INTEL CORPORATION

FOLSOM, CA 95630
Title
CLOCK SYNTHESIZER
1 Size Document Number Rev
1
A B C D E F G H I J
A B C D E
VTT
U24
F23
4,27 HA#[31:3] U3-1 MAA[10:0] 10,11
HA#3 M26 AC13 MAA0
VTT
VTT
4
HA#4 HA3# MAA0 MAA1 4
N26 AE13
HA#5 N23 HA4# MAA1 AB12 MAA2
HA#6 HA5# MAA2 MAA3
N24 AD13
HA#7 HA6# MAA3 MAA4
M25 AC14
HA#8 M24 HA7# VCC3 PINS: MAA4 AD15 MAA5
HA#9 HA8# MAA5 MAA6
N25 AC15
HA#10 M23 HA9# C3, E13, F20, G6, L11, MAA6 AD16 MAA7
HA#11 HA10# M11, N11, P11, P12, P22, MAA7 MAA8
L24 AC17
HA#12 HA11# MAA8 MAA9
L25 R3, R4, R11-13, T11-16, AE17
HA#13 L23 HA12# MAA9 AA18 MAA10
HA13# AD3, AD12, AD24 MAA10
HA#14 M22 AE18 MAA11
HA14# MAA11 MAA11 10,11
HA#15 K22 AE19 MAA12
HA15# MAA12 MAA12 10,11
HA#16 K25 AF19 MAA13
HA16# MAA13 MAA13 10,11
HA#17 K24
HA#18 L22 HA17#
HA18# MAB[10:0] 9
HA#19 J26
HA#20 J24 HA19# AD14 MAB0
HA#21 HA20# MAB0
J25 AF14 MAB1
HA21# MAB1
HA#22
HA#23
H25
J23 HA22# 82443LX RCSA6# / MAB2
AE14
AB14
MAB2
MAB3
HA#24 HA23# RCSA7# / MAB3
H23 492 BGA AE15 MAB4
HA#25 K21 HA24# SCAS3# / MAB4 AF15 MAB5
HA#26 HA25# SRAS3# / MAB5
G26 AA19 MAB6
HA26# RCSB0# / MAB6
HOST INTERFACE
HA#27 H24 AF16 MAB7
HA#28 J21 HA27# RCSB1# / MAB7 AB19 MAB8
HA#29 HA28# RCSB2# / MAB8
3 G25 AE16 MAB9 3
HA#30 H21 HA29# RCSB3# / MAB9 AF18 MAB10
HA#31 HA30# RCSB4# / MAB10
H22 AD18 MAB11 MAB11 9
HA31# RCSB5# / MAB11
AB18 MAB12 MAB12 9
K26 RCSB6# / MAB12 AD17
4,5,27 HRESET# MAB13 MAB13 9
CPURST# RCSB7# / MAB13
4,27 ADS# P26
ADS#
DRAM INTERFACE
P24
4,27 BNR# BNR#
3,13,28 HINIT# A13 RCSA#[1:0] 11
INIT#
4,27 BREQ#0 L26
R24 BREQ0# AB20
4,27 BPRI# RCSA#0 RCSA#[3:2] 10
BPRI# RCSA0#
4,27 DBSY# V25 AE20 RCSA#1
R22 DBSY# RCSA1# AF20
4,27 DEFER# RCSA#2 RCSA#[5:4] 9
DEFER# RCSA2#
4,27 DRDY# R26 AC20 RCSA#3
DRDY# RCSA3#
4,27 HIT# U26 AC19 RCSA#4
U25 HIT# RCSA4# AB17
4,27 HITM# RCSA#5
HITM# RCSA5#
4,27 HLOCK# B25 CDQA#[7:0] 9,10,11
P23 HLOCK#
4,27 HTRDY# HTRDY#
AD9 CDQA#0
CDQA0#
AC9 CDQA#1
T24 CDQA1# AF21
RS#0 CDQA#2
RS#0 CDQA2#
RS#1 W26 AD21 CDQA#3
U22 RS#1 CDQA3# AD11
RS#2 CDQA#4
RS#2 CDQA4#
4,27 RS#[2:0] AE11 CDQA#5
CDQA5#
HREQ#0 P25 AE21 CDQA#6
R23 HREQ#0 CDQA6# AC21
HREQ#1 CDQA#7
HREQ#1 CDQA7#
HREQ#2 T23
2 T25 HREQ#2 NOTE : 2
HREQ#3
HREQ#3
HREQ#4 R25 AF12 CDQB#1 9
HREQ#4 CDQB1# MUST USE CMOS BUFFER TO AVOID
4,27 HREQ#[4:0] AE12 CDQB#5 9
CDQB5# OVERIDE OF INTERNAL PULLDOWN
ON CKE SIGNAL.
MISC
5 PACHCLK T2 AF11 SRAS#0 11

HCLKIN SRAS0# U22
9,12,15,16,17 PCIRST# AE2 AC10 SRAS#1 10
V23 RSTIN# SRAS1# AF13 2 18
25 CRESET# CRESET# SRAS2# SRAS#2 9 A1 B1
U23 3 17
VCC3 ECC_ERR# A2 B2
R_TS1 AE25 4 16
B_CKE0 11
R31 TESTIN# A3 B3
VSS PINS: AD10 SCAS#0 11 5 15 B_CKE1 11
SCAS0# A4 B4
8.2K AE9 SCAS#1 10 6 14 B_CKE2 10
A1, A26, AA6, AA7-10, AA17, AA20, SCAS1# AF10 7 A5 B5 13
AA21, AB5, AB13, AB22, AF1, AF26, SCAS2# SCAS#2 9 A6 B6 B_CKE3 10
8 12 B_CKE4 9
B2 AD20 9 A7 B7 11
13 VREF5V C15, E5, E22, F6, F8, F9, F17, CKE B_CKE5 9
REF5V CKE A8 B8
F19, F21, G21, H6, J6, K6, L12-16,
M12-16, N22, N12-16, P13-16, R5, AF8 WE#0 11 19
VCC3 WE#0 AE10 1 G
R14-16 , T4, U21, V6, W6, W21 WE#1 WE#1 10 DIR
AF9 VCC3
R32 JP2 WE#2 WE#2 9
AC12
WE#3 74LVC245
8.2K 1
R164
2 R_CKEBUF
R236
3 PAC_1.0
82443LXa 8.2K
NOTE : IOQ DEPTH
1 5.6K
JP2 DEFAULT = 2-3 JP2 NOTE: INTEL CORPORATION 1
FOR MAX IOQ DEPTH.

1-2 1 CKE IS PULLED DOWN BY DEFAULT PCI COMPONENTS DIVISION
26 ECCERR# 2-3 MAX FOR CONFIGURATION 2. FOLSOM, CA 95630
SCHEMATICS WITH CONFIGURATION
Title
1 NEED A PULL-UP TO VCC3 PAC HOST AND DRAM INTERFACES


A B C D E
A B C D E
U3-2
12,16,17 AD[31:0] GAD[31:0] 15
AD0 H4 AB2 GAD0
AD0 GAD0
AD1 G4 AB1 GAD1
AD1 GAD1
AD2 G5 VCC3 PINS : AA3 GAD2
AD2 GAD2
AD3 F4 AA2 GAD3
AD3 C3, E13, F20, G6, L11, GAD3
AD4 E3 AA1 GAD4
AD4 M11, N11, P11, P12, GAD4
AD5 F5 Y2 GAD5
AD5 P22, R3, R4, R11-13, GAD5
AD6 E4 W5 GAD6
AD6 GAD6
AD7 D4 T11-16, AD12, AD3, W3 GAD7
4 AD7 GAD7 4
AD8 E6 AD24 W1 GAD8
AD8 GAD8
AD9 D5 V5 GAD9
AD9 GAD9
AD10 C2 V3 GAD10
AD10 GAD10
AD11 F7 V1 GAD11
AD11 GAD11
AD12 C1 V2 GAD12
AD12 GAD12
AD13 B3 U6 GAD13
AD13 GAD13
AD14 B1 U4 GAD14
AD14 GAD14
AD15 B4 T5 GAD15
AD15 GAD15
AD16 C8 N5 GAD16
AD16 GAD16
AD17
AD18
D7
B8
AD17 82443LX GAD17
N4 GAD17
N3 GAD18
AD19 E8
AD18 492 BGA GAD18
N2 GAD19
AD19 GAD19
AD20 D8 M4 GAD20
AD20 GAD20
AD21 C9 L5 GAD21
AD21 GAD21
PCI INTERFACE
AD22 B9 M2 GAD22
AD22 GAD22
AD23 E9 L4 GAD23
AD23 GAD23
AD24 D9 L1 GAD24
AD24 GAD24
AD25 D10 K5 GAD25
AD25 GAD25
AD26 C10 K2 GAD26
AD26 GAD26
AD27 F10 J3 GAD27
AD27 GAD27
AD28 B10 J1 GAD28
AD28 GAD28
3 AD29 E10 J2 GAD29 3
AD29 GAD29
AD30 B11 H2 GAD30
AD30 GAD30
AD31 E11 H1 GAD31
AD31 GAD31
AGP INTERFACE
12,16,17 C/BE#[3:0] GC/BE#[3:0] 15
C/BE#0 C4 W2 GC/BE#0
C/BE0# GC/BE0#
C/BE#1 A2 U5 GC/BE#1
C/BE1# GC/BE1#
C/BE#2 A7 M1 GC/BE#2
C/BE2# GC/BE2#
C/BE#3 A9 L2 GC/BE#3
C/BE3# GC/BE3#
12,16,17,28 FRAME# C7 P1 GFRAME# 15,28

FRAME# GFRAME#
12,16,17,28 DEVSEL# C6 N1 GDEVSEL# 15,28
DEVSEL# GDEVSEL#
12,16,17,28 IRDY# A6 P5 GIRDY# 15,28
IRDY# GIRDY#
12,16,17,28 TRDY# B6 U2 GTRDY# 15,28
TRDY# GTRDY#
12,16,17,28 STOP# A5 R1 GSTOP# 15,28
STOP# GSTOP#
12,16,17 PAR A3 P2 GPAR 15,28
PAR GPAR
16,17,28 PERR# C5 P4 GPERR# 15,28
PERR# GPERR#
12,16,17,28 SERR# A4 P3 GSERR# 15,28
SERR# GSERR#
16,17,28 PLOCK# B5 G1 GREQ# 15,28
PLOCK# GREQ#
D2 GGNT# 15,28
GGNT#
12,28 PHLD# E7
PHLD#
12,28 PHLDA# A8 AC1 PIPE# 15,28
PHLDA# PIPE#
V24 E2 SBA0
PCI ARB.
2 WSC# SBA0 2
E1 SBA1 SBA[7:0] 15
NOTE : SBA1
REQ#0 A12 F2 SBA2
REQ0# SBA2
REQ#1 E12 F1 SBA3
REQ#4 IS UNUSED. REQ1# SBA3
REQ#2 C13 G3 SBA4
REQ2# SBA4
PULLED UP ONLY. REQ#3 B13
REQ3# SBA5
J5 SBA5
REQ#4 D13 K4 SBA6
REQ4# SBA6
16,17,28 REQ#[4:0] J4 SBA7
SBA7
GNT#0 A11 VSS PINS :
GNT0#
GNT#1 D11 W4 RBF# 15,28
GNT1# A1, A26, AA6, AA7-10, DBF#
GNT#2 C11 ST[2:0] 15
GNT2# AA17, AA20, AA21, AB5,
GNT#3 B12 F3 ST0
GNT3# ST0
GNT#4 D12 AB13, AB22, AF1, AF26, D1 ST1
GNT4# ST1
16,17,28 GNT#[4:0] C15, E5, E22, F6, F8, F9, H5 ST2
ST2
F17, F19, F21, G21, H6,
C12 Y1 ADSTB-0 15,28
5 PACPCLK PCLKIN J6, K6, L12-16, M12-16, ADSTB-A
K1 ADSTB-1 15,28
N22, N12-16, P13-16, R5, ADSTB-B
G2 SBSTB 15,28
SBSTB
R14-16 , T4, U21, V6, W6, AGP_REFV 32
W21 T1
AGPREFV
INTEL CORPORATION
PAC_1.0
1 82443LXb PCI COMPONENTS DIVISION
1
FOLSOM, CA 95630
Title
PAC PCI AND AGP INTERFACES


A B C D E
A B C D E
U3-3
9,10,11 MD[63:0]
MD0 Y3 G22 HD#0
MD0 HD0# HD#1
MD1 Y5 G23 HD#[63:0] 3,27
MD1 HD1# HD#2
MD2 AA5 VCC3 PINS : F25
MD2 HD2# HD#3
MD3 AB4 G24
MD3 C3, E13, F20, G6, HD3# HD#4
MD4 AB6 F24
MD4 L11, M11, N11, P11, HD4# HD#5
MD5 AD1 F26
MD5 HD5# HD#6
4 MD6 AC5 P12, P22, R3, R4, E25 4
MD6 HD6# HD#7
MD7 AE1 R11-13, T11-16, AD12, E24
MD7 HD7# HD#8
MD8 AE3 AD3, AD24 F22
MD8 HD8# HD#9
MD9 AF3 E26
MD9 HD9# HD#10
MD10 AF4 D25
MD10 HD10# HD#11
MD11 AE5 C25
MD11 HD11# HD#12
MD12 AD6 D26
MD12 HD12# HD#13
MD13 AF6 B26
MD13 HD13# HD#14
MD14 AC7 E23
MD14 HD14# HD#15
MD15 AB8 D24
MD15 HD15# HD#16
MD16 AF23 B24
MD16 HD16# HD#17
MD17 AC22 A25
MD17 HD17# HD#18
MD18 AC23 A23
MD18 HD18# HD#19
MD19 AF25 A22
MD19 HD19#
MD20
MD21
AD25
AC24
MD20 82443LX HD20#
A24
B23
HD#20
HD#21
MD21 HD21# HD#22
MD22 AC26 492 BGA B22
MD22 HD22# HD#23
MD23 AB23 D23
MD23 HD23# HD#24
MD24 AA22 D22
MD24 HD24# HD#25
MD25 AA24 C22
MD25 HD25# HD#26
MD26 AA25 B21
MD26 HD26# HD#27
MD27 Y22 A21
MEMORY DATA BUS

MD27 HD27# HD#28
MD28 Y24 D20
MD28 HD28# HD#29
MD29 Y25 E21
HOST DATA BUS

3 MD29 HD29# HD#30 3
MD30 W24 D21
MD30 HD30# HD#31
MD31 W25 C21
MD31 HD31# HD#32
MD32 AB3 E20
MD32 HD32# HD#33
MD33 AA4 B20
MD33 HD33# HD#34
MD34 AC2 A19
MD34 HD34# HD#35
MD35 Y6 A20
MD35 HD35# HD#36
MD36 AC4 B19
MD36 HD36# HD#37
MD37 AD2 D19
MD37 HD37# HD#38
MD38 AB7 C20
MD38 HD38# HD#39
MD39 AF2 F18
MD39 HD39# HD#40
MD40 AD4 E18
MD40 HD40# HD#41
MD41 AE4 C18
MD41 HD41# HD#42
MD42 AD5 D17
MD42 HD42# HD#43
MD43 AF5 E19
MD43 HD43# HD#44
MD44 AE6 C19
MD44 HD44# HD#45
MD45 AD7 B18
MD45 HD45# HD#46
MD46 AE7 B17
MD46 HD46# HD#47
MD47 AF7 E17
MD47 HD47# HD#48
MD48 AE23 C17
MD48 HD48# HD#49
MD49 AF24 A17
MD49 HD49# HD#50
MD50 AD23 B15
MD50 HD50# HD#51
MD51 AE26 D16
MD51 HD51# HD#52
MD52 AD26 D18
2 MD52 HD52# HD#53 2
MD53 AC25 C16
MD53 HD53# HD#54
MD54 AB24 E16
MD54 HD54# HD#55
MD55 AB25 VSS PINS : D15
MD55 HD55# HD#56
MD56 AB26 A14
MD56 A1, A26, AA6, AA7-10, HD56# HD#57
MD57 Y21 B16
MD57 AA17, AA20, AA21, HD57# HD#58
MD58 AA26 C14
MD58 HD58# HD#59
MD59 W22 AB5, AB13, AB22, AF1, A16
MD59 HD59# HD#60
MD60 Y26 AF26, C15, E5, E22, A15
MD60 HD60# HD#61
MD61 W23 F6, F8, F9, F17, F19, D14
MD61 HD61# HD#62
MD62 V22 E15
MD62 F21, G21, H6, J6, K6, HD62# HD#63
MD63 V21 B14
MD63 L12-16, M12-16, N22, HD63#
9,10,11 MECC0
9,10,11 MECC[7:1] MECC0 AD8 N12-16, P13-16, R5,
MECC0
MECC1 AE8 R14-16 , T4, U21, V6,
MECC1
MECC2 AF22 W6, W21
MECC2
MECC3 AB21 C24 PAC_GTLREF1 32
MECC3 GTL_REF
MECC4 AC8 T22 PAC_GTLREF2 32
MECC4 GTL_REF
MECC5 AB9
MECC5
MECC6 AE22
MECC6
MECC7 AD22
MECC7
PAC_1.0
82443LXc INTEL CORPORATION
1 1
FOLSOM, CA 95630
Title
PAC DATA BUSES


A B C D E
A B C D E
DIMM CONNECTOR 0 VCC3 VCC3
8,10,11 MD[63:0]
102
110
124
133
143
157
168
18
26
40
41
90
49
59
73
84
J3
6
4 4
PAC AND DIMM SOCKET LOCATIONS. MD0 2 55 MD16
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
3 DQ0 DQ16 56
MD1 MD17
4 DQ1 DQ17 57
MD2 MD18
5 DQ2 DQ18 58
MD3 MD19
DQ3 DQ19
MD4 7 60 MD20
DQ4 DQ20
DIMM DIMM DIMM MD5 8
DQ5 DQ21
65 MD21
MD6 9 66 MD22
CONN. CONN. CONN. MD7 10 DQ6
NOTE:
DQ22 67 MD23
DQ7 DQ23
0 1 2 EDO PINS NAMES, IF THEY
MD8 11 ARE DIFFERENT FROM SDRAM, 69 MD24
DQ8 DQ24
MD9 13 70 MD25
14 DQ9 APPEAR ON THE INSIDE. DQ25 71
MD10 MD26
15 DQ10 DIFFERENT PIN NAMES DO DQ26 72
MD11 MD27
16 DQ11 NOT NECESSARILY DENOTE DQ27 74
MD12 MD28
DQ12 DQ28
MD13 17 DIFFERENT FUNCTIONALITY. 75 MD29
DQ13 DQ29
MAB[13:0] MD14 19
DQ14 DQ30
76 MD30
MD15 20 77 MD31
DQ15 DQ31
PAC
MAA[13:0] MD32 86
DQ32 DQ48
139 MD48
MD33 87 140 MD49
DQ33 DQ49
MD34 88 141 MD50
89 DQ34 DQ50 142
MD35 MD51
91 DQ35 DQ51 144
MD36 MD52
92 DQ36 DQ52 149
MD37 MD53
DQ37 DQ53
MD38 93 150 MD54
DQ38 DQ54
MD39 94 151 MD55
DQ39 DQ55
MD40 95 153 MD56
97 DQ40 DQ56 154
MD41 MD57
DQ41 DQ57
3 MD42 98 155 MD58 3
DQ42 DQ58
MD43 99 156 MD59
100 DQ43 DQ59 158
MD44 MD60
101 DQ44 DQ60 159
MD45 MD61
103 DQ45 DQ61 160
MD46 MD62
DQ46 DQ62
6 MAB[10:0] MD47 104 161 MD63
DQ47 DQ63
MAB0 33 134
117 A0 NC 135
MAB1
34 A1 NC 146
MAB2
A2 DU NC
MAB3 118 147
A3 NC
MAB4 35 164
119 A4 NC 62
MAB5
36 A5 DU NC
MAB6
120 A6 128
MAB7 B_CKE4 6
A7 DU CKE0
MAB8 37 63 B_CKE5 6
A8 NC CKE1
MAB9 121
38 A9 21
MAB10 MECC0 MECC0 8,10,11
123 A10(AP) CB0 22
6 MAB13 MAB13 MECC1 MECC[7:1] 8,10,11
126 A11 A13 CB1 52
6 MAB12 MAB12 MECC2
A12 DU CB2
132 53 MECC3
A13 DU CB3
105 MECC4
28 CB4 106
6,10,11 CDQA#0 MECC5
29 DQMB0 /CAS0 CB5 136
6 CDQB#1 MECC6
6,10,11 CDQA#2 MECC7
DQMB2 /CAS2 CB7
6,10,11 CDQA#3 47
DQMB3 /CAS3
6,10,11 CDQA#4 112
113 DQMB4 /CAS4 165
6 CDQB#5 DQMB5 /CAS5 SA0
6,10,11 CDQA#6
130
DQMB6 /CAS6 SA1
166 SLAVE ADDRESS = 1010000b
6,10,11 CDQA#7 131 167
2 DQMB7 /CAS7 SA2 2
6 MAB11 MAB11 122 82 SMBDATA 4,5,10,11,13,28

39 BA0 A11 SDA 83
MAB12 SMBCLK 4,5,10,11,13,28
BA1 A12 SCL
24 30 RCSA#4 6
NC /RAS0 /S0
25 114 RCSA#5 6
NC /RAS1 /S1
31 45
44 NC /OE0 /RAS2 /S2 129
48 NC /OE2 /RAS3 /S3 27
6 WE#2 NC /WE2 /WE0
50 111 SCAS#2 6
NC DU /CAS
51 115 SRAS#2 6
VCC3 NC DU /RAS
61
80 NC 42
NC DU CK0 DIMMHCLK0 5
81 125
109 79 DIMMHCLK2 5
R237 NC DU CK2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
108 163 DIMMHCLK3 5

NC DU CK3
145
NC
U14C 8.2K
1
12
23
32
43
54
64
68
78
85
96
107
116
127
138
148
152
162
5 6 SDRAM/EDO DIMM
6,12,15,16,17 PCIRST#
74ALS05
1 1
B_PCIRST 10,11 INTEL CORPORATION

THIS DRAWING CONTAINS INFORMATION 1900 PRAIRIE CITY RD. FM5-62
WHICH HAS NOT BEEN VERIFIED FOR FOLSOM, CA 95630
MANUFACTURING AN END USER PRODUCT.
INTEL IS NOT RESPONSIBLE FOR THE Title
MISUSE OF THIS INFORMATION. FIRST DIMM SOCKET


A B C D E
A B C D E
DIMM CONNECTOR 1
VCC3 VCC3
8,9,11 MD[63:0]
4 4
102
110
124
133
143
157
168
18
26
40
41
90
49
59
73
84
J4
6
MD0 2 55 MD16
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DQ0 DQ16
MD1 3 56 MD17
4 DQ1 DQ17 57
MD2 MD18
5 DQ2 DQ18 58
MD3 MD19
7 DQ3 DQ19 60
MD4 MD20
DQ4 DQ20
MD5 8 65 MD21
DQ5 DQ21
MD6 9 66 MD22
10 DQ6 DQ22 67
MD7 NOTE: MD23
DQ7 DQ23
EDO PINS NAMES, IF THEY
DQ8 DQ24
MD9 13 70 MD25
DQ9 APPEAR ON THE INSIDE. DQ25
MD10 14 71 MD26
MD11 MD27
MD12 MD28
17 DQ12 DQ28 75
MD13 DIFFERENT FUNCTIONALITY. MD29
DQ13 DQ29
MD14 19 76 MD30
DQ14 DQ30
MD15 20 77 MD31
DQ15 DQ31
MD32 86 139 MD48
87 DQ32 DQ48 140
MD33 MD49
DQ33 DQ49
MD34 88 141 MD50
DQ34 DQ50
MD35 89 142 MD51
91 DQ35 DQ51 144
MD36 MD52
92 DQ36 DQ52 149
MD37 MD53
93 DQ37 DQ53 150
MD38 MD54
DQ38 DQ54
3 MD39 94 151 MD55 3
DQ39 DQ55
MD40 95 153 MD56
97 DQ40 DQ56 154
MD41 MD57
98 DQ41 DQ57 155
MD42 MD58
DQ42 DQ58
MD43 99 156 MD59
DQ43 DQ59
MD44 100 158 MD60
101 DQ44 DQ60 159
MD45 MD61
103 DQ45 DQ61 160
MD46 MD62
104 DQ46 DQ62 161
6,11 MAA[10:0] MD47 MD63
DQ47 DQ63
MAA0 33 134
117 A0 NC 135
MAA1
34 A1 NC 146
MAA2
118 A2 DU NC 147
MAA3
A3 NC
MAA4 35 164
A4 NC
MAA5 119 62
36 A5 DU NC
MAA6
120 A6 128
MAA7 B_CKE2 6
37 A7 DU CKE0 63
MAA8 B_CKE3 6
A8 NC CKE1
MAA9 121
A9
MAA10 38 21 MECC0 MECC0 8,9,11
123 A10(AP) CB0 22
6,11 MAA13 MAA13 MECC1 MECC[7:1] 8,9,11
126 A11 A13 CB1 52
6,11 MAA12 MAA12 MECC2
132 A12 DU CB2 53
6,9,11 CDQA#[7:0] MECC3
A13 DU CB3
105 MECC4
CB4
CDQA#0 28 106 MECC5
CDQA#1 MECC6
46 DQMB1 /CAS1 CB6 137 VCC3
CDQA#2 MECC7
47 DQMB2 /CAS2 CB7
CDQA#3
DQMB3 /CAS3
2 CDQA#4 112 2
DQMB4 /CAS4 R33
CDQA#5 113
DQMB5 /CAS5 SA0
165 R_SA0 SLAVE ADDRESS = 1010001b
CDQA#6 130 166
DQMB6 /CAS6 SA1 4.7K
CDQA#7 131 167
DQMB7 /CAS7 SA2
6,11 MAA11 MAA11 122 82 SMBDATA 4,5,9,11,13,28

BA0 A11 SDA
MAA12 39 83 SMBCLK 4,5,9,11,13,28
BA1 A12 SCL
24 30
NC /RAS0 /S0 RCSA#2 6
25 114 RCSA#3 6
NC /RAS1 /S1
9,11 B_PCIRST 31 45
NC /OE0 /RAS2 /S2
44 129
48 NC /OE2 /RAS3 /S3 27
6 WE#1 NC /WE2 /WE0
50 111
NC DU /CAS SCAS#1 6
51 115 SRAS#1 6
NC DU /RAS
61
NC
80 42 DIMMHCLK4 5
81 NC DU CK0 125
109 79
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
108 163
145
NC
1
12
23
32
43
54
64
68
78
85
96
107
116
127
138
148
152
162
SDRAM/EDO DIMM

1 MANUFACTURING AN END USER PRODUCT. 1
MISUSE OF THIS INFORMATION. INTEL CORPORATION

FOLSOM, CA 95630
Title
SECOND DIMM SOCKET


A B C D E
A B C D E
DIMM CONNECTOR 2
VCC3 VCC3
4 8,9,10 MD[63:0] 4
102
110
124
133
143
157
168
18
26
40
41
90
49
59
73
84
J5
6
MD0 2 55 MD16
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
3 DQ0 DQ16 56
MD1 MD17
4 DQ1 DQ17 57
MD2 MD18
5 DQ2 DQ18 58
MD3 MD19
DQ3 DQ19
MD4 7 60 MD20
DQ4 DQ20
MD5 8 65 MD21
9 DQ5 DQ21 66
MD6 MD22
10 DQ6 DQ22 67
MD7 NOTE: MD23
DQ7 DQ23
EDO PINS NAMES, IF THEY
DQ8 DQ24
MD9 13 70 MD25
14 DQ9 APPEAR ON THE INSIDE. DQ25 71
MD10 MD26
MD11 MD27
MD12 MD28
DQ12 DQ28
MD13 17 DIFFERENT FUNCTIONALITY. 75 MD29
DQ13 DQ29
MD14 19 76 MD30
20 DQ14 DQ30 77
MD15 MD31
DQ15 DQ31
MD32 86 139 MD48
DQ32 DQ48
MD33 87 140 MD49
DQ33 DQ49
MD34 88 141 MD50
89 DQ34 DQ50 142
MD35 MD51
91 DQ35 DQ51 144
MD36 MD52
92 DQ36 DQ52 149
MD37 MD53
DQ37 DQ53
3 MD38 93 150 MD54 3
DQ38 DQ54
MD39 94 151 MD55
DQ39 DQ55
MD40 95 153 MD56
97 DQ40 DQ56 154
MD41 MD57
DQ41 DQ57
MD42 98 155 MD58
DQ42 DQ58
MD43 99 156 MD59
100 DQ43 DQ59 158
MD44 MD60
101 DQ44 DQ60 159
MD45 MD61
103 DQ45 DQ61 160
MD46 MD62
DQ46 DQ62
6,10 MAA[10:0] MD47 104 161 MD63
DQ47 DQ63
MAA0 33 134
117 A0 NC 135
MAA1
34 A1 NC 146
MAA2
A2 DU NC
MAA3 118 147
A3 NC
MAA4 35 164
119 A4 NC 62
MAA5
36 A5 DU NC
MAA6
120 A6 128
MAA7 B_CKE0 6
A7 DU CKE0
MAA8 37 63 B_CKE1 6
A8 NC CKE1
MAA9 121
38 A9 21
MAA10 MECC0 MECC0 8,9,10
123 A10(AP) CB0 22
6,10 MAA13 MAA13 MECC1 MECC[7:0] 8,9,10
126 A11 A13 CB1 52
6,10 MAA12 MAA12 MECC2
A12 DU CB2
6,9,10 CDQA#[7:0] 132 53 MECC3
A13 DU CB3
105 MECC4
28 CB4 106
CDQA#0 MECC5
CDQA#1 MECC6
46 DQMB1 /CAS1 CB6 137 VCC3
CDQA#2 MECC7
2 DQMB2 /CAS2 CB7 2
CDQA#3 47
DQMB3 /CAS3
CDQA#4 112
113 DQMB4 /CAS4 165
CDQA#5
DQMB5 /CAS5 SA0 R166
CDQA#6 130
DQMB6 /CAS6 SA1
166 R_SA1 SLAVE ADDRESS = 1010010b
CDQA#7 131 167 4.7K
DQMB7 /CAS7 SA2
6,10 MAA11 MAA11 122 82 SMBDATA 4,5,9,10,13,28

39 BA0 A11 SDA 83
MAA12 SMBCLK 4,5,9,10,13,28
BA1 A12 SCL
24 30 RCSA#0 6
NC /RAS0 /S0
25 114 RCSA#1 6
NC /RAS1 /S1
9,10 B_PCIRST 31 45
44 NC /OE0 /RAS2 /S2 129
48 NC /OE2 /RAS3 /S3 27
6 WE#0 NC /WE2 /WE0
50 111 SCAS#0 6
NC DU /CAS
51 115 SRAS#0 6
NC DU /RAS
61
80 NC 42
81 125
109 79 DIMMHCLK10 5
NC DU CK2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
108 163 DIMMHCLK11 5

NC DU CK3
145
NC
1
12
23
32
43
54
64
68
78
85
96
107
116
127
138
148
152
162
SDRAM/EDO DIMM

1 1
INTEL CORPORATION

FOLSOM, CA 95630
Title
THIRD DIMM SOCKET


A B C D E
A B C D E
U4A
AD0 B10 E15 SDD0
AD0 SDD0
AD1 A10 B15 SDD1
AD1 SDD1
AD2 D9 D14 SDD2
AD2 SDD2
AD3 C9 C14 SDD3
AD3 SDD3
AD4 B9 A14 SDD4
AD4 SDD4
AD5 A9 C13 SDD5
AD5 SDD5
AD6 D8 A13 SDD6
AD6 SDD6
AD7 E8 C12 SDD7
AD8 B8
AD7
AD8
IDE SDD7
SDD8
D12 SDD8
AD9 A8 B13
AD10 D7
AD9 SIGNALS SDD9
D13
SDD9
SDD10
AD10 SDD10
4 AD11 C7 B14 SDD11 4
AD11 SDD11
AD12 B7 E14 SDD12
AD12 SDD12
AD13 A7 A15 SDD13
AD13 SDD13
AD14 D6 C15 SDD14
AD14 SDD14
AD15 E6 D15 SDD15
AD15 SDD15
AD16 E4 SDD[15:0] 19
AD16
AD17 C4 C18 SCS3# 19
AD17 SCS3#
AD18 B4 H16 PCS3# 19
AD18 PCS3#
AD19 A4 B18 SCS1# 19
AD19 SCS1#
AD20 D3 H17 PCS1# 19
AD20 PCS1#
AD21 E3
AD21
AD22 C3
AD22
AD23 B3 U11 SA0
AD23 SA0
AD24 E2 T11 SA1
AD24 SA1
AD18 AD25 C2 W11 SA2
AD25 SA2
AD26 B2 Y11 SA3
AD26 SA3
AD27 A2 T10 SA4
AD27 SA4
AD28 D1
AD28
PCI BUS SA5
W10 SA5
AD29 E1 U9 SA6
AD30 C1
AD29 INTERFACE SA6
V9 SA7
VCC3 AD30 SA7
AD31 B1 Y9 SA8
AD31 SA8
T8 SA9
SA9
R35 W8 SA10
7,16,17 AD[31:0] SA10
C/BE#0 C8 U7 SA11
100 C/BE#0 SA11
R36 C/BE#1 C6 V7 SA12
C/BE#1 SA12
C/BE#2 D4 Y7 SA13
1K C/BE#2 SA13
C/BE#3 D2 V6 SA14
3 C/BE#3 SA14
7,16,17 C/BE#[3:0] Y6 SA15 3
SA15
PIIX4
CLKRUN# C10 T5 SA16
CLOCKRUN# SA16
E5 W5 SA17
7,16,17,28 DEVSEL# DEVSEL# SA17
A5 U4 SA18
7,16,17,28 FRAME# FRAME# SA18
R_AD18 A3 V4 SA19
IDSEL SA19
7,16,17,28 IRDY# B5 SA[19:0] 14,18,21,29
IRDY#
7,16,17 PAR B6
PAR
6,9,15,16,17 PCIRST# A1 V3 SD0
PCIRST# SD0
7,28 PHLD# B12 W3 SD1
PHOLD# SD1
7,28 PHLDA# A12
A6
PHOLDA# ISA/EIO SD2
U2 SD2
T2 SD3
7,16,17,28 SERR#
7,16,17,28 STOP#
D5
SERR#
STOP#
SIGNALS SD3
SD4
W2 SD4
7,16,17,28 TRDY# C5 Y2 SD5
TRDY# SD5
T1 SD6
SD6
28 PU_REQ#0 E10 V1 SD7
REQ0# SD7
28 PU_REQ#1 A11 W16SD8
REQ1# SD8
28 PU_REQ#2 B11 T16 SD9
REQ2# SD9
28 PU_REQ#3 C11 Y17 SD10
REQ3# SD10
19 SDA[2:0] V17 SD11
SD11
SDA0 C17 Y18 SD12
SDA0 SD12
SDA1 B17 W18SD13
SDA1 SD13
SDA2 A18 Y19 SD14
SDA2 SD14
19 PDDACK# G19 W19SD15
PDDACK# SD15
19 SDDACK# A17 SD[16:0] 14,18,29
SDDACK#
19 PDREQ F18
PDREQ
19 SDREQ A16 Y15 LA17
SDREQ LA17
19 PDIOR# F17 T14 LA18
2 PDIOR# LA18 2
19 PDIOW# F16 W14LA19
PDIOW# LA19
19 PIORDY G20 U13 LA20
PIORDY LA20
19 SDIOR# C16 V13 LA21
SDIOR# LA21
19 SDIOW# B16 Y13 LA22
SDIOW# LA22
19 SIORDY D16 T12 LA23
SIORDY LA23
PDA0 G16 LA[23:17] 18,29
PDA0
PDA1 G18 Y12 MEMCS16# 18,29
PDA1 MEMCS16#
PDA2 G17
PDA2 IDE MEMR#
V15 MEMR# 18,21,29
U15
19 PDA[2:0] SIGNALS MEMW#
W4
MEMW# 18,21,29
SMEMR# 18
SMEMR#
PDD0 F20
PDD0
PDD1 E18 U3 SMEMW# 18
PDD1 SMEMW#
PDD2 E20 T7 SYSCLK 18
PDD2 SYSCLK
PDD3 D18 U10 BALE 18
PDD3 BALE
PDD4 D20 Y1 IOCHK# 18,29
PDD4 IOCHK#
PDD5 C20
PDD5
PDD6 B20 W7 REFRESH# 18,29
PDD6 REFRESH#
PDD7 A20 V12 IOCS16# 18,29
PDD7 IOCS16#
PDD8 A19 Y3 ZEROWS# 18,29
PDD8 ZEROWS#
PDD9 B19
PDD9
PDD10 C19 W12 SBHE# 18
PDD10 SBHE#
PDD11 D19 W1 RSTDRV 14,26
PDD11 RSTDRV
PDD12 D17 Y5 IOR# 14,18,29
PDD12 IOR#
PDD13 E19 T4 IOW# 14,18,29
PDD13 IOW#
PDD14 E17 T3 IOCHRDY 14,18,29
PDD14 IOCHRDY
PDD15 F19 Y4 AEN 14,18
PDD15 AEN
1 1
INTEL CORPORATION
19 PDD[15:0] PIIX4_14
FOLSOM, CA 95630
Title
PIIX4 (PART I)


A B C D E
A B C D E
VCC3 VCC3 3V_STBY

VCC3
R15
R16
N16
E11
E12
E16
P15
F15
F14
G6
R6
R7
E9
K5
F6
F5
T6
U4B
14,18 DACK#[3:0]
DACK#0 U14 F1
VCC
VCC
VCC
VCC
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCSUS
VCCSUS
VCCUSB
VCC
DACK0# USBP1+ USBP1+ 20
DACK#1 W6 H2
DACK1# USBP1- USBP1- 20
DACK#2 Y10 G2 USBP0+ 20
DACK2# USBP0+
DACK#3 V5 H3 USBP0- 20
18 DACK#[7:5] DACK3# USBP0-
4
DACK#5 T15
DACK5#
USB OC0
J1 OC#0 20
4
DACK#6 V16 J2
DACK6# OC1 OC#1 20 5VSB
DACK#7 W17
DACK7#
14,18,29 DRQ0 W15
DREQ0 DMA EXTSMI#
V20 EXTSMI# 26,28
U6 W20 14 U5A
14,18,29
14,18,29
DRQ1
DRQ2 V2 DREQ1 SIGNALS SUSA# V19
U5 DREQ2 GPO15/SUSB# U18 1 2
14,18,29 DRQ3 SUSC# B_SUSC# 26
Y16 DREQ3 GPO16/SUSC#
18,29 DRQ5 DREQ5
18,29 DRQ6 U16 R1 C5 7
DREQ6 GPO17/CPU_STP#
18,29 DRQ7 U17 R2 74HCT14
DREQ7 GPO18/PCI_STP# K16 0.01 uF
M1 GPO19/ZZ T17
28 REQ#A REQA#/GPI2 GPO20/SUS_STAT1#
28 REQ#B N2 T18
REQB#/GPI3 GPO21/SUS_STAT2#
28 REQ#C P3
REQC#/GPI4
POWER GPI8/THERM#
H19 THERM# 4,28
U19
N1 MGMT. GPI9/BATLOW# M17
BATLOW# 28
GNTA#/GPO9 RSMRST# RSMRST# 26
P2 U20
GNTB#/GPO10 PWRBT# PWRBT# 26
P4 P16 LID 28
GNTC#/GPO11 GPI10/LID
T20 SMBDATA 4,5,9,10,11,28
SMBDATA VCC3
14,18 TC V10 R19 SMBCLK 4,5,9,10,11,28
J17 TC SMBCLK N17
H18 APICACK#/GPO12 DMA/IRQ GPI11/SMBALERT# P18
SMBALERT# 28
RI#A 28
APICCS#/GPO13 GPI12/RI#A
28 APICREQ# K18
APICREQ#/GPI5 SIGNALS
1
D1
H20 VCC
J20 IRQ0/GPO14
14,29 IRQ1 T9 IRQ1
3
14,18,29
14,18,29
14,18,29
IRQ3
IRQ4
IRQ5
W9
U8
V8
IRQ3
IRQ4
IRQ5 PIIX4 MMBD354LT1
R37
1K
3
3
14,18,29 IRQ6 Y8 IRQ6
14,18,29 IRQ7 IRQ7
14,29 IRQ#8 Y20
IRQ8/GPI6
U1 J16
14,18,29
14,18,29
IRQ9
IRQ10
U12
IRQ9
IRQ10
IRQ VREF VREF5V 6
W13
14,18,29 IRQ11 T13 IRQ11 SIGNALS +
C6
C7
14,18,29 IRQ12 V14 IRQ12
14,18,19,29 IRQ14 IRQ14 1.0 uF
Y14 P19 GPI1 28 0.1 uF
14,18,19,29 IRQ15 IRQ15 GPI1
L2 GPI13
J19 GPI13 J3 GPI14
28 GPI7 SERIRQ/GPI7 GPI14
PIRQ#A R3 L5 GPI15
15,16,17,28 PIRQ#A PIRQA# GPI15
15,16,17,28 PIRQ#B PIRQ#B R4 K3 GPI16
PIRQB# GPI16
16,17,28 PIRQ#C PIRQ#C P5 K4 GPI17
PIRQC# GPI17
16,17,28 PIRQ#D PIRQ#D G1 H1 GPI18
PIRQD# GPI18
K20
GPO/GPI/GPIO/SCAN GPI19
H4 GPI19
H5 GPI20
3,28 SLP# SLP# GPI20
M19 G3 GPI21
CPURST GPI21
K19 GPI[21:13] 28
3,28 FERR# FERR#
25,28 PX4_IGNNE# L17
L18 IGNNE#
3,6,28
25,28
HINIT#
PX4_INTR
L19 INIT
INTR
CPU
14,28 A20GATE P1
L20
A20GATE INTERFACE
25,28 PX4_NMI NMI
3,28 SMI# P20
J18 SMI#
3,28 STPCLK# STPCLK#
3V_STBY N20 G4
14,28 KBRST# RCIN# GPO0 FAN_ON 26
25,28 PX4_A20M# M20 T19 GPO8 1
2 A20M# GPO8 TP2 2
26 PWROK M18 G5 GPO27 1
PWROK GPO27 TP3
26 SPKR K17 F2 GPO28 1
V18 SPKR GPO28 F3 TP4
28 TEST# R17 TEST# GPO29 F4
SYSTEM/TEST
2
28 PX4_CFG1 CONFIG1 GPO30

D2 R_CFG2 R18
CONFIG2
R165 M4
14 XOE# XOE#/GPO23
8.2K M3
14 XDIR# XDIR#/GPO22
21 BIOSCS# M2
BIOSCS#
MMBD354LT1 L1 J4
X-BUS
3
RTCALE/GPO25 N/C
K2 N18
JP19 K1 RTCCS#/GPO24 N/C N3
R38 RTC_BAT 14 KBCCS#/GPO26 N/C
VB2 1 M5
2 L16 N/C M16
1K PX4_VBAT
VBAT N/C
3 RTCX2 R20 R5
RTCX2 N/C
RTCX1 N19
RTCX1 GND: D10,E7,E13,J9,J10,J11,J12,K9,K10,K11,K12
CMOS_CLR
3
C8 P17 L9,L10,L11,L12,M9,M10,M11,M12
MMBD354LT1 0.1 uF SUSCLK
5 48Mhz L3 N4
R234 R235 48Mhz VSSUSB: J5 MCCS#
5 OSC0 V11
OSC
5 PX4PCLK D11 L4 PGCS#0 1
PCICLK PGCS0# TP5
0 0 PROG CHIP SEL. PGCS1#
N5 PGCS#1 1
TP6
R232
D3 Y3
1
2 1 PIIX4_14
1K
32.768KHz
C9 C10
1 VB1
1
22pF 22pF 1
INTEL CORPORATION
BT1
CLEAR CMOS PCI COMPONENTS DIVISION
JP19 CONFIG
2
FOLSOM, CA 95630
1 -2 NORMAL Title
2 - 3 CLEAR CMOS PIIX4 (PART II)


A B C D E
1 2 3 4 5 6 7 8
NOTE: NS6 IS DEFAULT NO-STUFF

U8
NS6 0
13 RTC_BAT R_RTCBAT 121 37
VBAT 14CLK01
SIO_XTAL1 122 38
XTAL1 14CLK02
SIO_XTAL2 124 39 TP076 1 TP7
NS3 XTAL2 14CLK03
5 OSC3 22
14CLOCKI
12,18,29 IOR# 68
IOR#
VCC PINS : 16CLK
36 TP077 1 TP8
R199 12,18,29 IOW# 69 35 TP088 1
IOW# 24CLK TP9
32.763KHz 12,18 AEN 70
AEN
21, 60, 101,
12,26 RSTDRV 80 125, 139 14 INDEX# 23
RSTDRV INDEX#
12,18,29 IOCHRDY 90 9 DIR# 23
IOCHRDY DIR#
A 1M 12,18,29 SD[15:0] 10 STEP# 23 A
NS4 NS5 STEP#
SD0 72 11 WDATA# 23
SD0 WDATA#
SD1 73 12 WGATE# 23
SD1 WGATE#
22 pF 22 pF SD2 74 15 TRK0# 23
SD2 TRK0#
SD3 75 16 WPT# 23
SD3 WPT#
SD4 76 17 RDATA# 23
SD4 RDATA#
DO NOT INSTALL SD5 77
SD5 SIDE1#
13 SIDE1# 23
NS3, NS4 & NS5 SD6 78 18 DSKCHG# 23
SD6 DSKCHG#
SD7 79 4 MOTEA# 23
SD7 MTR0#
7 MOTEB# 23
MTR1#
13,18 TC 89 6 DRVSA# 23
TC DRVSEL0#
13,18,29 DRQ[7:0] 5 DRVSB# 23
DRVSEL1#
DRQ0 82 2 REDWC# 23
DRQ0 DRVDEN0
DRQ1 84 3 DRATE0 23
DRQ1 DRVDEN1
DRQ2 86 20 TP090 1 TP10
DRQ2 MEDID0
DRQ3 88 19 IRR4_MODE
DRQ3 MEDID1
13,18 DACK#[3:0]
DACK#0 81 PDR[7:0] 22
DACK0
DACK#1 83 138 PDR0
DACK1 PD0
DACK#2 85 137 PDR1
DACK2 PD1
DACK#3 87 136 PDR2
DACK3 PD2
135 PDR3
13,18,29 IRQ[7:0]
IRQ1 67
IRQ1
FDC37C932FR PD3
PD4
134 PDR4 VCC
IRQ3 66 133 PDR5 INSTALL FOR 370 CONFIG.
IRQ3 PD5
IRQ4 65 132 PDR6
13,29 IRQ#8 6 5 U24C IRQ5 64
IRQ4
IRQ5
160 PIN QFP PD6
PD7
131 PDR7
REMOVE FOR 3F0 CONFIG.
74AS07 IRQ6 63
IRQ6 R41
B IRQ7 62 140 SLIN#R 22 B
IRQ7 SLIN#
B_IRQ#8 61 141 INIT#R 22 10K
IRQ8# INIT#
13,18,29 IRQ9 IRQ9 59 143 AFD#R 22
IRQ9 AFD#
13,18,29 IRQ10 IRQ10 58 144 STB#R 22
IRQ10 STB#
13,18,29 IRQ11 IRQ11 57 128 BUSY 22 R42
IRQ11 BUSY
13,18,29 IRQ12 IRQ12 56 129 ACK# 22
IRQ12 ACK#
13,18,19,29 IRQ14 IRQ14 55 127 PE 22
IRQ14 PE 1K
13,18,19,29 IRQ15 IRQ15 54 126 SLCT 22
IRQ15 SLCT
12,18,21,29 SA[19:0] 142 ERR# 22 INSTALL FOR 3F0 CONFIG.
ERR#
SA0 41 REMOVE FOR 370 CONFIG.
SA0
SA1 42 145 RX0 23
SA1 RXD1
SA2 43 146 TX0 23
SA2 TXD1
SA3 44 148 RTS0# 23
SA3 RTS1#
SA4 45 149 CTS0# 23
SA4 CTS1#
SA5 46 150 DTR0# 23
SA5 DTR1#
SA6 47 147 DSR0# 23
SA6 DSR1#
SA7 48 152 RLSD0# 23
SA7 DCD1#
SA8 49 151 RI0# 23
VCC SA8 RI1#
SA9 50
SA9
SA10 51 155 RX1 23
SA10 RXD2
SA11 52 156 TX1 23
SA11 TXD2 VCC
SA12 53 158 RTS1# 23
SA12/CS RTS2#
SA13 27 159 CTS1# 23
R43 SA13/HDCS2# CTS2#
SA14 28 160 DTR1# 23 C11
8.2K SA14/HDCS3# DTR2#
SA15 29 157 DSR1# 23
SA15/IDE2_IRQ DSR2# 470pF JP4
154 RLSD1# 23
DCD2#
SIO_PU2 26 153 RI1# 23
IDE1_IRQ RI2# 6
C 1 TP080 23 KEY C
TP12 IDE1_OE# 5
1 TP081 24
VCC TP13 HDCS0# 4
1 TP082 25 96 TP092 1 TP15
TP14 HDCS1# GP10/IRQIN 3
1 TP083 30 97 TP091 1 TP17
RP1 TP16 IOROP# GP11/IRQIN 2
1 TP084 31 98 IRRX
TP18 IOWOP# GP12/IRRX 1
1 8 99 IRTX
GP13/IRTX
2 7 1 TP079 34 100 TP073 1 TP20 INFRARED HDR
TP19 IDE_A0 GP14/RS
3 6 1 TP078 33 102 TP072 1 TP22
TP21 IDE_A1 GP15/WS C12 C13
4 5 1 TP085 32 103 TP087 1 TP24
TP23 IDE_A2 GP16/JOYRS
4.7K 104 TP075 1 TP25 470pF
GP17/JSWS 470pF
24 KBCLK# 92 105 KBRST# 13,28
KCLK GP20/IDE2_OE C14 C15
24 KBDAT# 91 106 R_GP21
KDAT GP21/EEDIN
24 MSCLK# 94 107 TP071 1 TP26
MSCLK GP22/EDOUT
24 MSDAT# 93 108 TP070 1 TP27 0.1 uF 0.1 uF
MSDAT GP23/EECLK
109 TP069 1 TP28
GP24/EEEN
XD0 111 110 A20GATE 13,28
RD0 GP25/8042_P21
XD1 112
RD1
XD2 113
RD2 GND PINS :
XD3 114
RD3 VCC
XD4 115
RD4
XD5 116
RD5
1, 8, 40, 71, R162
XD6 117 95, 123, 130
RD6
XD7 118
RD7 8.2K
21 XD[7:0]
13 XOE# 119
ROMCS#
13 XDIR# 120
ROMOE#
D D
INTEL CORPORATION
FDC37C932FR_1.2

ULTRA I/O 1900 PRAIRIE CITY RD. FM5-62
FOLSOM, CA 95630
Title
INTEL IS NOT RESPONSIBLE FOR THE I/O CONTROLLER (ULTRA I/ O)

1 2 3 4 5 6 7 8
A B C D E
7 SBA[7:0]
7 ST[2:0]
VCC3 VCC3 J6 VCC3 VCC3

VCC +12V
B1 A1 R203
R204 SPARE 12V
B2 A2 4.7K
5V SPARE
4.7K
B3 A3
4 5V RESERVED 4
20 USBAGP+ B4 A4 USBAGP- 20
USB+ USB-
B5 A5 U24B
GND GND
2 1 U24A B_PIRQB# B_PIRQA# 3 4 PIRQ#A 13,16,17,28
13,16,17,28 PIRQ#B
74AS07 B6 A6
INTB# INTA#
74AS07
5 AGPHCLK B7 A7 PCIRST# 6,9,12,16,17
CLK RST#
7,28 GREQ# B8 A8 GGNT# 7,28

REQ# GNT#
B9 A9
VCC3.3 VCC3.3
ST0 B10 A10 ST1
ST0 ST1
ST2 B11 A11
ST2 RESERVED
7,28 RBF# B12 A12 PIPE# 7,28

RBF# PIPE#
B13 A13
GND GND
B14 A14
SPARE SPARE
SBA0 B15 A15 SBA1
SBA0 SBA1
B16 A16
VCC3.3 VCC3.3
SBA2 B17 A17 SBA3
SBA2 SBA3
B18 A18
7,28 SBSTB SB_STB RESERVED
B19 A19
GND GND
SBA4 B20 A20 SBA5
SBA4 SBA5
SBA6 B21 A21 SBA7
SBA6 SBA7
3 3
GAD31 B26 A26 GAD30

AD31 AD30
GAD29 B27 A27 GAD28
AD29 AD28
B28 A28
VCC3.3 VCC3.3
GAD27 B29 A29 GAD26
AD27 AD26
GAD25 B30 A30 GAD24
AD25 AD24
B31 A31
GND GND
7,28 ADSTB-1 B32 A32
AD_STB1 RESERVED
GAD23 B33 A33 GC/BE#3
AD23 GC/BE3#
B34 A34
Vddq3.3 Vddq3.3
GAD21 B35 A35 GAD22
AD21 AD22
GAD19 B36 A36 GAD20
AD19 AD20
B37 A37
GND GND
GAD17 B38 A38 GAD18
AD17 AD18
GC/BE#2 B39 A39 GAD16
C/BE2# AD16
B40 A40
Vddq3.3 Vddq3.3
7,28 GIRDY# B41 A41 GFRAME# 7,28

IRDY# FRAME#
B42 A42
SPARE SPARE
B43 A43
GND GND
B44 A44
SPARE SPARE
B45 A45
VCC3.3 VCC3.3
7,28 GDEVSEL# B46 A46 GTRDY# 7,28

DEVSEL# TRDY#
2 B47 A47 2
Vddq3.3 STOP# GSTOP# 7,28
7,28 GPERR# B48 A48

PERR# SPARE
B49 A49
GND GND
7,28 GSERR# B50 A50 GPAR 7,28

SERR# PAR
GC/BE#1 B51 A51 GAD15
C/BE1# AD15
B52 A52
Vddq3.3 Vddq3.3
GAD14 B53 A53 GAD13
AD14 AD13
GAD12 B54 A54 GAD11
AD12 AD11
B55 A55
GND GND
GAD10 B56 A56 GAD9
AD10 AD9
GAD8 B57 A57 GC/BE#0
AD8 C/BE0#
B58 A58
Vddq3.3 Vddq3.3
7,28 ADSTB-0 B59 A59
AD_STB0 RESERVED
GAD7 B60 A60 GAD6
AD7 AD6
B61 A61
GND GND
GAD5 B62 A62 GAD4
AD5 AD4
GAD3 B63 A63 GAD2
AD3 AD2
B64 A64
Vddq3.3 Vddq3.3
GAD1 B65 A65 GAD0
AD1 AD0
B66 A66
SMBCLOCK SMBDATA
1 AGP_CONN_1.3 1
7 GAD[31:0]
7 GC/BE#[3:0]
INTEL CORPORATION

FOLSOM, CA 95630
Title
ACCELERATED GRAPHICS PORT (AGP) CONNECTOR


A B C D E
1 2 3 4 5 6 7 8
DO NOT REPRODUCE
PCI CONNECTORS
VCC3 VCC3 VCC VCC
VCC3 1 AND 2 VCC3
-12V VCC -12V VCC

VCC +12V VCC +12V R216 R217
5.6K 5.6K
A A
J7 J8
B1 A1 B1 A1 PTRST#
-12V TRST- PTRST# 17 -12V TRST-
B2 A2 PTCK B2 A2
17 PTCK TCK +12V TCK +12V
B3 A3 B3 A3 PTMS
GND TMS PTMS 17 GND TMS
B4 A4 B4 A4 PTDI
TDO TDI PTDI 17 TDO TDI
B5 A5 R218 B5 A5
B6 +5V +5V A6 B6 +5V +5V A6
PIRQ#A 13,15,17,28 PIRQ#B
B7 +5V INTA- A7 B7 +5V INTA- A7
13,15,17,28 PIRQ#B PIRQ#C 13,17,28 5.6K PIRQ#C PIRQ#D
B8 INTB- INTC- A8 B8 INTB- INTC- A8 R219
13,17,28 PIRQ#D PIRQ#A
B9 INTD- +5V A9 B9 INTD- +5V A9
PRSNT#11 PRSNT#21
B10 PRSNT1- RSV A10 B10 PRSNT1- RSV A10
RSV +5V RSV +5V 5.6K
PRSNT#12 B11 A11 PRSNT#22 B11 A11
B13 GND GND A13 B13 GND GND A13
B15 RSV RSV A15 B15 RSV RSV A15
PCIRST# 6,9,12,15,17 PCIRST#
B16 GND RESET- A16 B16 GND RESET- A16
5 PCONNCLK1 CLK +5V 5 PCONNCLK2 CLK +5V
B17 A17 B17 A17
GND GNT- GNT#0 7,28 GND GNT- GNT#1 7,28
7,28 REQ#0 B18 A18 B18 A18
B19 REQ- GND A19 7,28 REQ#1 B19 REQ- GND A19
B20 +5V RSV A20 B20 +5V RSV A20
AD31 AD30 AD31 AD30
B21 AD(31) AD(30) A21 B21 AD(31) AD(30) A21
AD29 AD29
B22 AD(29) +3.3V A22 B22 AD(29) +3.3V A22
AD28 AD28
B23 GND AD(28) A23 B23 GND AD(28) A23
AD27 AD26 AD27 AD26
B24 AD(27) AD(26) A24 B24 AD(27) AD(26) A24
AD25 AD25
B25 AD(25) GND A25 B25 AD(25) GND A25
AD24 AD24
B26 +3.3V AD(24) A26 B26 +3.3V AD(24) A26
C/BE#3 R_AD26 C/BE#3 R_AD27
B27 C/BE-(3) IDSEL A27 B27 C/BE-(3) IDSEL A27
B28 AD(23) +3.3V A28 B28 AD(23) +3.3V A28
AD23 AD22 AD23 AD22
B29 GND AD(22) A29 B29 GND AD(22) A29
AD21 AD20 AD21 AD20
B30 AD(21) AD(20) A30 B30 AD(21) AD(20) A30
B
AD19 AD19
B31 AD(19) GND A31 B31 AD(19) GND A31
B
AD18 AD18
B32 +3.3V AD(18) A32 B32 +3.3V AD(18) A32
AD17 AD16 AD17 AD16
B33 AD(17) AD(16) A33 B33 AD(17) AD(16) A33
C/BE#2 C/BE#2
B34 C/BE-(2) +3.3V A34 B34 C/BE-(2) +3.3V A34
FRAME# 7,12,17,28 FRAME#
B35 GND FRAME- A35 B35 GND FRAME- A35
7,12,17,28 IRDY# IRDY#
B36 IRDY- GND A36 B36 IRDY- GND A36
TRDY# 7,12,17,28 TRDY#
B37 +3.3V TRDY- A37 B37 +3.3V TRDY- A37
7,12,17,28 DEVSEL# DEVSEL#
B38 DEVSEL- GND A38 B38 DEVSEL- GND A38
STOP# 7,12,17,28 STOP#
B39 GND STOP- A39 B39 GND STOP- A39
7,17,28 PLOCK# PLOCK#
B40 LOCK- +3.3V A40 B40 LOCK- +3.3V A40
7,17,28 PERR# SDONE_P1 PERR# SDONE_P2
B41 PERR- SDONE A41 B41 PERR- SDONE A41
SBO_P1 SBO_P2
B42 +3.3V SBO- A42 B42 +3.3V SBO- A42
7,12,17,28 SERR# SERR#
B43 SERR- GND A43 B43 SERR- GND A43
PAR 7,12,17 PAR
B44 +3.3V PAR A44 B44 +3.3V PAR A44
C/BE#1 AD15 C/BE#1 AD15
B45 C/BE-(1) AD(15) A45 B45 C/BE-(1) AD(15) A45
B46 AD(14) +3.3V A46 B46 AD(14) +3.3V A46
AD14 AD13 AD14 AD13
B47 GND AD(13) A47 B47 GND AD(13) A47
AD12 AD11 AD12 AD11
B48 AD(12) AD(11) A48 B48 AD(12) AD(11) A48
AD10 AD10
B49 AD(10) GND A49 B49 AD(10) GND A49
AD9 AD9
GND AD(09) GND AD(09)
KEY KEY
AD8 B52 A52 C/BE#0 AD8 B52 A52 C/BE#0
B53 AD(8) C/BE-(0) A53 B53 AD(8) C/BE-(0) A53
AD7 AD7
B54 AD(7) +3.3V A54 B54 AD(7) +3.3V A54
AD6 AD6
B55 +3.3V AD(06) A55 B55 +3.3V AD(06) A55
AD5 AD4 AD5 AD4
B56 AD(5) AD(04) A56 B56 AD(5) AD(04) A56
AD3 AD3
B57 AD(3) GND A57 B57 AD(3) GND A57
AD2 AD2
B58 GND AD(02) A58 B58 GND AD(02) A58
AD1 AD0 AD1 AD0
B59 AD(1) AD(00) A59 B59 AD(1) AD(00) A59
B60 +5V +5V A60 B60 +5V +5V A60
PU1_REQ64# PU1_ACK64# PU2_REQ64# PU2_ACK64#
B61 ACK64- REQ64- A61 B61 ACK64- REQ64- A61
C
B62 +5V +5V A62 B62 +5V +5V A62 C
+5V +5V +5V +5V
PCI_CONN PCI_CONN
7,12,17 C/BE#[3:0]
7,12,17 AD[31:0]
C16
PRSNT#11
VCC
0.1 uF
VCC C17 R48 R49

RP71 PRSNT#12 PU1_ACK64# AD26 R_AD26
SDONE_P1 1 8
SDONE_P2 2 7 0.1 uF R50 2.7K 100
SBO_P1 3 6 PU1_REQ64#
SBO_P2 4 5 C18 R51
PRSNT#21 2.7K R52 AD27 R_AD27
5.6K PU2_ACK64#
0.1 uF 100
R53 2.7K
D C19 PU2_REQ64# D
PRSNT#22
2.7K
INTEL CORPORATION
0.1 uF
THIS DRAWING CONTAINS INFORMATION FOLSOM, CA 95630
MANUFACTURING AN END USER PR ODUCT. Title
INTEL IS NOT RESPONSIBLE FOR THE PCI CONNECTORS 1 & 2

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
DO NOT REPRODUCE
PCI CONNECTORS
VCC3 VCC3
3 AND 4
VCC3 VCC3
-12V VCC -12V VCC

+12V +12V
VCC VCC
A A
J9 J10
B1 A1 B1 A1 PTRST#
-12V TRST- PTRST# 16 -12V TRST-
B2 A2 PTCK B2 A2
16 PTCK TCK +12V TCK +12V
B3 A3 B3 A3 PTMS
GND TMS PTMS 16 GND TMS
B4 A4 B4 A4 PTDI
TDO TDI PTDI 16 TDO TDI
B5 A5 B5 A5
B6 +5V +5V A6 B6 +5V +5V A6
PIRQ#C 13,16,28 PIRQ#D
B7 +5V INTA- A7 B7 +5V INTA- A7
13,16,28 PIRQ#D PIRQ#A 13,15,16,28 PIRQ#A PIRQ#B
B8 INTB- INTC- A8 B8 INTB- INTC- A8
13,15,16,28 PIRQ#B PIRQ#C
B9 INTD- +5V A9 B9 INTD- +5V A9
PRSNT#31 PRSNT#41
B11 RSV +5V A11 B11 RSV +5V A11
PRSNT#32 PRSNT#42
B15 RSV RSV A15 B15 RSV RSV A15
PCIRST# 6,9,12,15,16 PCIRST#
B16 GND RESET- A16 B16 GND RESET- A16
5 PCONNCLK3 CLK +5V 5 PCONNCLK4 CLK +5V
B17 A17 B17 A17
GND GNT- GNT#2 7,28 GND GNT- GNT#3 7,28
B18 A18 B18 A18
7,28 REQ#2 REQ- GND 7,28 REQ#3 REQ- GND
B19 A19 B19 A19
B20 +5V RSV A20 B20 +5V RSV A20
AD31 AD30 AD31 AD30
B21 AD(31) AD(30) A21 B21 AD(31) AD(30) A21
AD29 AD29
B22 AD(29) +3.3V A22 B22 AD(29) +3.3V A22
AD28 AD28
B23 GND AD(28) A23 B23 GND AD(28) A23
AD27 AD26 AD27 AD26
B24 AD(27) AD(26) A24 B24 AD(27) AD(26) A24
AD25 AD25
B25 AD(25) GND A25 B25 AD(25) GND A25
AD24 AD24
B26 +3.3V AD(24) A26 B26 +3.3V AD(24) A26
C/BE#3 R_AD29 C/BE#3 R_AD31
B27 C/BE-(3) IDSEL A27 B27 C/BE-(3) IDSEL A27
B28 AD(23) +3.3V A28 B28 AD(23) +3.3V A28
AD23 AD22 AD23 AD22
B29 GND AD(22) A29 B29 GND AD(22) A29
AD21 AD20 AD21 AD20
B30 AD(21) AD(20) A30 B30 AD(21) AD(20) A30
B
AD19 AD19
B31 AD(19) GND A31 B31 AD(19) GND A31
B
AD18 AD18
B32 +3.3V AD(18) A32 B32 +3.3V AD(18) A32
AD17 AD16 AD17 AD16
B33 AD(17) AD(16) A33 B33 AD(17) AD(16) A33
C/BE#2 C/BE#2
B34 C/BE-(2) +3.3V A34 B34 C/BE-(2) +3.3V A34
FRAME# 7,12,16,28 FRAME#
B35 GND FRAME- A35 B35 GND FRAME- A35
7,12,16,28 IRDY# IRDY#
B36 IRDY- GND A36 B36 IRDY- GND A36
TRDY# 7,12,16,28 TRDY#
B37 +3.3V TRDY- A37 B37 +3.3V TRDY- A37
7,12,16,28 DEVSEL# DEVSEL#
B38 DEVSEL- GND A38 B38 DEVSEL- GND A38
STOP# 7,12,16,28 STOP#
B39 GND STOP- A39 B39 GND STOP- A39
7,16,28 PLOCK# PLOCK#
B40 LOCK- +3.3V A40 B40 LOCK- +3.3V A40
7,16,28 PERR# SDONE_P3 PERR# SDONE_P4
B41 PERR- SDONE A41 B41 PERR- SDONE A41
SBO_P3 SBO_P4
B42 +3.3V SBO- A42 B42 +3.3V SBO- A42
7,12,16,28 SERR# SERR#
B43 SERR- GND A43 B43 SERR- GND A43
PAR 7,12,16 PAR
B44 +3.3V PAR A44 B44 +3.3V PAR A44
C/BE#1 AD15 C/BE#1 AD15
B45 C/BE-(1) AD(15) A45 B45 C/BE-(1) AD(15) A45
B46 AD(14) +3.3V A46 B46 AD(14) +3.3V A46
AD14 AD13 AD14 AD13
B47 GND AD(13) A47 B47 GND AD(13) A47
AD12 AD11 AD12 AD11
B48 AD(12) AD(11) A48 B48 AD(12) AD(11) A48
AD10 AD10
B49 AD(10) GND A49 B49 AD(10) GND A49
AD9 AD9
GND AD(09) GND AD(09)
KEY KEY
AD8 B52 A52 C/BE#0 AD8 B52 A52 C/BE#0
B53 AD(8) C/BE-(0) A53 B53 AD(8) C/BE-(0) A53
AD7 AD7
B54 AD(7) +3.3V A54 B54 AD(7) +3.3V A54
AD6 AD6
B55 +3.3V AD(06) A55 B55 +3.3V AD(06) A55
AD5 AD4 AD5 AD4
B56 AD(5) AD(04) A56 B56 AD(5) AD(04) A56
AD3 AD3
B57 AD(3) GND A57 B57 AD(3) GND A57
AD2 AD2
B58 GND AD(02) A58 B58 GND AD(02) A58
AD1 AD0 AD1 AD0
B59 AD(1) AD(00) A59 B59 AD(1) AD(00) A59
B60 +5V +5V A60 B60 +5V +5V A60
PU3_REQ64# PU3_ACK64# PU4_REQ64# PU4_ACK64#
B61 ACK64- REQ64- A61 B61 ACK64- REQ64- A61
C
B62 +5V +5V A62 B62 +5V +5V A62 C
+5V +5V +5V +5V
PCI_CONN PCI_CONN
7,12,16 C/BE#[3:0]
7,12,16 AD[31:0]
C20
PRSNT#31
VCC
0.1 uF
C21 R54
PRSNT#32 PU3_ACK64# R55
VCC AD29 R_AD29
RP72 0.1 uF R56 2.7K
SDONE_P3 1 8 PU3_REQ64# 100
SDONE_P4 2 7 C22
SBO_P3 3 6 PRSNT#41 2.7K R57 R58
SBO_P4 4 5 PU4_ACK64# AD31 R_AD31
0.1 uF
5.6K R59 2.7K 100
D C23 PU4_REQ64# D
PRSNT#42
2.7K
INTEL CORPORATION
0.1 uF
MANUFACTURING AN END USER PR ODUCT. Title
INTEL IS NOT RESPONSIBLE FOR THE PCI CONNECTORS 3 & 4

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
ISA SLOTS
VCC
R60
A A
1K
VCC
R61
1K
VCC
VCC
J11 J12
B1 A1 IOCHK# 12,29 B1 A1 IOCHK#
B2 GND IOCHK# A2 B2 GND IOCHK# A2
26 BRSTDRV SD7 12,14,29 BRSTDRV SD7
-5V B3 BRSTDRV SD7 A3 B3 BRSTDRV SD7 A3
SD6 12,14,29 SD6
B4 VCC SD6 A4 -5V B4 VCC SD6 A4
13,14,29 IRQ9 SD5 12,14,29 IRQ9 SD5
-12V IRQ9 SD5 IRQ9 SD5
B5 A5 SD4 12,14,29 B5 A5 SD4
-5V SD4 -12V -5V SD4
13,14,29 DRQ2 B6 A6 SD3 12,14,29 DRQ2 B6 A6 SD3
+12V B7 DREQ2 SD3 A7 B7 DREQ2 SD3 A7
SD2 12,14,29 SD2
B8 -12V SD2 A8 +12V B8 -12V SD2 A8
12,29 ZEROWS# SD1 12,14,29 ZEROWS# SD1
B9 ZEROWS# SD1 A9 B9 ZEROWS# SD1 A9
SD0 12,14,29 SD0
+12V SD0 +12V SD0
B10 A10 IOCHRDY 12,14,29 B10 A10 IOCHRDY
GND IOCHRDY GND IOCHRDY
12 SMEMW# B11 A11 AEN 12,14 SMEMW# B11 A11 AEN
B12 SMEMW# AEN A12 B12 SMEMW# AEN A12
12 SMEMR# SA19 12,29 SMEMR# SA19
B13 SMEMR# SA19 A13 B13 SMEMR# SA19 A13
12,14,29 IOW# SA18 12,29 IOW# SA18
B14 IOW# SA18 A14 B14 IOW# SA18 A14
12,14,29 IOR# SA17 12,21,29 IOR# SA17
IOR# SA17 IOR# SA17
B 13,14 DACK#3 B15 A15 SA16 12,21,29 DACK#3 B15 A15 SA16 B
DACK3# SA16 DACK3# SA16
13,14,29 DRQ3 B16 A16 SA15 12,14,21,29 DRQ3 B16 A16 SA15
B17 DREQ3# SA15 A17 B17 DREQ3# SA15 A17
13,14 DACK#1 SA14 12,14,21,29 DACK#1 SA14
B18 DACK1# SA14 A18 B18 DACK1# SA14 A18
13,14,29 DRQ1 SA13 12,14,21,29 DRQ1 SA13
B19 DREQ1 SA13 A19 B19 DREQ1 SA13 A19
12,29 REFRESH# SA12 12,14,21,29 REFRESH# SA12
REFRESH# SA12 REFRESH# SA12
12 SYSCLK B20 A20 SA11 12,14,21,29 SYSCLK B20 A20 SA11
SYSCLK SA11 SYSCLK SA11
13,14,29 IRQ7 B21 A21 SA10 12,14,21,29 IRQ7 B21 A21 SA10
B22 IRQ7 SA10 A22 B22 IRQ7 SA10 A22
13,14,29 IRQ6 SA9 12,14,21,29 IRQ6 SA9
13,14,29 IRQ5 SA8 12,14,21,29 IRQ5 SA8
13,14,29 IRQ4 SA7 12,14,21,29 IRQ4 SA7
IRQ4 SA7 IRQ4 SA7
13,14,29 IRQ3 B25 A25 SA6 12,14,21,29 IRQ3 B25 A25 SA6
IRQ3 SA6 IRQ3 SA6
13,14 DACK#2 B26 A26 SA5 12,14,21,29 DACK#2 B26 A26 SA5
B27 DACK2# SA5 A27 B27 DACK2# SA5 A27
13,14 TC SA4 12,14,21,29 TC SA4
B28 TC SA4 A28 B28 TC SA4 A28
12 BALE SA3 12,14,21,29 BALE SA3
B29 BALE SA3 A29 B29 BALE SA3 A29
SA2 12,14,21,29 SA2
VCC SA2 NS2 VCC SA2
5 OSC1 B30 A30 SA1 12,14,21,29 OSC1 B30 A30 SA1
OSC SA1 TBD OSC SA1
B31 A31 SA0 12,14,21,29 B31 A31 SA0
GND SA0 GND SA0
12,29 MEMCS16# D1 C1 SBHE# 12 MEMCS16# D1 C1 SBHE#

MEMCS16# SBHE# MEMCS16# SBHE#
12,29 IOCS16# D2 C2 LA23 12,29 IOCS16# D2 C2 LA23
IOCS16# LA23 IOCS16# LA23
13,14,29 IRQ10 D3 C3 LA22 12,29 IRQ10 D3 C3 LA22
D4 IRQ10 LA22 C4 D4 IRQ10 LA22 C4
13,14,29 IRQ11 LA21 12,29 IRQ11 LA21
13,14,29 IRQ12 LA20 12,29 IRQ12 LA20
13,14,19,29 IRQ15 LA19 12,29 NOTE : IRQ15 LA19
D7
IRQ15 LA19
C7 DEFAULT NO STUFF. IRQ14 D7
IRQ15 LA19
C7 LA18
13,14,19,29 IRQ14 IRQ14 LA18 LA18 12,29 IRQ14 LA18
13,14 DACK#0 D8 C8 LA17 12,29 THIS CAP USED DACK#0 D8 C8 LA17
D9 DACK0# LA17 C9 D9 DACK0# LA17 C9
13,14,29 DRQ0 MEMR# 12,21,29 DRQ0 MEMR#
D10 DREQ0 MEMR# C10 TO FILTER NOISE D10 DREQ0 MEMR# C10
13 DACK#5 MEMW# 12,21,29 DACK#5 MEMW#
D11 DACK5# MEMW# C11 D11 DACK5# MEMW# C11
13,29 DRQ5 SD8 12,29 DRQ5 SD8
C D12
DREQ5 SD8
C12 ON TC SIGNAL. DACK#6 D12
DREQ5 SD8
C12 SD9 C
13 DACK#6 DACK6# SD9 SD9 12,29 DACK6# SD9
13,29 DRQ6 D13 C13 SD10 12,29 DRQ6 D13 C13 SD10
D14 DREQ6 SD10 C14 D14 DREQ6 SD10 C14
13 DACK#7 SD11 12,29 DACK#7 SD11
D15 DACK7# SD11 C15 D15 DACK7# SD11 C15
13,29 DRQ7 SD12 12,29 DRQ7 SD12
D16 DREQ7 SD12 C16 D16 DREQ7 SD12 C16
SD13 12,29 SD13
VCC SD13 VCC SD13
29 RMASTER# D17 C17 SD14 12,29 RMASTER# D17 C17 SD14
MASTER# SD14 MASTER# SD14
D18 C18 SD15 12,29 D18 C18 SD15
GND SD15 GND SD15
CON_ISA16C CON_ISA16C
C24
ISA 0 ISA 1
47pF
C25
47pF
D D
INTEL CORPORATION

THIS DRAWING CONTAINS INFORMTION FOLSOM, CA 95630
MANUFACTURING AN END USER PRODUCT. Title
INTEL IS NOT RESPONSIBLE FOR THE ISA SLOTS

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
A A
IDE CONNECTORS
12 SDD[15:0]
12 PDD[15:0]
J13 J14
R62 R63
R_BRSTDRV#1 1 2 BRSTDRV# R_BRSTDRV#2 1 2
26 BRSTDRV#
33 33
DD7#1 3 4 DD8#1 DD7#2 3 4 DD8#2
RP2 DD6#1 5 6 DD9#1 RP3 RP4 DD6#2 5 6 DD9#2 RP5

PDD7 1 16 1 16 PDD8 SDD7 1 16 1 16 SDD8
PDD6 2 15 DD5#1 7 8 DD10#1 2 15 PDD9 SDD6 2 15 DD5#2 7 8 DD10#2 2 15 SDD9
PDD5 3 14 3 14 PDD10 SDD5 3 14 3 14 SDD10
B
PDD4 4 13 DD4#1 9 10 DD11#1 4 13 PDD11 SDD4 4 13 DD4#2 9 10 DD11#2 4 13 SDD11 B
PDD3 5 12 5 12 PDD12 SDD3 5 12 5 12 SDD12
PDD2 6 11 DD3#1 11 12 DD12#1 6 11 PDD13 SDD2 6 11 DD3#2 11 12 DD12#2 6 11 SDD13
PDD1 7 10 7 10 PDD14 SDD1 7 10 7 10 SDD14
VCC PDD0 8 9 DD2#1 13 14 DD13#1 8 9 PDD15 SDD0 8 9 DD2#2 13 14 DD13#2 8 9 SDD15
VCC
33 DD1#1 15 16 DD14#1 33 33 DD1#2 15 16 DD14#2 33
R64
DD0#1 17 18 DD15#1 R65 DD0#2 17 18 DD15#2
1K
1K
19 20 19 20
R66 R67
12 PDREQ R_PDDREQ# 21 22 12 SDREQ R_SDDREQ# 21 22
33 R68 33 R69
12 PDIOW# R_PDIOW# 23 24 12 SDIOW# R_SDIOW# 23 24
R70 33 R71 33
12 PDIOR# R_PDIOR# 25 26 R_SDIOR# 25 26
12 SDIOR#
33 R72 33 R73
27 28 PRI_PD1 12 SIORDY 27 28 SEC_PD1
12 PIORDY
470 470
RP6 29 30 RP7 29 30
12 PDDACK# 1 8 RPDACK# 12 SDDACK# 1 8 RSDACK#
13,14,18,29 IRQ14 2 7 RIRQ14 31 32 2 7 RIRQ15 31 32
13,14,18,29 IRQ15
PDA1 3 6 R_PDA1 SDA1 3 6 R_SDA1
R74 R75
PDA0 4 5 R_PDA0 33 34 PDA2 SDA0 4 5 R_SDA0 33 34 SDA2
33 33
33 35 36 R_PDA2 33 35 36 R_SDA2
R76 R77 PCS3# 12 R78 R79
12 PCS1# R_PCS1# 37 38 R_PCS3# 12 SCS1# R_SCS1# 37 38 R_SCS3# SCS3# 12
33 33 33 33
26 IDEACTP# 39 40 26 IDEACTS# 39 40
C C
12 PDA[2:0] 12 SDA[2:0]
PRIMARY SECONDARY
IDE CONN. IDE CONN.
R80 R81
5.6K 5.6K
D D
INTEL CORPORATION
THIS DRAWING CONTAINS INFORMATION PCI COMPONENTS DIVISION
WHICH HAS NOT BEEN VERIFIED FOR 1900 PRAIRIE CITY RD. FM5-62
MANUFACTURING AN END USER PRODUCT. FOLSOM, CA 95630
MISUSE OF THIS INFORMATION. Title
PCI IDE CONNECTORS


1 2 3 4 5 6 7 8
A B C D E
F1
VCC USB_PWR0
1.5-2.0A R82
470K
4 4
13 OC#0
R83 L1 J33
C26
560K
0.001uF
1 2 USBV0 1
VCC
C28
+ 5
5 UGND0
BLM31A700S USBD0- 2
C29 DATA-
120 uF USBD0+ 3
0.1 uF DATA+
F2 (TANTALUM) 6
6
VCC USB_PWR1 USBG0 4
2
GND
1.5-2.0A R84
L12
2
470K
USB_CON_0.0
C37
13 OC#1 470 pF L4 BLM31A700S
1
R85 BLM31A700S
C27
1
560K
3 0.001uF L2 J34 3
1 2 USBV1 1
VCC
+ 5
5 UGND1
BLM31A700S C30 USBD1- 2
C31 DATA-
0.1 uF USBD1+ 3
120 uF DATA+
6
6
(TANTALUM) USBG1 4
2
GND
L13
2
R86 USB_CON_0.0
13 USBP0- C36
27 470 pF L3 BLM31A700S
R87
13 USBP0+
1
27 BLM31A700S
1
R88 R89
13 USBP1-
27 0
R90 R91
13 USBP1+
2 27 0 2
C32 C33 C34 C35
47pF 47pF 47pF 47pF R92 R93 R94 R95
15K 15K 15K 15K
R_USBD1+ R96
USBAGP+ 15
0
DO NOT STUFF
R_USBD1- R97
USBAGP- 15
0
NOTE:
USE PIIX4
APPLICATION NOTE
FOR LAYOUT
GUIDELINES
INTEL CORPORATION
1 PCI COMPONENTS DIVISION 1

FOLSOM, CA 95630
Title
USB HEADER


A B C D E
1 2 3 4 5 6 7 8
SYSTEM ROM
A A
MODE J16
NORMAL 1-2
U21A
RECOVERY 2-3
1 2 B_SA17
J16
1
74HCT14 2 J_SA17
SA17 3
FLASH SOCKET
B 12,14,18,29 SA[19:0] XD[7:0] 14 B
U9
SA17 40 12
1 A17 DU
SA16
2 A16
SA15
A15
SA14 3
MODE JP17 JP18 SA13 4
A14
5 A13
PROG BOOT 1-2 SA12
2-3 SA11 6 A12
BLOCK 36 A11 25
SA10 XD0
VCC +12V A10 DQ0
PROG DEV SA9 7 26 XD1
(incl. boot block) 1-2 1-2 SA8 8
A9 DQ1
27 XD2
14 A8 DQ2 28
SA7 XD3
PnP 2-3 1-2 R100 SA6 15 A7 DQ3 32 XD4
16 A6 DQ4 33
WRITE PROT 2-3 8.2K SA5 XD5
2-3 SA4 17
A5 DQ5
34 XD6
A4 DQ6
J17 SA3 18 35 XD7
1 19 A3 DQ7
SA2
2 20 A2 13 +12V
SA1
3 21 A1 NC 29
R_RP# SA0
A0 NC
37
NC
12,18,29 MEMW# 9 38 J18
24 WE# NC 1
12,18,29 MEMR# OE#
22 11 FL_VPP 2
10 CE# VPP 3
FL2MPU FL1MPU
RP#
E28F002BC-T
TSOP SOCKET
C C
C38
0.01 uF
C39
0.01 uF
13 BIOSCS#
D D
INTEL CORPORATION

SYSTEM ROM


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
C40
180pF
A A
C41
180pF
C42
180pF
VCC
C43
180pF
D4
IN4148 C44
180pF
PAR5VOL TS
RP8 C45
14 PDR[7:0] 5 4 180pF
PARALLEL
6 3
7 2 C46 HEADER
8 1 180pF
J19
RP9 1K STB# AFD#
1 2
PDR0 5 4 PD0 ERR#
6 3 3 4
B 14 AFD#R PD1 INIT# B
5 6
14 STB#R 7 2 PD2 SLIN#
8 1 C47 7 8
14 INIT#R PD3
9 10
180pF PD4
11 12
33 PD5
C48 13 14
RP10 PD6
5 4 15 16
180pF PD7
17 18
6 3 ACK#
19 20
7 2 BUSY
21 22
PDR3 8 1 PE
23 24
SLCT
25 26
RP11 1K
PDR2 5 4 C49
14 SLIN#R 6 3 180pF
PDR1 7 2
8 1 C50
180pF
33
RP12
1 8
2 7 C51
3 6 180pF
4 5
C52
RP13 1K 180pF
PDR7 5 4
PDR6 6 3
PDR5 7 2
PDR4 8 1
33 C53
C C
RP14 180pF
5 4
6 3 C54
7 2 180pF
8 1
1K
14 ERR#
14 SLCT
14 PE C55
14 BUSY 180pF
14 ACK#
RP15
1 8
2 7
3 6
4 5 C56
180pF
1K

D D
INTEL CORPORATION

FOLSOM, CA 95630
Title
PARALLEL PORT


1 2 3 4 5 6 7 8
A B C D E
4 4
+12V VCC
U10
1 20 J20
VCC+ VCC
SP_DCD0 2 19 RLSD0# 14 SP_DCD0
RA RY 1
SP_DSR0 3 18 DSR0# 14 SP_DSR0
RA RY 2
SP_RXD0 4 17 RX0 14 SP_RXD0
RA RY 3
SP_RTS0 5 16 RTS0# 14 SP_RTS0
DY DA 4
SP_TXD0 6
DY DA
15 TX0 14 SP_TXD0
5
COM 0
SP_CTS0
SP_DTR0
7
8
RA RY
14
13
CTS0# 14 SP_CTS0
SP_DTR0
6 HEADER
DY DA DTR0# 14 7
SP_RI0 9 12 SP_RI0
RA RY RI0# 14 8
10 11
VCC- GND 9
10
GD75232SOP
C57 C58 C59 C60

3 -12V 100pF 100pF 100pF 100pF 3
C61 C62 C63 C64

100pF 100pF 100pF 100pF
+12V VCC
U11
1 20 J21
VCC+ VCC
SP_DCD1 2 19 RLSD1# 14 SP_DCD1
RA RY 1
SP_DSR1 3 18 DSR1# 14 SP_DSR1
RA RY 2
SP_RXD1 4 17 RX1 14 SP_RXD1
RA RY 3
SP_RTS1 5 16 RTS1# 14 SP_RTS1
DY DA 4
SP_TXD1 6 15 SP_TXD1
SP_CTS1 7
DY
RA
DA
RY
14
TX1 14
CTS1# 14 SP_CTS1
5
6
COM 1
SP_DTR1 8
DY DA
13 DTR1# 14 SP_DTR1
7
HEADER
SP_RI1 9 12 SP_RI1
RA RY RI1# 14 8
10 11
VCC- GND 9
10
GD75232SOP
C65 C66 C67 C68

-12V 100pF 100pF 100pF 100pF
2 2
C69 C70 C71 C72

VCC 100pF 100pF 100pF 100pF
RP16
5
6
4
3
FLOPPY
7 2 INTERFACE
8 1
HEADER
1K
R101
1.0K
J22
14 DSKCHG# 34 33
14 SIDE1# 32 31
14 RDATA# 30 29
14 WPT# 28 27
14 TRK0# 26 25
14 WGATE# 24 23
14 WDATA# 22 21
14 STEP# 20 19
14 DIR# 18 17
1 14 MOTEB# 16 15 1
14 DRVSA# 14 13 INTEL CORPORATION
14 DRVSB# 12 11
14 MOTEA# 10 9 PCI COMPONENTS DIVISION
14 INDEX# 8 7 1900 PRAIRIE CITY RD. FM5-62
14 DRATE0 6 5 FOLSOM, CA 95630
1 TP094
TP29 4 3
14 REDWC# 2 1 Title
SERIAL AND FLOPPY


A B C D E
1 2 3 4 5 6 7 8
A A
VCC
STUFFING
OPTION
F3 F4
1.25A 1.35A
KB5V
2
L5
B B
BLM31A700S
1
L6 J23
14 KBDAT# 2 1 KBDAT_FB #
1
1 TP095
TP30 2
BLM31A700S KBSIGND
3
KB5V_F B
4 KEYBOARD
KBCLK_FB #
L7 1 5 CONNECTOR
TP31 TP096
2 1 6
14 KBCLK# 7
8
BLM31A700S 9
L8 J24
14 MSDAT# 2 1 MSDAT_FB #
1
1 TP097
TP32 2
BLM31A700S 3
4 MOUSE
MSCLK_FB #
L9 5 CONNECTOR
1 TP098
TP33 6
14 MSCLK# 2 1
7
8
BLM31A700S 9
C C73 C74 C75 C76 C

470pf 470pF 470pF 470pF C77
0.1 uF KBSHGND
1
L10
BLM31A700S
2
L11
BLM31A700S
2
D D
INTEL CORPORATION

KEYBOARD/MOUSE INTERFACE


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
4 VID[4:0]
VCCVID +12V
+12V
A A
VCC VCC VCC3 VCC3
J25
A1 B1
5Vin 5Vin
A2 B2 R102
5Vin 5Vin 10K R103
A3 B3 10K
5Vin RES.
Processor Core Freq : LINT[1] LINT[0] IGNNE# A20M#
A4 B4
12Vin 12VIN System Bus Freq JP8 JP7 JP6 JP5
A5 B5 L L L L
RES. RES. 2
A6 B6 ROE1 L L L
ISHARE OUTEN 3 H
VID0 A7 B7 VID1 L
VID0 VID1 VRM_PWRGD 26 4 L L H
VID2 A8 B8 VID3 L
VID2 VID3 Reserved L H H
VCCVID
VID4 A9 B9 VCC3 L
VID4 PWRGD 5/2 L H L
A10 B10 7/2 L H L
VCCp Vss H
A11 B11 Reserved All Other Combinations, HLLL-HHHL
Vss VCCp
8
7
6
5
A12 B12 2
VCCp Vss RP17 H H H H
B B
A13 B13 4.7K
Vss VCCp
A14 B14
1
2
3
4
VCCp Vss
U12A
A15 B15 JP5
Vss VCCp
KL_CFG1 A20_PB 1 2 A20M# 3,28
A16 B16
VCCp Vss
JP6
A17 B17 KL_CFG2 74F07
Vss VCCp
A18 B18 JP7 U12B
VCCp Vss
KL_CFG3
A19 B19 IGNE_PB 3 4 IGNNE# 3,28
Vss VCCp
JP8
A20 B20 KL_CFG4
VCCp Vss
74F07
VRM8_1.3 U13 U12C
2 18 LINT0_PB 5 6 LINT0 3,28

1A1 1Y1
4 16
1A2 1Y2
6 14
1A3 1Y3
8 12 74F07
1A4 1Y4
13,28 PX4_A20M# 11 9
2A1 2Y1
13,28 PX4_IGNNE# 13 7 U12D
2A2 2Y2
13,28 PX4_INTR 15 5
2A3 2Y3
C 13,28 PX4_NMI 17 3 LINT1_PB 9 8 LINT1 3,28 C
2A4 2Y4
1
6 CRESET# 1G
CRESET_BF# 19 74F07
2G
U14A VCC3 74FCT3244
1 2 R105
74ALS05 330
VCC3
+12V VR2 2.5V REGULATOR

VTT REGULATOR
VCC3 VTT V25_G1 1 8
4
2
S/D IPOS
VR1 2 7
VIN INEG Q2 VCC2.5
2
VOUT R205
3 6 V25_R1 V2G 1
C100 GND GATE
3 10 MMFT3055EL
VIN C78 1.0 uF
+ 4 5 V25_R2
3
22 uF CERAMIC FB COMP C82
1 16V X7R R206 1.0 uF
GND 20%
LT1575_0.1
C80 LT1585-1.5 100
10uF +
NOTE : C101 V25_R3 R106 C102 + C79
D 20% D
16V 1.0 uF 1.0 uF 22 uF INTEL CORPORATION
VOLTAGE REGULATOR SHOULD 1.30K
V2R
CERAMIC 16V
BE LOCATED NEAR THE PAC 1% X7R 20%
R107 PCI COMPONENTS DIVISION
1.21K C103 C104 1900 PRAIRIE CITY RD. FM5-62
1% 2200pF 0.01 uF FOLSOM, CA 95630
THIS DRAWING CONTAINS INFORMATION Title

WHICH HAS NOT BEEN VERIFIED FOR DC-DC CONVERTER CONNECTORS
INTEL IS NOT RESPONSIBLE FOR THE Size Document Number Rev
MISUSE OF THIS INFORMATION. Custom Intel 440LX PCISET 1.4

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+12V
DO NOT REPRODUCE VCC
R238
POWER LED
1
8.2K
BRSTDRV# 19 R108 HEADER CPU FAN HEADER
220 2 Q3A
SI9933DY USE AMP P/N 640456-3
J27 HEADER OR EQUIVALENT.
U21B U21C PON
1
key
7
2 J26
12,14 RSTDRV 3 4 5 6
BRSTDRV 18 C84 3
B_FON#
3
SENSE
A FON
2
+12V A
74HCT14 74HCT14 470pF GND
SPEAKER 1
C83
640456-3
VCC 0.1 uF
R109 J28
U21D U24D
1
KEY 2
68 TP888 13 FAN_ON 9 8 FON# 9 8
TP34 3
4
R110
74HCT14
SPK2 BUZZ2 74AS07
68
U12E
R112 6 ECCERR# 11 10 EXTSMI# 13,28

13 SPKR SPK1 Q1
MMBT3904L C85
2.2K 0.1 uF 74F07
VCC VCC VCC

5VSB 5VSB
3V_STBY
R114 R115 R116 14 U5B 14

10K 10K 470 S1 U27A
PB1 3 4 PB2 1 2 PWRBT# 13
HARD DRIVE LED CONNECTOR
SW PUSHBUTTON 7 7
B 7407 B
U6A J30 R117 74HCT14
1 ILPU1 JP10 500K
19 IDEACTP# 1
3 IDE_LED
2 2
19 IDEACTS# 3
PON_JMP
4
74ALS08
4 HEADER
C87 C88
470pF 470pF
VCC3
3V_STBY
R119
240 VCC2.5
R200
VCC3 4.7K
5 DBRESET# R118
U14B 330
R121 3 4
POWERGOOD 3
4.7K
74ALS05
U26A U12F
1
5VSB
2 12 PG4 13 12 PG5
C 25 VRM_PWRGD C
13
74HC10 74F07 14 U5C

R122
13 B_SUSC# R239
JP_RST 5 6 PG6 PWROK 13
8.2K
7
100
+12V 74HCT14
C90 C89 (+3.3V) VCC3
PG3 R240
RESET J32 S2 VCC3 8.2K
0.01 uF 10uF (+5.0V)
SWITCH
VCC
HEADER
R169
J31 8.2K
5VSB
1 2
U21E U21F
3 4
5 6
PG1 11 10 PG2 13 12
7 8
9 10
11 12
74HCT14 74HCT14
13 14
3V_STBY 15 16
17 18
19 20 5VSB 5VSB
R123
14 U5D 14 U5E
56
-5V
3
9 8 BRSM1 11 10 RRST1 R241

RSMRST# 13
D5 -12V
8.2K
D C98 C99 7 7 D
MMBZ5226BL 0.01 uF 10uF R125 74HCT14 74HCT14
SOT-23 R_RSMRST# R242
1
8.2K
22K INTEL CORPORATION
C91
1.0 uF PCI COMPONENTS DIVISION
FOLSOM, CA 95630

WHICH HAS NOT BEEN VERIFIED FOR FRONT PANEL

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
GTL+ TERMINATION RESISTORS

VTT VTT VTT
RP18 RP19 RP20
HD#0 1 8 HD#20 1 8 HD#37 1 8
HD#1 2 7 HD#21 2 7 HD#38 2 7
HD#2 3 6 HD#22 3 6 HD#39 3 6
HD#3 4 5 HD#23 4 5 HD#40 4 5
56 ohm VTT 56 OHM VTT 56 ohm VTT
RP21 RP22 RP23
HD#4 1 8 1 8 HD#41 1 8
HD#5 2 7 2 7 HD#42 2 7
A HD#6 3 6 3 6 HD#43 3 6 A
HD#7 4 5 HD#24 4 5 HD#44 4 5
VTT 56 ohm VTT 56 OHM VTT 56 ohm
RP24 RP25 RP26
HD#8 1 8 HD#25 1 8 HD#45 1 8
HD#9 2 7 HD#26 2 7 HD#46 2 7
HD#10 3 6 HD#27 3 6 HD#47 3 6
HD#11 4 5 HD#28 4 5 HD#48 4 5
56 ohm VTT 56 OHM VTT 56 ohm VTT
RP27 RP28 RP29
HD#12 1 8 HD#29 1 8 HD#49 1 8
HD#13 2 7 HD#30 2 7 HD#50 2 7
HD#14 3 6 HD#31 3 6 HD#51 3 6
HD#15 4 5 HD#32 4 5 HD#52 4 5
VTT 56 ohm VTT 56 OHM VTT 56 ohm
RP30 RP31 RP32
HD#16 1 8 HD#33 1 8 HD#53 1 8
HD#17 2 7 HD#34 2 7 HD#54 2 7
HD#18 3 6 HD#35 3 6 HD#55 3 6
HD#19 4 5 HD#36 4 5 HD#56 4 5
56 ohm 56 OHM 56 ohm
3,8 HD#[63:0]
4,6 HA#[31:3]
VTT
RP33
HD#57 1 8
B
HD#58 2 7 B
HD#59 3 6
HD#60 4 5
VTT 56 ohm VTT
RP38 RP34
4,6 BPRI# 1 8 HD#61 1 8
4,6 DBSY# 2 7 HD#62 2 7
4,6 DEFER# 3 6 HD#63 3 6
4,6 DRDY# 4 5 HA#3 4 5
56 ohm VTT 56 ohm
RP35
VTT HA#4 1 8
RP41 HA#5 2 7
4,6 BREQ#0 BREQ#0 1 8 HA#6 3 6
4,6 BNR# 2 7 HA#7 4 5
4,6 ADS# 3 6 56 ohm VTT
4,6 HIT# 4 5 RP36
56 ohm VTT HA#8 1 8
RP43 HA#9 2 7
4,6 HITM# 1 8 HA#10 3 6
4,6 HLOCK# 2 7 HA#11 4 5
4,5,6 HRESET# 3 6 VTT 56 ohm
HREQ#0 4 5 RP37
VTT 56 ohm HA#12 1 8
RP45 HA#13 2 7
HREQ#1 1 8 HA#14 3 6
HREQ#2 2 7 HA#15 4 5
HREQ#3 3 6 56 ohm
HREQ#4 4 5
4,6 HREQ#[4:0] 56 ohm VTT
RP46 VTT
4,6 HTRDY# 1 8 RP39
C C
3,5 PRDY#0 2 7 HA#16 1 8
3 6 HA#17 2 7
4 5 HA#18 3 6
VTT 56 ohm HA#19 4 5
RP47 56 ohm VTT
1 8 RP40
RS#0 2 7 HA#20 1 8
RS#1 3 6 HA#21 2 7
RS#2 4 5 HA#22 3 6
56 ohm HA#23 4 5
VTT 56 ohm
4,6 RS#[2:0]
RP42
HA#24 1 8
HA#25 2 7
HA#26 3 6
HA#27 4 5
56 ohm VTT
RP44
HA#28 1 8
HA#29 2 7
HA#30 3 6
HA#31 4 5
56 ohm
NOTE : VTT = TERMINATION VOLTAGE
D D
INTEL CORPORATION

MANUFACTURING AN END USER PRODUCT. Title
INTEL IS NOT RESPONSIBLE FOR THE GTL TERMINATION

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
RP48 VCC
7,16,17 PERR# 2
3 R1
7,12,16,17 SERR# R2
7,16,17 PLOCK# 4
5 R3 1
7,12,16,17 STOP# R4 PU
7,12,16,17 DEVSEL# 6
7 R5
7,12,16,17 TRDY# R6
8
7,12,16,17 IRDY# R7
7,12,16,17 FRAME# 9
10 R8
PCI BUS
7 REQ#4 R9
A A
2.7K
RP49
13,16,17 PIRQ#D 2 VCC
3 R1 VCC2.5
13,16,17 PIRQ#C R2
13,15,16,17 PIRQ#B 4
R3 R127
13,15,16,17 PIRQ#A 5 1 PICD0
6 R4 PU
7,17 REQ#3 R5 150
7,17 REQ#2 7
8 R6
7,16 REQ#1 R7 R128
7,16 REQ#0 9 PICD1
10 R8
R9 3 PICD[1:0] 150
VCC3
2.7K
RP68 R163
3 TESTHI_PU
7 GNT#4 1 8
4.7K
7,17 GNT#3 2 7
3 6 R2
7,17 GNT#2 3 IERR_PU
7,16 GNT#1 4 5
220
R132
SLOT 1
8.2K 3 THERMTRIP#
RP69
1 8 220
7,16 GNT#0 R129
2 7 3 FLUSH# NOTE :
3 6
4 5 500
R130
RESISTOR VALUES ON SIGNALS
8.2K 3,13 STPCLK#
STPCLK#, SMI#, SLP# & HINIT#
410
R131
B 3,13 SMI# ENABLE AN LAI TO BE USED FOR B
410 BOARD DEBUG. IF AN LAI WILL
R1
3,13 SLP#
RP52 220
NOT BE USED FOR DEBUG THEN
2 VCC3
7,12 PHLD# R1 R233
7,12 PHLDA#
3 3,6,13 HINIT# THE RESISTOR VALUES SHOULD
4 R2
13 REQ#A R3 330
13 REQ#B
5 1 BE CHANGED TO 1K OHM.
6 R4 PU
13 REQ#C R5
7 RP51
13 APICREQ# 8 R6 2 VCC2.5
4,13 THERM# R7 3,25 IGNNE# R1
9 3
13,14 A20GATE R8 3,25 A20M# R2
10 4
13,14 KBRST# R9 3,13 FERR# R3
3,25 LINT0 5 1
6 R4 PU
8.2K 3,25 LINT1
7 R5
8 R6
RP53
2 3V_STBY 9 R7
13 TEST# R1 R8
3 10
13 SMBALERT# 4 R2 R9
13 BATLOW# 5 R3 1
13 LID 330
6 R4 PU
13 RI#A R5
7
13,26 EXTSMI# 8 R6
13 PX4_CFG1 R7
9
10 R8
R9 VCC3
8.2K
R225 VCC3
13 GPI1 R133
8.2K 7,15 GPERR#
C R226 8.2K R134 C
PIIX4
4,5,9,10,11,13 SMBDATA 7,15 GSERR#

8.2K R135 8.2K
R227 7,15 GSTOP#
4,5,9,10,11,13 SMBCLK 8.2K R136
8.2K 7,15 GDEVSEL#
RP67 8.2K
1 8 R137
12 PU_REQ#0 7,15 GTRDY#
2 7 8.2K
12 PU_REQ#1
AGP
3 6 R138
12 PU_REQ#2 7,15 GIRDY#
4 5 8.2K
12 PU_REQ#3 R139
7,15 GFRAME#
8.2K 8,2K R140
RP54 7,15 ADSTB-0
1 8 8.2K
13,25 PX4_INTR R141
2 7 7,15 ADSTB-1
13,25 PX4_IGNNE#
3 6 8.2K
13,25 PX4_A20M# R142
4 5 7,15 SBSTB
13,25 PX4_NMI
R215 8.2K
13 GPI[21:13] 2.7K 7,15 GPAR
RP55 8.2K
1 8 R228
GPI13 7,15 GGNT#
GPI14 2 7 8.2K
3 6 R229
GPI15 7,15 GREQ#
GPI16 4 5 8.2K R230
7,15 PIPE#
2.7K R231 8.2K
RP57 7,15 RBF#
GPI17 1 8 8.2K
GPI18 2 7
GPI19 3 6
GPI20 4 5
D D
2.7K
RP58
1 8 INTEL CORPORATION
GPI21
2 7
13 GPI7 PCI COMPONENTS DIVISION
3 6
4 5 1900 PRAIRIE CITY RD. FM5-62
FOLSOM, CA 95630
2.7K Title
WHICH HAS NOT BEEN VERIFIED FOR BUS RESISTORS
MISUSE OF THI INFORMATION. Custom Intel 440LX PCISET 1.4
1 2 3 4 5 6 7 8
A B C D E
UNUSED GATES
U26B
VCC 3
4 6
5VSB
4 5 4
3V_STBY R143 74HC10
R193 12,18 IOCHK# 14 U5F
13,14 IRQ#8
4.7K 13 12
8.2K U26C
R145 9 7
VCC 12,18 ZEROWS# 10 8 74HCT14
11
1K
RP70
74HC10
13,14,18 IRQ12 1 8 R147
13,14,18,19 IRQ14 2 7 12,14,18 IOCHRDY
13,14,18,19 IRQ15 3 6
4 5 1K
8.2K R148 U6B
18 RMASTER# 4
6
1K 5 U14D
RP59 VCC
13,14 IRQ1 2 R149 74ALS08 9 8
3 R1
13,14,18 IRQ3 R2 12,18 REFRESH#
4 74ALS05
13,14,18 IRQ4 R3
13,14,18 IRQ5 5 1 1K U6C
6 R4 PU 9
13,14,18 IRQ6 R5
13,14,18 IRQ7 7 R150 8 U14E
8 R6 10
13,14,18 IRQ9 R7 12,14,18 IOR#
13,14,18 IRQ10 9 11 10
10 R8
13,14,18 IRQ11 8.2K 74ALS08
R9 74ALS05
3 3
8.2K R151
12,18,21 MEMR# U6D
12
12,14,18 SD[15:0]
8.2K 11
RP60 VCC 13
SD0 2 R152
3 R1
SD1 12,18 MEMCS16# 74ALS08 5VSB
4 R2
SD2
5 R3 1
SD3 1K
R4 PU
ISA BUS
SD4 6
7 R5 14
SD5 R153
8 R6 U27B
SD6 12,18 IOCS16# U14F
9 R7 3 4
SD7
10 R8 13 12
SD8 1K
R9 7
74ALS05 7407
8.2K
5VSB
12,14,18,21 SA[19:0] RP61 VCC
RP62 VCC SA19 2
SD9 2 3 R1
SA18
SD10 3 R1 4 R2 14
SA17
SD11 4 R2 5 R3 1 U27C
SA16
SD12 5 R3 1 6 R4 PU 5 6
SA15
SD13 6 R4 PU 7 R5
SA14
SD14 7 R5 8 R6 7
SA13 7407
SD15 8 R6 9 R7
SA12
9 R7 10 R8
12,14,18 IOW# SA11 5VSB
10 R8 R9
12,18,21 MEMW# R9
8.2K
8.2K U24E
2 RP63 VCC 11 10 14 2
SA10 2 U27D
3 R1 9 8
SA9 74AS07
4 R2
RP64 SA8
2 5 R3 1 7
13,14,18 DRQ0 SA7 7407
3 R1 6 R4 PU U24F
13,14,18 DRQ1 SA6
4 R2 7 R5 13 12
13,14,18 DRQ2 SA5 5VSB
5 R3 1 8 R6
13,14,18 DRQ3 SA4
6 R4 PU 9 R7
13,18 DRQ5 SA3 74AS07
7 R5 10 R8
13,18 DRQ6 SA2
8 R6 R9 14
13,18 DRQ7 R7 U27E
9 8.2K
10 R8 11 10
R9 VCC
RP65
5.6K SA1 2 7
R1 7407
SA0 3
4 R2
LA23 5VSB
5 R3 1
LA22
6 R4 PU
LA21
7 R5
LA20
8 R6 14
LA19
9 R7 U27F
LA18
10 R8 13 12
LA17
R9
12,18 LA[23:17] 8.2K 7
7407
1 1
INTEL CORPORATION
FOLSOM, CA 95630
Title
ISA BUS PULLUPS
Custom
Intel 440LX PCIset 1.4
Date: Sheet 29 of 33
A B C D E
1 2 3 4 5 6 7 8
VCC3
DIMM
DECOUPLING
CD1 CD2 CD3 CD4 CD5 CD6
+
A 0.1 uF 0.1 uF 0.33 uF 0.33 uF 0.33 uF 33 uF VCC3 A
50V 50V 50V 50V 50V 16V
CLOCK DECOUPLING
+
0.1 uF 0.1 uF 0.33 uF 0.33 uF 0.33 uF 33 uF
50V 50V 50V 50V 50V 16V
CD13 CD14
+
0.1 uF 0.1 uF
0.1 uF 0.1 uF 0.33 uF 0.33 uF 0.33 uF 33 uF 50V 50V
50V 50V 50V 50V 50V 16V
CD21 CD22
+
0.1 uF 0.1 uF
0.1 uF 0.1 uF 0.33 uF 0.33 uF 0.33 uF 33 uF 50V 50V
50V 50V 50V 50V 50V 16V
CD29 CD30
+
0.1 uF 0.1 uF
0.1 uF 0.1 uF 0.33 uF 0.33 uF 0.33 uF 33 uF 50V 50V
50V 50V 50V 50V 50V 16V
CD37 CD38
+
0.1 uF 0.1 uF
0.1 uF 0.1 uF 0.33 uF 0.33 uF 0.33 uF 33 uF 50V 50V
B
50V 50V 50V 50V 50V 16V B
CD45 CD46
+
0.1 uF 0.1 uF
0.1 uF 0.1 uF 0.33 uF 0.33 uF 0.33 uF 33 uF 50V 50V
50V 50V 50V 50V 50V 16V
+
0.1 uF 0.1 uF 0.33 uF 0.33 uF 0.33 uF 33 uF
50V 50V 50V 50V 50V 16V
+
0.1 uF 0.1 uF 0.33 uF 0.33 uF 0.33 uF 33 uF
50V 50V 50V 50V 50V 16V
+
0.1 uF
50V
0.1 uF
50V
0.33 uF
50V
0.33 uF
50V
0.33 uF
50V
33 uF
16V
VCC3 PAC DECOUPLING
+
0.1 uF 0.1 uF 0.33 uF 0.33 uF 0.33 uF 33 uF CD77 CD78 CD79 CD80
50V 50V 50V 50V 50V 16V
C CD86 C
CD81 CD82 CD83 CD84 CD85 0.1 uF 0.01 uF 0.1 uF 0.01 uF
+
50V 50V 50V 50V
0.1 uF 0.1 uF 0.33 uF 0.33 uF 0.33 uF 33 uF CD87 CD88 CD89 CD90

50V 50V 50V 50V 50V 16V
0.1 uF 0.01 uF 0.1 uF 0.01 uF

50V 50V 50V 50V
CD91 CD92 CD93 CD94
0.1 uF 0.01 uF 0.1 uF 0.01 uF

50V 50V 50V 50V
CD95 CD96 CD97 CD98
0.1 uF 0.01 uF 0.1 uF 0.01 uF

50V 50V 50V 50V
D D
INTEL CORPORATION

FOLSOM, CA 95630
Title
DRAM AND PAC DECOUPLING CAPACITORS


1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
DO NOT REPRODUCE
A A
BULK DECOUPLING
VCC3 VCC
3 VOLT
VCC3 DECOUPLING
CD99 CD100
+
+
CD101 CD102
22 uF 22 uF
16V 16V 0.1 uF 0.1 uF
50v 50v
CD103 CD104
+
+
CD105 CD106
22 uF 22 uF
16V 16V 0.1 uF 0.1 uF
50v 50v
CD107 CD108
B
0.1 uF 0.1 uF B
50v 50v
-5v CD109 CD110
0.1 uF 0.1 uF
CD111 50v 50v
+
CD112 CD113
22 uF
16v
0.1 uF 0.1 uF
CD114 50v 50v
CD115 CD116
0.01 uF
50v
0.1 uF 0.1 uF
50v 50v
+12v CD117 CD118
0.1 uF 0.1 uF
CD119 50v 50v
CD120 CD121
+
22 uF
16v
0.1 uF 0.1 uF
CD122 50v 50v
C C
CD123 CD124
0.01 uF
50v
0.1 uF 0.1 uF
50v 50v
-12v CD125 CD126
0.1 uF 0.1 uF
CD127 50v 50v
+
22 uF
16v
CD128
0.01 uF
50v
D D
INTEL CORPORATION

FOLSOM, CA 95630
WHICH HAS NOT BEEN VERIFIED FOR Title
MANUFACTURING AN END USER PR ODUCT. 3.3 VOLT AND BULK POWER DECOUPLING
MISUSE OF THIS INFORMATION. Size Document Number Rev

1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
4 VID[4:0]
VCCVID +12V
+12V
A A
VCC VCC VCC3 VCC3
J25
A1 B1
5Vin 5Vin
A2 B2 R102
5Vin 5Vin 10K R103
A3 B3 10K
5Vin RES.
Processor Core Freq : LINT[1] LINT[0] IGNNE# A20M#
A4 B4
12Vin 12VIN System Bus Freq JP8 JP7 JP6 JP5
A5 B5 L L L L
RES. RES. 2
A6 B6 ROE1 L L L
ISHARE OUTEN 3 H
VID0 A7 B7 VID1 L
VID0 VID1 VRM_PWRGD 26 4 L L H
VID2 A8 B8 VID3 L
VID2 VID3 Reserved L H H
VCCVID
VID4 A9 B9 VCC3 L
VID4 PWRGD 5/2 L H L
A10 B10 7/2 L H L
VCCp Vss H
A11 B11 Reserved All Other Combinations, HLLL-HHHL
Vss VCCp
8
7
6
5
A12 B12 2
VCCp Vss RP17 H H H H
B B
A13 B13 4.7K
Vss VCCp
A14 B14
1
2
3
4
VCCp Vss
U12A
A15 B15 JP5
Vss VCCp
KL_CFG1 A20_PB 1 2 A20M# 3,28
A16 B16
VCCp Vss
JP6
A17 B17 KL_CFG2 74F07
Vss VCCp
A18 B18 JP7 U12B
VCCp Vss
KL_CFG3
A19 B19 IGNE_PB 3 4 IGNNE# 3,28
Vss VCCp
JP8
A20 B20 KL_CFG4
VCCp Vss
74F07
VRM8_1.3 U13 U12C
2 18 LINT0_PB 5 6 LINT0 3,28

1A1 1Y1
4 16
1A2 1Y2
6 14
1A3 1Y3
8 12 74F07
1A4 1Y4
13,28 PX4_A20M# 11 9
2A1 2Y1
13,28 PX4_IGNNE# 13 7 U12D
2A2 2Y2
13,28 PX4_INTR 15 5
2A3 2Y3
C 13,28 PX4_NMI 17 3 LINT1_PB 9 8 LINT1 3,28 C
2A4 2Y4
1
6 CRESET# 1G
CRESET_BF# 19 74F07
2G
U14A VCC3 74FCT3244
1 2 R105
74ALS05 330
VCC3
+12V VR2 2.5V REGULATOR

VTT REGULATOR
VCC3 VTT V25_G1 1 8
4
2
S/D IPOS
VR1 2 7
VIN INEG Q2 VCC2.5
2
VOUT R205
3 6 V25_R1 V2G 1
C100 GND GATE
3 10 MMFT3055EL
VIN C78 1.0 uF
+ 4 5 V25_R2
3
22 uF CERAMIC FB COMP C82
1 16V X7R R206 1.0 uF
GND 20%
LT1575_0.1
C80 LT1585-1.5 100
10uF +
NOTE : C101 V25_R3 R106 C102 + C79
D 20% D
16V 1.0 uF 1.0 uF 22 uF INTEL CORPORATION
VOLTAGE REGULATOR SHOULD 1.30K
V2R
CERAMIC 16V
BE LOCATED NEAR THE PAC 1% X7R 20%
R107 PCI COMPONENTS DIVISION
1.21K C103 C104 1900 PRAIRIE CITY RD. FM5-62
1% 2200pF 0.01 uF FOLSOM, CA 95630

WHICH HAS NOT BEEN VERIFIED FOR DC-DC CONVERTER CONNECTORS

1 2 3 4 5 6 7 8
A B C D E
REVISION 1.0 - First release of 440LX PCISet schematics. REVISION 1.2 - Update of Rev 1.1 440LX PCISet schematics. REVISION 1.3 - Update of Rev 1.2 440LX PCISet schematics. REVISION 1.4 - Update of Rev 1.3 440LX
PCIset schematics.
REVISION 1.1 - Update of Rev 1.0 440LX PCISet schematics. PAGE 3 : Slot 1 pin B12, UP#, now no-connect. PAGE 3 : Slot 1 pinout changed : pin B01 from RESERVED
to EMI; pin B15 from FANFAIL# to RESERVED; PAGE 3 : Pullups on SLP#, IERR# and
PAGE 4 : Slot 1 pin B109, VCC, now no-connect. TESTHI moved to Page 28.
PAGE 3 : TESTHI pulled to 2.5 volts thru 220 ohms. pin B21 from EMI to 100/66#; pin B100 from
PAGE 5 : New CK3D pinout used for Host/DRAM/PCI RESERVED to EMI; pin B101 from EMI to S_O#.
clock. Connected signal SLP# from PIIX4 to Slot 1 PAGE 4 : VID[4:0] jumpers pulled to
PAGE 5 : Pinout of 20-pin I/O clock syntheszer to support sleep state. VCC instead of VCC3.
4 device updated. REFOUT routed to XTALIN of CKIO, crystal 4
circuit removed from CKIO XTALIN/OUT. PAGE 4 : Added LM75 Thermal Sensor device to THERM#
and SMB bus. PAGE 5 : Series termination changed
330 ohm pullup to 2.5 volts added 10 ohm series termination added to clock from 10 ohms to 22 ohms on
to PREQ#0. outputs. Added zero ohm resistors and jumpers to SDRAM-I/O clocks and 33 ohms
Pullups on PREQ#[3:1], SMBDATA, and VID[4:0] for voltage select on VRM. on all other clocks.
MECC0 and Freq. Sel. jumper. removed, Sel
SMBCLK deleted. pin pulled up. Connected pin B101 to GND.
PAGE 6 : VCCA pin R3 renamed VCC.
PG 6,7,8 : PAC ballout as of 9-26-96 used. PG 9,10,11 : DIMM SA[2:0] changed to match S.V. board Connected pin B109 to VCC ( 5 volts ). AGND pin R5 renamed GND.
for BIOS compatibility. DIMM0=2H, VCC pins AD12 & R4 added
CKE from PAC buffered with 74LVC245 PAGE 7 : PAC pin W4 name changed from DBF# to RBF#. to list of VCC pins on part.
DIMM1=4H, DIMM2=0H.
CMOS device. PAGE 12 : Signal renamed from DBF# to RBF# also.
PIIX4 pinout modified, GPI8/HCT# renamed JP2 changed to 3-pin jumper.
PG 9,10,11 : MAA11 routed to DIMM SA0, MAA12 to GPI8/THERM#. PG 9,10,11 : DIMM SA[2:0] changed to DIMM0=0H, DIMM1=1H, Pulldown R236 added to config
PAC with IOQD = MAX.
SA1, MAA13 to A11. PCI REQ#[3:0] routed to pullups only. DIMM2=2H.
DIMM pins 31 and 44 grounded and pin PAGE 13 : Added 2 jumpers,’HCT14 and ’HC32 PAGE 13 : Removed resistor NS1 from PIIX4 RTC crystal PG 9,10,11 : PCIRST routed through U14,
48 -> WEx# for EDO DIMMs. to A20M# from PIIX4. circuit. 74ALS05, to OE pins on all
DIMM modules to disable
DIMM control signals ( WEx#, SRASx#, Schottky diodes converted to dual Signal GPI17 named incorrectly for PIIX4 pin MECC[7:0] output during
SCASx#, RCSAx#, and CDQxx# ) for DIMMs Schottky diodes. J19, changed to GPI7 and pulled to 3.3V board reset.
0 and 2 swapped. Renamed IDE interface signals on through 2.7K.
the PIIX4 and IDE page. Device U5 changed from 74HC14 to 74LVC14 PAGE 13 : Added R234 & R235 to PIIX4
SMBus address starts from 02H on DIMMs
for 3V compatibility. RTC crystal inputs.
( SA2:0 ). PAGE 14 : Added crystal and 2 caps to XTAL
circuit of Ultra I/O. Removed JP3, route RTC_BAT direct to PIIX4, GPO0 connected to signal
PAGE 11 : placed 0 ohm in series to SMC input. Added FAN_ON instead of TP1.
3 CDQA#x signals re-ordered on the pins of PAGE 15 : Deleted 74AS07 buffers and pullups 3
DIMM connector #2. JP19 to clear CMOS. U5A changed to 74HCT14
on PIRQ#x .
Removed JP11 & 12, U21 & U23. A20M# circuit powered by 5VSB on signal
PAGE 13 : SUSCLK pin on PIIX4 became no-connect. SMBCLK connected to pin B66,SMBDATA not needed for B-0 PIIX4 units. B_SUSC#.
to A66. PAGE 14 :
IRQ#8 now shown as a bi-directional signal. Added 74AS07 gate to IRQ#8 to convert from
5V to 3V_STBY. PAGE 15 : SMBDATA & SMBCLK no longer
’ALS08 and ’07 deleted because INIT# on PAC PAGE 20 : Header broken into 2 USB connectors. routed to AGP connector.
PAGE 15 : Added 74AS07 gates with 4.7K pullups
is now OD output. Polarity symbols added to polarized caps. to 3.3V on PIRQ#A and PIRQ#B. PAGE 26 :
CONFIG2 pin on PIIX4 pulled to ground with Circuitry on signals PWRBT#,
PAGE 25 : UP# now no-connect on Slot1, pulled up Pin A66 name changed, SMB1 -> SMBDATA, PWROK, RSMRST# and FAN_ON
8.2K resistor.
on VRM. B66 name changed, SMB0 -> SMBCLOCK. modified and converted from
RCIN# name changed to KBRST# and pulled 3V_STBY to 5VSB.
PAGE 26 : External SMI jumper and circuit deleted PAGE 16,17 : Added pullups to SBO, SDONE, TMS & TDI,
to 3.3V thru 8.2K.
(jumper, U6B ’ALS08, U12F ’F07, debounce pulldowns to TRST# & TCK to comply with PAGE 28 :
Signal A20GATE pulled to 3.3V thru 8.2K Added pullups for SLP#,IERR#
circuit) PCI 2.1 Spec. and TESTHI. Added note about
resistor. PWROK circuit modified : U5C,D & E from Changed PCI connector IDSELs from AD28 - 31 resistor changes for LAI use.
74HC14 to 74ALS05 powered by VCC, U17 to AD26, AD27, AD29, AD31.
PAGE 14 : OSC0 clock to PIIX4 deleted due to redundancy.
(74HC32) deleted. PAGE 25 : Changed 2.5V generation from LT1587 to LT1575 PAGE 29 : Added unused 74AS07 gates.
XTAL1 input pulled up to VCC through 8.2K R120 & R124 changed to 8.1K on PWROK plus power FET and associated circuit.
resistor. circuit.
VRM8 pinout changed, pin B5 from UP# to
KEYLOCK# input pulled up to VCC through 8.2K R126 replaced with Zener diode, R123 RESERVED. Pullup R104 deleted.
resistor. changed from 3.48K to 410 ohm on 3V_STBY PAGE 26 : Removed voltage divider resistors R120, 124,
Infrared header rewired, IRRX - pin 1, circuit.
201 & 202 on RSMRST# and PWROK .
IRTX - pin2. C91 on RSMRST# changed from 0.01uF
2 to 1.0uF. Replaced three 74ALS05 gates wire-ored with 2
PAGE 15 : SMB0 & SMB1 pins on AGP connector now 74HC10 and 74F07 on POWERGOOD circuit.
RSMRST# now powered from 5VSB, added 2
noconnects. ’HCT14 gates and voltage divider to Device U5 changed from 74HC14 to 74LVC14,
PAGE 18 : New symbol used for ISA connectors. circuit. RSMRST# powered by 3V_STBY .
PAGE 19 : Pullup on SDIOR# moved to SIORDY. Deleted R168 & C96, added 2 ’HC14 gates R123 changed from 410 to 56 ohmon 3V_STBY,
to PWROK from power connector. R125 changed from 1K to 22K on RSMRST#.
PAGE 21 : Deleted 0 ohm resistors R98 and R99, updated CPU fan header changed to 3-pin header. PAGE 28 : PCI control pullups changed to 2.7K -> 5V
jumper tables. from 8.2K -> 3.3V. GNTx still pulled to
Added 0.1 uF cap for debounce to PWR_BTN
FLASH changed to TSOP pinout instead of PSOP. 3.3V thru 8.2K.
circuit.
GPAR pulled to 3.3V through 8.2K per DCN #70.
PAGE 26 : Capacitor on CPU Fan header changed from PAGE 28 : All PCI control signals pulled through
470pF to 0.1uF. 8.2K to 3.3V. RP56 broken into discrete resistors for AGP
layout considerations. R133 - R138 converted
POWEROK circuitry revised with HC14 & HC32 PIPE# and DBF# pulled to 3.3V through
from 10K to 8.2K.
replacing HCT14 & F32 and power from 3.3V 8.2K.
RP66 broken into discrete resistors. SMBDATA
Standby. GPI1 and PX4_CFG1 pulled to 3V_STBY and SMBCLK pulled to 3.3V thru 8.2K.
thru 8.2K. PAGE 29 :
PAGE 27 : Swapped signals PX4_INTR and PX4_A20M# on R-Pack added to pull IRQ1 to VCC thru 8.2K.
74FCT3244 and 7407 buffers. RP55, 57 & 58 changed from 1K to 2.7K.
Pullup on ZEROWS#, MEMCS16# & IOCS16#
Pullups on PCI control signals changed from PAGE 29 : IRQ12 pulled to 5.0V through 8.2K. changed from 300 ohm to 1K.
PAGE 28 :
10K to 2.7K. Pullup on REFRESH# changed from 300
PAGE 29 : Pullup on REFRESH# changed from 300 to 1K. to 1K ohms.
1 IRQ8# now pulled to 3V_STBY thru 8.2K. 1
Unused gates added to ISA pullup page. INTEL CORPORATION

FOLSOM, CA 95630
Title
REVISION HISTORY

Custom
Intel 440LX PCIset 1.4
Date: Sheet 33 of 33
A B C D E
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Intel 440lx r1.4 Schematics

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A B C D E

440LX CUSTOMER REFERENCE DESIGN

TITLE PAGE OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR

VRM 25 Philips Corporation.

Size Document Number Rev

THIS DRAWING CONTAINS INFORMATION

CONN. 492 BGA

2 USB CONN. PGS. 16,17

PGS. 12,13 ADDR/DATA

Size Document Number Rev

Date: Thursday, May 07, 1998 Sheet 2 of 33

VCCVID VTT VTT

B01 EMI VCC_VTT A01

0 0 0 PCI COMPONENTS DIVISION

Size Document Number Rev

Date: Thursday, May 07, 1998 Sheet 3 of 33

5,6,27 HRESET# B74 RESET# GND A74

LM75 IS 3.3 VOLT THERMAL SENSOR.

VCC VCC3 VCC3

JP14 1 SEL_VID0 R207 U25

Size Document Number Rev

Date: Thursday, May 07, 1998 Sheet 4 of 33

PCI COMPONENTS DIVISION

Date: Thursday, May 07, 1998 Sheet 5 of 33

5 PACHCLK T2 AF11 SRAS#0 11

FOR MAX IOQ DEPTH.

Size Document Number Rev

Date: Thursday, May 07, 1998 Sheet 6 of 33

12,16,17,28 FRAME# C7 P1 GFRAME# 15,28

Size Document Number Rev

Date: Thursday, May 07, 1998 Sheet 7 of 33

MEMORY DATA BUS

HOST DATA BUS

Size Document Number Rev

Date: Thursday, May 07, 1998 Sheet 8 of 33

DIMM CONNECTOR 0 VCC3 VCC3

6 MAB11 MAB11 122 82 SMBDATA 4,5,10,11,13,28

108 163 DIMMHCLK3 5

B_PCIRST 10,11 INTEL CORPORATION

PCI COMPONENTS DIVISION

Size Document Number Rev

Date: Thursday, May 07, 1998 Sheet 9 of 33

6,11 MAA11 MAA11 122 82 SMBDATA 4,5,9,11,13,28

THIS DRAWING CONTAINS INFORMATION

PCI COMPONENTS DIVISION

Size Document Number Rev

Date: Thursday, May 07, 1998 Sheet 10 of 33

6,10 MAA11 MAA11 122 82 SMBDATA 4,5,9,10,13,28

108 163 DIMMHCLK11 5

THIS DRAWING CONTAINS INFORMATION

PCI COMPONENTS DIVISION

Size Document Number Rev

Date: Thursday, May 07, 1998 Sheet 11 of 33

Size Document Number Rev

Date: Thursday, May 07, 1998 Sheet 12 of 33

VCC3 VCC3 3V_STBY

28 PX4_CFG1 CONFIG1 GPO30

Size Document Number Rev

Date: Thursday, May 07, 1998 Sheet 13 of 33

NOTE: NS6 IS DEFAULT NO-STUFF

THIS DRAWING CONTAINS INFORMATION

Date: Thursday, May 07, 1998 Sheet 14 of 33

VCC3 VCC3 J6 VCC3 VCC3

7,28 GREQ# B8 A8 GGNT# 7,28