Tuesday, October 24, 2017

Experiment 7: VHDL Code for FUNCTION BT15ECE021 BT15ECE039

VHDL CODE FOR FUNCTION

Objective
To implement VHDL Codes for a FUNCTION for following cases :

1. Binary to Integer Conversion

2. 4 bit Adder to store 5 bit Output

And Obtain the RTL view for these circuits. Simulate and Synthesize all the Codes.

Codes

1. Binary to Integer Conversion

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

ENTITY conv_int IS
PORT ( a: IN integer range 0 to 255;
y: OUT std_logic_vector(7 downto 0));
END conv_int;

ARCHITECTURE my_arch OF conv_int IS

function convert(int : integer)
return std_logic_vector is

variable temp, int1: integer range 0 to 255;

variable bin: std_logic_vector(7 downto 0);
variable i,j: integer;
begin
int1 := int;
for i in 0 to 7 loop
temp := int1 / 2;
j := int1 mod 2;
int1 := temp;
if j = 0 then
bin(i) := '0';
else
bin(i) := '1';
end if;
end loop;
Tuesday, October 24, 2017
Experiment 7: VHDL Code for FUNCTION BT15ECE021 BT15ECE039
return bin;
end convert;

begin
y <= convert(a);
end my_arch;

2. 4 bit Adder to store 5 bit Output

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity add4bit is
port(x,y :in std_logic_vector(3 downto 0);
z: in std_logic;
s: out std_logic_vector(4 downto 0));
end entity;

architecture behave of add4bit is

function addf(a,b: std_logic_vector(3 downto 0); carry: std_logic)
return std_logic_vector is
variable sum: std_logic_vector(4 downto 0);
variable cout: std_logic;
variable cin: std_logic := carry;
begin
for i in 0 to 3 loop
sum(i) := (a(i) xor b(i)) xor cin;
cout := (a(i) and b(i)) or (a(i) and cin) or (b(i) and cin);
cin := cout;
end loop;
sum(4) := cout;
return sum;
end addf;
begin
s<= addf(x,y,z);
end behave;
Input

We force desired inputs to each of these cases to get our desired output
Tuesday, October 24, 2017
Experiment 7: VHDL Code for FUNCTION BT15ECE021 BT15ECE039

Output

1. Binary to Integer Conversion

a[7..0] y[7..0]
Tuesday, October 24, 2017
Experiment 7: VHDL Code for FUNCTION BT15ECE021 BT15ECE039

a[7]~input y[7]~output

a[0..7] I O I O

IO_IBUF IO_OBUF

a[6]~input y[6]~output

I O I O

IO_IBUF IO_OBUF

a[5]~input y[5]~output

I O I O

IO_IBUF IO_OBUF

a[4]~input y[4]~output

I O I O

IO_IBUF IO_OBUF

a[3]~input y[3]~output

y[0..7]
I O I O

IO_IBUF IO_OBUF

a[2]~input y[2]~output

I O I O

IO_IBUF IO_OBUF

a[1]~input y[1]~output

I O I O

IO_IBUF IO_OBUF

a[0]~input y[0]~output

I O I O

IO_IBUF IO_OBUF

2. 4 bit Adder for 5 bit output

Tuesday, October 24, 2017
Experiment 7: VHDL Code for FUNCTION BT15ECE021 BT15ECE039

cout~8
cout~9
cout~13
cout~14
cout~18
cout~3 cout~6
cout~19
y[3..0]
cout~11
z
cout~16
cout~0 cout~4 s[4..0]
sum~3
x[3..0]
sum~5

cout~1 sum~7

cout~5

cout~10

cout~15

sum~1

y[0]~input
cout~21
cout~22
y[0..3] I O DATAA
COMBOUT DATAA cout~24
DATAB
DATAB cout~25
IO_IBUF COMBOUT DATAA s[4]~output
LOGIC_CELL_COMB (8888) DATAC COMBOUT DATAA
DATAB
x[0]~input DATAD DATAB
COMBOUT I O
LOGIC_CELL_COMB (FEE0) LOGIC_CELL_COMB (8888) DATAC

x[0..3] I O DATAD
sum~3 IO_OBUF s[0..4]
s[1]~output LOGIC_CELL_COMB (FEE0)
DATAA
IO_IBUF
DATAB sum~7
COMBOUT I O s[3]~output
DATAC DATAA

cout~20 DATAD DATAB

IO_OBUF COMBOUT I O
z I z~input O DATAA LOGIC_CELL_COMB (9996) DATAC

DATAB COMBOUT DATAD

IO_OBUF
IO_IBUF DATAC LOGIC_CELL_COMB (9996)

LOGIC_CELL_COMB (A8A8)
x[1]~input sum~9 s[2]~output
sum~8 s[0]~output DATAA

I O DATAA DATAB COMBOUT I O

DATAB COMBOUT I O DATAC

IO_IBUF DATAC LOGIC_CELL_COMB (9696) IO_OBUF

LOGIC_CELL_COMB (9696) IO_OBUF

y[1]~input

I O

IO_IBUF

x[2]~input

I O

IO_IBUF

y[2]~input
cout~23
I O DATAA

DATAB COMBOUT

IO_IBUF DATAC

LOGIC_CELL_COMB (A8A8)
x[3]~input

I O

IO_IBUF

y[3]~input

I O

IO_IBUF
Tuesday, October 24, 2017
Experiment 7: VHDL Code for FUNCTION BT15ECE021 BT15ECE039
Result

VHDL Programs have been implemented as per the directed objective.

The codes have been simulated and synthesized in Altera Quartus to obtain the RTL view and
Technology Map alongwith the Waveforms.