DESIGNING OF TEST BENCH FOR IP CORE AS PER DO254

INTRODUCTION
1. VHDL:

VHSIC is Very High Speed Integrated Circuit Hardware Description language is

a hardware description language used in electronic design automation to
describe digital and mixed-signal systems such as field-programmable gate arrays
(FPGA) and integrated circuits. VHDL has become popular for use in design
entry in CAD system.CAD tools are used in synthesizing VHDL code into a
hardware implementation of the described circuit. VHDL has constructs which
enable to express the concurrent or sequential behavior of digital systems with or
without timing. It also allows interconnecting components.

2. DO254:

DO-254/ED-80 is a means of compliance to aviation regulations for all airborne

electronic hardware classified as custom micro-coded devices such as FPGAs,
ASICs and PLDs. These devices are often as complex as software controlled
microprocessor-based systems; therefore, they need a stringent development
approach to satisfy airworthiness requirements. The main purpose of the guidance
is to ensure that the device built meets the requirements and safely performs all
intended functions under normal and abnormal operating conditions . In order to
obtain compliance, the applicant must implement the stringent development and
verification process of DO-254, and satisfy the underlying objectives at the device
level.
3.IP core:
An IP (intellectual property) core is a block of logic or data that is used in
making a field programmable gate array FPGA or application-specific integrated
circuit ASIC for a product. As essential elements of design re-use, IP cores are part
 DESIGNING OF TEST BENCH FOR IP CORE AS PER DO254

of the growing electronic design automation EDA industry trend towards repeated
use of previously designed components. Ideally, an IP core should be entirely
portable - that is, able to easily be inserted into any vendor technology or design
methodology. Universal Asynchronous Receiver/Transmitter (UART), central
processing units (CPU), Ethernet controllers, Universal Serial Bus (USB) and PCI
interfaces are all examples of IP cores. Intellectual Property (IP) systems with
dynamic runtime reconfiguration capabilities, in order to mitigate component
obsolescence and to provide increased flexibility and decreased design time.
4.Test Bench:
To simulate your design, you need both the design under test (DUT) or unit
under test (UUT) and the stimulus provided by the test bench. A test bench is HDL
code that allows you to provide a documented, repeatable set of stimuli that is
portable across different simulators. A test bench can be as simple as a file with
clock and input data or a more complicated file that includes error checking, file
input and output, and conditional testing.
5. Design vs. Test Bench:

 Design is the creation of a plan or convention for the construction of an

object, system or measurable human interaction.

 A test bench is a HDL code-but it designed specifically for testing of

another piece of HDL code.

 Original design code don’t have any specific timing info on input signal
high/low.

 Test bench is nothing to do with the timing but it provides the clock and
address to the memory to check the output with different test cases.
DESIGNING OF TEST BENCH FOR IP CORE AS PER DO254

LITERATURE SURVEY
1. Rabie Ben Atitallah; Venkatasubramanian Viswanathan; Nicolas
Belanger; Jean-Luc Dekeyser: “FPGA-Centric Design Process for Avionic
Simulation and Test” IEEE Transactions on Aerospace and Electronic
Systems Year: 2017, Volume: PP, Issue: 99. Real-time computing systems
are increasingly used in aerospace and avionic industries. In the face of
power challenge, performance requirements and demands for higher
flexibility, hardware designers are directed towards reconfigurable
computing using FPGAs (Field Programmable Gate Arrays) that offer high
computation rates per watt and adaptability to the application constraints.
2. P. A. McCabe: “VHDL-based system simulation and performance
measurement” Proceedings of VHDL International Users Forum Year:1994
Pages: 48 – 57 IEEE Conference Publications. The system simulation
approach is discussed, including simulation model types, their development
and validation, and test-bench structure. Additionally, techniques for
performance measurement and analysis of the simulation results are
discussed, which can be used to improve the system design at the chip and
board levels. Finally, conclusions drawn from this effort are presented, along
with indications of future work to be performed.
3. Satish Chandra Tiwari; Mohammad Ayoub Khan; Kunwar
Singh; Ankur Sangal: “Standard test bench for optimization and
characterization of combinational circuits”. IEEE International Conference
on Signal Processing, Computing and Control Year: 2012. Choice of a
combinational circuit among large number of circuits having same
functionality has been always a complex and time consuming task for digital
designers. The paper proposes a standard test bench for optimization and
DESIGNING OF TEST BENCH FOR IP CORE AS PER DO254

characterization of combinational circuits. Finally using the proposed

methodology a combinational circuitry has been successfully characterized.
4. M. F. Sullivan; J. O. Bondi; D. J. Kopca; N. D. Patel: “Integrating
hierarchical test benches into an evolving VHDL design environment”
Proceedings of VHDL International Users Forum Year: 1994. Flexible,
hierarchical test benches are developed naturally as part of the normal model
development process. The integration of these tool-automated VHDL test
benches is described. Automated development of VHDL test benches and
integration of test bench development into the VHDL modeling process are
being employed successfully. The novel hierarchical structuring technique
described integrates automated VHDL test bench capabilities with the
historical design environment.

5. Vacius Jusas; Tomas Neverdauskas : “Stimuli generator

for testing processes in VHDL” 2014 NORCHIP IEEE Conference
Publications. Verification is the most crucial part of the chip design process.
Test benches, which are used to test VHDL code, need perform efficiently
and effectively. Each process in VHDL is executed in parallel. This concept
introduces problems of how to test and verify complex systems. We present
the new framework Test Bench Multi that is able to generate test stimuli for
parallel VHDL designs. The experiments were carried out on synthesizable
VHDL circuits at the behavioral level. The obtained code coverage results
were confirmed in the real implementation using Xilinx FPGA hardware.
 DESIGNING OF TEST BENCH FOR IP CORE AS PER DO254

3. SOFTWARE TOOLS

XILINX:
The Integrated Software Environment (ISE®) is the Xilinx® design software suite
that allows you to take your design from design entry through Xilinx device
programming. The ISE Project Navigator manages and processes your design
through the following steps in the ISE design flow.

1. Design Entry: Design entry is the first step in the ISE design flow. During
design entry, you create your source files based on your design objectives.
You can create your top-level design file using a Hardware Description
Language (HDL), such as VHDL, Verilog, or ABEL, or using a schematic.
You can use multiple formats for the lower-level source files in your design.
2. Synthesis: After design entry and optional simulation, you run synthesis.
During this step, VHDL, Verilog, or mixed language designs become netlist
files that are accepted as input to the implementation step.
3. Implementation: After synthesis, you run design implementation, which
converts the logical design into a physical file format that can be
downloaded to the selected target device. From Project Navigator, you can
run the implementation process in one step, or you can run each of the
implementation processes separately. Implementation processes vary
depending on whether you are targeting a Field Programmable Gate Array
(FPGA) or a Complex Programmable Logic Device (CPLD).
4. Verification: verify the functionality of your design at several points in the
design flow. You can use simulator software to verify the functionality and
timing of your design or a portion of your design. The simulator interprets
VHDL or Verilog code into circuit functionality and displays logical results
DESIGNING OF TEST BENCH FOR IP CORE AS PER DO254

of the described HDL to determine correct circuit operation. Simulation

allows you to create and verify complex functions in a relatively small
amount of time. You can also run in-circuit verification after programming
your device.
5. Device Configuration: After generating a programming file, you configure
your device. During configuration, you generate configuration files and
download the programming files from a host computer to a Xilinx device.
6. Additional Resources: For additional high-level information, see the
following resources:
 Project Navigator overview describes how to process your design
using project Navigator.
 FPGA Design Flow overview describes the steps in the FPGA design
flow.
 CPLD Design Flow overview explains the basic steps for processing a
CPLD design.
 ISE Quick Start Tutorial helps you get started using the ISE software.
 DESIGNING OF TEST BENCH FOR IP CORE AS PER DO254

Design Flow: