ISRO PAX 301 Rev1

ISRO-PAX-301
Issue 3, April 2013
Design Requirements for

Printed Circuit Board Layout
ISRO Reliability Standards
Directorate of Systems Reliability and Quality, ISRO Headquarters, Bangalore

¦ÉÉ®úiÉÒªÉ +xiÉÊ®úIÉ +xÉÖºÉÆvÉÉxÉ ºÉÆMÉ`öxÉ Indian Space Research Organisation
+xiÉÊ®úIÉ Ê´É¦ÉÉMÉ Department of Space
Government of India
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Antariksh Bhavan
+xiÉÊ®úIÉ ¦É´ÉxÉ
New BEL Road, Bangalore - 560 231, India
xªÉÚ ¤ÉÒ.<Ç.B±É. ®úÉäb÷, ¤ÉåMÉ±ÉÚ®ú-560 231, ¦ÉÉ®úiÉ Telephone : +91-80-2341 5241/2217 2333
nÚ®¦ÉÉ¹É: +91-80-2341 5241/2217 2333 Fax : +91-80-23415328
¡èòCºÉ: +91-80-23415328 e-mail : chairman@isro.gov.in
Dr. K. Radhakrishnan
Chairman
MESSAGE
ISRO Reliability Standards, addressing the various disciplines of Engineering, have been
in vogue for almost three decades now. These standards are followed across ISRO
centres as well as external work centers for design, fabrication, testing, analysis and
other processes involved in the realization of Launch Vehicles, Spacecraft, Space
Applications, Ground support systems and other launch infrastructure. The need for
standardization of processes towards achieving high reliability systems can never be
over emphasized, and ISRO Reliability Standards are just an attempt towards explicitly
stating this.
With the advent of newer techniques and with the evolution of technology itself, over the last 30 years, it
has become essential to revisit the existing ISRO Reliability Standards and revise and update the standards
wherever essential. Towards this, the Directorate of Systems Reliability and Quality (DSRQ) at ISRO
Headquarters has taken an initiative to re-invigorate the reach and visibility of ISRO Reliability standards
across all the Centres of ISRO. Specific Inter-centre teams were formed to revise each of these documents
and I would like to place on record their commendable efforts in bringing out these documents.
There is a pressing need for ensuring uniformity of practices, across various functions of design, fabrication,
testing, review mechanisms etc., across the centres and units of ISRO. Towards this goal, the mandatory
adoption of ISRO Reliability Standards will ensure standardization in quality processes and products. I am
certain that this will go a long way towards ensuring overall system level Quality and Reliability and in
achieving the goal of zero defects in the delivery of space systems of ISRO.
K Radhakrishnan
Chairman, ISRO
Directorate of Systems Reliability & Quality
ISRO Headquarters
Antariksh Bhavan
New BEL Road, Bangalore -560231
Ph :080 - 2341 5414
Fax :080 – 2341 2826
S Selvaraju Cell:09448397704
Senior Advisor, Systems Reliability and Quality Email: sselvaraju@isro.gov.in
PREFACE
ISRO Reliability standards are a result of the need for standardization of processes towards achieving high
reliability systems. The transfer of knowledge and techniques from the seniors to their successors is best
done with proper documentation and checklists translating the entire know-how into black and white.
Various design aspects of Printed Circuit Boards (PCB) that employ both surface mount devices and
through-hole devices are addressed in this document, ‘Design requirements for Printed Circuit Board
layout’. Considering the advancement of technology, this document has undergone a total makeover and
large scale revision compared to its previous version. Mandatory standards for making the master pattern,
productionisation, footprint design, electrical design factors and inspection of PCB layout are addressed
in detail. Details of preparation and inspection of computer aided design layouts including dimensions and
tolerances are also brought out. Standards for generation of design output and considerations for generation
of land pattern designs for various parts are also elucidated. The involvement of quality professionals and
the layout design process certification plan including re-certification and renewal are elaborated.
It is deemed essential that these standards be strictly adhered to, in order to ensure uniformity of practices
across ISRO centers and achieve zero defects in the delivery of space systems.
I am grateful to Chairman ISRO, for being the source of inspiration in the release of these documents.
Thanks are also due to the centre Directors for their encouragement. I am also thankful to the Heads of
SR Entities/Groups of various ISRO centres for their relentless support and guidance. I am also indebted
to the members of the Integrated Product Assurance Board (IPAB) for the meticulous review of these
documents. I also owe gratitude to the task team members and other experts for putting efforts in the
realization of these documents. I am glad to carry forward this rich lineage of ISRO reliability standards,
championed by Shri R Aravamudan, a revered pioneer in the area of Quality & Reliability in ISRO.
S Selvaraju
Sr. Advisor (SRQ)
List of CONTENTS
1 INTRODUCTION 01
1.1 Scope 01
1.2 Applicable documents 01
1.3 Order of precedence 02
2 DIMENSIONS AND TOLERANCES FOR LAND PATTERNS 03

2.1 Units 03
2.2 Component and land pattern tolerancing 03
2.3 Standardization 03
3 PRODUCTIONISATION 04
3.1 Design for large volumes 04
3.2 Standard component selection 04
3.3 Assembly considerations 04
3.4 Vias as test points 04
3.5 Component placement file 04
3.6 Component placement considerations 05
3.7 Grid-based component placement 05
3.8 Double sided component mounting 05
3.9 Stencil preparation 05
3.10 Fiducial marks & Other markers 05
3.10.1 Global Fiducials 05
3.10.2 Local Fiducials 05
3.10.3 Other Markers 06
3.11 Standard fabrication allowances 06
3.12 Soldermask 06
3.12.1 Soldermask clearances 06
4 REQUIREMENTS 07
4.1 Facility requirements 07
4.2 PCB design software requirements 07
5 LAYOUT GUIDELINE 08
5.1 Design technology 08
5.2 Functional correctness of schematic circuit 08
5.2.1 Connectivity correctness inspection 08
5.2.2 Signal naming conventions 08
5.3 Net properties 09
5.3.1 Net width and spacing 09
5.4 Schematic 10
5.4.1 PCB design library 13
5.4.2 Schematic drawing header 13
5.4.3 Schematic design export to PCB design 14
5.4.4 Traveler card of PCB design process 14
5.5 Design rules 15
5.6 Buried via pairs 16
5.7 Template / document file 16
5.8 Design file name 17
5.9 Check-plot size 17
5.10 Placement plot definitions 17
5.11 Plot definitions 17
5.11.1 Pads 18
5.11.2 Vias 18
5.12 Selection of grid 18
5.13 View of the Layout 18
5.14 Conductive Pattern Shape 18
5.15 PCB layout data sheet 21
5.16 Solderable pads 22
5.17 Identification 22
5.17.1 General 22
5.17.2 PCB identification 23
5.17.3 Component identification 23
5.18 List of identifications that have to appear on the finished PCBs 25
5.19 Pattern and pad identification 25
6 ELECTRICAL DESIGN FACTORS 27

6.1 Current carrying capacity, track width 27
6.2 Power plane designs 27
6.3 Current carrying capacity in pulsed mode operations 28
6.4 Spacing between conductors 28
6.5 Surface conductors 28
6.6 Vias within component land pattern 28
6.7 Component mounting provisions 29
6.8 Turret mounting 30
6.9 Torroidal transformer / Coil 30
6.10 Radiation shielding 31
6.11 Additional requirements 31
6.12 Component mounting holes 31
6.12.1 General 31
6.13 Hole placement requirement 32
6.13.1 Hole location 32
6.13.2 Vias under components 32
6.13.3 Thermal vias for metal core boards 32
6.14 PCB design Documentation 32
6.14.1 Card number 32
6.14.2 Mechanical drawing 32
6.14.3 Layout data sheet 32
6.14.4 Component list 33
6.15 Checklist for the designer 35
7 DESIGN OUTPUT GENERATION 36

7.1 Gerber file generation 36
7.1.1 Layers required to be made ON 36
7.2 Report generation 36
7.2.1 Board status report 36
7.2.2 Assignment report 36
7.2.3 Symbol availability report 36
7.2.4 Drill tool table report 37
7.3 Drill file generation 37
7.4 Fabrication and assembly wiring details 38
7.4.1 Drilling details print 38
7.4.2 Component marking print 38
7.4.3 PTH marking print 38
7.4.4 Ordering data for PCB 38
7.5 PCB design folder generation - hard copy 40
7.6 Output CD Preparation 40
8 INSPECTION OF PCB LAYOUTS 42

8.1 General 42
8.2 On-screen inspection 42
8.2.1 Gerber /NC drill/NC rout file inspection 42
8.3 PCB Layout inspection check lists 42
8.3.1 Checklist for schematic symbol 43
8.3.2 Checklist for foot print inspection 43
8.3.3 Checklist for part inspection 43
8.3.4 Checklist for schematic drawing 44
8.3.5 Checklist for design initiation 45
8.3.6 Checklist of items required for final layout approval 45
8.3.7 Checklist for component list 46
8.3.8 Checklist for component verification 47
8.3.9 Checklist for mechanical details 47
8.3.10 Checklist for PCB layout design file 48
8.3.11 Checklist for conductors 50
8.3.12 Checklist for clearance 50
8.3.13 Checklist for gerber files 51
8.3.14 Checklist for NC drill/rout files 53
8.3.15 Checklist for Component marking print 53
8.3.16 Checklist for PTH marking print 53
8.3.17 Checklist for CD data contents 54
9 MASTER PATTERN 55
9.1 Introduction 55
9.2 Requirements of Master pattern shall completely match to the approved gerber file 55
9.3 Material for master patterns and its tolerance 55
9.4 Handling and storage 55
9.5 Preconditioning of films 55
9.6 Mis-registration 55
9.7 Checklists for Master Pattern 56
10 Consideration for Generation of Land Pattern Designs 58

10.1 Introduction 58
10.2 Considerations for land pattern design 58
10.3 Axial lead - passive/active components 58
10.4 Axial lead passive components with welded leads and with lacing holes 59
10.5 Axial lead passive components without welded leads and with lacing holes 59
10.6 Radial lead passive components 59
10.7 Surface mount passive leadless devices 59
10.8 Surface Mount Active Devices with un-formed lead devices 60
10.9 Surface Mount Active Device with formed lead devices 60
10.10 Surface Mount Active Device with formed J-leaded devices 60
10.11 Other considerations 61
11 LAYOUT DESIGN PROCESS CERTIFICATION PLAN 62

11.1 PCB layout designer / inspector training 62
11.1.1 Course material 62
11.1.2 Course duration 62
11.1.3 Evaluation and certification 62
11.1.4 Maintenance of certification 62
11.2 Re-Certification 63
11.3 Renewal of certification 63
12 TERMS AND DEFINITIONS 65
13 CURRENT CARRYING CAPACITY IN PULSED MODE OPERATIONS 71
14 HIGH SPEED PCB DESIGN GUIDELINES 72

14.1 Critical length 72
14.1.1 Single-ended transmission lines 72
14.1.2 Surface Microstrip 72
14.1.3 Embedded Microstrip (Stripline) 73
14.1.4 Coated Microstrip 73
14.1.5 Differential transmission lines 73
14.2 Ringing 74
14.2.1 Minimize ringing 74
14.3 Overshoot and Undershoot 74
14.4 Reflection, Reasons and its elimination 74
14.4.1 Solutions to eliminate reflections 75
14.5 Cross-Talk 75
14.5.1 Capacitive cross-talk 75
14.5.2 Inductive cross-talk 76
14.5.3 Design techniques to prevent cross talk 76
14.6 Cross talk and its reduction techniques for wires 76
14.7 Clock skew 77
14.8 Design guidelines for LVDS signals 77
14.8.1 Differential Traces 77
14.9 Methods to reduce EMI 78
14.9.1 General Design Rules EMI control 79
14.10 Signal integrity Analysis Reports 81
15 RIGID FLEX PCB DESIGN GUIDELINES 83

15.1 Construction details of a rigid flex PCB 83
15.2 Design features of rigid-flex PCBs 83
15.3 Additional requirements for rigid-flex PCBs 84
16 DESIGN RULES FOR PCB LAYOUT DESIGNS HAVING BGA /CCGA DEVICES 85
16.1 Design rules for PCB layout designs having BGA devices 85
ANNEXURE-1
AXIAL RESISTORS 88
ISRO_RCR05_268 88
ISRO_RCR07_443 88
ISRO_RCR20_593 88
ISRO_RCR32_833 88
ISRO_RCR42_998 88
ISRO_RLR05_278 89
ISRO_RLR07_427 89
ISRO_RLR20_604 89
ISRO_RLR32_833 89
ISRO_RB52_1249 89
ISRO_RNR50_321 90
ISRO_RNR55_443 90
ISRO_RNR60_600 90
ISRO_RNR65_818 90
ISRO_RNR70_1067 90
ISRO_RNC55_438 91
ISRO_RNC60_571 91
ISRO_RNC65_756 91
ISRO_RNC70_1067 91
ISRO_RW69_754 92
ISRO_RW70_564 92
ISRO_RW74_1172 92
ISRO_RW78_2077 92
ISRO_RW79_824 92
ISRO_RWR71_1065 93
ISRO_RWR80_570 93
ISRO_RWR81_397 93
ISRO_RWR82_459 93
ISRO_RWR84_1172 93
ISRO_RWR89_814 93
ISRO_MOX200_462 94
ISRO_MOX300_597 94
ISRO_MOX400-23_672 94
ISRO_MOX750-23_1042 94
SMD RESISTORS 95
ISRO_RM0505_76 95
ISRO_RM0603_81 95
ISRO_RM0705_1OZ _106 95
ISRO_RM0705_2OZ _107 95
ISRO_RM0805_89 95
ISRO_RM1005_100 95
ISRO_RM1206_1OZ _137 95
ISRO_RM1206_2OZ _137 95
ISRO_RM1505_150 96
ISRO_RM2010_200 96
ISRO_RM2208_225 96
ISRO_RM2512_211 96
ISRO_RM0402_43 96
RESISTOR NETWORK 97
ISRO_RNW8_700 97
ISRO_RNW9_800 97
ISRO_RNW10_900 97
ISRO_RCNW10_900 97
ISRO_RCNW11_1000 97
AXIAL CAPACITORS 98
ISRO_CLR@_T1_978 98
ISRO_CLR@_T2_1166 98
ISRO_CSR13A_543 98
ISRO_CSR13B/CSR21C_730 98
ISRO_CSR13C_972 98
ISRO_CSR13D/CSR 21D_1073 98
ISRO_CRH01_850 99
ISRO_CRH01_912 99
ISRO_CRH01/06_1037X200 99
ISRO_CRH01/06_912X250 99
ISRO_CRH01/06_1037X250 99
ISRO_CRH01/06_1037X300 99
ISRO_CRH01/06_1163X300 99
ISRO_CRH01/06_1205X400 100
ISRO_CRH01/06_1455X400 100
ISRO_CRH01/06_1767X400 100
ISRO_CRH01/06_1767X500 100
ISRO_CRH01/06_1809X600 100
ISRO_CRH01/06_2309X600 100
ISRO_CRH01/06_2309X700 100
ISRO_CRH02/07_850X191 101
ISRO_CRH02/07_912X191 101
ISRO_CRH02/07_1037X200 101
ISRO_CRH02/07_1163X200 101
ISRO_CRH02/07_1037X250 101
ISRO_CRH02/07_1163X250 101
ISRO_CRH02/07_1037X300 101
ISRO_CRH02/07_1163X300 101
ISRO_CRH02/07_1205X400 101
ISRO_CRH02/07_1455X400 101
ISRO_CRH02/07_1518X500 102
ISRO_CRH02/07_1767X500 102
ISRO_CRH02/07_1809X600 102
ISRO_CRH02/07_1809X700 102
ISRO_CRH02/07_2309X700 102
ISRO_CRH03/08_850X200 103
ISRO_CRH03/08_912X200 103
ISRO_CRH03/08_1038X200 103
ISRO_CRH03/08_1038X250 103
ISRO_CRH03/08_1163X250 103
ISRO_CRH03/08_1038X300 103
ISRO_CRH03/08_1163X300 103
ISRO_CRH03/08_1413X300 103
ISRO_CRH03/08_1453X400 103
ISRO_CRH03/08_1516X500 103
ISRO_CRH03/08_1560X600 104
ISRO_CRH03/08_1810X600 104
ISRO_CRH03/08_1810X700 104
ISRO_CRH03/08_2310X700 104
ISRO_CRH03/08_2310X750 104
ISRO_CRH03/08_2810X1000 104
ISRO_CYR10_511 105
ISRO_CYR15_636 105
ISRO_CYR20_940 105
ISRO_CYR30_972 105
RADIAL CAPACITORS 107
ISRO_CKR05_200_V 107
ISRO_CKR06_200_V 107
ISRO_CKR05_200_H 108
ISRO_CKR06_200_H 108
ISRO_CMR04_150_H 109
ISRO_CMR08_1050_H 109
ISRO_CMR04_150_V 110
ISRO_CMR08_1050_V 110
SMD CAPACITORS 111

ISRO_CDR31_1OZ_89 111
ISRO_CDR11A_1OZ _84 112
ISRO_CDR13B_1OZ_125 112
ISRO_CDR01_1OZ _94 113
ISRO_CDR01_2OZ _97 113
ISRO_CDR02_1OZ _190 113
ISRO_CDR02_2OZ _190 113
ISRO_CDR03_1OZ _190 113
ISRO_CDR03_2OZ _190 113
ISRO_CDR04_1OZ _190 113
ISRO_CDR04_2OZ _190 113
ISRO_CDR05_1OZ _190 113
ISRO_CDR05_2OZ _190 113
ISRO_CDR06_1OZ _235 113
ISRO_CDR06_2OZ _235 113
ISRO_CWR06A_1OZ_104 114
ISRO_CWR06A_2OZ_107 114
ISRO_CWR06B_1OZ_151 114
ISRO_CWR06B_2OZ_151 114
ISRO_CWR06C_1OZ_200 114
ISRO_CWR06C_2OZ_200 114
ISRO_CWR06D_1OZ_150 114
ISRO_CWR06D_2OZ_150 114
ISRO_CWR06E_1OZ _200 115
ISRO_CWR06E_2OZ _200 115
ISRO_CWR06F_1OZ _220 115
ISRO_CWR06F_2OZ _220 115
ISRO_CWR06G _1OZ _245 115
ISRO_CWR06G_2OZ _245 115
ISRO_CWR06H_1OZ _265 115
ISRO_CWR06H_2OZ _265 115
ISRO_CWR09A_110 116
ISRO_CWR09B_110 116
ISRO_CWR09C_152 116
ISRO_CWR09D_110 116
ISRO_CWR09E_152 116
ISRO_CWR09F_182 116
ISRO_CWR09G_227 116
ISRO_CWR09H_247 116
ISRO_CWR11A_97 117
ISRO_CWR11B_97 117
ISRO_CWR11C_158 117
ISRO_CWR11D_209 117
ISRO_CWR15L_84 118
ISRO_CWR15R_108 118
ISRO_CWR15A_108 118
ISRO_CWR19/29A_110 119
ISRO_CWR19/29B_110 119
ISRO_CWR19/29C_152 119
ISRO_CWR19/29D_110 119
ISRO_CWR19/29E_152 119
ISRO_CWR19/29F_182 119
ISRO_CWR19/29G_227 119
ISRO_CWR19/29H_247 119
ISRO_CWR19/29X_226 119
ISRO_CKS51_134 120
ISRO_CKS52_142 120
ISRO_CKS53_160 120
ISRO_CKS54_204 120
ISRO_ATC0402_1OZ_71 121
ISRO_ATC0402_2OZ_71 121
ISRO_ATC0403_1OZ_88 121
ISRO_ATC0403_2OZ_88 121
ISRO_TYPE 1825_217 122
ISRO_TYPE 2220_233 122
ISRO_CTC21E_C_395 122
ISRO_CTC21E_D_395 122
ISRO_CNC 81-PLE_276 123
ISRO_CH41_323 123
ISRO_CH42_323 123
ISRO_CH43_323 123
ISRO_CH44_323 123
ISRO_CH51-54_400 124
ISRO_CH61-64_551 124
ISRO_CH71-74_600 124
ISRO_CH91-94_785 124
ISRO_MLC1_437 125
ISRO_MLC2_787 125
ISRO_MLC3_437 125
ISRO_MLC4_390 125
ISRO_MLC5_239 125
ISRO_MLC6_1241 125
ISRO_CNC54NEA_400 126
ISRO_CNC54NEB_400 126
ISRO_CNC54NEC_400 126
ISRO_CNC54NED_400 126
AXIAL DIODE 127
ISRO_DO7_432 127
ISRO_DO13_770 127
ISRO_DO13/202 AA _770 127
ISRO_DO14_432 127
ISRO_DO15_486 127
ISRO_DO35_320 127
ISRO_PKG- A_418 127
ISRO_PKG-E_540 127
ISRO_PKG-E_365 127
ISRO_PKG-G_435 127
ISRO_AITC_492 127
ISRO_DO_312 127
ISRO_DO_266 127
SMD DIODES 128

ISRO_PKG-A _ 184 128
ISRO_PKG-B _183 128
ISRO_DO_ 194 128
ISRO_PKG-E _ 238 128
ISRO_PKG-G _ 286 128
ISRO_ PKG-B_196 128
ISRO_SRD _216 128
ISRO_D035_181 129
ISRO-D5A_177 129
ISRO_D5B _ 220 129
ISRO_D5D _221 129
ISRO_MELF-D5B_216 129
ISRO_MELF-CDS_175 129
ISRO_DO213AA_147 129
SMD INDUCTORS 130

ISRO_SESI14/15SR_500 130
ISRO_PA_2OZ _105 130
ISRO_CI_107 130
TRANSISTORS 131
ISRO_TO5-3_ST 131
ISRO_TO18-3_SP 131
ISRO_TO39-3_ST 131
ISRO_TO46-3_SP 131
ISRO_TO72-4_SP 131
ISRO_TO3 132
ISRO_TO66 132
ISRO_TO204AE 132
ISRO_TO78-6 133
ISRO_TO99-8 133
ISRO_TO100-10 133
ISRO_TO8-12 134
ISRO_SOT_75 135
ISRO_SOT_210 136
ISRO_SOT_240 136
ISRO_TO254AA_150 137
ISRO_TO258_100 138
DUAL IN-LINE PACKAGE ICS 139

ISRO_DIP8_300 139
ISRO_DIP14_300 139
ISRO_DIP16_300 139
ISRO_DIP18_300 139
ISRO_DIP20_300 139
ISRO_DIP22_400 139
ISRO_DIP24_300 139
ISRO_DIP24_400 139
ISRO_DIP24_600 139
ISRO_DIP28_300 139
ISRO_DIP28_600 139
ISRO_DIP32_400 139
ISRO_DIP40_600 139
HMC 140
ISRO_HMC14_300 140
ISRO_HMC24_600 140
ISRO_HMC24_1100 140
ISRO_HMC28_600 140
ISRO_HMC34_1100 140
ISRO_HMC38_800 140
ISRO_HMC40_1100 140
ISRO_HMC34_600 141
ISRO_HMC44_1100 142
ISRO_HMC54_1100 143
QUAD FLAT PACK ICS 144
ISRO_QFN16_4.00 144
ISRO_ CQFP16_380 145
ISRO_CLCC20_ 336 146
ISRO_LCC20_ 320 147
ISRO_QFN20_ 4.45 148
ISRO_CQFJ44_ 670 149
ISRO_CQFJ48_10.60 150
ISRO_CQFP52_1116 151
ISRO_QFP56_8.80 152
ISRO_QFP64_13.60 153
ISRO_QFP68_970 154
ISRO_QFP68_1140 155
ISRO_QFP68_1056 156
ISRO_PQFJ84_22.31 158
ISRO_CQFJ84_1300 160
ISRO_MQFP84_1310 161
ISRO_CQFP92_ 57.41 162
ISRO_CQFP100_1510 163
ISRO_CQFP100_16.80 164
ISRO_CQFP128_23.83 165
ISRO_CQFP132_1110A 166
ISRO_CQFP132_1110B 167
ISRO_CQFP132_1110C 168
ISRO_CQFP172_1340 169
ISRO_CQFP172_1310 170
ISRO_CQFP196_1510 171
ISRO_CQFP196_36.62 172
ISRO_CQFP208_33.21 173
ISRO_CQFP228_1710 174
ISRO_PQFP240_34.39 175
ISRO_CQFP256_1620 176
ISRO_MQFP256_1620 177
ISRO_CQFP256_40.00 178
ISRO_CQFP352_52.00 179
DUAL FLAT PACK ICS 180

ISRO_CFP8_200 180
ISRO_CFP8_224 181
ISRO_CFP8_452 182
ISRO_CFP8_6.40 183
ISRO_MFP8_365 184
ISRO_CFP10_400 185
ISRO_CFP10_840 186
ISRO_CFP14_7.90 187
ISRO_CFP14_390A 188
ISRO_CFP14_390B 189
ISRO_CFP14_412 190
ISRO_CFP14_500 191
ISRO_CFP14_1046 192
ISRO_CFP14_1200 193
ISRO_ PFP16_256 194
ISRO_CFP16_390 195
ISRO_CFP16_380 196
ISRO_CFP16_425 197
ISRO_CFP16_430 198
ISRO_CFP16_10.97 199
ISRO_CFP16_460 200
ISRO_PFP20_308 201
ISRO_PFP20_380 202
ISRO_ CFP20_394 203
ISRO_CFP20_425 204
ISRO_CFP20_12.95 205
ISRO_CFP20_550 206
ISRO_CFP24_760 207
ISRO_CFP28_14.22 208
ISRO_CFP28_650 209
ISRO_CFP28_660 210
ISRO_CFP30_1290 211
ISRO_CFP32_453 212
ISRO_CFP32_595 213
ISRO_CFP32_754 214
ISRO_CFP32_812 215
ISRO_CFP36_790 216
ISRO_CFP36_17.13 217
ISRO_CFP36_20.65 218
ISRO_ CFP40_924 219
ISRO_CFP40_935 220
ISRO_CFP48_540 221
ISRO_CFP54_11.08 222
ISRO_CFP64_9.40 223
ISRO_CFP70_1160 224
ISRO_CFP70_1233 225
ISRO_MFP84_30.23 226
RELAY 227
ISRO_E210/215 227
ISRO_EL210/215 227
ISRO_E410/415 228
ISRO_EL410/415 228
ISRO_TO5R_8 229
ISRO_TO5R_10 229
ISRO_GP250_200 230
ISRO_GP250F_200 231
ISRO_GP5_200 232
ISRO_GP5F_200 233
ISRO_3SBC_150 234
ISRO_SCDO1CFY_430 235
CONNECTORS 236
NOMENCLATURE: STANDARD DENSITY FRB CONNECTOR 236
STANDARD DENSITY 90º BENT FRB CONNECTOR 237

ISRO_FRBSD17P/S_RA_1200 237
STANDARD DENSITY STRAIGHT FRB CONNECTORS 239

ISRO_FRBSD17P/S_ST_1200 239
NOMENCLATURE OF HIGH DENSITY FRB CONNECTOR 245
HIGH DENSITY 90º BENT FRB CONNECTOR 246

ISRO_FRBHD26P/S_RA_1200 246
HIGH DENSITY STRAIGHT FRB CONNECTORS 248

ISRO_FRBHD26P/S_ST_1200 248
NOMENCLATURE OF D-TYPE CONNECTOR 252
STANDARD DENSITY 90º BENT D TYPE PLUG CONNECTOR 253

ISRO_SD-RA_ 9P_984 253
ISRO_SD-RA_15P_1312 253
ISRO_SD-RA_25P_1852 253
ISRO_SD-RA_37P_2500 253
ISRO_SD-RA_50P_2406 254
STANDARD DENSITY 90º BENT D TYPE SOCKET CONNECTOR 255

ISRO_SD-RA_9S_984 255
ISRO_SD-RA_15S_1312 255
ISRO_SD-RA_25S_1852 255
ISRO_SD-RA_37S_2500 255
ISRO_SD-RA_50S_2406 256
STANDARD DENSITY STRAIGHT D TYPE PLUG CONNECTOR 258
ISRO_SD-ST_ 9P_984 258
ISRO_SD-ST_15P_1312 258
ISRO_SD-ST_25P_1852 258
ISRO_SD-ST_37P_2500 258
ISRO_SD-ST_50P_2406 259
STANDARD DENSITY STRAIGHT D TYPE SOCKET CONNECTOR 260

ISRO_SD-ST_ 9S_984 260
ISRO_SD-ST_15S_1312 260
ISRO_SD-ST_25S_1852 260
ISRO_SD-ST_37S_2500 260
ISRO_SD-ST_50S_2406 261
HIGH DENSITY 90º BENT D TYPE PLUG CONNECTOR 264

ISRO_HD-RA_ 15P_984 264
ISRO_HD-RA_26P_1312 264
ISRO_HD-RA_44P_1852 264
ISRO_HD-RA_62P_2500 264
ISRO_HD-RA_78P_2406 265
HIGH DENSITY 90º BENT D TYPE SOCKET CONNECTOR 266

ISRO_HD-RA_ 15S_984 266
ISRO_HD-RA_26S_1312 266
ISRO_HD-RA_44S_1852 266
ISRO_HD-RA_62S_2500 266
ISRO_HDRA_78S_2406 267
HIGH DENSITY STRAIGHT D TYPE PLUG CONNECTOR 269

ISRO_HD-ST_15P_984 269
ISRO_HD-ST_26P_1312 269
ISRO_HD-ST_44P_1852 269
ISRO_HD-ST_62P_2500 269
ISRO_HD-ST_78P_2406 270
HIGH DENSITY STRAIGHT D TYPE SOCKET CONNECTOR 271

ISRO_HD-ST_ 15S_984 271
ISRO_HD-ST_26S_1312 271
ISRO_HD-ST_44S_1852 271
ISRO_HD-ST_62S_2500 271
ISRO_HD-ST_78S_2406 272
NOMENCLATURE OF MICRO-D CONNECTOR 274
MICRO-D 90º BENT PLUG & SOCKET 275

ISRO_MD9P/S_RA_1150 275
MICRO-D STRAIGHT PLUG & SOCKET 279

ISRO_MD9P/S_ST_1150 279
ISRO_MD100P_ST_2800 282
LIST OF FIGURES
Figure 1 Block diagram of typical CAD PCB design process using Cadstar software 07
Figure 2 Schematic symbol for polarized capacitor 09
Figure 3 Recommended conductor routing styles. 19
Figure 4 Orientation of Component identification 23
Figure 5 Surface mount passive leadless device component and footprint 60
Figure 6 Single-ended Transmission Lines 72
Figure 7 Surface Microstrip 73
Figure 8 Coated Microstrip 73
Figure 9 Differential Transmission line 73
Figure 10 Crosstalk 75
Figure 11 Differential traces in Microstrip & Stripline configuration 77
Figure 12 Typical example of single flexi layer - Rigid flex PCB construction 83
Figure13 Illustrative example of CCGA footprint 86
Figure 14 Illustrative examole of BGA footprint 87

LIST OF TABLES
Table 1 Applicable documents 01
Table 2 Symbols used in schematic drawing 11
Table 3 Schematic drawing header 14
Table 4 PCB design process traveler card 14
Table 5 Design Rules for Layout Design 15
Table 6 Buried via pairs 16
Table 7 PCB Layout Data Sheet 21
Table 8 Color of identification marks 22
Table 9 Component identification symbols in the Layout 24
Table 10 Hole and Pad identification requirements 25
Table 11 Current carrying capacity of conductor 27
Table 12 Conductor spacing requirements 28
Table 13 List of components that require additional support 29
Table 14 Types of turrets placement requirements ( in Mils) 30
Table 15 Spacing requirements between turrets & coils/transformers 31
Table 16 Identification codes to be mentioned in component list 33
Table 17 Component list (Integrated circuits only) 34
Table 18 Component list (Discrete devices) 34
Table 19 Checklist for the designer 35
Table 20 List of details required in each layer of spool files 36
Table 21 Drill tool table report (Sample) 37
Table 22 PTH drill tool allocation table 37
Table 23 NPTH Drill tool allocation table 38

Table 24 PCB ordering data sheet 39
Table 25 List of details required for the folder generation 40
Table 26 List of information and format to be stored in design output CD 41
Table 27 List of details to be submitted along with new layout 42
Table 28 Format for design completion record 64
Table 29 Design features of a rigid-flex PCB 83
Table 30 Design Rules for Layout Design having BGA devices and through vias 85
LIST OF CHECKLISTS
Checklist 1 Checklist for schematic symbol 43
Checklist 2 Checklist for footprint inspection 43
Checklist 3 Checklist for schematic part 43
Checklist 4 Checklist for schematic drawing 44
Checklist 5 Checklist for PCB design initiation 45
Checklist 6 Checklist of items required for final layout approval 45
Checklist 7 Checklist for component list 46
Checklist 8 Checklist for component verification 47
Checklist 9 Checklist for mechanical details 47
Checklist 10 Checklist for PCB layout design file 48
Checklist 11 Checklist for conductors 50
Checklist 12 Checklist for clearance 50
Checklist 13 Checklist for gerber files 51
Checklist 14 Checklist for NC Drill/rout files 53
Checklist 15 Checklist for component marking print 53
Checklist 16 Checklist for PTH marking print 53
Checklist 17 Checklist for CD data contents 54
Checklist 18 Checklist for master patterns 56

1 INTRODUCTION
The trend in the electronics industry has moved from Plated Through Hole (PTH) to surface mount technology
(SMT). This trend has accelerated recently due to rise in the use of high-density packages that have greatly reduced
terminal spacing. These reduced spacing make through-hole insertion undesirable, hence the move towards
SMT accelerated, which makes the boards easier to build, increase in their reliability, low volume and weight.
This document is generated to ensure the PCB layout design for high reliability of soldered electrical connections
to through hole and surface mounted devices, intend to withstand normal and terrestrial conditions, vibrational
G-loads and other environments imposed during the space flight.
1.1 Scope
This document lays down the guidelines for footprint design, PCB design, preparation and inspection of CAD
(computer aided design) layouts and production of master pattern (photographic film) of printed circuit boards that
uses both surface mount devices and through hole devices.
This standards is applicable to ISRO Space programs involving PCBs designs for flight hardware, mission critical
ground support equipment and elements.
The intent of the information presented herein is to provide the appropriate size, shape and tolerance of surface
mount land patterns to ensure sufficient area for the appropriate solder fillet and also to allow for inspection and
testing of the solder joints.
Reliable soldered connections result from proper design, control of tools, materials, work environments and
careful workmanship. This document provides information only on design, other factors shall be considered in the
appropriate stages to maintain the quality standards.
This specification is applicable for both single layer board and multi layer with conductive pattern on one side
(type-1) or on both sides (type-2) and multi layer (type 3) connected with a through hole plating in case of type-2
and type-3.
This specification is also applicable for both through hole mount technology (Class-A), or mixed technology (Class-B)
and surface mounted technology (Class-C) printed wiring assemblies which uses . Glass epoxy laminates and Duroid
substrates (Double sided only).
1.2 Applicable documents

The following documents form a part of this standard to the extent specified herein.
Table 1: Applicable documents

ESA PSS 01-738 High reliability soldering for surface mount and mixed technology printed circuit boards.
NHB 5300.4(3Z) Workmanship requirements for surface mount mixed technology printed circuit boards.
IPC-SM-782A Surface mount land pattern design requirements.
1
IPC-2221 Generic standard on printed board design.
MIL-P-55110 General specifications for rigid printed wiring boards.
IPC-D-390A Automated design guide lines
IPC-T-50 Terms and definitions
ISRO-PAX-304 Qualification of Printed Circuit Boards
ISRO-PAX-300 Workmanship Standards for fabrication of Electronic Packages
1.3 Order of precedence

For the purpose of interpretation and in case of conflicts, the document shall rank in the following order:
• This standard
• Other standard /document as per the order referred in Table 1
2
2 DIMENSIONS AND TOLERANCES FOR LAND PATTERNS
In analyzing the design of a land pattern for a component, following parameters are to be considered for a reliable
solder joint design:
• Photo plotting tolerances of master pattern
• Standard fabrication tolerances of PCB
• Size and position tolerances of the component lead
• Thickness tolerance of component lead termination
• Placement accuracy of the man / machine to center the part to the land pattern
• The amount of solder area to be made available for a solder joint for formation of a toe, heel and side fillet
2.1 Units
Since the components used in the design follow either mil/mm dimension system, the design dimensions are
expressed in mils or mm as appropriately. When no unit of measurement is shown, the unit shall be assumed to be
in “mils”. However controlling dimensions of manufacturer data sheet shall be final.
2.2 Component and land pattern tolerancing

Component data sheets provide dimensions of parts with applicable tolerances. The following guide lines to be
followed for the land pattern and component profile dimension calculations.
• Body outline (package outline) of the component shall be of maximum dimensions
• Pitch of the component lead shall be of nominal dimensions
• Inter land dimension (inner edge to inner edge) of the land pattern shall be decided based on the minimum
dimension of the component with maximum metallization
• Outer land dimension (outer edge to outer edge) of the land pattern shall be decided based on the maximum
dimension of the component
• For hole diameter calculation, maximum dimension of the lead diameter to be considered
The land patterns are to be determined using the guidelines specified in Annexure-1.
2.3 Standardization
Although, in many instances, the land pattern geometries can be slightly different based on the type of soldering used
to attach the electronic part, wherever possible, land patterns are defined in such a manner that they are transparent
to the attachment process being used.
Designers should be able to use the information contained herein to establish standard configurations for manual
and computer aided design systems.
Whether parts are mounted on one or both sides of the board, subjected to wave, reflow or other type of soldering,
the land pattern are optimized to ensure proper solder joint and inspection criteria.
For lead free soldering the requirement of patterns / dimensions shall be considered as and when need arises.
Although patterns are standardized, since they are a part of the printed board circuitry geometry, they are subjected
to the producibility levels and tolerances associated with plating, etching or other conditions.
3
3 PRODUCTIONISATION
3.1 Design for large volumes
In view of the productionisation of electronic assemblies, the layout design process as shown in para 4.2, the designer
has to take appropriate attentions during the planning phase. Specific areas addressed during planning includes
following steps.
• Panalization of small PCBs

• Additional test boards for Quality Control in SMT boards
• Component selection and orientation for automated assemblies
• Need for testability points for automated testing
Care shall be taken by the PCB designer for all these aspects and shall be properly implemented in the design. The
reworking of a layout will take considerable amount of time and also may affect the predefined project schedules.
3.2 Standard component selection

All the devices should be selected from Approved PPL of respective centre.The standard components will be available
from multiple sources and will usually be compatible with all assembly processes. For those devices developed to
meet specific applications like ASICs, standard packaging is often available. Care shall be taken to ensure that package
type shall be compatible with the approved device.
3.3 Assembly considerations

Following assembly considerations shall be made to improve the productivity.
• Maintaining a consistent spacing between components will ease the assembly process.
• Component reference designator increment mode may be left to right and top to bottom with respect to
card code, which will help assembly technician to locate component faster.
• Direction of polarized devices in same direction will reduce the assembly errors. In addition, when common
orientation is maintained, machine programming is simplified and component verification, solder inspection
and repairs are simplified.
3.4 Vias as test points

Via holes are used for connecting the traces between layers or to connect surface mounted component lands to
conductor layers. They may also be used as test targets for bed-of-nails type probes. Via holes shall not be covered
with solder mask/tented if they are required for node testing.
3.5 Component placement file

Auto placing file (Gerber file of the design shall be provide to the manufacturing agency) can be generated from the
CAD systems that will enable the use of auto placement machines. The file origin shall be at the left bottom most
corner pad.
4
3.6 Component placement considerations
The land pattern design information discussed so far is important for reliability of assemblies. However, the designer
shall take care of manufacturability, testability and repairability of assemblies. A minimum inter-card spacing of
140mil/3.5mm is required to meet the vibration requirements. It is preferred to distribute the components evenly
across the board area for weight and thermal considerations.
3.7 Grid-based component placement

It is preferred to use 1mil grid pattern for the component placement of SMT devices and through hole devices.
In case of mm grid designs, it is preferred to use 0.1 mm grid
3.8 Double sided component mounting

It is preferred to use all SMT devices at one side of the card and the through hole devices at the other side so that
the automation is easy. However combination of both side SMT and through hole is also acceptable.
3.9 Stencil preparation

The solder stencil is the primary vehicle by which solder paste is applied to the SMT printed board. With this, the
exact location and volume of solder paste deposition is precisely controlled. The artwork for the stencil generally
consists of the component mounting lands from the outer layers of the board with all other circuitry deleted.
The openings in the stencil should be 80% of the lands on the board for all components.
The stencil is made by using spool file generated from the CAD systems. The format shall be in RS274X compatible
to the various systems. The file origin shall be at the left most bottom corner of the alignment pad. And the file shall
contain all the SMT land pattern openings and alignment pad for stencil cutting and registration.
3.10 Fiducial marks & Other markers

A Fiducial Mark is a printed wiring board feature that is created in the same process as the circuit artwork. The
fiducial and circuit pattern artwork will be etched in the same step.
The Fiducial Marks provide common measurable points for all steps in the assembly process. This allows equipment
used for assembly to accurately locate the circuit pattern. Fiducial shall be circular (Completely filled). There are
two types of Fiducial Marks, namely:
3.10.1 Global Fiducials

Fiducial marks used to locate the position of all circuit features on an individual board. When a multi image circuit
is processed in panel form, the Global fiducials are referred to as Panel Fiducials.
3.10.2 Local Fiducials

Fiducial marks used to locate the position of an individual component. A minimum of three local marks are required.
Two should be in x axis and one should be in y axis.
5
3.10.3 Other Markers
Board edge markers, registration pads (79 mil/2mm), indexing pads (59mil/1.5 mm), plating measurements pads
(118mil/3 mm) shall be placed in the design (At corners)
3.11 Standard fabrication allowances

Manufacturing tolerances or Standard Fabrication Allowances (SFA) exist in all PCB fabrication shops. PCB
manufacturer shall add required manufacturing process tolerances to meet the end product requirements.
3.12 Soldermask
In referring to the outer layers of the multilayer PCB, there is a difference between the concepts of soldermask and
having no conductors on the outer layers.
Conventional SMT design rules allow routing conductors on the outer layers, running the conductors between
Surface Mount lands and then applying soldermask to cover the conductors and leave the lands exposed. The solder
masking technique will allow the designer to improve the spacing requirements.
Solder masking allows finer traces of size up to 5mil/0.125mm and spacing as close as 5mil/0.125mm without the
danger of solder bridging during soldering.
3.12.1 Soldermask clearances

A soldermask may be used to isolate the land pattern from other conductive features on the board such as vias,
lands or conductors.
4mil/0.1 mm spacing could be acceptable for the lands and pads for the solder mask generation. As far as possible
mask patterns between the space of CQFP is desirable. In case of BGAs and CQFPs 2mil/0.05mm clearance for
soldermask is acceptable.
6
4 REQUIREMENTS
4.1 Facility requirements
When layouts are designed at a vendor facility, it shall be approved by QC/QA. The certification is issued by QC/
QA of ISRO centre concerned for a period of 1 year and can be renewed periodically. Any unsatisfactory outputs
continuously for three times from a vendor will cancel the certification and the vendor shall have to undergo the
re-certification program listed in para 11.
4.2 PCB design software requirements

PCB design facility shall be equipped with required/applicable software for design of printed circuit boards. Any
change in the design software after certification, shall be with the consent of certifying agency.
Design facility shall maintain a separate symbol/parts and foot print library for onboard PCB designs. Foot print
geometries and dimensions shall comply the dimensional requirements of this document. Symbol/parts/footprint
library shall not be modified without prior approval from QC/QA of ISRO centre concerned.
Note: Inability to introduce design requirements, unjustifiable delays in the design time and incompatible output with
ISRO centre facility etc., will be considered as unsatisfactory outputs. Qualification /certification, re-certification and
renewal of certification shall be carried out as per para 11.
Figure 1: Block diagram of typical CAD PCB design process using Cadstar software
7
5 LAYOUT GUIDELINE
5.1 Design technology
The design technology set for the onboard/Hi-Rel layout shall meet the requirements of this standard described
herein.
Assignments for pads, patterns and DRC rules shall conform to this document. Only through hole vias and buried
vias may be used for onboard layout designs. Blind vias are not permitted. Buried via pairs shall not be mixed in the
design technology. Acceptable buried via pairs are listed in para 5.6.
Pads in any layer shall not be suppressed. It is preferred to use positive outputs for all the layers for power plane. In
special cases, negative outputs shall be considered.
5.2 Functional correctness of schematic circuit

Functional and electrical correctness of the circuit shall be verified by the circuit design engineer. Electrically and
functionally approved schematic drawing shall be used for the onboard PCB layout design. Schematic drawing header
para 5.4.2 shall have approval signature of circuit design engineer.
5.2.1 Connectivity correctness inspection

During the realization of the PCB layouts it is necessary to verify the connectivity correctness with help of respective
component data sheet by the circuit designer and PCB layout designer.
5.2.2 Signal naming conventions

The following signal naming convention shall be used in the schematic drawing for facilitating the ease of inspection
and de-bugging.
o + DC volt net shall start with + symbol followed by voltage.

• +5V_M for main system
• +5V_R for redundant system
o - DC volt net shall start with - symbol followed by voltage.
• -3.3V_M for main system
• -3.3V_R for redundant system
o Clock nets shall be named clk_clock frequency without space in it (clk_20MHz).
o No space shall be put in the net name.
o Ground nets shall be in any of the following way:
• GND
• AGND
• DGND
• +15V_RTN (Voltage name followed by _RTN indicate return line)
• -15V_RTN
o Reset line net name shall start with reset_type of reset
o Net name shall resemble the function of the signal in electronic circuit.
8
Global signals like VCC, GND, AGND,VDD,VEE, DGND shall be separately designated as signal_M and signal_R for
separating main and redundant systems in the same card.
Shorting of alternate pins for dual component mounting shall be made in the schematic itself, using applicable
symbols which map to the corresponding foot prints.
Designers shall evolve a common net naming practice and schematic verification engineer in subsystem shall enforce
these rules into practice. This will increase the readability of the circuit design and certainly alert subsequent
personnel down in the design chain to detect errors, if any.
5.3 Net properties

Net properties like width, spacing shall be mentioned in the schematic drawing. Other properties like layer
specific, length (propagation delay), skew (relative propagation delay), net_shield, differential pair net_thermal etc.
shall be communicated to the PCB designer either through schematic net attributes or through separate design
instructions. Any other special requirements which are to be taken care during component placement/routing shall
be communicated to the PCB designer and shall be verified by the circuit designer prior to the electrical approval.
5.3.1 Net width and spacing

Circuit designer shall specify the trace width and spacing at schematic level using the integrated tool features so that
trace width and spacing requirements are not violated in the PCB design.
The following additional mandatory checks are to be carried out during the PCB layout realization process.
o Polarized capacitors
• It is necessary to use only polarized capacitor symbols for polarized capacitors. Also pin number
1 of the polarized capacitor shall be assigned as positive. Subsystem engineer shall ensure this while
clearing the schematic electrically.
Figure 2: Schematic symbol for polarized capacitor
• In PCB design file pin number 1 of the polarized capacitor shall be assigned as positive. Checklist used
by the PCB design vendor shall ensure the above need and PCB layout inspector shall verify the above
requirements are met after due verification of schematic and PCB design file.
o Diodes/zeners
• It is necessary to use only relevant symbols (diode symbol shall match to the function/type of the device)
for diodes. Diode symbol shall not be used for Zener and vice versa. Also pin number 1 of diodes shall
be assigned as anode. Subsystem engineer shall ensure this while clearing the schematic electrically.
9
• In PCB design file pin number 1 of the diode/Zener shall be assigned as anode. Checklist used by the PCB
design vendor shall ensure the above need and PCB layout inspector shall verify the above requirement
is met after due verification of schematic and PCB design file.
o Transistors, MOSFETs, dual transistors, opto couplers and regulators
• The emitter, base, collector or source, drain, gate or input, ref, ground locations vary based on part
number of the device. Hence pin numbering/naming alone will not ensure the connectivity correctness.
• Symbol used for the device shall match to the type of device used.
• Numbering or naming of the pins shall be as per the data sheet or shall be in such a way that functional
pin in schematic matches to the physical location of the pin on package.
o Relays
• As coil +, Coil -, NO, NC, pins vary based on the part number of the device, pin numbering/naming alone
will not ensure the connectivity correctness.
o Resistor/Capacitor networks
• Common pin (if any/parallel networks) of the device shall be matched to the physical common pin on the
device package using the device data sheet.
o ASICs/FPGAs/RF Devices
• In device datasheet pin incrementing direction of component is normally mentioned using top view. In
case, device datasheet shows the bottom view of the component then foot print is to be modified for
top view.
• Pin number 1 and pin number last of the component and pin incrementing directions shall be available in
the device data sheet.
Checklist used by the PCB design vendor shall ensure the above needs.The above requirement shall be checked and
verified by the subsystem engineer while clearing the PCB layout electrically. PCB layout inspector shall verify the
above requirement is met after due verification of schematic and PCB design file. Since the electrical connectivity
correctness of the circuit is related to the foot print pin mapping, final electrical connectivity correctness shall be
conducted by the subsystem engineer /PCB designer and approved by the PCB layout designer/executive.
Apart from the regular inspection procedures, PCB layout audit shall be carried out as per project audit plans and
verify that all the aspects of the layout are as per standard procedures.
5.4 Schematic
Only Authorized schematic shall be used for layout preparation and approval. Symbols and logic diagram used for
drawing the onboard schematic circuit shall conform to the following documents:
10
Sl No Standard Relevance
Graphic symbols for Electrical and Electronic
1. IEEE STD 315
Diagram
IEEE standard for graphic symbols for logic
2. IEEE STD 91
functions
3. IEEE STD 991 IEEE Standard for logic circuit diagrams
Schematic drawing shall be completely synchronized with the PCB layout without any mismatch including net_name,
connections, packages (styles), foot prints, values, voltages etc. Few examples of the symbols are shown in the
following table.
Table 2 : Symbols used in schematic drawing

Sl No Symbol Name Symbol Name Stem
1. Resistor R
2. Variable resistor R or P
3. Thermistor TH
4. Capacitor C
5. Electrolytic capacitor C
6. Variable capacitor C
7. Diode D
8. Zener Diode Z
11
9. Tunnel diode D
10. Varactor Diode VR
11. Diac D
12. Triac D
13. SCR D
Schottky diode
14. D
15. LED D
16. PNP Q
17. NPN Q
12
18. UJT Q
Depletion PMOS
19. Q
Enhancement NMOS
20. Q
Depletion NMOS
21. Q
Enhancement PMOS
22. Q
23. Darlington Pair NPN Q
24. Darlington Pair PNP Q
New symbols may be added by the centre concerned as and when required.
5.4.1 PCB design library

In CADTSAR PCB layout design flow, there are mainly three libraries used for storing the component information.
• Symbol library: This contains symbol information like symbol of resistors, capacitors, transistors, gates etc.
Symbols are used in the schematic drawing.
• Footprint library: This contains footprint information of the components.
• Parts library: This maps a symbol to the foot print correctly so that while placing a symbol in the schematic
drawing, it ensures the correct package style in the PCB layout without manual intervention.This feature also
enables the front and back annotation without having risk of connectivity error.
PCB designer shall make sure that complete part library for the design of the PCB layout shall be available prior to
the start of design.
5.4.2 Schematic drawing header

Typical schematic drawing header is shown in the following table. Schematic drawing shall be checked by the circuit
design engineer and shall be signed either electronically or physically by him/her for its correctness.
13
Table 3 : Schematic drawing header
CENTRE NAME
Project Card No P a c k a g e Model Subsystem Group
No. Name
Drawn Checked Rev X.X
Date Date
Work Order Number and Drawn by Vendor/Facility Name
5.4.3 Schematic design export to PCB design

Schematic drawing shall be transferred to PCB using integrated tool environment which allow Engineering Change
Order and back annotation. Integrity of PCB design with respect to schematic drawing shall be verified prior to the
electrical approval of the PCB layout.
5.4.4 Traveler card of PCB design process

PCB design folder (Hard copy folder) shall have a traveler card which depicts the activities carried out in PCB layout
design after the schematic approval by circuit and PCB design engineers. Format of traveler card is shown below.
Table 4 : PCB design process traveler / Change Control Sheet
Card No: Project: Model:

Date M/R Change request description Change incorporation history
M = Modification
R= Rework
PCB design/documentation folder shall also have schematic revision control sheet.
14
5.5 Design rules
Design rules are summarized in Table 5.
Table 5 : Design Rules for Layout Design

Sr. No. Objects Specs in mm Specs in mil
1 Comp to comp placement 0.25 10
2 Copper to Board edge for external layers 1.00 40
3 Copper to Board edge for internal layers 1.00 40
4 Copper to Copper 0.20 8
5 Holes’ edge to edge 1.00 40
6 Minimum track length 0.50 20
7 Route to pad 0.20 8
8 Route to route 0.20 8
9 Route to via 0.20 8
10 Pad to board 1.00 40
11 Pad to copper 0.25 10
12 Pad to pad 0.20 8
13 Pad to SMD pad 0.20 8
14 Pad to Via 0.20 8
15 Route to board 1.00 40
16 Route to copper 0.20 8
17 Route to SMD pad 0.20 8
18 SMD pad to board 1.00 40
19 SMD pad to copper 0.50 20
20 SMD pad to SMD pad 0.125 5
21 SMD pad to Route in case of fine pitched devices 0.10 4*
22 Test land to board 1.00 40
23 Test land to component 0.50 20
24 Test land to Test land 0.50 20
25 Minimum route width 0.2 8
26 Minimum route width for high density 0.15 6
27 Minimum via pad 1.2 48
28 Minimum via pad size for high density (Non solderable) 1.0 40
29 Minimum via hole 0.50 20
30 Minimum via hole for high density 0.40 16
31 Via to board 1.00 40
32 Via to Copper 0.20 8
33 Via to SMD pad 0.20 8
34 Via to Via 0.20 8
35 Text size/thickness 1.50/0.25 60/10
36 Power plane to free holes or power planes 0.50 20
37 Card edge to component body 1.00 40
15
Space between DIP ICs/any other radial lead components with
38 2.54 100
local potting
39 TO CAN to any other components 1.00 40
40 Turrets to any other components 1.00 40
41 CQFJ to any other radial lead components 2.54 100
42 CQFP to any other radial lead components 2.54 100
43 Card edge to stack hole center where d is hole dia 1.3xd
44 Power plane to unconnected pads in inner layer 0.25 10
45 External layer copper/power plane to turret pad spacing 0.50 20
46 External layer copper/power plane to unconnected pads 0.38 15
Conductor to any metallic spacer of mechanically mounted
47 0.50 20
component bodies
1 “*” Provided the traces nearby are solder masked. In specific applications minimum track width
may be decided by considering current carrying capacity requirements.
2 Body dimensions shall include radiation shielding or additional attachments if any.
3 Minimum feature dimensions mentioned above is subject to vendor’s capability
5.6 Buried via pairs

Buried via pairs can be used as per the following table. However, usage of buried via designs is subject to the
qualification of process
Table 6 : Buried via pairs

No. of Layers Buried via pairs
6 3&4
8 3&4, 5&6
10 3&4, 5&6, 7&8
12 3&4, 5&6, 7&8, 9&10
14 3&4, 5&6, 7&8, 9&10, 11&12
16 3&4, 5&6, 7&8, 9&10, 11&12, 13&14
5.7 Template / document file

The card size, stack hole positions, diameter etc. will be common to all the cards in one package. Hence designer shall
maintain a master file (called template file) in the design systems which contains the board shape definitions, stacking
hole locations, track restricted areas and assignment definitions (like pad, via, track width, spacing etc.) edge markers,
test coupons, cross hair pads and registration pads which conform to this specification. This will greatly reduce
the design errors. If the CAD software allows scripting (skill file); common script file shall be used for template
generation. In order to identify no-track areas and component height restriction areas without dimensional errors,
with respect to mechanical drawing, importing DXF format file from mechanical CAD tools is also advisable. All
no track zones / height restricted areas (if feasible) shall be appropriately defined to enable automatic verification
through software design rule check.
16
5.8 Design file name
Design filename shall be given in such a way, that it identifies the card number (as in para 5.17.2 PCB identification).
Separate folder shall be maintained for each card number. The designer shall maintain two separate copies of the
finished approved layout file and its spool files. Blank spaces shall not be given between words in the file name.
Separate directory in the electronic media shall be maintained for each layout version. It is the responsibility of the
design engineer to maintain the latest version of schematic files, design files and output files with him/her and a
copy in the division library. PCB Layout approving agency shall maintain soft copy of approved versions of designs,
associated library files (if any) and a register. In order to make use of the upgraded version of design software for
modification, the custodian shall upgrade the master design files and libraries, as and when the design software is
upgraded or original design is modified whichever is earlier.
5.9 Check-plot size

The plot /print out of a particular PCB layout to be plotted on a single plain sheet in case of type-1 (SSB) or type-2
(DSB) boards. In case of type-3 (MLB), the number of plot sheets shall be equal to number of layers (preferably in
1:1 scale for approval). The layout data sheet shall be as per the package or assembly details duly approved by QC/
QA and their respective subsystem engineer/designer.
Any special requirement that is not mentioned in this document but is/are necessary shall be indicated on the sheet
away from the card boundary and also in the PCB layout data sheet. When approved by QC/QA of the respective
centre of ISRO, the same shall be incorporated in the further stages like photo plotting and film.
5.10 Placement plot definitions

A placement plot with pads, component name, component outlines and conductors shall be provided along with
spool files, card mechanical dimension details and component list for inspection/approval by QC/QA. In order to
maintain contrast in the placement plots, it is preferred to use lighter colors for pads and conductors and deeper
color for outlines and names. The definitions are as below.
5.11 Plot definitions

Only one color, particularly black shall be used to mark patterns and pads in case of single sided PCB. For double
sided or multilayer PCB, three colors shall be used as follows:
Red color shall be used to draw tracks on component side (side-1).
Blue color shall be used to draw tracks on solder side (side-2).
Black color shall be used for those tracks that have to appear on both component side and solder side.
17
5.11.1 Pads
1 True size unfilled/filled Black color for through hole pads, Red color for component side pads, Blue color
for pattern side pads.
2 All the free holes/stacking holes/lacing holes, pad dia in the layout may be 40 mil / 1mm smaller than the
hole size. Free holes less than 40mil/1mm dia shall have at least 50% less pad dia than the hole size.
3 Prohibited /no track /no via area shall be marked in the plot in true dimension with hatched/filled lines.
4 The fiducial pads shall have pads in all the layers even though it has null drill code.
5 Slots shall be as per mechanical drawing.
5.11.2 Vias
1 In a yellow color grid sheet use green color for through hole vias and any other distinguishable color for
buried vias.
2 Increase via size appropriately for high current requirement.
5.12 Selection of grid

It is preferred to use 1mil/0.0254mm grid for routing the traces. However, for the components whose pads / lands
do not fall on grid, routing may be done in the appropriate sub grid.
5.13 View of the Layout

All the layouts shall be viewed from the component side & viewing side shall be clearly mentioned in the “Layout
Data Sheet “(as shown in Table 7).
Component side of the layout shall be identified as “C” in copper. For multilayer board, all the layers shall have view
from component side (top to bottom) only.
Each layer shall have layer code identification like NTC10MB101/1 (the slash number indicates layer code) or Layer
1. The layer identification texts shall be straight and mirrored in alternate layers based on the layer stack used in
PCB manufacturing. Text size shall be in accordance with Table 5.
5.14 Conductive Pattern Shape

The design features of the conductive pattern in layout shall be as per the following provisions:
1 Conductive pattern length between two electrically connected points shall be as short as possible.
2 Conductor to conductor junctions making angles less than 90o shall be avoided. However, where such
junctions are unavoidable, they shall be filleted/filled with copper.
3 Sharp corners shall be mitered.
4 Conductor lines shall preferably follow the main axis of the laminate, but may follow any angular direction
with smooth curvature based on photo plotter capability. No pattern shall run under flush mounted
components having metallic body (e.g. relay, flat pack ICs, etc). In case the patterns are drawn, provision
for providing suitable insulation on patterns shall be made in the layout. The insulation so provided shall
project by 40 mil/1mm outside the component body.
5 Larger conductive area (greater than one square inch (6.25Sq.cm.)), either in case of ground plane, voltage
plane or heat sink, shall be broken up (relieved) into strips but the continuity and functionality of the
18
connections shall be retained. This is to reduce warp, twist and blisters in the finished PCB. The width of
the strip shall not be greater than 118 mil/3mm and less than 10 mil/0.254mm. The spacing between two
strips shall be equal to width of the strip. Star bursting or strip hatching method boundary line shall use
minimum 20 mil/0.508mm.
6 In double sided cards, pattern density on component side and solder side shall be maintained equal, to the
possible extent, in order to reduce warp and twist of the finished PCB. Large conductive area, if possible,
shall be designed on component side of the PCB. In case of type-3 boards, patterns on surface layers shall
be kept to a minimum.
7 Provision for interfacial connection in type-2 (DSBs) and type-3 (MLBs) boards shall be made by means
of plated through holes. Standoff, eyelets, rivets, etc. shall not be used as interfacial connection.
8 In power plane design layouts, arrangements shall be made to provide minimum of 40 mil/1.0mm isolation
between card edge and copper.
9 Minimum spoke width/length shall be kept 10mil/0.254mm and preferable length shall be 20mil/0.508 mm
with one number of spoke for 35micron thick copper plane. For higher thermal mass boards, one spoke
of appropriate width and length with 59mil/1.5 mm may be used. Number of spokes requirements may be
modified based on operational requirements.
Figure 3: Recommended conductor routing styles.
Recommended Not recommended
19
Recommended Not recommended
20
5.15 PCB layout data sheet
Table 7 : PCB Layout Data Sheet
Card no & Card
Project: Model: Subsystem:
Name
Card size: Package size: Package No: Total cards/Model:
Laminate type: Card Thickness in mm ESD Classification:
No. of layers:
FR4/TFG/RTD 0.8/1.7/2.25/3.2 0/1/2
Scale: 1:1 Plating: No. of ‘S’ holes: Buried layer pairs:
Library and system used: PCB File name and size: Drill File name:
Shield layer Nos:
Software used: VCC layer Nos: GND layer Nos:
Track width (norm): Track width (T1): Track width (T2): Track width (T3):
Max Current: Current (max): Current (max): Current (max):
Max.Voltage: Max.Voltage Max.Voltage Max.Voltage
Spool file format: Basic Gerber /274X/DPF
Lay up order 1 2 3 4 5..............................................14
Total copper
thickness in
microns
Layer
Identification
Hole & Pad details (Refer drilling
ITEM
details for location of drill)
Code/ Hole dia Pad dia
LAYOUT
Name in mm in mm
Registration error
FILM
F-F C-F
WIRING DATA
Special requirements (Attach separate sheet if required): (Y/N)

Solder mask required: (Y/N):
Certified that the track width and spacing provided in the layout meet all the requirements including the de-rating
as specified. Polarity verification and connectivity correctness of components is verified.
S/S Designers Engineers Name: Signature & Date Telephone No:
S/S Contact Persons Name: Signature & Date Telephone No:
Layout drawn by: Signature & Date Telephone No:
Approval Project Manager / Designer QC Mechanical QC Electrical
21
5.16 Solderable pads
All Solderable pads shall be preferably circular in shape except for pin no.1 and surface mount component lands. Pin
no. 1 pad may be oval shaped. The size of the pads shall be chosen depending upon the hole size. Refer Table 10.
The width of annular ring of the finished PCB shall not be less than 10 mil/0.254 mm for unsupported hole (NON
PTH) and 5 mil/0.125 mm for supported hole (PTH Holes).
If there is no sufficient space then, chip component / capacitor polarity may be marked with a rectangle (10mil x 10mil;
0.254mm x 0.254mm) connected to the pad. Suppressed pad configuration is not permitted for MLB layouts.
5.17 Identification
5.17.1 General
Color identification for check-plots as shown below.
Table 8 : Color of identification marks

ITEM SIDE COLOUR Mirroring
Track Component Red Not Applicable
Track Pattern side Blue Not Applicable
Pad Both Component and Black Not Applicable
pattern side
Pad Pattern side Blue Not Applicable
(for SMD)
Copper Text (Which has Component side Red No
to come in Film)
Copper Text (Which has Pattern side Blue Yes
to come in Film)
Component names Component side Any color No
Component names Pattern side -do- Yes
Text in Layer ID box All layers Concerned track No
color
Card number Text Odd layers Track color No*
Card number Text Even layers Track color Yes*
Pad component side (for SMD) Red Not applicable
• *Readable as per the layer stack.
Identification, which has to be reproduced on the component side of the PCB, shall appear on component side of
the layout and it shall be in TEXT mode or ADD COPPER mode. It shall be noted that the names of the components
in the layout design shall not be used for reproducing as copper text on PCB.
Table 9 gives the necessary component identification that has to be reproduced on the PCB. Component side of the
layout shall be identified as “C”. Size and height of the identifications shall be 60 mil & 10mil minimum respectively.
However it shall be clear, legible and uniform when photo plotted. All the identification marks shall meet the
minimum spacing requirements of Table 5.
22
5.17.2 PCB identification
Nomenclature of PCB shall be mentioned in accordance with the following code:
Project Subsystem Package No Revision No. Card No.

N TC 10 0 01
where,
N INSAT
TC Tele-command
10 Package code (only 2 digits)
0 Revision number. In case of every revision, this code will be increased by 1.
01 Card code (only 2 digits)
For multilayer boards, card codes and layer numbers shall be provided in all layers. Layer numbers shall be denoted
as 1, 2, 3… in top side layer code box. However the respective ISRO Centres may adopt their own coding system.
5.17.3 Component identification

Component identification need not appear on the PCB but shall be identified in name mode in the layout. It is
preferred to keep component names in the silkscreen layers. Names shall not be switched ON while creating
spool file. Orientation of component identification in a layout shall be as shown below. Other orientations are not
accepted.
Figure 4: Orientation of Component identification
Not acceptable Acceptable

R1
R1
R1
R1
R1
R1
Component list for all the components used in the layout shall be provided in accordance with the Table 17 and
Table 18. Parts list output from the CAD system shall not be used as the component list. However it may be used
for checking PCB layout designs.
In case of polarized components, either active or passive, the polarities shall be clearly marked in the layout and it
23
shall be in copper mode. (e.g. Polarity of capacitors, serial numbers of transistors, ICs, and Relays etc.). Diodes shall
be identified with their symbols. Serial number of the terminals like bifurcated terminal, turret terminals, etc., shall
be marked at every fifth terminal and duplicate numbers are not allowed.
For TO-5 CAN-ICs & Relays, two pins (The first pin and the last pin) shall be identified clearly, close to the pad. If
such markings are not done then the projection from one of the pads / or oval shape pad of IC or Relay shall be
assumed to be the last pin of that IC or Relay.
Provision for turret terminals shall not be made on connector plate side since soldering and inspection accessibility
is less on this side. For fine pitch devices, it is preferred to put a 10x10mil highlighter dot on every 10th pin to
facilitate pin counting / inspection and rework during assembly.
Table 9 : Component identification symbols in the Layout

Sr. No. Component Type Symbol Name Copper Text
1. Integrated Circuit. U Yes
2. HMC U Yes
3. Diode D No
4. Zener Z No
5. Veractor VR No
6. Resistor R No
7. Capacitors C No
8. Inductor or Transformer L /T Yes
9. Terminal Serial Nos. Every 5 turrets in one line
10. Bead B No
11. Crystals Oscillator Xc Yes
12. Relay RL Yes
13. Fuse F No
14. Connector K Yes
Standard D-Type
- Straight K-s
- Right angle K-r
FRB K-f
Micro-D K-m
Combo-RF K-c
FRC K-fr
15. Resistor Network RN, RS, RP, RCN Yes
16. Jumper J1-J2 No
17. Variable capacitor C No
18. Test pads, headers TP No
19. Transistors, MOSFETs Q Yes
20. Pulse transformers TX Yes
21. Mixer M Yes
22. Isolators ISO Yes
24
Sr. No. Component Type Symbol Name Copper Text
23. Filters FL Yes
24. RF Choke L No
25. Crystal XL No
5.18 List of identifications that have to appear on the finished PCBs

1 PCB Identification (PCB nomenclature) and layer Number
2 Serial Nos. of ICs, Connectors, Relays, Transistors, Transformers / Coils with their symbols like U1—Un
for ICs, K1—Kn for connectors etc. may be used if space is available. Otherwise it shall be given on
component marking print. The last pin of TO CAN ICs shall be identified with notch marking on both the
sides and the first pin shall be identified with square pad.
3 Serial No. of turrets for every fifth turret in case of single row termination (ie. every tenth turret in case
of dual row termination).
4 Polarities of the polarized component (e.g. Electrolytic capacitors, with +/- sign)
5 Component side identification of the PCB.
6 Special requirements (if any)
7 Board edge markers and pads.
8 Indexing pad diameter of 59mil/1.5mm, Registration pad diameter of 79 mil/2mm and plating measurement
pad diameter of 118mil/3mm on all four corners of the card (outside the card boundary).
9. For components with more than 40 pins, 10th pin identification
5.19 Pattern and pad identification

The codes and widths of the pattern/pad shall be provided in the PCB layout data sheet (Table 7). It is preferable that
different track widths shall be shown with different colors.
Table 10 : Hole and Pad identification requirements

Finished
Hole Diameter Hole Drill Pad Diameter
Diameter Code
mil mm mm mil mm
PTH 16 0.41 0.4 B 40 1.0
PTH 20 0.51 0.5 C 47 1.2
PTH 24 0.61 0.6 D 51 1.3
PTH 28 0.71 0.7 E 55 1.4
PTH 32 0.81 0.8 F 59 1.5
PTH 36 0.91 0.9 G 63 1.6
PTH 40 1.02 1.0 H 67 1.7
PTH 44 1.12 1.1 I 71 1.8
PTH 48 1.22 1.2 J 75 1.9
PTH 52 1.32 1.3 K 79 2.0
PTH 56 1.42 1.4 L 83 2.1
25
Finished
Hole Diameter Hole Drill Pad Diameter
Diameter Code
mil mm mm mil mm
PTH 60 1.52 1.5 M 87 2.2
PTH 64 1.63 1.6 N 91 2.3
PTH 68 1.73 1.7 O 95 2.4
PTH 72 1.83 1.8 P 98 2.5
PTH 76 1.93 1.9 Q 102 2.6
PTH 80 2.03 2.0 R 106 2.7
PTH User Defined S to Z
NPTH 12 0.30 0.3 a 51 1.3
NPTH 16 0.41 0.4 b 55 1.4
NPTH 20 0.51 0.5 c 59 1.5
NPTH 24 0.61 0.6 d 63 1.6
NPTH 28 0.71 0.7 e 67 1.7
NPTH 32 0.81 0.8 f 71 1.8
NPTH 36 0.91 0.9 g 75 1.9
NPTH 40 1.02 1.0 h 79 2.0
NPTH 44 1.12 1.1 i 83 2.1
NPTH 48 1.22 1.2 j 87 2.2
NPTH 52 1.32 1.3 k 91 2.3
NPTH 56 1.42 1.4 l 95 2.4
NPTH 60 1.52 1.5 m 98 2.5
NPTH 64 1.63 1.6 n 102 2.6
NPTH 68 1.73 1.7 o 106 2.7
NPTH 72 1.83 1.8 p 110 2.8
NPTH 76 1.93 1.9 q 114 2.9
NPTH 80 2.03 2.0 r 118 3.0
Pad Diameter < drill
Free Hole s to z
diameter
General rule is drill dia + 0.7mm for pad diameter of PTHs and drill dia and 1mm for pad
diameter of NPTHs, this rule is not applicable for High Density ckts
For estimating turret hole and pad diameter, Table 14 shall be used.Vias that are not soldered shall have minimum of
16mil/0.41mm hole dia with 40 mil/ 1.0mm pad diameter.
26
6 ELECTRICAL DESIGN FACTORS
6.1 Current carrying capacity, track width
The width of conductor track is decided on the basis of temperature rise above ambient due to the current flowing
in the conductor. In space environments, the conventional mode of heat transfer (i.e. convection) is absent due to
vacuum and heat transfer takes place mainly by radiation and conduction. Hence, the current carrying capacity of
the conductors must be sufficiently de-rated.
De-rated current carrying capacities of conductors are shown in the following table. In any case the conductor track
width in the layout shall not be less than 6mil (0.15 mm).
Table 11 : Current carrying capacity of conductor

Max current (amps) for
Max current (amps) for 35 µm Basic Copper
Conductor width 35 µm Basic Copper thickness
thickness (For Launch Vehicles)
(For Spacecraft)
In mil / mm
6 / 0.15 0.1 0.15
10 / 0.25 0.2 0.25
20 / 0.50 0.4 0.50
26 / 0.75 0.575 0.750
40 / 1.0 0.668 1.00
50 / 1.25 0.785 1.25
60 / 1.50 0.896 1.50
70 / 1.75 1.0 1.75
80 / 2.00 1.1 2.00
100 / 2.50 1.3 2.50
120 / 3.00 1.5 3.00
140 / 3.50 1.7 3.50
200 / 5.00 2.1 5.00
6.2 Power plane designs

It is preferred to use the power plane or split power plane in designs where fast switching is used. Minimum
10mil/0.254 mm isolation shall be provided around the connected and unconnected pads in the power planes /
inner layers. Unconnected pads shall not be suppressed in the design. All connected pads shall not have more than
one connection to the plane from the pad. Minimum spoke width/length shall be kept 10mil/0.254mm and preferable
length shall be 20mil/0.508 mm with one number of spoke for 35micron thick copper plane. For higher thermal mass
boards one spoke of appropriate width and length with 59mil/1.5 mm may be used. Number of spokes requirements
may be modified based on operational requirements.
Sufficient isolations shall be provided between NPTH holes to power planes. The power plane layers shall be clearly
identified in the PCB layout data sheet and symbol report. Split plane isolation shall be at least 20 mil / 0.508mm.
27
In order to avoid the inter plane shorts while fabrication of PCBs; extreme care shall be taken from the designer end
to deal with free holes and cutouts through the power planes. At least 20mil /0.508 mm spacing shall be maintained
between power planes to any free hole in all the layers. Test coupon shall be modified according to the board type.
Refer Table 5 for other isolation requirements, if any.
6.3 Current carrying capacity in pulsed mode operations

During pulsed mode operations, conductor current shall not be more than rated current and average current shall
not be more than the de-rated current. Rated current is ~ three times of the de-rated current.
6.4 Spacing between conductors

The following guidelines shall be followed while designing spacing between conductors for PCB:
1 For Glass-Epoxy boards of NEMA grades - G10 / G11, FR-4 / FR-5, spacing of 0.003mm per peak volt shall
be maintained for more than 500V potential difference.
2 Spacing between any conductor track or pad and metallic case or mounting hardware (screw/washer)
shall not be less than 20mil /0.508 mm
3 Refer following table for further details.
Table 12 : Conductor spacing requirements

Voltage between conductors DC Minimum Spacing
or AC peak (volts) ( In mil / mm )
0-50 6 / 0.150
51-100 8 / 0.250
101-300 16 / 0.400
301-500 32 / 0.800
Greater than 500 V 0.003 mm per volt
6.5 Surface conductors

Wide conductors connecting to a land area can act as a solder thief by drawing solder away from the land and down
to the conductor. Further, if the conductor goes to a via which is connected to an inner layer power or ground
plane, the wide conductor may act as a heat sink and draw heat away from the land/lead area during reflow solder
resulting in a cold solder joint. Hence, conductor width of 40mil /1.0mm & length of 59mil/1.5mm shall be used for
such connections.
6.6 Vias within component land pattern

Vias or plated-through holes shall have minimum hole dia 16 mil/0.41mm. Vias are not permitted within the land
patterns of the flush mount two leaded devices. However if the devices are raise mounted, then vias must be located
away by 20 mil/0.508mm from the component lands to prevent solder migration from the component land during
soldering.
28
6.7 Component mounting provisions
The following guidelines shall apply to layouts for component mounting.
1 All the components shall be selected from PPL only.
2 Location and orientation of the components shall be in such a way that any component can be removed
/ mounted from / to the card without disturbing the other components.
3 A minimum spacing of 10 mil/0.25mm shall be provided from one component body to the nearest other
component body. For vertically mounted components, minimum clearance between two components
shall be 40mil/1.0mm. This is required to accommodate local potting application.
4 Provision for component mounting shall be made so as to avoid the air entrapment.
5 A minimum clearance of 40mil/1.0mm shall be provided between the card edge and component body.
6 Mounting for a component that has to dissipate more than 1watt power or leading to temperature rise of
more than 10oC above the ambient temperature shall include heat sinks or thermal conductive material
or both.
7 Component having weight more than 7 grams per lead shall have provision for additional support like
lacing thread, C clamp as shown in Annexure-1.
8 Provision for all axial lead components weighing less than 14grams, dissipating a temperature of less than
10oC above the ambient, not clamped otherwise supported, shall be made with its body flush with the
PCB. Mounting gap i.e, hole-to-hole dimension shall be in accordance with the para 10.
• Refer Annexure-1 for further details.
Table 13 : List of components that require additional support

Sr. No. Type of the component
1 CSR13 B
2 CSR13C
3 CSR13D
4 CLR79 T1
5 CLR79 T2
6 CLR79 T3
7 CLR79 T4
8 CRH: All body types
9 EL210
10 EL215
11 EL410
12 EL415
13 Torroidal Coils wound dia greater than
480mil/12mm.
14 Power transistor/ICs TO3 (nut bolt/ heat sink)
15 Power transistor TO66 (nut bolt /heat sink)
Note: Maximum body length includes the weld if any. But in view of the automatic lead-bending machine the
mounting provisions of the axial lead components (generally used) shall be as per Annexure-1.
29
9 Mounting provision for components not listed in Annexure-1 shall be made in consultation with QC/QA.
In such cases, mechanical drawing of the component giving all dimensions shall be provided.
10 For all radial lead components, mounting provisions shall be made to support the body on the PCB.
However, in case provision cannot be made for flush mounting, it shall be left perpendicular to the PCB.
In such cases approximately 59mil/1.5mm clearance shall be given for potting the components. Mounting
provisions for some of the radial lead components that are generally used shall be as per Annexure-1.
11 Trimpots, variable capacitors, resistors, inductors shall not be used in FM layouts.
12 Mounting provisions for components that are susceptible for damage in handling shall not be placed at the
layout edge (like glass diodes, vertically mounted CKR-05/06 capacitor, etc). The component at the card
edge prone for handling damages shall be flat/flush mounted.
13 Style, shape and dimensions of the components that are to be used are given in Annexure-1.
14 A clearance of minimum 3mm shall be provided between spacer (stacking hole) and PCB edge
connector.
15 De-coupling capacitors shall be placed closer to the power pins of the IC.
16 Table 5 shows clearance requirement between the components. (heat sinks or fasteners etc)
6.8 Turret mounting

Turrets for wire routing shall be placed on the periphery (edges) of the card. The second row turrets shall be
staggered with respect to first row. Inter turret spacing shall be worked out based on the turrets, swaging tool and
wiring practice planned. For terminal-less soldering (i.e. Direct termination of wires to pad) only one wire shall be
terminated in one hole.
Table 14 :Types of turrets placement requirements ( in Mils)

Sl. No TURRET Type from Card Turret to clearance whEN Pad Drill
/ HOLE DIA Edge Turret staggered Dia dia
1 D9 200 150 NIL 80 52
2 D9 200 200 200 80 52
3 D12 200 150 NIL 100 64
4 D12 200 200 200 100 64
5 D26 400 400 NIL 200 120
6 D26 400 400 300 200 120
6.9 Torroidal transformer / Coil

Normally torroidal transformers/Coils input /output wires shall be terminated to turrets. The mounting hole of
transformers /coils shall be 3.2mm NPTH or as per coil size. The spacing requirements are as shown in following
table.
30
Table 15 : Spacing requirements between turrets & coils/transformers
Sl No. No. of D12 terminals Spacing
1 4 5mm
2 8 6mm
3 12 8mm
For the transformers/coils which are vertically mounted using potting/staking shall be terminated to 3mm square
pads/lands or even 0.8mm PTH may be used with 5mm spacing from the outer edge of the wounded coil.
6.10 Radiation shielding

Radiation shielding provision shall be provided for the devices which require shielding in the card level and 100mil
(2.54mm) spacing shall be provided around the TO-CAN components, to do adequate radiation shielding. For the
components that needs radiation shielding, shielding thickness shall be mentioned in the component lists remarks
column by the designer. If thickness of the shielding is not mentioned, the minimum value will be considered as the
thickness.
6.11 Additional requirements

In general, the following requirements shall be followed:
1 Provision shall be made to lace the wires that would run on the PCB as in the case of relay wiring, etc., at
regular intervals of 1000mil/25mm.
2 Lacing holes shall be provided along all the four edges and corners of the card maintaining a pitch of
2000mil/50mm or two inches.
3 Provision to mount parts or larger masses like transformers relays, tantalum or wet slug capacitors,
torroidal coils, etc., shall be made closer to the supporting member of the PCB, in order to reduce the
potential destructive forces on parts and supporting members.
4 Maximum redundancy of patterns may be provided i.e., by providing tracks on both the sides
(if possible).
5 Components which requires dam and fill shall have minimum 5 mm space from land edge.
6.12 Component mounting holes

6.12.1 General
For all component mounting holes, both plated through holes and non-plated through holes, the finished hole
diameter shall be decided on the basis of the following requirements.
Hole dia = Maximum lead dia. + 8mil/0.2mm OR Nominal diameter + 0.3mm. It is preferred that number of different
hole sizes in any particular board shall not exceed 32 types. Hole provisions for mounting components with ribbon
leads shall be made as per Annexure-1. In such case, the difference between the lead thickness and hole diameter
shall not be greater than 20mil/ 0.508mm. Minimum hole size in any board shall not be less than 16mil/0.41mm
(Subject to PCB manufacturer is qualified). List of components and its footprint details are given in Annexure-1 and
same shall be used for PCB layout design.
31
6.13 Hole placement requirement
Spacing between adjacent component mounting holes (edge to edge) shall be such that the pad area surrounding the
hole meets the conductor spacing requirements. Refer Table 5 for further details.
6.13.1 Hole location

All the holes location shall be at the grid intersection. Hole provision for parts whose lead terminate in a pattern
which varies from grid intersection (e.g., Power Transistor TO 3, TO 66, relays etc) shall be made by one of the
following methods:
1 A hole pattern, where the hole, at least for one lead, is located at grid intersection and others are
dimensioned from that grid location.
2 A hole pattern, where the center of the pattern is located at the grid intersection and others dimensioned
from the grid location.
3 Provisions for any hole that is to be located at the card edge shall be made as follows:
Minimum distance from edge to center of hole = 1.3 x diameter of the hole that is to be located at the
card edge. PCB layout shall be drawn using approved mechanical PCB drawing.
6.13.2 Vias under components

Via holes underneath zero clearance components on the bottom side shall be avoided on boards without solder
mask.Via holes may be located underneath zero clearance surface mount non metallic packages in full surface mount
assemblies.Vias shall not be provided under flush mounted metallic body components.
6.13.3 Thermal vias for metal core boards

Thermal via provision shall be provided for sinking the heat generated by high heat dissipating components. The size
of via shall be at least 20mil/0.508mm dia. These vias shall not be used for providing electrical connection between
any layers. Similar thermal vias shall be provided at the edges of the card (200mil/5.08mm inside from the edge of
the card) to sink the heat to the box walls. Card mounting hole may be used as plated through holes connecting
through the embedded thermal layers.
6.14 PCB design Documentation

6.14.1 Card number
Card number shall be as per the Para 5.17.2.
6.14.2 Mechanical drawing

Mechanical drawing consists of dimensional details of PCB like card size, boundary details, stack hole locations and
pitch, no track areas, cutouts and connector locations, height restrictions, location of mechanically fitted components
etc. These drawings shall be authorized and approved by concerned Project, QA mechanical for onboard use. PCB
layout shall be drawn using approved mechanical PCB drawing.
6.14.3 Layout data sheet

Format of layout data sheet is shown in Table 7.The requirements shall be completely filled by the designer and shall
be signed. One Copy of layout data sheet shall be provided for the layout inspection.
32
6.14.4 Component list
A Format for component list is as shown in Table 17 and Table 18. Designers shall use this format for the component
list.The entire component list shall be submitted at a time. Components, which are test selectable, shall be identified
as TBD in the value column, with nominal values specified along with +/- tolerances, and other columns shall be filled
appropriately. Components, which are not required to be mounted in the card, shall be identified as NC in the value
columns, all other columns shall be filled appropriately.
Dittos for the subsequent rows shall not be allowed. Components which are mounted on turrets shall be identified
as TM in the remarks column of component list and as a note it shall be expanded as “TM-Turret mount “at the
bottom of the component list. Components which are to be raised mounted shall be identified as RM in the remarks
column of component list and as a note it shall be expanded as “RM-raised mount “at the bottom of the component
list. Components which are to be mounted on box shall be identified as BM in the remarks column of component
list and as a note it shall be expanded as “BM-box mount “at the bottom of the component list. Components, which
are to be mounted on heat sink, shall be identified as HS in the remarks column of component list and as a note it
shall be expanded as “HS-Mounted on heat sink “at the bottom of the component list. If the component is mounted
on heat sink, a detailed drawing of heat sink shall be supplied along with the layout for inspection. Components
which are to be mounted with chotherm, silpad etc. shall be identified in the component list with CM & SM in the
remarks column of component list and as a note it shall be expanded as “CM-Mounted on Chotherm “SM-Mounted
with Silpad “ at the bottom of the component list. Components, which are to be mounted on pattern side, shall be
identified as “P” and as a note it shall be expanded as P-“Pattern side” at the bottom of the component list.
Table 16 : Identification codes to be mentioned in component list

Item Code Meaning Identification column
R1 NC Not connected Value
R2 RM Raise mounted Remarks
R3 SEL Selectable Value
C1 TBD To be decided / Test Select Value
D1 TM Turret mount Remarks
C2 P Pattern side Remarks
Q1 RS Radiation Shielding Remarks
D2 L Mounted with L clamp Remarks
U1 BM Box mount Remarks
T1/L1 VM/HM Vertical mount/Horizontal mount Remarks
C4 FM Flat mount Remarks
Q3 HS Mounting with heat sink Remarks
33
Table 17 : Component list (Integrated circuits only)
COMPONENT LIST
PROJECT PACKAGE CARD NO
CODE
MODEL FM/ETM SYSTEM STACK CODE
Sr. Component / Package Library Mil

Ref.Des Function Location Remarks Tsl . No
No Part Number Style No. Spec
Signature of Inspector Signature of subsystem Engineer
Table 18 : Component list

COMPONENT LIST
PROJECT PACKAGE CARD NO
CODE
MODEL FM/ETM SYSTEM STACK CODE
Sr Ref. Package Library Alt Tol Minimum Mil Test.

Value Function Location Remarks
No Des Style Number Value % Rating Spec Slno
Note : P – Pattern /Solder side
Signature of Inspector Signature of subsystem Engineer
34
6.15 Checklist for the designer
It is observed that the lack of checklists is the major cause of design errors in the layout. Each designer shall verify
a Checklist before starting layout design. The designer shall make sure that “YES” answer for the questionnaires in
the following table.
Table 19 : Checklist for the designer

SR.
CHECKLIST FOR THE DESIGNER ACTION
No.
Whether all the components required for this layout are available in
1
the approved parts list of the concerned project.
Does the system library contain all the parts which are required in the
2
proposed layout.
Do you have the complete mechanical drawing of the proposed PCB
3
layout, which is duly approved by QA mechanical and PROJECT.
Do you have the complete information of wire routing in and out of
4
the layout.
Do you have the height information of the components, brackets,
spacers, and heat sinks, position of the card in the package, the package
5
mechanical configurations like size and shape of base, side rings,
connectors, type of turrets
Is this a new layout or old layout for revision. If for revision did you go
6
through the history sheet traveler of the old card.
Did you consider the proposed track width / components de-rating
7
factors and fabrication tolerances.
8 Package Design Review Recommendation has been implemented
35
7 DESIGN OUTPUT GENERATION
7.1 Gerber file generation
Design Rule Check (DRC) shall be conducted before creating the spool files. It is preferred to generate an
assignment report and design status report to verify the design requirements. File shall be generated in EXTENDED
GERBER (RS274X) format or compatible format. Aperture size less than 2mil/0.05mm shall not to be used for
photo plotting.
7.1.1 Layers required to be made ON

Only one electrical layer and associated non-electrical layers shall be switched ON for creating spool file for a layer.
Designers shall check whether all the relevant information for documentation of layouts as per Table 20 is complied
while creating the spool file. The following table shows the required details in each layer.
Table 20 : List of details required in each layer of spool files

Layer Tracks Vias Pads Buried Texts Layer ID in box, Layer ID, layer code Figures
no. vias outside the card inside the card
area
1 Yes Yes Yes No Yes Yes Yes Yes*
2 Yes Yes Yes No Yes# Yes Yes# Yes*
3 Yes Yes Yes Yes* Yes Yes Yes Yes*
4 Yes Yes Yes Yes* Yes# Yes Yes# Yes*
9 Yes Yes Yes No Yes Yes Yes Yes*
10 Yes Yes Yes No Yes# Yes Yes# Yes*
*- If required only; #-Shall be mirrored;
7.2 Report generation

The following reports shall be generated during the spool file generation.
7.2.1 Board status report

Board status report shall be generated for the routing completion verification prior to generation of output files.
7.2.2 Assignment report

This describes the complete assignment information of the pads, patterns, design rules etc. The report format may
be as per the system output.
7.2.3 Symbol availability report

This report is used for photo plotting applications. Standard symbol table report output from PCB design file is
acceptable. This report is not essential when RS274X format is used.
36
7.2.4 Drill tool table report
The drill file shall be generated in EXCELLONE OR Compatible format. The origin of the file shall be at the
left-bottom most pad. For PTH, NPTH and buried vias, separate drill files shall be generated. The number of tool
changes including the pilot tools in one file shall be restricted to a maximum of 32. The drill table report shall be as
below.
Table 21 : Drill tool table report (Sample)

PROJECT INSAT 2E CARD NUMBER NTC10203
MODEL FLIGHT No. of Layers 8
FORMAT EXCELLON Buried via design Yes
LAYER PAIR DRILL FILE NAME DESCRIPTION
C&S tc2021.drl PTH Drill file
3&4 tc2023.drl Buried via pair (PTH Drill file)
5&6 tc2025.drl Buried via pair (PTH Drill file)
C&S tc2028.drl NPTH Drill file
Tool code and drill sizes shall be as per Table 22 and Table 23. It is not essential to generate this report when
enhanced excellone or compatible drill format is used.
7.3 Drill file generation

The drill dia requirements shall be as per Table 10. The file shall be in EXCELLON or compatible format. Separate
drill files shall be generated for NON PTH and PTH holes. It is to be noted that the Registration and Indexing pads
shall have separate and unique tool codes. (For example T1,T2 is reserved for registration purposes). The number
of drill types NPTH or PTH in one card shall be limited to 32 including pilot drills.
Table 22 : PTH drill tool allocation table

SR No Tool Code Finished Hole Dia
1 T1 Registration
2 T2 Indexing
3 T3 3.0mm
4 T4 0.8mm
5 T5 0.9mm
6 T6 1.0mm
7 T7 1.2mm
8 T8 1.6mm
37
Table 23 : NPTH Drill tool allocation table
Tool Code Finished Hole Dia
T1 Registration
T2 Indexing
T3 3.0mm
T4 1.2mm
T5 3.2mm
T6 4.5mm
T7 5.5mm
T8 7.5mm
7.4 Fabrication and assembly wiring details

Following hard copies shall be generated for the fabrication and assembly of PCBs. Design shall accompany component
list, Component marking / component placement plot, mechanical drawing, drilling details, inner layer copies, layer
stack diagram, PCB layout data sheet and PCB layout ordering sheet. One set of softcopies of the above details shall
be provided.
7.4.1 Drilling details print

Drill file may be generated and used from CAD system, this refers to NC drilling.
It is preferred that various colors are used for indicating different hole sizes to be drilled.
7.4.2 Component marking print

For component marking print the following guidelines shall be followed:
Except for diodes, the component symbols need not be used and only component numbers are to be indicated. The
orientation of the component identification marks shall be in the same orientation of component.
If components are mounted on solder layer (pattern side) a mirrored component marking print shall be generated
and aligned to the top side marking print.
Component reference designators & polarity should be clearly legible.
7.4.3 PTH marking print

Unused PTHs having size more than 0.5 mm, shall be identified for PTH filling.
Any special requirements to be taken care in fabrication stage (either PCB manufacturing or electronic fabrication)
shall be clearly mentioned in the following details: drilling details, component marking print, mechanical drawing and
component list.
7.4.4 Ordering data for PCB

Filled PCB ordering data sheet shall be approved by QA/QC before sending to the manufacturer.
The PCB ordering data is as shown in table below.
38
Table 24 : PCB ordering data sheet
SR. NO. CHARACTERISTICS NOMINAL VALUES
1 Specification doc. ISRO-PAX-301, ISSUE-3
2 Master pattern (film) name/no.
3 Process As per approved PID
4 Base material and dielectric constant
(a). Single sided. ,
(b). Double sided with PTH (Default),
5 PCB Type
(c). Multi layer (no of layers) (Buried Via or Normal)
(d) Flexi-Rigid PCB
(a). 0.8mm + 0.1mm
Total Thickness of PCB with tolerance (metal to (b). 1.70mm + 0.15mm
6
metal) (c). 2.25+-0.15mm
(d). 3.20mm + 10%
Layer Nos. & lay-up
1 2 3 4 5 6 7 ..........13 14
order.
Total Copper thickness
in microns
7 Layer Details
Film print (+/-)
VCC/GND layers
Metal core layers
8 Buried via pairs
(a). Increase 0.00mm
9 Finished pattern variation compared to films (b). Maximum decrease in pattern shall not exceed double the copper
thickness
(a). Solder coating (default)
(b). Solder plating
10 Type of protective plating (c). Gold with nickel under plate
(d). Only gold
(e). Solder mask on bare copper
(a). As per enclosed hard copy (default)
11 Drilling details (b). NC drill soft copy
(c). Buried via pairs drill details soft copy
Yes/No, If Yes
12 Solder mask required Colour Thickness Material
Green 17.5µm Epoxy
13 Solder mask layer films / files provided Yes/No
14 PCB layout data sheet provided Yes/No
(a). CDO./.PCB/.BRD file
15 PCB file for CAD layout
(b). Spool file in Extended Gerber format
16 Mechanical base drawing of PCB/ NC Rout file Yes/No
Controlled impedance / metal core/ rigid flex
17 Layer stack provided Yes /No/ NA
layer stack
Note: Polarity of film (+/-) shall be filled by film inspector (in case of MLB)
DATE:
Recommended by:
Name:
Signature:
39
7.5 PCB design folder generation - hard copy
The details required in the hard copy folder are as shown in table below.
Table 25 : List of details required for the folder generation all hard copy
items required to
items required IN
Sl send Fabrication
Item DescripTion PCB DESIGN FOLDER
No. facility
yes/no quantity yes/no quantity
Mechanical (Card base) Drawing of the
1. Yes 1 No
card
2. Layout data sheet Yes 1 No
3. PCB ordering data Yes 1 No
Approval sheet (yellow sheet) of layout
4. along with reworks reported during Yes 1 No
inspection
Symbol availability report with file size
5. Yes 1 No
and date.
Design status report (If system is
6. Yes 1 No
capable of giving the report)
Registration check report of films
7. Yes 1 No
( for multilayer only)
8. Approval sheet (yellow sheet) of film Yes 1 No
9. Component lists Yes 1 Yes 1
10. Component marking prints Yes 1 Yes 1 /Card
11. PTH marking prints Yes 1 Yes 1/Card
12. Drilling details Yes 1 No
13. Inner layer copy Yes 1 No
14. NC drill report Yes 1 No
15. Special requirement details copy Yes 1 Yes 1
16. Stack drawings (for mother boards only) Yes 1 Yes 1
Schematic drawing revision control
17. Yes 1 No
form
18. Schematic drawing hard copy Yes 1 No
19. PCB Design traveler card Yes 1 No
20. Layer stack drawing (If any) Yes 1 No
Note: Card number, project, model shall be written on the right top page of the folder.
7.6 Output CD Preparation

The design output CD shall contain the following information and their formats are as below. In the root directory
of the CD or root directory of card name, if multiple cards are written in one CD, a readme.txt file shall be made
depicting the file name and purpose of file.
40
Table 26: List of information and format to be stored in design output CD
STATUS\REMARKS
ITEM FORMAT FILE NAME
YES No
Design files in design directory
PCB Design file Cadstar/allegro CardNumber.pcb/.brd
Schematic file Cadstar/orcad CardNumber.sch/.dsn
Documentation in docs directory
PCB Layout data
MS Word Layout_data_sheet.doc
sheets
PCB Ordering sheet MS Word Pcb_order_sheet.doc
MS Word / Microsoft
Component list Comp_list.doc. Comp_list.xls
Excel
Component
Postscript, gif/jpg/pdf Comp_mark.ps, gif/jpg/pdf
marking prints
PTH marking prints Postscript, gif/jpg/pdf Pth_mark.ps, gif/jpg/pdf
Drill marking prints Postscript, gif/jpg/pdf Drill_mark.ps, gif/jpg/pdf
Layer_mark
Inner layer prints Postscript, gif/jpg/pdf
. ps, gif/jpg/pdf
Nc drill report file MS Word/Note pad Nc_report.rpt
HPGL, GIF/jpg/
Check plot, PCB Penplot.plt, gif/jpg/ps
postscript
Schematic prints Postscript/pdf Sch_files.zip/pdf
Schematic Netlist
ASCII Sch_netlist.cdi
File
PCB Netlist ASCII Pcb_netlist.cdi
Base drawing Postscript, gif/jpg/pdf Base_dwg.ps, gif/jpg
Layer stack Doc/Pdf/jpg CardNumber_Layerstack.doc/pdf/jpg
IPCD356 netlist ASCII CardNumber_IPCD356.net
Output Files : in output directory
Spool files for
Gerber 274X only Gerber_files.spl/gbr
photoplotting
NC drill file and
Excellon 2.4 format Nc_drill.drl, route.rou
rout file
Library Files : in library directory
Symbol library Symbol.lib cadstar
Parts library Parts.lib Cadstar/orcad
Footprint library Footprint.lib Cadstar/allegro
41
8 INSPECTION OF PCB LAYOUTS
8.1 General
All the layouts shall be inspected in accordance with this document. Only those PCB layouts which are electrically
approved by the concerned subsystem/design engineers shall be taken up for inspection.
Layouts of a particular package shall be submitted for inspection along with the following details.
Table 27 : List of details to be submitted along with new layout

Sl No. ITEM Qty.
1. Approved mechanical drawings of the card. Indicating its size, stacking hole 1
locations, connector locations if any, track restricted area, maximum allowable
component height at various locations etc.
2. PCB layout data sheet 1
3. Schematic design file 1
4. PCB design file 1
5. Symbol, Parts, Foot print libraries 1
6. Component list 1
7. Special information if any 1
8. All files listed in para 7.5 as hard copy in folder and listed in para 7.6 as soft 1
copy in CD
N : Number of PCBs required to be fabricated
When the layout is approved, all the copies of component list and PCB layout data sheet shall also be approved. A
copy of the component list per PCB and package drawing of a particular package shall be attached in PCB design
folder.
8.2 On-screen inspection

This inspection includes the checking of dimensions of components used in CAD library of PCB layouts designed
in CAD. Inspector shall also inspect various electrical and fabrication parameters of PCB layout. Inspector shall
conduct on-screen inspection to verify the Design Rule Check (DRC) and other reports.
8.2.1 Gerber /NC drill/NC rout file inspection

Dimensional details of the foot prints, mechanical dimensions of the card, conductor spacing, line width parameters,
drill and rout dimensions etc, shall be verified using the Gerber viewer / editor software.
8.3 PCB Layout inspection check lists

Layout shall be checked in the following manner. A detailed Checklist for each step of design process is provided
below. Since PCB layout design is a dynamic process, new check points surfacing during the course of time shall be
added to relevant check lists.
42
8.3.1 Checklist for schematic symbol
Checklist 1 : Checklist for schematic symbol
Sl. No Checklist for the designer Observation
1. Unique name for the symbol is provided
2. Conforming the standard symbol practices of ANSI/IEEE
3. Names, pin numbers, texts are legible.
Size of symbols shall not be too big/small and preferably use 0.1”
4.
grid spacing.
8.3.2 Checklist for foot print inspection

Checklist 2 : Checklist for footprint inspection
1. Foot print name / Lib.no. matched to approved foot print drawing
Profile (body profile, Notch mark, square pad, chamfer) of polarized
2.
component shall match to the polarity / pin number 1
3. Dimension meets with approved foot print drawing
4. Pad stack is matching to the approved foot print drawing
5. Drill information match to the approved foot print drawing
6. Stay out area marking match to the approved foot print drawing
7. Height information matches to datasheet / footprint drawing
Pin numbering and orientation is matching with approved foot print
8.
and data sheet
9. Soldermask definitions are correct
10. Paste mask definitions are correct
11. Anti pad definitions are correct
12. Any other attributes if added shall match to the datasheet
8.3.3 Checklist for part inspection

Checklist 3 : Checklist for schematic part
1. Unique part name to identify the part is provided
2. Power/GND pins are named correctly
3. Number of symbols in part matches to the data sheet
Pins of symbol correctly mapped to the part / footprint as per
4.
datasheet
All the pins defined like input, output, in-out, passive, pin type etc. is
5.
correct and matches to the datasheet.
All the pins are numbered (Mechanical pins need not be numbered
6.
if CAD system permits)
7. Pin numbers, names does not overlap with drawing features
All pins are named (mandatory only for Alphanumeric pin
8.
numbering)
9. Pin, Gate swapping provisions are defined
10. Pin 1 is +ve for polarized capacitors
43
11. Pin 1 is anode for diodes
12. Any other attributes if added shall match to the datasheet
8.3.4 Checklist for schematic drawing

Checklist 4 : Checklist for schematic drawing
Sl. No Checklist for schematic drawing Observation
Polarities of polarized capacitors are marked and correct symbol
1.
is used.
2. Nets are named as per standard naming practices
3. Pin no. 1 of polarized capacitor is +ve
4. Pin number 1 of diodes is matching to anode.
5. Alphanumeric numbering of pins if any verified.
6. Two types of symbols for same type of part not allowed
7. Values of all the components match to component list
8. Style of all the components match to the component list
9. Voltage of all components match to the component list
10. Trace width and necking information is defined in schematic
Pin numbering of all symbols matches to the pin number in foot
prints defined in the component library.
Verify this specifically for
11. Relays
Transistors
MOSFETS
Optocouplers
12. Power connected to ground or output not allowed
13. Power connected to tristate not allowed
14. GND connected to power or output not allowed
15. GND connected to tristate not allowed
16. Output connected to output when not OR tieable
17. Output connected to tri-state not allowed
18. Card number and revision is identified
19. Un allocated symbols not allowed
Power and ground signals are separately identified for main and
20.
redundant systems
21. All the required nets are listed and no unwanted nets are listed.
22. Nets to be connected across the pages are connected
Schematic drawing is electrically approved by system engineer and
23.
date entered
24. Schematic revision control sheet is verified.
44
8.3.5 Checklist for design initiation
Checklist 5 : Checklist for PCB design initiation
Sl. No Checklist for PCB design initiation Observation
Schematic drawing is approved and has incorporated all the
1.
modifications of previous revision if any.
Polarities of electrolytic capacitors are correctly marked in the
2.
given schematic.
Whether all the components required for this layout are available in
3.
the approved parts list of the concerned project.
4. All components required in the design available in parts library
Complete mechanical drawing of the proposed PCB layout which is
5.
duly approved by Mechanical/ DPD
Complete list of non conformances observed on the previous
6.
version. (For revising the layout)
List of modifications to be incorporated and reasons. (For revising
7.
the layout)
8. Information of wire routing ‘in and out’ of the layout is provided.
Height information of the components, brackets, spacers, heat
sinks. Position of the card in the package, the package mechanical
9.
configurations like size and shape of base, side rings, connectors,
type of turrets.
Is this is a new layout or old layout for revision. If for revision
10. did you go through the history sheet (Available in the fabrication
folder) traveler of the old card is provided.
Track width proposed conforms de-rating factors and fabrication
11.
tolerances.
All the components listed in layout is from PPL or non PPL
12. components has necessary approval from component approving
agency.
8.3.6 Checklist of items required for final layout approval

Checklist 6 : Checklist of items required for final layout approval
ITEMS/ DESCRIPTION
SI. No Observations
(Provided as soft copy in CD)
1. Schematic file and Schematic net list
2. PCB design file and PCB net list
3. Library files
4. Spool files
5. Assignment report and design status report
6. Approved base drawing
7. Approved package drawing for mother boards only
8. Components list
9. Special requirement lists
10. PCB layout data sheet
11. PCB ordering data
45
ITEMS/ DESCRIPTION
SI. No Observations
(Provided as soft copy in CD)
12. NC drill file and Route file
13. Drill drawings and NC drill report
14. Component marking print
15. PTH marking print
16. Inner layer prints
17. Layer stack diagram (If required)
8.3.7 Checklist for component list
Checklist 7 : Checklist for component list

SI No Check Parameters Observations
Components are selected from PPL /QML list and components list
1.
is as per standard format.
2. Connectors details like type and ESCC /MIL part number.
3. Relays details like part number, MIL number and coil voltages etc.,
4. IC’s details like type, package, function, and MIL number.

SMD’s details like type, values, Alt value, tolerances, voltage and MIL
5.
number.
6. IC’s, HMCs, CQFPs have pin count details with package type.
Transistors details like part number, package style, MIL number is as
7.
per PPL
Diodes /zeners details like part number, package style, MIL number,
8.
voltage is as per PPL
Resistor details like style, value, Alt.value, tolerance, min rating, MIL
9.
number is as per PPL
Resistor networks details like type, value, Min rating, tolerance and
10.
MIL No.
Capacitors details like style, value, Alt.value, tolerance, min rating,
11.
MIL number is as per PPL
Transformers details like maximum height /size, wire gauges & no. of
12.
wires used for winding
Transformer details like full winding diameter, core part no. “SEL”
13. in value column, HM,VM and to be ecco-bonding requirement in
remarks column.
Components requiring clamps/heat sinks are identified in C/L and
14.
details of the requirement are given in drawings.
Components, which requires radiation shielding and potting is
15.
identified in C/L in remarks column including thickness.
Turret mount components are identified in C/L remarks column
16.
as “TM”
Box mount components are identified in C/L remarks column
17.
as “BM”
46
SI No Check Parameters Observations
Any box mount components require extra space in the card
18. to accommodate projections or wire routing and the same is
mentioned in C/L or in drawings.
Pattern side components are marked as ‘P’ in the C/L and Flat
19.
mounting components marked as ‘FM’ in the C/L.
Any repeated / missing SI. No’s of component symbols does not
20.
exist
SEL/NC component shall have all columns filled except value
column. SEL/NC shall be marked in the value column. Devices like
21.
FPGA, PROM’s and RAM shall be clearly mentioned as “SEL” in
value column along with component name in function column.
The daughter cards components list is enclosed, If it is
22.
mother board
23. Component list shall be signed by S/S and Layout Inspector
24. Special requirement is mention in C/L remarks column
8.3.8 Checklist for component verification

Checklist 8 : Checklist for component verification
Compliance to approved
footprint drawing
Component type/ Pad dia Drill dia document and pin
SL No
No. of pins mm mm mapping of component
data sheet
Y/N
1
2
..
..
8.3.9 Checklist for mechanical details

Checklist 9 : Checklist for mechanical details
SI. No Check Parameters Observations
1. PCB Identification No. is placed as per PCB design file.
2. PCB size (L x W x T) is mentioned.
Stack hole locations and pitch/ different mounting hole diameter
3.
as per the mechanical drawing.
4. Whether tolerance requirements is achievable or not?
No Track area, No Via area, No component area shall be clearly
5.
drawn/Identified.
Board marker location and shape/cutting edges/routing path
6.
details available.
Card edge to package wall spacing provided is sufficient for wire
7.
routing / connector assembly.
47
Metal parts/spacer to track/pad/component body spacing
8.
(20mil/0.5mm).
9. Type of laminate used is mentioned.
Maximum allowed component height on component and pattern
side, card edge to ‘S’ hole, clamp M hole, connector M hole,
10.
scooping dimensions are mentioned in drawing and layout comply
with the requirement.
‘S’ hole placement and chamfering in layout is as per card base
11.
drawing.
Sl. No. of connectors are mentioned in mech. Drawing and match
12. to the component list. Connector mounting hole pitch, Connector
to adjacent component (connectors with brackets) are taken care.
Number of layers and thickness of PCBs (With tolerance) is as per
13.
data sheet.
Mechanical drawing is approved and signed by Mechanical QA /DPD
14.
Subsystem.
If it is motherboard Whether the daughter cards approved
15. mechanical details enclosed. Dimensions shall be referenced from
common datum (absolute).
Inter card spacing (for mother boards only) depends on tray height
16. or highest component used and ‘viewed from inside‘ method is
preferred.
Highest component allowed in tray type design is “card surface
to tray top spacing – 1.5mm”. Inter card spacing on non tray type
17.
design is highest component height + 3.5mm (when no components
are mounted on pattern side of top card)
Maximum height of component mentioned in mech. drawing
18.
conforms to the tray used.
8.3.10 Checklist for PCB layout design file

Checklist 10 : Checklist for PCB layout design file
1. Design integrity with respect to schematic drawing is checked
Schematic drawing component list, PCB design component list and
2.
hard copy component list shall match for value, voltage and styles.
Card Identification No, Layer Identification / Layer identification box
3.
is provided.
Component placement orientation /locations/ pad code/ and pin
4. number 1 identifications /card edge to trace/pad/component spacing
is verified.
Component names shall be provided in between component pads
5.
and texts shall be close to the components.
6. Component dimensions are as per foot print document.
Spacing between components, switch on profile alone and make
7. sure that no profiles are overlapping each other (Min 10 mils
spacing for general components).
48
Texts for IC’s, Relays, connectors, transformer, transistor and coils
pin No’s identifications, polarities for capacitors, etc. and their
8. readability. (Polarity in case of SMD CWR, CTC; first and last pin
identifications in case of CQFP and TO can IC’s). Min Text size 60/10
mils.
Pattern side mounting as mentioned in C/L and is it possible to
9. remove the components without disturbing the other components.
(Reworkability).
Power transistor/ICs additional termination pads are provided and
10. identification of B, C, E. Spacing between two power transistor shall
be 5mm.
Turret mounting types, locations, spacing, lacing holes in between
11. turrets, identification no for every 5th turret. Board to turret first
row 200 mils, Staggered second row 400/350 mils.
Lead termination details of Box mounting components on PCB is
12.
provided.
For components requiring wire terminations like, TO-3, TO-66, TO-
13. 204AE check spacing and drill size (1mm for TO-66 and 2.5mm for
TO-3 and 3.2mm for TO204AE B & E pads)
For components which are to be mounted on clamps /heat sinks, S
14.
hole placement should be as per Mechanical drawing.
Placement of PTHs/ track underneath the components that have
metallic bottom/body/Lead spread devices (Like relays, TO5,
15. IC’s, TO18, TO72 transistors, opto couplers, RER resistors, power
transistors, coils, vertical mount coils, transformers etc.) is not
allowed.
Vibration sensitivity and potting clearance of components like glass
16.
diodes/ Resistor N/W/ Relays/ HMCs
17. Text assignments height to width. Min 60/10 mils.
18. Copper assignments height to width. Min 60/10 mils
For Surface mounted components avoid acute angles and ensure
19. that trace is routed in between pads; vias are not allowed in
between/on SMD pads.
Lacing of components having weight more than 7 Gms/lead or
20.
welded leads is taken care.
Turret mounting provision is given for more power dissipating
21. components or component which requires multiple removal /
replacement.
22. Pad/via to trace ratio 1.5: 1 is taken care.
23. Special requirements are complied with (if mentioned in data sheet).
24. Layout is signed by S/S and mentioned as Electrically OK.
49
8.3.11 Checklist for conductors
Checklist 11 : Checklist for conductors
SI.No Check Parameters Observations
1. Different trace sizes identified in data sheet
2. De-rated current carrying capacity is complied
3. Acute angles / Acid traps are avoided
4. Tangential connections not allowed
5. One mil shift of traces are not allowed
6. Hanging traces are not allowed (except for guard traces, guard
traces at least one end shall be terminated)
7. Multiple traces are not allowed.
8. Track assignments: Min 15 mils (typ)
Varies for CQFP/ Fine pitch devices (10 mil with ½ oz Cu )
9. For 3 oz copper thickness minimum track width is 20 mils.
10. Identification of tracks having more than 100V
Spacing between tracks as per Table 12
11. Necked tracks to be verified with S/S for maximum current capacity.
12. For 2 oz copper thickness minimum track width is 12 mils in
inner layers .
13. Routing and connectivity is verified and 100% routed.
8.3.12 Checklist for clearance

Checklist 12 : Checklist for clearance
SI.No. Check Parameters Observations
Card edge to trace /pad / components / text 40mils/ turret 200
1.
mils/ lacing holes 100 mils/ mounting holes.1.3d min and 1.5d max
HMC to adjacent components spacing:
2.
HMC to HMC 300 mils, HMC to component 250 mils.
Crystal oscillator to adjacent components. Minimum 300 mils
3.
No track/via below crystal area.
Minimum hole edge to hole edge spacing (free hole), is greater than
4.
the thickness of PCB.
Relays and their terminal spacing EL-210, 215 min 1500 mils (M.
5. hole to Turret 1500 mils clearance for harness).Vias are not allowed
under the harness running area.
6. Metallic bodies to track/pads spacing. Min 20 mils.
7. Spacing between traces/pads/vias. Min 8 mils.
Spacing between raw bus to any net Min. 20 mils for intra layer, 6
8.
mil inter layer (dielectric thickness)
If main and redundant circuits are used in same PCB they shall be
9. separated by at least 50 mil within the layer. Main and redundant
circuit traces/planes shall not overlap between layers.
10. All spacing assignments to be checked.
11. DRC check is carried out
50
12. Layer stack drawing is provided for high voltage designs
8.3.13 Checklist for gerber files

Checklist 13 : Checklist for gerber files
1. Spool files in Extended Gerber format (274X) is provided
2. System Assignments reports are checked for correctness
3. Status reports of PCB after DRC is generated
4. Card Identification No is checked
5. Readability of all files verified
6. Card size (L x W) is mentioned
Card edges to corner M holes & Stack hole pitch as per the
7.
drawing is verified
8. Trace size and its decodes are verified
9. Pad size and its decodes are verified
No via, No track area/chamfer in the PCB as per the Mechanical
10.
drawing
11. Isolation requirements in power plane: 10 mils
Card edge to stack hole dimensions
12.
Max 1.5D, Min 1.3D
13. Card edge to track /pad/component body edge spacing. Min 40 mils
14. Spacing between tracks. Min 8 mils
15. Spacing between pads. Min 8 mils
16. Spacing between pads to tracks. Min 8 mils
17. Pad to trace ratio 1.5: 1
18. Component texts & polarities, Min size 60/10
19. Components pin No.s markings
Measure the fine pitch comp dimensions, Ist and last pin
20.
Identifications
21. Mirroring of texts in even layers
22. Minimum track/ pad sizes
23. Current carrying capacity of trace/pad/vias
24. Board markers only in external layers
Moire, registration, index & plating measurement pads (157mil,
25.
80mil, 60mil & 120mil)
26. Test coupon location, connections and ids and film registration pads
Connector locations and pin no.1 identification with plug/socket, 90
27.
deg bent/straight identification.
28. Turret locations and lacing holes
29. Turret No’s and order
30. For MLBs no inner layer connections present to Turrets
31. Layer identification numbers
51
32. Origin setting of layers
Avoid multiple power/GND plane connection to same solderable
33.
pad
34. Copper filling and filling decodes
Positive power plane files to be used; Recommended to use 2nd and
35.
Last-but-one layer as Power plane layers.
36. Multiple pad/trace not allowed
37. Dangling traces not allowed
38. One mil shifts not allowed
39. Square traces not allowed
Looping of traces not allowed (if provided get s/s engineer’s
40.
consent)
41. Track to pad entry is centered.
42. Save Gerber files in 274x format if any corrections done.
Power –plane pad conversion .Isolation in power plane layers from
43.
card edge minimum 40mil, & isolation for all NPTH holes
44. Verify pad count in different layers to avoid missing /multiple pads.
45. NPTH area and spacing requirements in all layers
46. Compare spool file report and system report
Origin of all layers shall be same and minimum 0.5” away from
47. bottom left corner of PCB or left bottom corner of PCB. (All data
shall be in first quadrant)
48. Generate solder mask files with 10 mil bulging if required
Check addition of open window trace for peel strength pattern in
49.
solder mask layer
50. Split power plane layers/ free hole to plane (Min 20 mils isolation)
51. Add layer identity text in the first solder mask layer
52. Add mirrored identity text in the last solder mask layer
53. Isolated copper with blocking in split power plane design.
Prepare layer stack and generate net-list. Check whether VCC and
54. GND/any other power lines shorts.
Floating copper in power plane layer (confirm s/s requirement)
If S holes are PTH, Pads in all layers and in mask layers shall be
55.
increased.
For 5&3 pin flat mounted regulators soldermask shall be opened
56. for Cu areas, and it shall be mentioned soldermask is open in layout
data sheet.
For controlled impedance layout layerstack shall be provided and
57. the same shall be mentioned in data sheet and ordering data.
Controlled Impedance test coupon to be added in spool files.
58. Component to component generic: 10 mil
52
8.3.14 Checklist for NC drill/rout files
Checklist 14 : Checklist for NC Drill/rout files
1. Card Identification No
2. Drilling details hard copy inspection signed by designer and
inspector
3. Check and count all PTH pads
4. Check drill size with respect to component lead size
5. Check and count all Non PTH pads
6. Check for no drill pads
7. Check NC drill report file with Excellon 2.4x format
8. Check readability of file
9. Check all drill decodes of NPTH and PTH
10. Separate color for each drill codes
11. Check Route file for card size as per base drawing.
12. Check for registration and redundant pads
8.3.15 Checklist for Component marking print

Checklist 15 : Checklist for component marking print
1. Card Identification no. on both sides
2. All components names are legible and mounting sides are matched
with component list.
3. Repetition/ overlapping/ merged with pads of components shall not
be allowed. Component names/Text size shall be legible 60/10.
4. Symbols for diodes, zeners and polarities for capacitors are
provided and match to the layout/schematic.
5. Computer prints shall be provided.
6. Component side & pattern side shall be aligned and stapled
properly.
7. Missing of component names are not allowed
8. Signed by designer and Inspector with full name
9. Special instructions (if any)
8.3.16 Checklist for PTH marking print

Checklist 16 : Checklist for PTH marking print
1. Card Identification No on both sides
2. Unused PTHs having size more than 0.5 mm, shall be identified in
separate colour
3. Thermal via/stitching vias/ vias which are directly connected to
ground without spokes shall not be marked for via filling
4. Signed by designer and Inspector with full name
5. Special instructions (if any)
53
8.3.17 Checklist for CD data contents
Checklist 17 : Checklist for CD data contents
STATUS\REMARKS
ITEM FORMAT FILE NAME
YES No
Design files
PCB Design file CadStar CardNumber.cdo or pcb
Schematic file CadStar, Orcad CardNumber.csd or sch
Documentation
PCB Layout data Layout_data_sheet.doc
MS Word
sheets
PCB Ordering Pcb_order_sheet.doc
MS Word
sheet
MS Word / Microsoft
Component list Comp_list.doc. Comp_list.xls
Excel
Component
Postscript, gif/jpg/pdf Comp_mark.ps, gif/jpg/pdf
marking prints
PTH marking
Postscript, gif/jpg/pdf Pth_mark.ps, gif/jpg/pdf
prints
Drill marking
Postscript, gif/jpg/pdf Drill_mark.ps, gif/jpg/pdf
prints
Layer_mark
Inner layer prints Postscript, gif/jpg/pdf
. ps, gif/jpg/pdf
Nc drill report
MS Word/Note pad Nc_report.rpt
file
HPGL, GIF/jpg/
Check plot, PCB Penplot.plt, gif/jpg/ps
postscript
Sch_files.zip/pdf
Schematic prints Postscript/pdf
Schematic Netlist
ASCII Sch_netlist.cdi
File
PCB Netlist ASCII Pcb_netlist.cdi
Base drawing Postscript, gif/jpg/pdf Base_dwg.ps, gif/jpg
CardNumber_layerstack.doc/
Layer stack Doc/pdf/jpg
pdf/jpg
IPCD356netlist ASCII CardNumber_IPCD356.net
Output Files
Spool files for
Gerber 274X only Gerber_files.spl/gbr
photoplotting
NC drill file and
Excellon 2.4 format Nc_drill.drl, route.rou
rout file
Library File
Symbol Symbol.lib cadstar
Parts Parts.lib Cadstar/orcad
Footprint Footprint.lib Cadstar/allegro
54
9 MASTER PATTERN
9.1 Introduction
Master Pattern or Photomaster is the photo plotted film of the spool file in automatic photo plotters. Masters are
always 1:1 scaled films that are used in the PCB manufacturing. It is the last crucial stage in the process of the PCB
before actual PCB manufacturing is undertaken.
9.2 Requirements of Master pattern

Master pattern shall completely match to the approved gerber file.
The entire master pattern shall be in positive and in 1:1 scale. All the pads in the master pattern shall be solid and
annular pads are not allowed. In case of double sided cards, the entire component side pattern (side-1) shall appear
in one film and the solder side pattern (side-2) shall appear in the other. The master pattern shall have Right reading,
emulsion down. When inspected at 10X magnification master patterns shall not have any pin holes, cuts, scratches,
residual emulsion, discoloration or any other defect that may cause poor photographic reproduction on further
processing. Multi layer master pattern shall have flow control patterns at the edges, test coupons and moir pads for
registrations.
9.3 Material for master patterns and its tolerance

Base material and emulsion shall be dimensionally stable. Thermal coefficient or linear expansion shall be 0.001%/
0
C and humidity coefficient of linear expansion shall be 0.0013% / 1% change in relative humidity. Processing
dimensional change shall be less than 10% in processed film. The polyester films shall be of 7 mil thick. If glass plates
are used they shall be of 60mil thick. Films or plates shall be of very high contrast type for better line definition and
good contrast is required for manufacturing PCB.
9.4 Handling and storage

The master patterns shall be submitted for inspection only in flat containers. In order to avoid scratches, each film
shall be kept in separate polythene covers. Films shall not be exposed to direct sun light or photocopying machines
or ammonia print machines. This will affect the stability of films and thereby cause registration errors. The films shall
never be rolled. The flat container shall be opaque and shall have adequate strength to protect films from physical
handling damages.
9.5 Preconditioning of films

The films shall not be exposed to temperatures beyond 25 0C. The films shall be kept at the lab temperature of 22
+ 2 oC for at least 4 hours before conducting any measurements on the films. This is done to stabilize the films.
9.6 Mis-registration
Only preconditioned films shall be subjected to registration error check. Registration error between layers shall be
within +1mil (+/-0.5 mil for fine via PCBs) about the absolute value with respect to the spool files. For each set of
films, registration error print report of measured values and absolute values shall be maintained in the PCB design
folder. The registration error shall be measured in the maximum diagonal length.
55
9.7 Checklists for Master Pattern
The entire master pattern shall be inspected using the following check list.
Checklist 18 : Checklist for master patterns

QC
S/N CHECK PARAMETERS SPECIFICATION / REQUIREMENT
OBSERVATION
1 Ensure PCB number on all the layers
Ensure approval of layout(s) and Layout data sheet(s) should have
2
spool file(s) approval seal and signature
Handling damages like ragged edges,
Minor – Acceptable
3 scratches, cuts, impressions, bends Minor / Major/ Nil
Major – not Acceptable
etc.,.
Shall be free from dirt, grease, chemical /
4 Cleanliness of the film OK. / Not OK.
solvent residues etc.,.
5 Thickness of the film 7 Mil
+0.000mm
6 Dimensional tolerance of the film
-0.030mm
50 microns, maximum (25 microns for
7 Registration error
fine via PCBs)
Evidence of under exposed / over
8 Exposure of the film
exposed development- Not allowed
9 Track to track/pad joining angle Shall not be <90º
10 Track width / pad diameter As per data sheet +0.00 mm;- 0.030 mm
0.20 mm or 0.003 mm/V peak to peak,
Minimum spacing between tracks/
11 whichever is greater (except for SMD
pads
pads and Strip-line tracks)
Spacing from card edge to tracks /
12 1.00 mm, minimum
components / pads
Defects like pinholes, voids, nicks, cuts The defects shall not reduce track width
13
etc., on tracks / pads / pad dia by more than 10 %
Check for unconnected tracks,
14 Not allowed
missing patterns, shorts etc.,.
Ensure that (1) Board edge
markers, (2) Registration pads, (3),
15
indexing pads, (4) plating thickness
measurement pads are provided.
Not <2 nos. for panels having one card;
16 Number and location of test coupons Not<3 nos. for panels having more than
2 cards; diagonally opposite
Card no. to be printed in external
layers of all test coupons with correct
17 Test coupon identification
orientation, HORIZONTAL & VERTICAL
marking
Ensure that unconnected pads in
18
power plane layers are visible
56
QC
S/N CHECK PARAMETERS SPECIFICATION / REQUIREMENT
OBSERVATION
Isolation of unconnected pads in 10 mil isolation surrounding the pads
19 power plane inner layers as well as in inner layer. Normal pads 15 mil and
external layers Turret pad 20 mil in external layers
Connected pads in power plane inner Single cut; isolation = pad diameter + 10
20
layers mil
Connected pads in power plane 2 cuts maximum; isolation = pad dia + 10
21
external layer mil
Ensure that Tray stay-out area is free
22
of pattern/ pads/ components
Ensure that top, bottom and solder
23
mask layers are positive
Ensure that all inner layers are
24 negative or positive based on process
type followed
Ensure that all buried via films are
25
positive
Ensure that all odd layers are
26 mirrored (and even layers are not
mirrored).
Ensure that layer number is provided
27
in each of the inner layers.
Ensure that hatch patters are
28
provided with logo.
Ensure that multi-line alignment pads
29
are provided.
30 Others, if any (specify)
NOTE: ISOLATION requirements are for general PCBs. For high voltage designs appropriate spacing requirements
shall be met.
57
10 Consideration for Generation of Land Pattern Designs for Various parts
10.1 Introduction
This section provides information about calculation of land pattern (foot print) dimensions for various components
used in onboard PCB layouts. The intent of information herein is to provide size, shape and mounting configurations
to ensure conformance to workmanship standards/ guidelines for foot print design/inspection.
Continued emphasis on increased functionality, faster, smaller and lighter electronic systems is making component,
PCB and system packaging more complex. The complexity increase is due to increasing use of surface mount
packages, which is the key to miniaturization of electronic products. Lead pitch plays a critical role in the complexity
of manufacturing process and also demands changes in design, fabrication and assembly processes.
Land pattern geometries can be slightly different based on the type of assembly techniques used to attach the
electronic part. Wherever possible, land patterns are defined in such a manner that they are transparent to the
attachment/assembly process.
The compilation of footprints in this document addresses land pattern designs for all types of passive and active
components including DIP, axial, radial, chip devices, small outline devices, flat packs, quad flat pack (QFP), Quad flat
no-lead (QFN), quad flat pack J-lead (CQFJ) packages and Leadless Chip Carrier (LCC) etc.
Designers should be able to use the information for the computer aided designs. For specific packaging/assembly
techniques which are not discussed in this document, the designer shall consult the QC/QA of the respective
centre regarding the PCB design, attachment/assembly process, inspection and testing details etc. before finalizing
the onboard PCB layout design.This is to ensure that design, assembly and inspection process will result in a reliable
product.
10.2 Considerations for land pattern design

This section discusses the broad guidelines adopted for the design of land patterns for various types of components:
active/passive, axial/radial, through hole/Surface Mount Devices etc. At a few places, these guidelines are tailored to
meet specific needs of each component.
Note: 1. Unless otherwise specified, all components are viewed from the top of the component for
the design of its footprint.
2. Maximum Body Length = Body Length+ Positive Tolerance
3. Lead diameter for hole calculation shall consider the maximum lead diameter ie. nominal lead diameter
+ tolerance.
10.3 Axial lead - passive/active components

Components like RCR, RNR, Diode Outline (DO) and related components are considered under this category.
Following method is used for the determination of the land pattern design.
• Inter hole Distance (Center to Center) = Maximum Body Length + 6 to 12 times of lead diameter. Nominal
dimension taken in the document is 6 times lead diameter (d)
58
• Finished Hole Diameter = Lead Diameter in mm + 0.2 mm
• Pad diameter = Finished Hole Diameter in mm + 0.7mm
10.4 Axial lead passive components with welded leads and with lacing holes
Components like CSR, CLR (Tantalum capacitors) and related components are considered under this
category. Following method is used for the determination of the land pattern design.
• Inter hole Distance (Center to Center) = Maximum Body Length (including weld) + 6 times of lead diameter
+ hump diameter (if required) 5mm x 2; in case of loop no extra space is required.
• Finished Hole diameter = lead diameter in mm + 0.2 mm
• Pad diameter = Finished Hole diameter in mm + 0.7mm
• Lacing holes to be spaced within the body length, on either side of the device and distance between them
must be equal to the body diameter. Lacing hole drill dia is 1.2mm free hole.
10.5 Axial lead passive components without welded leads and with lacing holes
Components having large volume like CRH and related components are considered under this category.
• Inter Hole Distance (Center to Center) = Maximum body length + 6 times of lead diameter. Considering the
loop, no Extra space required (In case of camel hump method, diameter of 5 mm x 2 shall be added)
• Finished Hole diameter = Lead diameter in mm + 0.2 mm
• Lacing holes to be spaced within the body length, on either side of the device and distance between them
must be equal to the body diameter. Lacing hole dia is 1.2mm free hole.
10.6 Radial lead passive components

Components like CKR and related components are considered under this category. Following method is
used for the determination of the land pattern design.
• Inter Hole Distance (Center to Center) = Lead center to lead center distance (if pads are not touching each
other).
• Body to bend distance (if flat mounted) = height of the device + 6 times of lead diameter.
• Finished Hole diameter = Lead diameter in mm + 0.2 mm
Note: Flat mounting preferred.
10.7 Surface mount passive leadless devices

SMD Components like chip resistors 1206, 0603 and related components are considered under this category.
59
Figure 5: Surface mount passive leadless device component and footprint
• X = max width (W) + process tol. in mm+ placement tol. in mm+ 0.15mm x2
• A =G+Y
• Z = max length in mm + prt. in mm+ plt. in mm+ 0.75mm x2
• G = Lmin – (2 x e + prt + plt)
• Y = Z- G/2
Prt = Process tolerance for 1 oz copper = 0.13mm
Prt = Process tolerance for 2 oz copper = 0.20mm
Plt = Placement tolerance = 0.1mm
10.8 Surface Mount Active Devices with un-formed lead devices

Components Packages like FP14, FP16, and CQFP84 to 356 and similar components are considered under
this category. Following method is used for the determination of the land pattern design.
• Inter land spacing(Inner edge to inner edge) B = Body width nominal + 40 mil
• Land width(LW)= 1.5 times Lead width, (Min 7 mil inter land space is to be maintained).
• Land length = 120 mil
• G= B+Land Length; where G is land center to land center distance.
10.9 Surface Mount Active Device with formed lead devices

Components Packages like CQFPXX, FPXX, SOXX are considered under this category. Following method
is used for the determination of the land pattern design.
• Inter land spacing (inner edge to inner edge) B = Wing Span – 2 x Feet Length – 4 x Lead Width – Prt.
• Land width 1.5 times of lead width, provided 7 mil inter land space is available else maintain inter land spacing
to 7mil while trimming the land width.
Note: Prt. = Process tolerance=5mil
10.10 Surface Mount Active Device with formed J-leaded devices

Components like CQFJ84 are considered under this category. The following formula is used for the
determination of the land pattern design.
• Inter land spacing (inner edge to inner edge) B = ‘J’ lead’s center to center – 2R –2 x1. 1mm. (Heel)
• Note: Corner lands if found touching then shall be chamfered.
60
• Land outer edge to Land outer edge = wing span (lead outer edge to lead outer edge) +2 x lead thickness +
2 x 1.1mm (toe)
• Land width 1.5 times of lead width, provided 7 mil inter land space is available else maintain inter land spacing
to 7mil while trimming the land width.
• Note: For 50 mil pitch component 35mil width land is standardized.
• Land length = (outer edge – inner edge)/2
• R = Radius of J lead formation
10.11 Other considerations

1. Component whose body temperature raises 10oC above the ambient shall be placed with suitable heat
sinking provisions.
2. Component which are weighing more than 14 grams or which has welded leads shall have additional
mechanical support like fasteners, or lacing provisions.
3. If component body is live (attached to any electrically functional pins), necessary isolation shall be provided
to isolate them from trace/copper in the PCB.
4. Trace routing /via is not allowed under lead spread devices on top layer below the component (Like TO18,
TO72, TO can Ics or relays).
5. Via and traces are not allowed under the power dissipating metallic body flush mounted devices.
6. Components that require radiation shielding (as per maximum thickness requirement) shall be given with
space for shielding.
7. Component that requires potting (vertical mounted CMR/CKR capacitors etc) shall be given with space
around.
10. Dip Mica (CMR) type capacitors with styles above CMR04 shall be flush mounted.
11. Positioning a component shall consider the available height above and below the PCB. A minimum of
2mm clearance shall be provided to the nearby assembly.
12. Unless otherwise specified, thermal rails, thermal planes/cores, or heat sinks on the PCB shall be
thermally connected to the package housing. Also thermal rails/planes/cores shall not be used for electrical
functions.
13. Trace entry to turrets shall be on external layers only.
14. Minimum trace to pad width ratio 1:1.5
61
11 LAYOUT DESIGN PROCESS CERTIFICATION PLAN
11.1 PCB layout designer / inspector training
PCB Layout designers shall be certified by the concerned centre QA for the design/inspection activities.Training and
certification plan is as below.
11.1.1 Course material

Study Material for the certification comprises of PCB designers training manual based on ISRO-PAX-301 and other
relevant standards
Total program shall be divided into five sections:
• Design considerations
• Layout principles
• Component and assembly issues
• Printed board characteristics
• Documentation and dimensioning
11.1.2 Course duration
Total training is planned for 5 days where first half of the day is identified for theory and second half for hands-on
training on software tools used for the PCB design and manufacturing file generation.
11.1.3 Evaluation and certification

At the end of training there is a comprehensive evaluation to assess the participants understanding, knowledge, skill
level and problem solving capability. Evaluation is conducted for both theory and practical aspects.
11.1.4 Maintenance of certification

At regular interval, a refreshment training shall be provided to the candidates who has passed the certification
examination. This is to update the current technologies, developments, tool sets, features and discussion on list
of nonconformance observed in the EDA (Electronic Design Automation) environment and onboard PCB layouts
designed at respective ISRO centres.
Major steps for the layout design process certification shall be as follows:
1. Facility evaluation by the concerned centre team.
2. Preparation of design process document.
3. Generation of symbols for the components
a. Resistors
b. Capacitors
c. Discrete devices
d. Integrated Circuits
e. Relays and connectors
f. List of newly added components which are not in the existing PPLs
4. Generation of footprints.
62
5. Generation of on-board parts library using parts library editor.
6. Parts library approval from QC/QA
7. Generation of schematic drawing given for certification process.
8. Component list preparation as per standard component list format.
9. Create board area with stack hole, no track area, etc.
10. Set design rules, layer stack, constraints, etc
11. Component placement and approval.
12. Request for change of placement
13. Routing and smoothening.
14. Generation of hard-copies required for Electrical inspection
a. 2:1 color plots for top and bottom
b. Net list
c 1:1 layer printouts
d Layout data-sheet
15. Request for change of schematic correction and engineering change order
16. Pin/gate swapping, component renaming and back annotation.
17. Manufacturing detail creation.
18. Gerber file generation with power plane conversion.
19. NC drill file generation, Route file generation & Wiring data generation.
20. Component & PTH marking.
21. Drilling detail
22. Component list
23. PCB Layout data sheet
24. PCB ordering information sheet
25. Final approval of layout and issue of certification from the concerned ISRO centres
11.2 Re-Certification
Re-certification is carried out on the following events.Vendor shall undergo certification process or processes listed
by concerned centre QA to obtain the certification.
• Vendor has not supplied any approved PCB layout designs for a period of 6 months.
• Change in the design tool (not the revision of software tool).
• Changes in the design process and process identification document.
• Unsatisfactory work output for three continuous PCB layouts.
11.3 Renewal of certification

Renewal of certification is invoked when the period of certificate validity to be extended for next one year. This is
issued based on the performance of the vendor for past one year. Vendor is required to list down all the onboard
63
PCB layout designs completed during immediate past two years. This shall be listed in the following format along
with their internal assessment on adequacy of close outs generated for each design and effectiveness of close out
in controlling recurrence.
Table 28 : Format for design completion record

Inspection / Audit Close out Adequacy of close out &
Sl No Design Name
observations by QA provided Recurrence control (Yes/No)
1.
2.
Assessment of Online quality control of the vendor. Assessment and recommendation of the QA for issuing renewal
certificate.
64
12 TERMS AND DEFINITIONS
Terms and definitions used herein are in accordance with IPC-T-50.
Assembly
A number of parts of subassemblies or any combination thereof joined together.
Note: When this term is used in conjunction with other terms listed herein, the following definitions shall prevail.
Assembly, double-sided
A packaging and interconnecting structure with components mounted on both the primary and secondary sides.
Assembly, multilayer printed circuit

A multilayer printed circuit board on which separately manufactured components and parts have been added.
Assembly, multilayer printed wiring

A multilayer printed wiring board on which separately manufactured components and parts have been added.
Assembly, packaging and interconnecting (P&I)

The generic term for an assembly that has electronic components mounted on either one or both sides of a
packaging and interconnecting structure.
Assembly, printed board

An assembly of several printed circuit assemblies or printed wiring assemblies, or both.
Assembly, printed circuit

A printed circuit board on which separately manufactured components and parts have been added.
Assembly, printed wiring

A printed wiring board on which separately manufactured components and parts have been added.
Assembly, single-sided
A packaging and interconnecting structure with components mounted only on the primary side.
Base material
The insulating material upon which the conductor pattern may be formed.The base material may be rigid or flexible.
It may be a dielectric sheet or insulated metal sheet.
Basic dimension
Theoretically exact location of a component feature, indicated by a symbol or a number in a box. (The tolerance on
a basic dimension provides the limits of the variation from the basic dimension location.)
BGA (BALL GRID ARRAY)

A surface mount device whose leads are array of balls under the device.
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Castellation
Metallized features that are recessed on the edges of a chip carrier which are used to interconnect conducting
surfaces or planes within or on the chip carrier.
Chip carrier
A low-profile rectangular component package, usually square, whose semiconductor chip cavity or mounting area is
a large fraction of the package size and whose external connections are usually on all four sides of the package.
Chip-on-board (COB)
Integrated circuit device mounted directly to the printed board and interconnected with wire bonds.
Coefficient of thermal expansion (CTE)

The linear thermal expansion per unit change in temperature.
Component
A separable part of a printed board assembly which performs a circuit function (e.g., a resistor, capacitor,
transistor, etc.)
Component Mounting Side

A location on a P&I structure that consists of a land pattern and conductor fan-out to additional lands for testing or
vias that are associated with the mounting of a single component.
Conductive pattern
The configuration or design of the conductive material on the base material. (Includes conductors, lands and through
connections when these connections are in integral part of the manufacturing process.)
Conductor
A single conductive path in a conductive pattern.
Constraining core
A supporting plane that is internal to a packaging and interconnecting structure.
Dual in-line package (DIP)

A component which terminates in two straight and parallel rows of pins or lead wires.
Fine-pitch technology (FPT)

Surface mounted components with a lead or termination pitch of 25 mil or less.
Fiducial
A feature of the PB used to provide common measurable points for all steps in the assembly process.
Flat pack
A component with two straight rows of leads (normally on 1.27mm centers) which are parallel to the
component body.
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Footprint
(see preferred term “Land Pattern”)
FPGA
Field programmable gate array. This device can be used for realizing digital circuits from schematic or hardware
description languages.
Grid
An orthogonal network of two sets of parallel equidistant lines used for locating points on a printed board. (Note:
Connections should be located on the cross-points of the grid lines.The position of conductors may be independent
of the grid, i.e., not necessarily following the gridlines.)
Integrated circuit (IC)

An assembly of miniature electronic components simultaneously produced in batch processing, on or within a single
substrate to perform an electronic circuit function.
Jumper Wire
An electrical connection that is a part of the original design, added between two points on a printed wiring board
after the intended conductive pattern is formed.
Land
A portion of a conductive pattern usually, but not exclusively, used for the connection, or attachment, or both of
components.
Land pattern
A combination of lands intended for the mounting, interconnection and testing of a particular component.
Leadless chip carrier

An electronic component whose external connections consist of metallized termination’s containing a single
integrated circuit chip.
Leaded chip carrier

An electronic component whose external connections consist of leads emanating from the sides of the package,
which contains a single circuit chip.
Layout
Layout is one of the design steps for fabrication of PCB. It is drawn on a inch / mm graph paper or directly using CAD
software, identifying the conductor pattern, shape, width, length and spacing with other conductor or component. It
also gives the orientation, mounting pads, clearance between components, heat sink mounting requirements photo
plotting requirements, MLB layer alignment provisions etc
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Master drawing
A document that shows the dimensional limits or gird locations applicable to any or all parts of a printed board
(rigid or flexible), including the arrangement of conductive and nonconductive patterns or elements; size, type, and
location of holes; and any other information necessary to describe the product to be fabricated.
Microvia
A blind via whose size is less than 0.1mm. These are normally placed on the lands of surface mount pads to transfer
the traces to inner layers. Micro via process require laser drilling and conductive material filling. These are essential
to route micro BGA designs.
Mixed mounting technology

A component mounting technology that uses both through-hole and surface mounting technologies on the same
packaging and interconnecting structure.
Module
A separable unit in a packaging scheme
Nominal
Design dimension for the size of a feature. (The tolerance on a nominal dimension gives the limits of variation of a
feature size.)
Packaging and interconnecting structure (P&I)

The generic term for a completely processed combination of substrates, metal planes or constraining cores, and
interconnection wiring used for the purpose of mounting components.
Plated-through hole (PTH)

A hole in which electrical connection is made between internal or external conductive patterns, or both, by the
plating of metal on the wall of the hole.
Primary side
That side of the packaging and interconnecting structure that contains the most or more complex components.
The primary side establishes layer one of the P&I structure. (The same as the “component side” in through-hole
component mounting technology.)
Printed board
The general term for completely process printed circuit or printed wiring configurations. It includes rigid or flexible,
double and multilayer boards.
Printed wiring
The conductive pattern intended to be formed on a common base, to provide point-to-point connection of discrete
components, but not to contain printed components.
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Registration
The degree of conformity of the position of a pattern, or a portion thereof, with its intended position or with that
of any other conductor layer of a board.
Secondary side
That side of the packaging and interconnecting structure that is opposite of the primary side. (The same as the
“solder side’ in through-hole component mounting technology.)
Single in-Line package (SIP)

A component which terminates in one straight row of pins and lead wires.
Static electricity
An electrical charge that has accumulated or built up on the surface of a material.
Static electricity control

A technique where materials and systems are employed to eliminate/discharge static electricity build up by providing
continuous discharge paths.
Supported hole
A hole in a printed board that has its inside surface plated or otherwise reinforced.
Supporting plane
A planer structure that is a part of a packaging and interconnecting structure to provide mechanical support,
thermo-mechanical constraint, thermal conduction and/or electrical characteristics. (It may be either internal or
external to the packaging and interconnecting structure.)
Surface mount technology (SMT)

The technology where electrical connection of components is made to the surface of a conductive pattern of a
printed board and does not utilise component lead holes.
Thermal expansion mismatch

The absolute difference in thermal expansion of two components (materials).
Through connection
An electrical connection between conductive patterns on opposite sides of an insulating base, e.g., plated-through
hole or clinched jumper wire.
Through-hole technology (THT)

An assembly process for mounting component packages where leads are passed through supported (plated through)
or unsupported (bare) holes in an interconnection substrate.
Tooling feature
A specified physical feature on a printed board or a panel such as a marking, hole, cut-out, notch, slot or edge, used
exclusively to position the board or panel or to mount components accurately. (See Fiducial)
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Via
A plated-through hole used as a through connection, but in which there is no intention to insert a component lead
or other reinforcing material.
Blind via
A via that is connected to either the primary side or secondary side and one or more internal layers of a multilayer
packaging and interconnecting structure, but not to both sides.
Buried via
A via that is connected to neither the primary side nor the secondary side of a multilayer packaging and interconnecting
structure, i.e., it connects only between inner layers.
Tented via
A blind or through-hole via that has the exposed surface of the primary or secondary or both sides of a packaging
and interconnecting structure fully covered by a masking material, such as a dry film polymer coating (solder
mask), pre-impregnated glass cloth (prepreg), etc., in order to prevent hole access by process solutions, solder, or
contamination.
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13 CURRENT CARRYING CAPACITY IN PULSED MODE OPERATIONS
During pulsed mode operations, conductor current shall not be more than rated current and average current shall
not be more than the de-rated current. Rated current is ~ three times of the de-rated current.
The formula for estimation of temperature rise at ground environment is ;
[ ]
1 2.2727
Temperature rise in oC T =
k.(A)0.725
OR Current I = k*A 0.725
*T 0.44
I = Current in Amperes
A = Cross section area of the conductor in mils
K = 0.024 for internal layers / external layers in vacuum conditions
Current calculated for 10o C, is de-rated to 66% is used for estimating the current carrying capacity in
space environment. As thumb rule, pulse current shall be less than 3 times of the de-rated current calculated at
100 C. For further details, refer IPC-2152 current carrying capacity charts for vacuum/ space environment.
Assuming spacecraft ambient temperature as 30o C, Temperature raise from above ambient shall be limited to
50o C at any conditions.
Average current = Pulse ON current * Duty cycle
Note : Above equation assumes pulse OFF current = Zero
[ ]
Pulse ON Time
Where duty cycle =
Pulse OFF Time + Pulse ON Time’
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14 HIGH SPEED PCB DESIGN GUIDELINES
Objective of this guide lines are to;
• Minimize the high speed signal reflections and the associated signal losses / radiations
• Minimize the cross talk
• Minimize or eliminate the timing related errors within matched group signals of data, address or
control lines
• Minimize the skew within the differential pairs
14.1 Critical length

The critical length, as used in Signal Integrity & in this document, is taken to be a quarter of the wavelength of the
signal being transmitted.
14.1.1 Single-ended transmission lines

The circuit in figure below is an example of a single-ended transmission line. The impedance value is determined by
the dimensions of the trace, dielectric constant of board material & thickness of the dielectric.
Figure 6: Single-ended Transmission Lines
Single-ended transmission lines
Input Controlled impedance Output

A B
Terminating Resistance
There are several configurations of PCB microstrip:
 Surface Microstrip
 Embedded Microstrip
 Coated Microstrip (the coating will usually be solder mask)
These structures are illustrated in the following diagrams. Note that in the following diagrams the signal trace is
actually trapezoidal in profile & width ‘W’ refers to the trace width nearest to the upper surface, ‘W1’ refers to
the trace width nearest to the lower surface, T is the thickness of traces & εr the dielectric constant of the board
material.
14.1.2 Surface Microstrip

Surface microstrip is the simplest configuration where the surface of the live conductor is exposed as shown in
figure below.
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Figure 7: Surface Microstrip
14.1.3 Embedded Microstrip (Stripline)

Embedded/buried/Microstrip is similar to the surface microstrip, however the signal line is embedded in a dielectric
& located at a known distance H1 from the reference plane.
14.1.4 Coated Microstrip

Coated microstrip is same as the surface version, however the signal line is covered by a solder mask. The
solder mask coating can lower the impedance by up to a few Ohms (depending on the type & thickness of the
solder mask).
Figure 8: Coated Microstrip
14.1.5 Differential transmission lines

Controlled impedance PCBs are usually produced using microstrip or stripline transmission lines in single-ended
(unbalanced) or differential (balanced) configurations. The differential mode of operation is shown here
Figure 9: Differential Transmission line
Controlled impedance
Input Output
A B
Terminating Resistance
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The differential configuration is used when better noise immunity & improved timing are required in critical
applications. This configuration is an example of a balanced line ie. the signal & return paths have similar geometry.
The lines are driven as a pair with one line transmitting a signal waveform of the opposite polarity to the other. Fields
generated in the balanced lines will tend to cancel each other, so EMI & RFI will be lower than that with unbalanced
lines & problems with external noise are reduced.
14.2 Ringing
Ringing is a signal timing related problem & can be defined as the number of times the wave form moves up and
down following a logic level transition ie. ringing is repeated overshoots & undershoots. It can occur due to several
reasons such as lack of termination resistor, reflection, device rise time, line length, line impedance mismatching,
discontinuities & loading.
14.2.1 Minimize ringing

Ringing can be reduced by making the electrical line length shorter than critical length. Ringing can be reduced by
providing better matching of the source & load impedances to that of the transmission line.
14.3 Overshoot and Undershoot

Overshoot is the first peak or valley past the settling voltage - the highest voltage for a rising edge & the lowest
voltage for a falling edge. Undershoot is the next valley or peak. Excessive overshoot can cause protection diodes to
turn ON, leading to early field failures.
Undershoot is the second peak or valley past the settling voltage - the deepest valley for a rising edge & the
highest peak for a falling edge. Excessive undershoot can cause false clocking or data errors.
Pin-to-pin delay is the time difference between the driver state change & the receiver state change.
These changes are usually taken at 50% of the supply voltage. The minimum delay is taken when the output
first crosses a defined threshold and the maximum delay is taken when the output last crosses the voltage
threshold measured.
14.4 Reflection, Reasons and its elimination

A reflection on a transmission line is an echo. A portion of the signal power (V & I) transmitted down the line goes
into the load, & a portion is reflected. Reflections are prevented if the load & the line have the same impedance.
Reflections are observed when impedance discontinuities exist in the transmission line. The discontinuities are:
 Lack of termination
 Improperly matched termination circuits.
 Change in trace width
 Vias between routing layers
 T-tubs, branched or bifurcated traces
 Changes in impedance of the trace
 Varying load and logic families
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 Connector transitions
 Large power plane discontinuities.
14.4.1 Solutions to eliminate reflections
Reflections in a net is primarily due to the impedance mismatch between the source, destination and conductor
(transmission line) connecting source to destination. In order to minimize the reflections the following methods can
be implemented.
• Design the PCB with Power planes and signal layer pairs so that controlled impedance can be achieved.
• Terminate the signals using the standard termination procedures
• High frequency nets with long routes should be terminated to avoid extra high frequency harmonics. Each
track has a critical length above which reflections are a maximum and below which they are reduced. This
critical length occurs when the round-trip delay time along the track is equal to the rise-time of the signal.
It is recommended practice to terminate lines whose length is close to or above this critical value. Series
terminator shall be at source or parallel terminator at receiver end.
• Ensure the case is electrically continuous where possible.
• For a split case ensures a good electrical contact is made when the halves are clamped together- this might
involve using conductive gasketing. The case must be electrically continuous, so any display windows, cooling
slots, etc need grilles fitting if the wavelength of the incident RF is less than the dimensions of the aperture.
Ensure that unshielded wires don’t pass directly through the shielded enclosure.
• Connect case to main RF ground or star point ground.
• Use shielded cables for high sensitivity inputs.
• GND shielded cables at both ends unless this results in pickup & radiating loops.
• The shield of a cable must always be terminated in a connector & connected to the wall of the enclosure.
14.5 Cross-Talk
In a printed circuit board (PCB), crosstalk involves interaction between signals on two different electrical nets.
The one creating cross talk is called an aggressor and the one receiving it is called a victim. Often, a net is both an
aggressor and a victim. Crosstalk depends on the length of the parallel traces, the space between them & the rise &
fall time of the signal.
Figure 10 : Crosstalk
14.5.1 Capacitive cross-talk

Capacitive cross talk results from traces lying one over the other. In this case, electrostatic coupling is much larger
than electromagnetic field coupling.
 Coupling amount is a direct function of the spacing between the traces and the overlap area.
(capacitor size)
 Coupled signal exceeds design limits in very short runs.
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 Coupling can be so severe that such overlapping parallelism should be prohibited.
 Cross-talk can be controlled by carefully selecting the geometry in each signal layer.
 Adjacent signal layer cross-talk is best controlled with orthogonal routing rules.
 Care must be taken to ensure that logic families of different voltage swings, such as LVDS and MOS are
properly spaced to ensure that interfamily cross-talk is properly managed.
14.5.2 Inductive cross-talk
Inductive/electromagnetic coupling results from traces running side by side. In this case, magnetic field coupling is
much larger than electrostatic field coupling.
14.5.3 Design techniques to prevent cross talk

Some of the measures to be taken to reduce cross talk are:
 Minimize physical distance between components during placement.

 Minimize parallel routed trace lengths.
 Group logic families according to functionality. Keep bus structure tightly controlled.
 Provide proper termination on impedance-controlled traces, or traces rich in RF harmonic energy.
 Locate components away from Input/Output interconnects & other areas susceptible to data corruption
& coupling.
 Reduce trace impedance and signal drive level.
 Reduce signal-to-ground reference distance separation.
 Route adjacent layers (microstrip/stripline) orthogonal. This prevents capacitive coupling between
adjacent layers
 Avoid routing of traces parallel to each other. Provide sufficient separation between traces to minimize
inductive coupling(the 3 W Rule: )
o 3 W Rule: The distance of separation between traces must be 3 times the width of the traces,
measured center-line to center-line - This rule for trace separation will reduce the crosstalk flux by
approximately 70%. (For a 98% reduction, change the 3W to 10W.)
 Isolate signal layers that must be routed in the same axis by a solid planar structure (typical of backplane
stack up assignments).
 Partition or isolate high noise emitters (clock, I/O, high-speed interconnects, etc.) onto different layers
within the stackup assignment.
 Keep the clock lines away from the I/O signal lines or have a good clock shielding to prevent coupling.
 Keep spacing between the adjacent active traces greater than trace width.
 Keep clock & other HF signals grouped together & separated from connectors and other low speed &
sensitive traces such as interrupt or reset lines.
 Do not share vias of multiple power supply lines for ground (GND) returns.
14.6 Cross talk and its reduction techniques for wires

Crosstalk refers to unintended electromagnetic coupling between traces, wires, trace-to-wire, cable assemblies,
components, & other electrical components subject to EM field disturbance. Crosstalk depends on the length of the
parallel traces, the space between them & the rise & fall times of the signal. It is to note that;
 Decreasing the trace separation increases the mutual capacitance (Cm) & the crosstalk.
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 With parallel traces, longer parallel lengths increase the mutual inductance (Lm) & the crosstalk.
 Decreasing the rise time of the signal, increases the cross-talk.
Some of the measures to be taken to reduce crosstalk are:
 Provide a band-limiting filter on specific transmission lines to prevent RF from coupling between source
& victim traces. This filter consists of a simple RLC resonant shunt circuit in series between the source
trace & 0V-reference.
 Route signal on adjacent layers perpendicular to each other wherever possible. (especially keep analog
and digital signals are routed together).
 Keep spacing between the adjacent active traces greater than trace width.
 Use narrow traces (8 mils or less) to increase HF dumping & reduce capacitive coupling.
14.7 Clock skew

Skew is the variation between the rising edge of one signal versus the rising edge of another signal. It can also be
measured between the falling edge of one signal versus the falling edge of another signal.
14.8 Design guidelines for LVDS signals

Low-voltage differential signaling (LVDS) is a high speed, low voltage, low power and low noise general-purpose I/O
interface standard. Its low-voltage swing and differential current mode outputs significantly reduce electromagnetic
interference (EMI). These outputs have fast edge rates that cause signal paths to act as transmission lines.
14.8.1 Differential Traces

LVDS utilizes a differential transmission scheme, which means that every LVDS signal uses two lines. The voltage
difference between these two lines defines the value of the LVDS signal. For successful transmission of LVDS signals
over differential traces, the following guidelines should be followed while laying out the board.
 Select the trace width and spacing to maintain the differential impedance of 100 Ohms (or as specified
by the designer)
o To ensure minimal reflections and maintain the receiver’s common mode noise rejection, run the
differential traces as closely as possible after they leave the driving IC.
o To avoid discontinuities in the differential impedance, the distance between the differential LVDS
signals shall remain constant over the entire length of the traces.
Figure:11 Differential traces in Microstrip & Stripline configuration
For better coupling within a differential pair, make S < 2W, S < B, and D = 2S where:
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W = width of a single trace in a differential pair
S = space between two traces of a differential pair
D =space between two adjacent differential pairs
B = thickness of the board
For good coupling between two conductors of a differential pair, the following rules shall be followed:
o Space between the conductors shall not be more than twice the width (S < 2W)
o Thickness of the board (Dielectric thickness from trace to ground plane) shall be more than the
space between the conductors (B > S)
o Space between two adjacent differential pairs shall be greater than or equal to twice the space
between the two individual conductors. (D > 2S)
 To minimize skew, the electrical lengths between the differential LVDS traces should be the same (within
5mm skew). Arrival of one of the signals before the other creates a phase difference between the signal
pair, which impairs the system performance by reducing the available receiver skew margin.
 Minimize/avoid vias or other discontinuities on the signal path.
 Any parasitic loading, such as capacitance, must be present in equal amounts to each line of the differential
pair.
 To avoid signal discontinuities, arcs or 45 o traces are recommended instead of 90o bents/turns.
The following guidelines shall be used while selecting the termination resistor for an LVDS channel.
 Place the termination resistor at the far end of the differential interconnect from the transmitter. A single
100 Ohms resistor is sufficient (Use as specified by the circuit designer).
 Use surface-mount thick-film leadless 0603 or 0805 size chip resistors (Avoid usage of leaded
resistors).
 Install the termination resistor within 7 mm of the receiver, as close to the receiver as possible.
Other general guidelines are:
 Keep the LVDS drivers and the receiver as close to any connectors as possible.
 The physical length of each trace between the transmitter outputs and the connector shall be matched
to within 5 mm of each other to reduce data skew.
 Isolate LVDS signals from TTL signals to reduce cross talk (preferably on different layers).
 Separate LVDS ground and supply planes.
 Keep stub lengths as short as possible.
14.9 Methods to reduce EMI

The following guidelines may be implemented by the designer to resolve EMI problems.
 Segregate digital circuits and analog circuits.

 Connect the oscillator directly to the microcontroller (switching IC) GND pin, using a short, direct trace.
Do not use a shared trace.
 Use a ceramic-bypass capacitor (.01 to 0.1 µ F) at the microcontroller’s VCC and GND pin connection.
 Use short leads and short traces.
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 Locate electrolytic caps on VCC at the Power connector before splitting analog & digital VCC.
 Assign each digital IC its own decoupling capacitor and place them in close proximity.
 Use short traces and small loops for driven digital outputs.
 Add filtering for noisy repetitive output signals. Use a series damping resistor (22 to 47 ohm) or inductor
placed at the output pin.
 If allowed, use EMI ferrite beads to replace less effective devices such as series R or L. This reduces I/O
signal interference. Use beads specifically designed for EMI suppression, placing output signal beads at the
driving pin and input beads at the input connector.
 Locate pull-up resistors at the corresponding signal driving output pin, not at the input pin.This minimizes
loop area.
 Use small loop areas for good ESD & external EMI immunity. This minimizes ESD GND input problems.
 Terminate the ESD ground to the chassis ground. If no chassis ground exists, terminate the ESD GND to
the power input ground at the connector.
 Use a 1-10nF decoupling capacitor right at the device connector. Connect the GND to ESD GND.
 Use ESD techniques for improved OTP-mode pin operation:
o Minimize circuit loop areas and provide diode clamps to VCC.
o Place a clamping diode on the microcontroller’s, OE, CE and VPP. Place these diodes close to the
microcontroller to reduce induced noise. Verify correct pin placement by checking pin diagram in
the product specification.
 Border the PCB with chassis GND or place the VCC plane back from the edge of the board by preferably
20 times the distance between planes.
o The ground plane should exceed the power plane by 20H where H is the total thickness between
the power and ground planes
 Avoid slit apertures in PCB layout, particularly in GND planes or near current paths.
 Track mitering (beveling of edges and corners) reduces field concentration.
 Don’t leave floating conductor areas, as they act as EMI radiators; if possible connect to GND plane.
 Guard traces surround the high-threat traces (critical clocks, periodic signals, differential pairs, etc.) and
are connected to the ground plane.
o The guard trace should be smallest, tolerable manufacturable spacing from the signal.
o The guard trace shall be connected to ground.
o If a ground plane is available, make ground connections no farther than 20 λ apart.
14.9.1 General Design Rules EMI control

The following design guidelines shall be followed for EMI critical packages..
14.9.1.1 Placement Rules

 Clock generators should be placed at the center of the region formed by the components they drive.
 Connectors and the components which are not connected electrically should not be closer than a
specified (by design engineer) minimum distance.
 Connectors and the components they are connected to, should not be further than a specified maximum
distance. This excludes passive and discrete components.
 High frequency regions/signals/groups shall be separated from the low frequency regions/signals/groups.
This is mandatory requirement.
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 The components of each clock generator circuit (and other high speed high current switching circuits)
should all be placed in their own floor planned room. This will allow them to be physically isolated and
shielded from the rest of the board.
 The boundaries of regions having different critical EMI properties should be fenced off with Faraday
shields. The fences should be placed at specified sensitive distances to the boundary and have a required
ratio of overlap with the boundary segments. This is mandatory requirement
14.9.1.2 Associated Placement Rules
 Filter elements (capacitors, resistors, ferrite beads, feed-through filters, etc.) associated with particular
elements (oscillators, connectors, power pins, etc.) will be placed immediately adjacent to the output or
input pin of the element they are intended to filter as designated by the engineer. Thus, maintaining the
shortest length of etch possible between the filter components and the element they are filtering.
 High frequency oscillators (clocks) are the worst source of EMI on a board. Their placement and the
nets to the elements they supply are usually the most critical nets. These clocks and their critical output
nets are usually placed first. One objective is to have the shortest length of interconnect etch possible.
Another objective is often to have nearly equal etch length to all elements supplied with clock signal.This
minimizes skew between clock signals.
 Large format (size) chips (DSPs, ASICs, microprocessors, etc.) with their associated EMI critical signal
nets are usually the next most critical elements to place. Such chips with very fast edge rate switching
are the next worse source of EMI. They are often also the most susceptible to receive EMI. As well, they
are often high heat dissipaters.
 A common EMI shielding technique is to place a ground shape (sometimes a heat sink) on the component
layer under a large chip in direct contact with its body. It is possible for such a copper area to act as both
an EMI shield and a heat spreader. One consideration is to place such components near the edge of the
PCB card where the copper area can come in contact with metal card edge guide rails. When thinking
about employing this technique it’s best to consult with the design engineer and assembly engineers
because the design choices can be technically complex while implementing.
14.9.1.3 Bypass Rules
 Bypass capacitors should be of specified types by the switching IC manufacturer.
 High current, high speed ICs and switching transistors should have a specified (by design engineer)
minimum number of bypass capacitors per I/Os.These bypass capacitors should be of specified types (by
design engineer). Banking of bypass capacitors to one pin and leaving other pin without bypass capacitors
shall be avoided.
 I/Os and switching transistors should have their bypass capacitors a certain specified (by design engineer)
distance from their power pins. This is mandatory requirement
 Critical high speed, high current I/Os and switching transistors should not have the loop area of their
power-ground paths greater than a specified amount (to be identified by the circuit designer). This is
mandatory requirement
 The boundary between adjacent EMC regions having different frequency classifications requires a specified
(by design engineer) minimum number of bypass capacitors per unit length. These bypass capacitors
should be of specified types.
14.9.1.4 Power and Ground Plane Rules
 Components shall be placed so as to cause the fewest number and size of voids, holes, slots and other
discontinuities in the power and ground planes.
The power and ground planes will cover the maximum usable (not counting edge keep outs, etc.) PCB
surface area.
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 Symmetrical ground shapes are to be placed under each clock generator.
 Z-axis separation between power and ground planes should be neither less than nor more than a
specified amount. This is mandatory requirement.
14.9.1.5 DC Routing Rules
 Power trace segments longer than specified amounts are to be bypassed to ground. Longer power trace
segments require a specified number of (equally spaced) bypass capacitors per unit length.
 The trace parasitic resistance between the voltage source pin (or power plane via) and the supply pin of
an IC or switching transistor shall not exceed a maximum permissible value. Likewise for the ground pin.
This is mandatory requirement
 The power and ground trace widths must be greater than a specified minimum amount.This is mandatory
requirement
14.9.1.6 Signal Routing & Quality Rules (Mandatory requirements)
 Critical nets will be ranked by EMI and timing priority. They will be routed in order of those priorities.
Critical nets are not to be routed within a specified (by design engineer) minimum distance to a card
edge. This distance may be different for buried (surrounded by shield layers) and exposed nets.
 Critical net exposed lengths shall not exceed a specified (by design engineer) amount.
 Critical nets shall not exceed their Manhattan length (Delta X + Delta Y Distance from node to node)
by a specified percentage (by the design engineer).
 Critical nets shall not have more than a specified number (by design engineer) of vias.
 Critical net via to pin ratio shall not exceed a specified (by design engineer) amount.
 Critical net to connector net cross talk cannot exceed a specified amount.
 Nets routed over clean ground shapes must cross the moat at right angles and have a minimum etch path
length within the clean ground shape.
 Critical nets must not be routed through connector footprints.
 Clock frequency spectral content may not exceed a specified spectral content envelope variable.
 Critical net overshoot and undershoot should not exceed a maximum percentage of the voltage swing.
 Critical nets must be terminated when the driver rise/fall is less than twice the propagation delay.
 Differential mode EMI for critical nets routed on external layers shall not exceed a specified amount.
 Total differential mode EMI for a board shall not exceed a specified amount (by the designer).
14.10 Signal integrity Analysis Reports

Following are the details/ reports required to be submitted for signal integrity/ controlled impedance analysis
Impedance reports
PCB layouts which require controlled impedance requirement need to be supplied along with reflection analysis
report. Layer stack used for the calculation of impedance shall be identical to that of the one used for PCB
manufacturing. Material type, dielectric constant and dissipation factor entries shall match to the material specification
of laminates.
Reflection analysis report
PCB layouts which require signal integrity analysis need to be supplied along with reflection analysis report. The
stimulus applied on the net while doing reflection analysis shall have the worst case signal rise time, amplitude and
frequency.
81
Matched group relative propagation delay check report
It is required to route the high speed address, data, control and clock lines in the matched groups constraints so
that timing errors can be eliminated. All the required matched groups and nets associated with each group shall
be mentioned by the designer. Constraints like relative propagation delay (if necessary) shall be mentioned in
requirement column and shall be verified against the requirements in the PCB layout design.
Propagation delay check report for bus groups

It is preferred to apply constraints like propagation delay for the nets having series terminators (multiple nets forms
Xnets and total etch length constraint becomes invalid). Total delay can be set between driver and receivers (pin
pairs) instead of nod to nod.
Cross talk analysis report

PCB layouts which require signal integrity analysis need to be supplied along with cross talk analysis report. The
stimulus applied on the net while doing cross talk analysis shall be the worst case signal rise time, amplitude and
frequency
82
15 RIGID FLEX PCB DESIGN GUIDELINES
15.1 Construction details of a rigid flex PCB
Figure 12:Typical example of single flexi layer - Rigid flex PCB construction
450 to 600 70 microns 50 microns 50 microns 70 microns

micorns total minimum cover Polyimide Copper
Polyimide Copper lay Kapton Core
Prepregs, Flexible PCB

Minimum 150 to 200
75 microns
microns
Strain relief compound may be

applied at rigid flex transition areas
Rigid PCB 1.7

+ 0.15 mm Prepreg Minimize the cover
Minimum 75 lay protrusion into
microns the rigid section
15.2 Design features of rigid-flex PCBs
Table 29 : Design features of a rigid-flex PCB.
SL No PARAMETER Specification
1. Track width 15 mil minimum

2. Track spacing 10 mil minimum
3. Pad dia 60 mil minimum
4. Land size 60 mil minimum
5. Hole dia 32 mil minimum
6. Effective card size Up to 18” x 14”
7. Warp and twist 1.0% maximum
50 microns minimum for flexible layers.
8. Dielectric thickness
100 microns minimum for rigid layers.
9. Cover-lay film 50 microns minimum with single side adhesive.
10. Finished card thickness 1.7 + 0.15 mm for rigid layer
11. Buried vias Not permitted.
Glass-Polyimide for rigid layers
12. Laminate material
All Polyimide for flex layers
Subtractive process with Laminate type construction
and SMOBC on rigid portion only.
13. Process
Cover lay bonding through separate lamination
process.
83
SL No PARAMETER Specification
14. Annular ring 0.13 mm in external layers, 0.05mm in internal layers.

15. Registration errors Annular Ring requirement must meet.
Solder using HASL, Solder mask 17 to 25 microns.
16. Protective coating
Matte-green color
17. Copper thickness 35 / 70 microns
One for dynamic application.
18. No. of layers in flexible area
2 for static application.
19. No. of layers in rigid area Rigid PCB rules can be applied.
15.3 Additional requirements for rigid-flex PCBs

For maximum dynamic flex life and maximum reliability for flex to install, conductors in the bend area should adhere
to the following considerations:
 Traces in the flexible area shall be perpendicular to the bend

 Evenly spaced across the flexible area. Guard traces for critical nets to avoid cross talk.
 Maximized cross section bend area (Preferable increased width not the thickness) of the trace. Do not
use plated copper in flexible area use only rolled copper.
 Do not neck traces in the flexible area. Locate wider traces at the outer edges and middle of the flexible
PCB (2.5mm inside) for stiffening.
 Conductors in double-sided circuits should not be placed directly over each other. This condition may
be necessary due to electrical considerations; however, mechanical installation requirements must be
considered.
 The number of layers in the flexible area should be kept to a minimum (less than or equal to 2). If traces
are bending at flexible area, they shall have curved bent and provision for holding/clamping the curved
portion to be made in the assembly. Vias and PTHs in flexible areas not allowed.
 The neutral axis, where possible, should be located at the center of the conductor. A balanced construction
can be achieved by using materials of equivalent modulus values and thickness on each side of the
conductor.
84
16 DESIGN RULES FOR PCB LAYOUT DESIGNS HAVING BGA /CCGA
DEVICES
16.1 Design rules for PCB layout designs having BGA devices
Design rules are summarized in the following table. This table is to be used in conjunction with check lists for the
approval of fine line PCB layout designs.
Table 30 : Design Rules for Layout Design having BGA devices and through vias.
Sl. no. Objects Specs in milS
Routing under BGA devices: ½ oz basic copper, external layer,
1. 5
minimum trace width
Routing under BGA devices: 1 oz basic copper, internal layer, minimum
2. 5
trace width,
Routing under BGA devices: ½ oz basic copper, external layer, minimum

3. 4
trace to land/via spacing, working voltage shall be less than 5v
Routing under BGA devices: 1 oz basic copper, internal layer, minimum

4. 4
trace to via spacing, working voltage shall be less than 5v
Land dia of BGA devices: minimum land dia shall be 90% of BGA ball
5. dia; ½ oz basic copper, external layer, working voltage shall be
less than 5v
Through via under BGA: minimum via : 0.2mm hole on 0.45mm pad
6.
(or more).
Solder mask pad for BGA lands maximum of 4 mil (nearby traces shall
7.
not be exposed)
8. Solder mask on vias (via shall be masked at least BGA side)
Illustrative footprints for 1272 pins CCGA and 1148 pins BGA are as follows.
85
Land Pattern Geometry for 1272 Pins,
1.00 mm Pitch, CCGA Device,
ISRO_CCGA1272
Figure13: Illustrative example of CCGA footprint

i
b
45º
c h
D
d
Feature Dimension (mm)

Solder Mask Window, b 0.80
Mounting Pad, a 0.70
Line Width, c 0.20
Via Hole Dia., d 0.20
Via Pad Dia., e 0.46
g 0. 50
h 0.50
Pitch, i 1.00
D/E 37.88
Height (max.) 5.94
Note: This is an illustrative foot print, ISRO centres may decide the necessary cleanrances according to
requirements.
- The above shown figure gives the typical dimension for dog-bone style non-solder mask defined
(NSMD) pad.
- Selective solder-mask shall be used for CCGA land-pattern area on component side only.
86
Land Pattern Geometry for 1148 Pins
1.00 mm Pitch, BGA Device
ISRO_BGA1148
Figure 14: Illustrative examole of BGA footprint
Feature Dimension (mm)

Solder Mask Window, b 0.70
Mounting Pad, a 0.60
Line Width, c 0.20
Via Hole Dia., d 0.30
Via Pad Dia., e 0.50
g 0. 50
h 0.50
Pitch, i 1.00
D1/E1 33.00
Note: This is an illustrative foot print, ISRO centres may decide the necessary cleanrances according to
requirements.
- In the sequence of card fabrication, the via-holes shall be filled & cured with conductive epoxy. Then the
solder mask shall be applied to cover the other areas except the mounting pad.
- Conductor track of 150 micron width can be run between the two mounting pads wherever required.
87
ANNEXURE-1
AXIAL RESISTORS TYPE: RCR
Device Pad Hole Lead

Sr No. Lib. No L W A
Type Dia Dia Dia
4.06 1.91 6.82 1.5 0.8 0.46
1 ISRO_RCR05_268 RCR05
(160) (75) (268) (59) (31) (18)
7.14 2.51 11.28 1.6 0.9 0.69
(281) (100) (443) (63) (35) (27)
10.32 4.01 15.06 1.7 1.0 0.79
(407) (158) (593) (67) (39) (31)
15.06 6.1 21.18 1.9 1.2 1.02
(593) (241) (833) (75) (47) (40)
18.49 8.5 25.33 2.1 1.4 1.14
(728) (335) (998) (84) (55) (45)
88
AXIAL RESISTORS TYPE: RLR

Type Dia Dia Dia
4.32 1.91 7.08 1.4 0.7 0.46
1 ISRO_RLR05_278 RLR05
(170) (75) (278) (55) (28) (18)
6.73 2.29 10.87 1.6 0.9 0.69
(265) (100) (427) (63) (35) (27)
10.16 3.51 15.32 1.7 1.0 0.86
(400) (150) (604) (67) (39) (34)
15.06 6.35 21.18 1.9 1.2 1.02
(593) (250) (833) (75) (47) (40)
AXIAL RESISTORS TYPE: RB

Type Dia Dia Dia
27.00 10.31 31.80 1.7 1.00 0.80
1 ISRO_RB52_1249 RB52
(1063) (406) (1249) (67) (39) (31)
89
AXIAL RESISTORS TYPE: RNR

Type Dia Dia Dia
5.72 2.03 8.18 1.4 0.7 0.41

1 ISRO_RNR50_321 RNR50
(225) (80) (321) (55) (28) (16)
7.14 3.81 11.28 1.6 0.9 0.69
(281) (150) (443) (63) (35) (27)
11.1 4.19 15.24 1.6 0.9 0.69
(437) (165) (600) (63) (35) (27)
16.66 6.35 20.80 1.6 0.9 0.69
(656) (250) (818) (63) (35) (27)
ISRO_RNR70_1067 22.23 8.89 27.09 1.7 1.0 0.81
5 RNR70
(875) (350) (1067) (67) (39) (32)
90
AXIAL RESISTORS TYPE: RNC
Hole Lead
Device L W A Pad
Sr No. Lib. No Dia Dia
Type Dia
7.32 2.54 11.16 1.6 0.9 0.64

1 ISRO_RNC55_438 RNC55
(288) (100) (438) (63) (35) (25)
10.70 3.70 14.54 1.6 0.9 0.64
(421) (146) (571) (63) (35) (25)
15.40 5.50 19.24 1.6 0.9 0.64
(606) (217) (756) (63) (35) (25)
22.23 8.89 27.09 1.7 1.0 0.81
(875) (350) (1067) (67) (39) (32)
91
AXIAL RESISTORS TYPE: RW

Type Dia Dia Dia
14.27 6.4 19.13 1.7 1.0 0.81
1 ISRO_RW69_754 RW69
(562) (252) (754) (67) (39) (32)
11.1 3.2 14.1 1.4 0.7 0.5
(438) (126) (564) (55) (28) (20)
23.8 8.7 24.8 1.9 1.2 1.0
3 ISRO_RW74_1172 RW74
(938) (343) (1172) (75) (47) (39)
46.79 10.3 52.79 1.9 1.2 1.0
4 ISRO_RW78_2077 RW78
(1843) (406) (2077) (75) (47) (39)
15.8 5.6 20.66 1.7 1.0 0.81
(632) (221) (824) (67) (39) (32)
92
AXIAL RESISTORS TYPE: RWR

Type Dia Dia Dia
22.17 5.6 27.03 1.7 1.0 0.81

1 ISRO_RWR71_1065 RWR71
(873) (221) (1065) (67) (39) (32)
11.1 3.17 14.40 1.5 0.8 0.55
(438) (125) (570) (59) (31) (22)
6.73 2.36 10.03 1.5 0.8 0.55
(265) (93) (397) (59) (31) (22)
8.30 2.40 11.60 1.4 0.7 0.55
(327) (95) (459) (55) (28) (22)
23.80 8.70 29.80 2.0 1.2 1.0
(938) (343) (1172) (79) (47) (39)
15.79 5.54 20.65 1.7 1.0 0.81
(622) (219) (814) (67) (39) (32)
93
AXIAL RESISTORS TYPE: MOX

Type Dia Dia Dia
7.62 2.67 11.76 1.6 0.9 0.69

1 ISRO_MOX200_462 MOX200
(300) (105) (462) (63) (35) (27)
11.05 3.68 15.19 1.6 0.9 0.69
2 ISRO_MOX300_597 MOX300
(435) (145) (597) (63) (35) (27)
12.95 4.19 17.09 1.6 0.9 0.69
3 ISRO_MOX400-23_672 MOX400-23
(510) (165) (672) (63) (35) (27)
22.35 4.19 26.49 1.6 0.9 0.69
4 ISRO_MOX750-23_1042 MOX750-23
(880) (165) (1042) (63) (35) (27)
94
SMD RESISTORS TYPE: RM
Device
Sr No. Lib. No X Y A G Z
Type
1.65 1.52 1.92 0.40 3.44
1 ISRO_RM0505_76 RM0505
(65) (60) (76) (16) (136)
1.55 1.55 2.05 0.5 3.6
2 ISRO_RM0603_81 RM0603
(61) (61) (81) (20) (142)
1.93 1.7 2.7 1.0 4.4
3 ISRO_RM0705_1OZ _106 RM0705(1oz)
(76) (67) (106) (39) (173)
2.0 1.73 2.73 1.0 4.46
4 ISRO_RM0705_2OZ _107 RM0705(2oz)
(79) (68) (107) (39) (175)
2.0 1.75 2.25 0.5 4.0
5 ISRO_RM0805_89 RM0805
(79) (69) (89) (20) (158)
1.65 1.64 2.54 0.90 4.18
6 ISRO_RM1005_100 RM1005
(65) (65) (100) (35) (165)
2.28 1.59 3.49 1.90 5.08
7 ISRO_RM1206_1OZ _137 RM1206(1oz)
(90) (63) (137) (75) (200)
2.35 1.66 3.49 1.83 5.15
8 ISRO_RM1206_2OZ _137 RM1206(2oz)
(93) (65) (137) (72) (202)
95
SMD RESISTORS TYPE: RM
Device
Sr No. Lib. No X Y A G Z
Type
1.65 1.64 3.81 2.17 5.45
9 ISRO_RM1505_150 RM1505
(65) (65) (150) (85) (215)
2.92 1.64 5.08 3.44 6.72
10 ISRO_RM2010_200 RM2010
(115) (65) (200) (135) (265)
2.29 1.64 5.72 4.08 7.36
11 ISRO_RM2208_225 RM2208
(90) (65) (225) (161) (291)
3.56 1.64 5.35 3.71 7.00
12 ISRO_RM2512_211 RM2512
(140) (65) (211) (146) (276)
ISRO_RM0402_43 0.88 0.68 1.08 0.4 1.76
13 RM0402
(34) (26) (43) (16) (68)
96
RESISTOR NETWORK: RNW
SIP PACKAGE
No.
Pad Hole
Sr No. Lib. No of L W A P Height
Dia Dia
Pins
27.0 3.5 17.78 2.54 8.6 1.5 0.8
1 ISRO_RNW8_700 8
(1063) (138) (700) (100) (344) (59) (31)
27.0 3.5 20.32 2.54 8.6 1.5 0.8
2 ISRO_RNW9_800 9
(1063) (138) (800) (100) (344) (59) (31)
27.0 3.5 22.86 2.54 8.6 1.4 0.7
3 ISRO_RNW10_900 10
(1063) (138) (900) (100) (344) (55) (28)
27.5 4.0 22.86 2.54 11.0 1.5 0.8
4 ISRO_RCNW10_900 10
(1100) (158) (900) (100) (440) (59) (31)
30.0 4.5 25.4 2.54 11.0 1.5 0.8
5 ISRO_RCNW11_1000 11
(1182) (177) (1000) (100) (440) (59) (31)
97
AXIAL CAPACITORS TYPE: CLR & CSR (POLARIZED CAPACITOR)
Sr Device Hole Pad Lead

Lib. No. L W A B C
No Type Dia. Dia. Dia.
CLR79/81/ 21.03 5.56 24.87 12.30 6.10 0.90 1.60 0.64
1 ISRO_CLR@_T1_978
90/91-T1 (828) (219) (978) (484) (240) (35) (63) (25)
CLR79/81/ 25.8 7.92 29.64 13.60 7.30 0.90 1.60 0.64
2 ISRO_CLR@_T2_1166
90/91-T2 (1016) (312) (1166) (535) (287) (35) (63) (25)
CLR79/81/ 28.98 10.31 32.82 14.40 8.0 0.90 1.60 0.64
3 ISRO_CLR@_T3_1291
90/91-T3 (1141) (406) (1291) (567) (315) (35) (63) (25)
CLR79/81/ 36.49 10.31 40.33 16.30 9.90 0.90 1.60 0.64
4 ISRO_CLR@_T4_1587
90/91-T4 (1437) (406) (1587) (642) (390) (35) (63) (25)
10.72 3.68 13.78 0.80 1.50 0.51
5 ISRO_CSR13A_543 CSR13-A - -
(423) (145) (543) (31) (59) (20)
CSR13-B 15.49 4.95 18.55 11.0 0.80 1.50 0.51
6 ISRO_CSR13B/CSR21C_730 -
CSR21-C (610) (195) (730) (434) (31) (59) (20)
20.88 7.62 24.72 7.37 7.37 0.90 1.60 0.64
7 ISRO_CSR13C_972 CSR13-C
(822) (300) (972) (290) (290) (35) (63) (25)
ISRO_CSR13D/CSR CSR13-D 23.42 9.17 27.26 11.0 8.0 0.90 1.60 0.64
8
21D_1073 CSR21-D (923) (362) (1073) (434) (315) (35) (63) (25)
Note: CLR@ = CLR79/81/90/91
• Lacing Hole Diameter (H) = 1.20(47) mm free Hole

• For CSR13B/CSR21C single lacing hole pair given.
98
AXIAL CAPACITORS TYPE: CRH01/06
Sr. Capacitance Hole Pad Lead

Lib. No. L W A B C
No. Range (µF) Dia. Dia. Dia.
1 ISRO_CRH01_850 0.00-0.022 17.78 5.08 21.62 6.35 6.35 0.9 1.6 0.64
(700) (200) (850) (250) (250) (35) (63) (25)
2 ISRO_CRH01_912 0.02-0.056 19.35 5.08 23.19 6.50 6.50 0.9 1.6 0.64
(762) (200) (912) (256) (256) (35) (63) (25)
3 ISRO_ 0.068-0.12 22.53 5.08 26.37 8.13 8.13 0.9 1.6 0.64
CRH01/06_1037X200 (887) (200) (1037) (320) (320) (35) (63) (25)
4 ISRO_ 0.15 19.35 6.35 23.19 6.50 6.50 0.9 1.6 0.64
CRH01/06_912X250 (762) (250) (912) (256) (256) (35) (63) (25)
5 ISRO_ 0.18-0.39 22.53 6.35 26.37 8.13 8.13 0.9 1.6 0.64
CRH01/06_1037X250 (887) (250) (1037) (320) (320) (35) (63) (25)
6 ISRO_ 0.47-0.68 22.53 7.62 26.37 8.13 8.13 0.9 1.6 0.64
CRH01/06_1037X300 (887) (300) (1037) (320) (320) (35) (63) (25)
7 ISRO_ 0.82-1.2 25.73 7.62 29.50 8.38 8.38 0.9 1.6 0.64
CRH01/06_1163X300 (1013) (300) (1163) (330) (330) (35) (63) (25)
Note: - H- Lacing Hole Diameter = 1.20(47) Free Hole
99
AXIAL CAPACITORS TYPE: CRH01/06 ( Cont.)
Capacitance
Sr. Hole Pad Lead
Lib. No. Range L W A B C
No. Dia. Dia. Dia.
(µF)
ISRO_ 25.73 10.16 30.59 8.89 8.89 1.10 1.80 0.81
8 1.5-2.2
CRH01/06_1205X400 (1013) (400) (1205) (350) (350) (43) (71) (32)
ISRO_ 32.08 10.16 36.94 10.92 10.92 1.10 1.80 0.81
9 2.7-3.3
CRH01/06_1455X400 (1263) (400) (1455) (430) (430) (43) (71) (32)
ISRO_ 40.01 10.16 44.87 13.40 13.40 1.10 1.80 0.81
10 3.9
CRH01/06_1767X400 (1575) (400) (1767) (530) (530) (43) (71) (32)
ISRO_ 40.01 12.7 44.87 13.40 13.40 1.10 1.80 0.81
11 4.7-5.6
CRH01/06_1767X500 (1575) (500) (1767) (530) (530) (43) (71) (32)
ISRO_ 40.01 15.24 46.01 12.70 12.70 1.30 2.00 1.0
12 6.8-10.0
CRH01/06_1809X600 (1575) (600) (1809) (500) (500) (51) (79) (39)
ISRO_ 52.7 15.24 58.7 15.24 15.24 1.30 2.00 1.0
13 12.0-15.0
CRH01/06_2309X600 (2075) (600) (2309) (600) (600) (51) (79) (39)
ISRO_ 52.7 17.78 58.7 17.78 17.78 1.30 2.00 1.0
14 20.0-22.0
CRH01/06_2309X700 (2075) (700) (2309) (700) (700) (51) (79) (39)
Note: -Lacing Hole Diameter (H) = 1.20 (47) free Hole
100
AXIAL CAPACITORS TYPE : CRH02/07
Capacitance
Sr. Hole Pad Lead
No. Dia. Dia. Dia.
(µF)
17.78 4.83 21.62 6.35 6.35 0.90 1.60 0.64
1 ISRO_CRH02/07_850X191 0.001-0.0068
(700) (191) (850) (250) (250) (35) (63) (25)
19.35 4.83 23.19 6.50 6.50 1.00 1.60 0.64
2 ISRO_CRH02/07_912X191 0.0082-0.033
(762) (191) (912) (256) (256) (39) (63) (25)
22.53 5.08 26.37 8.13 8.13 0.90 1.60 0.64
3 ISRO_CRH02/07_1037X200 0.039-0.068
(887) (200) (1037) (320) (320) (35) (63) (25)
25.73 5.08 29.57 8.38 8.38 0.90 1.60 0.64
4 ISRO_CRH02/07_1163X200 0.082-0.1
(1013) (200) (1163) (330) (330) (35) (63) (25)
22.53 6.35 26.37 8.13 8.13 0.90 1.60 0.64
5 ISRO_CRH02/07_1037X250 0.12-0.15
(887) (250) (1037) (320) (320) (35) (63) (25)
25.73 6.35 29.57 8.38 8.38 0.90 1.60 0.64
6 ISRO_CRH02/07_1163X250 0.18-0.22
(1013) (250) (1163) (330) (330) (35) (63) (25)
22.53 7.62 26.37 8.13 8.13 0.90 1.60 0.64
7 ISRO_CRH02/07_1037X300 0.27-0.33
(887) (300) (1037) (320) (320) (35) (63) (25)
25.73 7.62 29.57 8.38 8.38 0.90 1.60 0.64
8 ISRO_CRH02/07_1163X300 0.39-0.5
(1013) (300) (1163) (330) (330) (35) (63) (25)
25.73 10.16 30.59 8.89 8.89 1.10 1.80 0.81
9 ISRO_CRH02/07_1205X400 0.56-0.68
(1013) (400) (1205) (350) (350) (43) (71) (32)
32.08 10.16 36.94 10.92 10.92 1.10 1.80 0.81
10 ISRO_CRH02/07_1455X400 0.82-1.8
(1263) (400) (1455) (430) (430) (43) (71) (32)
101
Capacitance
Sr. Hole Pad Lead
No. Dia. Dia. Dia.
(µF)
33.66 12.7 38.52 10.41 10.41 1.10 1.80 0.81
11 ISRO_CRH02/07_1518X500 2.0-2.2
(1326) (500) (1518) (410) (410) (43) (71) (32)
40.01 12.7 44.87 13.40 13.40 1.10 1.80 0.81
12 ISRO_CRH02/07_1767X500 2.7-3.3
(1575) (500) (1767) (530) (530) (43) (71) (32)
40.01 15.24 45.40 12.70 12.70 1.30 2.0 1.0
13 ISRO_CRH02/07_1809X600 3.9
(1575) (600) (1809) (500) (500) (51) (79) (39)
40.01 17.78 45.40 12.70 12.70 1.30 2.0 1.0
14 ISRO_CRH02/07_1809X700 4.7-5.6
(1575) (700) (1809) (500) (500) (51) (79) (39)
52.7 17.78 58.7 17.78 17.78 1.30 2.0 1.0
15 ISRO_CRH02/07_2309X700 6.8-10.0
(2075) (700) (2309) (700) (700) (51) (79) (39)
102
Sr. Capacitance Hole Pad Lead

Lib. No. L W A B C
No. Range(µF) Dia Dia Dia
19.35 5.08 23.19 6.35 6.35 0.9 1.6 0.64
1 ISRO_CRH03/08_850X200 0.001-0.0056
(700) (200) (850) (250) (250) (35) (63) (25)
19.35 5.08 23.19 6.50 6.50 0.9 1.6 0.64
2 ISRO_CRH03/08_912X200 0.0068-0.0082
(762) (200) (912) (256) (256) (35) (63) (25)
22.53 5.08 26.37 8.13 8.13 0.9 1.6 0.64
3 ISRO_CRH03/08_1038X200 0.01-0.033
(888) (200) (1038) (320) (320) (35) (63) (25)
22.53 6.35 26.37 8.13 8.13 0.9 1.6 0.64
4 ISRO_CRH03/08_1038X250 0.039-0.056
(888) (250) (1038) (320) (320) (35) (63) (25)
25.73 6.35 29.57 8.38 8.38 0.9 1.6 0.64
5 ISRO_CRH03/08_1163X250 0.068
(1013) (250) (1163) (330) (330) (35) (63) (25)
22.53 7.62 26.37 8.13 8.13 0.9 1.6 0.64
6 ISRO_CRH03/08_1038X300 0.082-0.12
(888) (300) (1038) (320) (320) (35) (63) (25)
25.73 7.62 29.57 8.38 8.38 0.9 1.6 0.64
7 ISRO_CRH03/08_1163X300 0.15-0.22
(1013) (300) (1163) (330) (330) (35) (63) (25)
32.08 7.62 35.92 11.58 11.58 0.9 1.6 0.64
8 ISRO_CRH03/08_1413X300 0.27-0.33
(1263) (300) (1413) (456) (456) (35) (63) (25)
32.08 10.16 36.94 10.92 10.92 1.1 1.8 0.81
9 ISRO_CRH03/08_1453X400 0.39-0.56
(1263) (400) (1453) (430) (430) (43) (71) (32)
33.66 12.7 38.52 10.41 10.41 1.1 1.8 0.81
10 ISRO_CRH03/08_1516X500 0.68-0.82
(1326) (500) (1516) (410) (410) (43) (71) (32)
103
Capacitance
Sr. Hole Pad Lead
No. Dia Dia Dia
(µF)
ISRO_ 33.66 15.24 39.66 12.19 12.19 1.3 2.0 1.0
11 1.00-1.20
CRH03/08_1560X600 (1326) (600) (1560) (480) (480) (51) (79) (39)
ISRO_ 40.01 15.24 46.01 12.70 12.70 1.3 2.0 1.0
12 1.50
CRH03/08_1810X600 (1576) (600) (1810) (500) (500) (51) (79) (39)
ISRO_ 40.01 17.78 46.01 12.70 12.70 1.3 2.0 1.0
13 2.0-2.2
CRH03/08_1810X700 (1576) (700) (1810) (500) (500) (51) (79) (39)
ISRO_ 52.71 17.78 58.71 17.78 17.78 1.3 2.0 1.0
14 2.7-3.3
CRH03/08_2310X700 (2076) (700) (2310) (700) (700) (51) (79) (39)
ISRO_ 52.71 19.05 58.71 17.78 17.78 1.3 2.0 1.0
15 3.9-5.6
CRH03/08_2310X750 (2076) (750) (2310) (700) (700) (51) (79) (39)
ISRO_ 65.41 25.4 71.41 22.86 22.86 1.3 2.0 1.0
16 6.8-10.0
CRH03/08_2810X1000 (2576) (1000) (2810) (900) (900) (51) (79) (39)
104
AXIAL CAPACITORS TYPE : CYR
Lead
Device Hole Pad
Sr. No. Lib. No L W A Dia
Type Dia Dia
9.93 5.00 12.93 0.70 1.40 0.5

1 ISRO_CYR10_511 CYR10
(391) (197) (511) (28) (55) (20)
13.10 7.50 16.10 0.70 1.40 0.5
(516) (296) (636) (28) (55) (20)
20.20 12.50 23.80 0.80 1.50 0.6
(796) (493) (940) (31) (59) (24)
CYR30 21.03 22.00 24.63 0.80 1.50 0.6
4 ISRO_CYR30_972
(828) (867) (972) (31) (59) (24)
105
AXIAL COMPONENTS MOUNTING WITH SPECIAL STRESS RELIEF
PROVISION:
TYPE-1
TYPE-2
NOTE:
1. For Type-1 Stress Relief Loop, no extra space is required (For interhole spacing).
2. For Type-2, 2X Hump Diameter (5mm) is to be added in interhole distance mentioned for respective
component
3. Lacing holes of 1.2mm diameter may be spaced within the body length, on either side of device, keeping
distance between them twice the body diameter, wherever required as mentioned in footprint details of
the device.
106
RADiaL CAPACITORS TYPE : CKR
Vertical Mounting
Device Hole Pad Lead

Sr. No. Lib. No. L/H W A
Type Dia Dia Dia
4.83 2.29 5.08 0.80 1.50 0.6
1 ISRO_CKR05_200_V CKR05_V
(190) (90) (200) (31) (59) (24)
7.37 2.29 5.08 0.80 1.50 0.6
2 ISRO_CKR06_200_V CKR06_V
(290) (90) (200) (31) (59) (24)
Note: V-Vertical Mounting
107
RADiaL CAPACITORS TYPE : CKR
Device Hole Lead

Sr. No. Lib. No. L/H W A B Pad Dia
Type Dia Dia
4.83 2.29 5.08 9.00 0.80 1.50 0.6
1 ISRO_CKR05_200_H CKR05_H
(190) (90) (200) (355) (31) (59) (24)
7.37 2.29 5.08 11.00 0.80 1.50 0.6
2 ISRO_CKR06_200_H CKR06_H
(290) (90) (200) (394) (31) (59) (24)
Note: H-Horizontal Mounting
108
RADiaL CAPACITORS TYPE : CMR
Sr. Device Pad Hole Lead

Lib. No. L W A B
No. Type Dia Dia Dia
10.16 5.72 3.81 12.70 1.50 0.80 0.5
1 ISRO_CMR04_150_H CMR04_H
(400) (225) (150) (500) (59) (31) (20)
12.07 5.72 5.72 12.70 1.60 0.90 0.69
(475) (225) (225) (500) (63) (35) (28)
17.78 8.89 8.89 17.50 1.70 1.00 0.81
(700) (350) (350) (700) (67) (39) (32)
21.59 11.43 10.80 27.50 1.90 1.20 1.0
(850) (450) (425) (1100) (75) (48) (39)
38.10 12.70 26.67 30.48 1.90 1.20 1.0
(1500) (500) (1050) (1200) (75) (48) (39)
Note: H-Horizontal Mount
109
RADiaL CAPACITORS TYPE : CMR
Sr. Device Pad Hole Lead

Lib. No. L W A
No. Type Dia Dia Dia
1 ISRO_CMR04_150_V CMR04_V 10.16 5.72 3.81 1.50 0.80 0.60
(400) (225) (150) (59) (31) (24)
2 ISRO_CMR05_225_V CMR05_V 12.07 5.72 5.72 1.60 0.90 0.69
(475) (225) (225) (63) (35) (28)
3 ISRO_CMR06_350_V CMR06_V 17.78 8.89 8.89 1.70 1.00 0.81
(700) (350) (350) (67) (39) (32)
4 ISRO_CMR07_425_V CMR07_V 21.59 11.43 10.80 1.90 1.20 1.0
(850) (450) (425) (75) (48) (39)
5 ISRO_CMR08_1050_V CMR08_V 38.10 12.70 26.67 1.90 1.20 1.02
(1500) (500) (1050) (75) (48) (40)
Note: V- VERTICAL MOUNTING
110
SMD CAPACITORS TYPE : CDR31-35
Device Copper
Sr. No. Lib. No. X Y A G Z
Type Thickness
1.98 1.68 2.25 0.57 3.93
1 ISRO_CDR31_1OZ_89 1 OZ
(78) (67) (89) (23) (157)
CDR31
2.05 1.75 2.25 0.5 4.00
(81) (69) (89) (20) (158)
2.33 1.68 3.45 1.77 5.13
(92) (67) (136) (70) (204)
CDR32
2.4 1.75 3.45 1.7 5.20
(95) (69) (136) (67) (205)
3.23 1.68 3.45 1.77 5.13
(128) (67) (136) (70) (204)
CDR33
3.30 1.75 3.45 1.7 5.20
(130) (69) (136) (67) (205)
3.93 1.68 4.75 3.07 6.43
(155) (67) (188) (121) (255)
CDR34
4.00 1.75 4.75 3.00 6.50
(158) (69) (188) (119) (257)
7.13 1.68 4.75 3.07 6.43
(281) (67) (188) (121) (255)
CDR35
7.20 1.75 4.75 3.00 6.50
(284) (69) (188) (119) (257)
111
CHIP CAPACITORS TYPE : CDR11-14
Sr. Device Copper

Lib. No. X Y A G Z
No. Type Thickness
2.31 1.61 2.11 0.5 3.72
1 ISRO_CDR11A_1OZ _84 1 OZ
CDR11 (91) (64) (84) (20) (148)
CASE A 2.38 1.68 2.18 0.5 3.86
(94) (67) (87) (20) (154)
2.31 1.87 2.37 0.5 4.24
CDR12 (91) (74) (94) (20) (168)
CASE A 2.38 1.94 2.44 0.5 4.38
(94) (77) (97) (20) (174)
3.83 1.87 3.16 1.29 5.03
5 ISRO_CDR13B_1OZ_125 1 OZ
CDR13 (151) (74) (125) (51) (199)
CASE B 3.9 1.94 3.16 1.22 5.1
(154) (77) (126) (49) (203)
3.83 2.25 3.16 0.91 5.41
CDR14 (151) (89) (124) (35) (214)
CASE B 3.9 2.32 3.16 0.84 5.48
(154) (92) (126) (34) (218)
112
CHIP CAPACITORS TYPE : CDR01-06
Device Copper
Type Thickness
2.18 1.87 2.37 0.5 4.24
1 ISRO_CDR01_1OZ _94 1 OZ
(86) (74) (94) (20) (168)
CDR01
2.25 1.94 2.44 0.5 4.38
(89) (77) (97) (20) (174)
2.18 1.87 4.81 2.94 6.68
(86) (74) (190) (116) (264)
CDR02
2.25 1.94 4.81 2.87 6.75
(89) (77) (190) (113) (267)
2.94 1.87 4.81 2.94 6.68
(116) (74) (190) (116) (264)
CDR03
3.01 1.94 4.81 2.87 6.75
(119) (77) (190) (113) (267)
4.09 1.87 4.81 2.94 6.68
(162) (74) (190) (116) (264)
CDR04
4.16 1.94 4.81 2.87 6.75
(164) (77) (190) (113) (267)
7.39 2.00 4.81 2.81 6.81
(291) (79) (190) (111) (269)
CDR05
7.46 2.07 4.81 2.74 6.88
(294) (82) (190) (108) (272)
7.39 2.00 5.96 3.96 7.96
(291) (79) (235) (156) (314)
CDR06
7.46 2.07 5.96 3.89 8.03
(294) (82) (235) (154) (318)
113
CHIP CAPACITOR TYPE : CWR06 (POLARIZED CAPACITOR)
Case Copper
Code Thickness
2.18 2.12 2.62 0.5 4.74
1 ISRO_CWR06A_1OZ_104 1 OZ
(86) (84) (104) (20) (188)
A
2.25 2.19 2.69 0.5 4.88
2 ISRO_CWR06A_2OZ_107 2 OZ
(89) (87) (107) (20) (194)
2.18 2.12 3.8 1.68 5.92
3 ISRO_CWR06B_1OZ_151 1 OZ
(86) (84) (151) (67) (235)
B
2.18 2.12 3.8 1.68 5.92
4 ISRO_CWR06B_2OZ_151 2 OZ
(86) (84) (151) (67) (235)
2.18 2.12 5.07 2.95 7.19
5 ISRO_CWR06C_1OZ_200 1 OZ
(86) (84) (200) (116) (285)
C
2.25 2.19 5.07 2.88 7.26
6 ISRO_CWR06C_2OZ_200 2 OZ
(89) (87) (200) (113) (288)
3.45 2.12 3.8 1.68 5.92
7 ISRO_CWR06D_1OZ_150 1 OZ
(136) (84) (150) (66) (235)
D 5.99
3.52 2.19 3.8 1.61
8 ISRO_CWR06D_2OZ_150 2 OZ (238)
(139) (87) (150) (63)
114
CHIP CAPACITOR TYPE : CWR06 (POLARIZED CAPACITOR) Cont,
Case Copper
Code Thickness
3.45 2.12 5.07 2.95 7.19
9 ISRO_CWR06E_1OZ _200 1 OZ
(136) (84) (200) (116) (285)
E
3.52 2.19 5.07 2.88 7.26
10 ISRO_CWR06E_2OZ _200 2 OZ
(139) (87) (200) (113) (288)
4.34 2.12 5.58 3.46 7.7
11 ISRO_CWR06F_1OZ _220 1 OZ
(171) (84) (220) (136) (305)
F
4.41 2.19 5.58 3.39 7.77
12 ISRO_CWR06F_2OZ _220 2 OZ
(174) (87) (220) (133) (308)
3.7 2.63 6.21 3.58 8.84
13 ISRO_CWR06G _1OZ _245 1 OZ
(146) (104) (245) (141) (349)
G
3.77 2.7 6.21 3.51 8.91
14 ISRO_CWR06G_2OZ _245 2 OZ
(149) (107) (245) (138) (353)
4.72 2.63 6.72 4.09 9.35
15 ISRO_CWR06H_1OZ _265 1 OZ
(186) (104) (265) (161) (370)
H
4.79 2.7 6.72 4.02 9.42
16 ISRO_CWR06H_2OZ _265 2 OZ
(189) (107) (265) (158) (373)
115
CHIP CAPACITORS TYPE : CWR09 (POLARIZED CAPACITOR)
Case
Sr. No. Lib. No. X Y A G Z Height
Code
2.00 2.37 2.77 0.4 5.14 1.65
1 ISRO_CWR09A_110 A
(79) (94) (110) (16) (204) (65)
2.00 2.37 2.77 0.4 5.14 1.65
2 ISRO_CWR09B_110 B
(79) (94) (110) (16) (204) (65)
2.00 2.37 3.85 1.48 6.22 1.65
3 ISRO_CWR09C_152 C
(79) (94) (152) (58) (246) (65)
3.14 2.37 2.77 0.40 5.14 1.65
4 ISRO_CWR09D_110 D
(124) (94) (110) (16) (204) (65)
3.14 2.37 3.85 1.48 6.22 1.65
5 ISRO_CWR09E_152 E
(124) (94) (152) (58) (246) (65)
4.03 2.63 4.62 1.99 7.25 2.16
6 ISRO_CWR09F_182 F
(159) (104) (182) (78) (286) (85)
3.40 3.64 5.75 2.11 9.39 3.17
7 ISRO_CWR09G_227 G
(134) (144) (227) (83) (371) (125)
4.41 3.64 6.26 2.62 9.9 3.17
8 ISRO_CWR09H_247 H
(174) (144) (247) (103) (391) (125)
116
Case
Code
1.75 2.05 2.45 0.40 4.5 1.80
1 ISRO_CWR11A_97 A
(69) (81) (97) (16) (178) (71)
2.75 2.05 2.45 0.40 4.5 2.10
2 ISRO_CWR11B_97 B
(109) (81) (97) (16) (178) (83)
2.90 2.70 4.00 1.30 6.7 2.80
3 ISRO_CWR11C_158 C
(115) (107) (158) (51) (265) (111)
3.10 2.70 5.30 2.60 8.0 3.10
4 ISRO_CWR11D_209 D
(122) (107) (209) (102) (317) (122)
117
Case
Code
1.68 1.73 2.13 0.40 3.86 1.05
1 ISRO_CWR15L_84 L
(67) (68) (84) (16) (152) (42)
2.78 2.33 2.73 0.40 5.06 2.25
2 ISRO_CWR15R_108 R
(110) (92) (108) (16) (200) (89)
2.80 2.10 2.73 0.60 4.80 1.80
3 ISRO_CWR15A_108 A
(111) (83) (108) (23) (190) (71)
118
CHIP CAPACITORS TYPE : CWR19/29 (POLARIZED CAPACITOR)
Case
Code
2.00 2.37 2.77 0.4 5.14 1.65
1 ISRO_CWR19/29A_110 A
(79) (94) (110) (16) (204) (65)
2.00 2.37 2.77 0.4 5.14 1.65
2 ISRO_CWR19/29B_110 B
(79) (94) (110) (16) (204) (65)
2.00 2.37 3.85 1.48 6.22 1.65
3 ISRO_CWR19/29C_152 C
(79) (94) (152) (58) (247) (65)
3.14 2.37 2.77 0.4 5.14 1.65
4 ISRO_CWR19/29D_110 D
(124) (94) (110) (16) (204) (65)
3.14 2.37 3.85 1.48 6.22 1.65
5 ISRO_CWR19/29E_152 E
(124) (94) (152) (58) (247) (65)
4.03 2.63 4.62 1.99 7.25 2.16
6 ISRO_CWR19/29F_182 F
(159) (104) (182) (78) (287) (86)
3.40 3.64 5.75 2.11 9.39 3.17
7 ISRO_CWR19/29G_227 G
(134) (144) (227) (83) (372) (125)
4.41 3.64 6.26 2.62 9.9 3.17
8 ISRO_CWR19/29H_247 H
(174) (144) (247) (103) (392) (125)
3.78 3.26 5.73 2.47 8.99 3.12
9 ISRO_CWR19/29X_226 X
(149) (129) (226) (97) (356) (123)
119
CHIP CAPACITORS TYPE : CKS 51-54
Device
Type
3.00 3.00 3.40 0.40 6.40 1.77
1 ISRO_CKS51_134 CKS51
(119) (119) (134) (15) (254) (70)
4.42 3.19 3.59 0.40 6.78 2.03
(174) (126) (142) (16) (268) (80)
3.91 3.19 4.04 0.85 7.23 2.03
(154) (126) (160) (34) (286) (80)
8.29 3.29 5.16 1.87 8.45 2.16
(327) (130) (204) (74) (334) (85)
120
CHIP CAPACITOR TYPE : ATC CERAMIC MULTILAYER
Device
Type
ATC0402 1.21 1.79 0.58 3.0
1 ISRO_ATC0402_1OZ_71 1.29 (51)
1OZ (48) (71) (23) (119)
ATC0402 1.28 1.79 0.51 3.07
2 ISRO_ATC0402_2OZ_71 1.36 (54)
2OZ (51) (71) (20) (123)
ATC0403 1.31 2.22 0.91 3.53
3 ISRO_ATC0403_1OZ_88 1.29 (51)
1OZ (52) (88) (36) (140)
ATC0403 1.38 2.22 0.84 3.6
4 ISRO_ATC0403_2OZ_88 1.36 (54)
2OZ (55) (88) (33) (144)
121
CHIP CAPACITORS TYPE : 1825 & 2220 (SMPS/MLC)
Sr. No. Lib. No. Device Type X Y A G Z Height

8.50 4.00 5.50 1.50 9.50 3.30
1 ISRO_TYPE 1825_217 TYPE 1825
(335) (158) (217) (59) (376) (130)
6.50 3.50 5.90 2.40 12.40 1.80
2 ISRO_TYPE 2220_233 TYPE 2220
(256) (138) (233) (95) (491) (71)
CAPACITORS TYPE: CTC21E
Sr. No. Lib. No. Case Code X Y A A1 G1 G2 Height

ISRO_ 3.50 3.00 10.00 4.50 1.00 7.00 5.00
1 C
CTC21E_C_395 (138) (119) (395) (177) (39) (276) (197)
ISRO_ 4.50 3.00 10.00 7.20 2.70 7.00 6.00
2 D
CTC21E_D_395 (178) (119) (395) (284) (106) (276) (237)
122
CHIP CAPACITORS TYPE: CNC 81-PLE
Y
8
1 X
P
4
Sr. No. Lib. No. Device Type X Y A P

1.5 4.7 8.85 2.54
1 ISRO_CNC 81-PLE_276 CNC 81-PLE
(59) (185) (348) (100)
CAPACITORS TYPE: CH41-44
Case Type Hole Pad

Sr. No. Lib. No. L W A B Height
(Variant) Dia. Dia.
8.70 9.20 8.20 2.54 5.80 0.9 1.6
1 ISRO_CH41_323 CH41(07)
(343) (363) (323) (100) (229) (35) (63)
8.70 9.20 8.20 2.54 9.40 0.9 1.6
2 ISRO_CH42_323 CH42(09)
(343) (363) (323) (100) (370) (35) (63)
8.70 9.20 8.20 2.54 13.10 0.9 1.6
3 ISRO_CH43_323 CH43(11)
(343) (363) (323) (100) (516) (35) (63)
8.70 9.20 8.20 2.54 16.80 0.9 1.6
4 ISRO_CH44_323 CH44(13)
(343) (363) (323) (100) (662) (35) (63)
Note: Total No. of leads per side are 3 for all Device Type
123
CAPACITORS TYPE: CH**
Device Leads/ Hole Pad

Sr. No. Lib. No. L W A B
Type Side Dia. Dia.
10.70 10.70 10.2 2.54 0.9 1.6
1 ISRO_CH51-54_400 CH51-54 4
(421) (421) (400) (100) (35) (63)
13.6 14.9 14.0 2.54 0.9 1.6
2 ISRO_CH61-64_551 CH61-64 5
(536) (587) (551) (100) (35) (63)
21.6 16.8 15.2 2.54 0.9 1.6
3 ISRO_CH71-74_600 CH71-74 7
(851) (662) (600) (100) (35) (63)
40.6 24.0 20.32 2.54 0.9 1.6
4 ISRO_CH91-94_785 CH91-94 14
(1599) (945) (785) (100) (35) (63)
124
CAPACITORS TYPE: SMPS STACKED MLC
Case Leads/ Hole Pad

Sr. No. Lib.. No. L W A B Height
Code Side Dia. Dia.
55.33 14.70 11.10 2.54 18.20 0.8 1.5
1 ISRO_MLC1_437 1 20
(2179) (579) (437) (100) (717) (31) (59)
41.63 24.10 20.00 2.54 18.20 0.8 1.5
2 ISRO_MLC2_787 2 15
(1639) (949) (787) (100) (717) (31) (59)
29.93 14.70 11.10 2.54 18.20 0.8 1.5
3 ISRO_MLC3_437 3 10
(1179) (579) (437) (100) (717) (31) (59)
12.93 12.30 9.90 2.54 18.20 0.8 1.5
4 ISRO_MLC4_390 4 4
(510) (485) (390) (100) (717) (31) (59)
9.65 9.02 6.05 2.54 18.20 0.8 1.5
5 ISRO_MLC5_239 5 3
(380) (356) (239) (100) (717) (31) (59)
ISRO_ 55.33 36.30 31.50 2.54 18.20 0.8 1.5
6 6 20
MLC6_1241 (2179) (1430) (1241) (100) (717) (31) (59)
125
CAPACITORS TYPE: CNC54NE
Case Hole Pad

Sr. No. Lib. No. L W A B Height
Code Dia. Dia.
10.70 10.70 10.16 2.54 4.0 1.0 1.7
1 ISRO_CNC54NEA_400 A
(421) (421) (400) (100) (158) (39) (67)
10.70 10.70 10.16 2.54 8.0 1.0 1.7
2 ISRO_CNC54NEB_400 B
(421) (421) (400) (100) (315) (39) (67)
10.70 10.70 10.16 2.54 12.0 1.0 1.7
3 ISRO_CNC54NEC_400 C
(421) (421) (400) (100) (473) (39) (67)
10.70 10.70 10.16 2.54 16.0 1.0 1.7
4 ISRO_CNC54NED_400 D
(421) (421) (400) (100) (630) (39) (67)
126
AXIAL DIODES:
Hole Pad Lead

Sr. No. Lib. No. L W A Part No
Dia Dia Dia
7.62 3.18 10.92 0.80 1.50 0.55
1 ISRO_DO7_432
(300) (125) (432) (31) (59) (22)
14.22 7.62 19.62 1.10 1.80 0.9
2 ISRO_DO13_770
(560) (300) (770) (44) (71) (35)
ISRO_DO13/ 14.22 5.97 19.62 1.10 1.80 0.9
3 1N6036 to 1N6072A
202 AA _770 (560) (235) (770) (44) (71) (35)
7.62 3.81 10.92 0.80 1.80 0.55
4 ISRO_DO14_432
(300) (150) (432) (31) (71) (22)
7.62 3.81 12.30 1.00 1.50 0.78
5 ISRO_DO15_486
(300) (150) (486) (39) (59) (31)
6 5.08 2.54 8.08 0.80 1.50 0.5
ISRO_DO35_320
(200) (100) (320) (31) (59) (20)
6.35 2.54 10.61 0.9 1.60 0.71
7 ISRO_PKG- A_418
(250) (100) (418) (36) (60) (28)
7.62 5.08 13.74 1.2 2.0 1.02
8 ISRO_PKG-E_540
(300) (200) (540) (47) (79) (40)
4.70 3.43 9.20 1.00 1.70 0.75
9 ISRO_PKG-E_365 1N6102 to 1N6137A (500W)
(185) (135) (365) (39) (67) (30)
4.95 4.70 11.07 1.20 1.90 1.02
10 ISRO_PKG-G_435 1N6138 to 1N6173A (1500W)
(195) (185) (435) (47) (75) (40)
7.62 3.81 12.48 1.00 1.90 0.81
11 ISRO_AITC_492
(300) (150) (492) (39) (75) (32)
4.57 1.91 7.93 0.80 1.50 0.56
12 ISRO_DO_312 1N6638 / 1N6642/ 1N6643
(180) (75) (312) (31) (59) (22)
4.32 1.93 6.78 0.80 1.50 0.41 1N5711, 1N5712,
13 ISRO_DO_266
(170) (76) (266) (31) (59) (16) 5082-2300,5082-2800
127
SMD DIODE :
Sr. No. Lib. No. X Y A G Z Part No.
3.38 2.22 4.67 2.45 6.89 1N6638US TO 1N6643US

1 ISRO_PKG-A _ 184
(133) (88) (184) (96) (272) (Switching diode)
2.60 2.10 4.60 2.54 6.70
2 ISRO_PKG-B _183 1N6642US
(102) (83) (183) (100) (266)
1N 6309US to1N 6355US
2.65 1.75 4.85 3.10 6.60 (Voltage regulator)
3 ISRO_DO_ 194
(106) (70) (194) (124) (264) 1N 6638US to 1N 6643US
(Switching diode)
4.80 2.79 6.05 3.26 8.84
4 ISRO_PKG-E _ 238
(189) (110) (238) (128) (348)
6.23 3.36 7.26 3.90 10.62
5 ISRO_PKG-G _ 286
(245) (132) (286) (154) (418)
3.34 2.53 4.9 2.37 7.43 1N6309US to 1N6336US
6 ISRO_ PKG-B_196
(134) (101) (196) (95) (297) (Microsemi)
2.00 2.50 5.50 3.00 8.00
7 ISRO_SRD _216 SRD (MA 4408-186)
(79) (98) (216) (118) (314)
128
SMD DIODE :
Sr. No. Lib. No. X Y A G Z Part No.

2.85 2.10 4.60 2.50 6.70 1N 6638U,1N 6642U,
8 ISRO_D035_181
(112) (83) (181) (98) (264) 1N 6643U
3.50 2.50 4.50 2.00 7.00 1N5802US, 1N5804US,
9 ISRO-D5A_177
(138) (98) (177) (79) (275) 1N5806US
1N 5811US,1N 5809US,
4.57 2.54 5.59 3.05 8.13
10 ISRO_D5B _ 220 1N 5807US,1N 5820US,
(180) (100) (220) (120) (320)
1N 5821US,1N 5822US
2.50 3.40 5.60 2.20 9.00
11 ISRO_D5D _221 1N6642US
(98) (134) (221) (87) (355)
7.24 2.56 5.48 2.92 8.04
12 ISRO_MELF-D5B_216 1N5820US to 1N5882US
(285) (101) (216) (115) (317)
2.90 2.75 4.45 1.70 7.20
13 ISRO_MELF-CDS_175 CDS-748(MELF)
(114) (108) (175) (67) (283)
1N759AUR-1, 1N746AUR-1,
1N4370AUR-1,
2.00 2.50 3.75 1.25 6.25 1N4372AUR-1,
14 ISRO_DO213AA_147
(79) (98) (147) (49) (245) 1N4569AUR-1,
1N4565AUR-1,
1N4584AUR-1
129
SMD INDUCTOR:
Sr. No. Lib. No. Device Type X Y A G Z

15.2 5.5 12.5 7.0 18.0
1 ISRO_SESI14/15SR_500 SESI-14/15 SR
(608) (220) (500) (280) (720)
3.267 1.812 2.65 0.84 4.46
2 ISRO_PA_2OZ _105 PA SERIES 2OZ
(129) (72) (105) (34) (178)
3.45 2.1 2.7 0.6 4.8
3 ISRO_CI_107 CI04, CI05, & CI13
(138) (83) (107) (24) (189)
130
TRANSISTOR TO-** PACKAGES:
Device No. of Hole Pad

Sr No. Lib. No. A B H L
Type Pins Dia. Dia.
5.08 2.54 10.16 10.54 0.8 1.5

1 ISRO_TO5-3_ST TO-5 3
(200) (100) (400) (415) (31) (59)
5.08 2.54 7.62 7.62 0.8 1.5
2. ISRO_TO18-3_SP TO-18 3
(200) (100) (300) (300) (31) (59)
5.08 2.54 10.16 10.54 0.8 1.5
3 ISRO_TO39-3_ST TO-39 3
(200) (100) (400) (415) (31) (59)
5.08 2.54 7.62 7.62 0.8 1.5
4 ISRO_TO46-3_SP TO-46 3
(200) (100) (300) (300) (31) (59)
5.08 2.54 7.62 7.62 0.8 1.5
5 ISRO_TO72-4_SP TO-72 4
(200) (100) (300) (300) (31) (59)
Note:
 For all above packages Hole Dia. = 0.8 (31) & Pad Dia. =1.5 (59) SP- Spreaded leads, ST- Straight leads
 No Tracks & Vias to be placed below spreaded lead device
 Mapping of functional Pins to be decided based on manufacturer’s Data Sheet
131
POWER TRANSISTOR TO-** PACKAGES:
Hole Hole
Sr. Device
Lib. No. A X Y Z L W H Dia. Dia.
No. Type
pin 1,2 pin 3,4
29.5 12.50 7.00 11.50 35.10 28.00 12.50 2.50 3.2
1 ISRO_TO3 TO-03
(1176) (500) (675) (450) (1375) (1100) (500) (98) (126)
24.5 9.50 5.00 5.00 28.5 17.50 9.00 1.00 3.2
2. ISRO_TO66 TO-66
(975) (375) (600) (200) (1125) (700) (350) (39) (126)
TO- 30.15 13.25 16.89 10.92 39.37 25.53 7.74 3.2 3.2
3 ISRO_TO204AE
204AE (1187) (522) (665) (430) (1550) (1005) (305) (126) (126)
Note:
1. Holes marked as 1,2,3 & 4 are free holes.
2. Three terminal pads for E,B,C should be PTH with 2.5mm pad & 1.6mm Hole Diameter, outside transistor
body dimension or of SMD type 3mm size square shape on solder side, minimum 5mm away from free
holes from where leads project. Connection to be done by flexible wire.
132
TRANSISTOR TO-5 PACKAGES: OPTOCOUPLERS AND ICS
STANDARD LAYOUT PATTERN FOR TO-CAN TRANSISTORS IN 2:1 SCALE FOR

PLATED THROUGH HOLE TERMINATIONS IN INCH GRAPH SHEETS
Device No. OF Hole Pad

Sr No. Lib. No. H L
Type Pins Dia. Dia.
6.20 10.54 0.8 1.5
1. ISRO_TO78-6 TO-78 6
(245) (415) (31) (59)
8.1 10.54 0.8 1.5
2. ISRO_TO99-8 TO-99 8
(324) (415) (31) (59)
8.7 10.54 0.8 1.5
3. ISRO_TO100-10 TO-100 10
(348) (415) (31) (59)
133
TRANSISTOR TO-8 PACKAGE
Device No. of Hole Pad

Sr No. Lib. No. H L
Type Pins Dia. Dia.
7.30 12.82 0.8 1.5
1. ISRO_TO8-12 TO-8 12
(288) (505) (31) (59)
Note: θ= 45 degree
134
SMD TRANSISTOR PACKAGES:
Device
Sr No Lib. No A/B C D E F H Part No
Type
2N3700,
UB & 1.11 0.33 1.21 1.76 0.48 0.70
1. ISRO_SOT_75 2N2222A,
UBC (44) (13) (48) (69) (19) (28)
2N2907A
Note:
• Height of component max. for UB is 1.42mm & for UBC is 1.80mm.
• Pad 4 is Shielding connected to the lid
• Pad 4 is optional as per designer requirement
135
SMD TRANSISTOR PACKAGES:
Sr No. Lib. No L xW X xY C P G Part No.

10.16 x 10.92 4.31 x 3.81 5.33 8.03 1.52
1. ISRO_SOT_210 15CLQ100
(400 x 430) (170 x 150) (210) (316) (60)
11.43 x 12.45 4.31 x 3.81 6.10 8.92 2.28
2. ISRO_SOT_240 2N7269U
(450 x 490) (170 x 150) (240) (351) (90)
136
MOSFET TO-254AA PACKAGE:
Device
Sr No. Lib. No L W A B P Part No.
Type
IRHM7360SE/
ISRO_ 20.32 24.13 17.4 4.00 3.81 IRHM597260/
1. TO254AA
TO254AA_150 (800) (950) (685) (158) (150) IRHM593260/
IRHM7260SE
Note:
• For Pin 1, 2 & 3 Pad Dia. =3.00mm, PTH Hole Dia. =1.3mm
• PTH Pin 4 Hole Dia. =3.2mm Free Hole.
• Pin Identification: 1: Drain, 2: Source and 3: Gate
137
REGULATOR TO-258 PACKAGE
Device
Sr. No. Lib. No L W A B P Part No.
Type
omr9608sc/
SF, omr9804sc/
SF, omr9808sc/
20.32 24.13 17.95 4.00 2.54
1. ISRO_TO258_100 TO258 SF, omr9805sc,
(800) (950) (707) (158) (100)
MSK5921RH,
IRUH3301A2BK,
OM7764ASC
Note:
• For Pin 1 to 5 Pad Dia. =2.0 mm, Hole Dia. =1.1mm PTH
138
DUAL IN-LINE PACKAGE ICS
No. of Hole
Sr. No. Lib. No. L A P Pad Dia
Pins Dia
12.70 7.62 2.54 0.8 1.50
1 ISRO_DIP8_300 8
(500) (300) (100) (31) (59)
20.32 7.62 2.54 0.8 1.50
2 ISRO_DIP14_300 14
(800) (300) (100) (31) (59)
22.86 7.62 2.54 0.8 1.50
3 ISRO_DIP16_300 16
(900) (300) (100) (31) (59)
25.40 7.62 2.54 0.8 1.50
4 ISRO_DIP18_300 18
(1000) (300) (100) (31) (59)
27.94 7.62 2.54 0.8 1.50
5 ISRO_DIP20_300 20
(1100) (300) (100) (31) (59)
28.19 10.16 2.54 0.8 1.50
6 ISRO_DIP22_400 22
(1110) (400) (100) (31) (59)
33.02 7.60 2.54 0.8 1.50
7 ISRO_DIP24_300 24
(1300) (300) (100) (31) (59)
30.86 10.16 2.54 0.8 1.50
8 ISRO_DIP24_400 24
(1215) (400) (100) (31) (59)
32.76 15.24 2.54 0.8 1.50
9 ISRO_DIP24_600 24
(1290) (600) (100) (31) (59)
37.72 7.62 2.54 0.8 1.50
10 ISRO_DIP28_300 28
(1485) (300) (100) (31) (59)
38.10 15.24 2.54 0.8 1.50
11 ISRO_DIP28_600 28
(1500) (600) (100) (31) (59)
41.15 10.16 2.54 0.8 1.50
12 ISRO_DIP32_400 32
(1620) (400) (100) (31) (59)
53.34 15.24 2.54 0.8 1.50
13 ISRO_DIP40_600 40
(2100) (600) (100) (31) (59)
139
HMC
No. of Hole Pad

Sr. No. Lib. No. X Y A P Part No
Pins Dia. Dia.
22.10 12.70 7.62 2.54 0.8 1.50
1 ISRO_HMC14_300 14 SAW FILTER
( 870) (500) (300) (100) (31) (59)
141IB,142WB,
222DM,583PR,
303RD, 304RD,
305RD, 734RA,
33.26 19.56 15.24 2.54 0.8 1.50 306RD, 716LF,
2 ISRO_HMC24_600 24
(1300) (770) (600) (100) (31) (59) 752LB, 735RA,
307BS, 741LR,
711BF, 743LR,
712AG, 724IC,
732PC, 752LB
111RD, 113TD,
212AM, 718AG,
213AM, 223BM,
ISRO_HMC24_1100 31.75 31.75 27.94 2.54 0.8 1.50
3 24 302RD, 351FD,
(1250) (1250) (1100) (100) (31) (59)
717BF, 321SR,
719TT, 502HD,
722SC, 751LF
37.34 19.56 15.24 2.54 0.8 1.50
4 ISRO_HMC28_600 28 723 PA2, 725 1A
(1470) (770) (600) (100) (31) (59)
344CI, 901CL,
46.48 33.78 27.94 2.54 0.8 1.50 921AC, 941TC,
5 ISRO_HMC34_1100 34
(1830) (1330) (1100) (100) (31) (59) 742LR, 104MT,
151PM
50.54 25.14 20.32 2.54 0.8 1.50 715IA2, 714AA,
6 ISRO_HMC38_800 38
(1990) (990) (800) (100) (31) (59) 766LP
52.76 31.76 27.94 2.54 0.8 1.50 SAW Device
7 ISRO_HMC40_1100 40
(2077) (1250) (1100) (100) (31) (59) (WIE 8500-1)
140
HMC
No. of Hole Pad

Sr. No. Lib. No. X Y A1 A P Part No
Pins Dia Dia
33.26 19.55 27.94 15.24 2.54 0.8 1.50 563PS,

8 ISRO_HMC34_600 34
(1270) (770) (1100) (600) (100) (31) (59) 501MM
141
HMC
No.
Hole Pad
Sr. No. Device Type of X Y A1 A P Part No
Dia Dia
Pins
585CS, 311DR,
151LC, 581PS,
331DM,
31.75 31.75 27.94 27.94 2.54 0.8 1.50
9 ISRO_HMC44_1100 44 312TD,
(1250) (1250) (1100) (1100) (100) (31) (59)
211AM,
931AD,
582CS, 152LC
142
HMC
No.
Hole Pad
Sr. No. Device Type of X Y A1 A P Part No
Dia Dia
Pins
ISRO_ 46.48 33.78 40.64 27.94 2.54 0.8 1.50 131AD, 584FP,
10 54
HMC54_1100 (1830) (1330) (1600) (1100) (100) (31) (59) 562AC, 721DB
143
QUAD FLAT PACK ICs

0.65 mm Pitch, QFN Device,
Part No: EL 7457 (INTERSIL)
ISRO_QFN16_4.00
Lib. No P LL x LW A B G Part No Height
EL7457-CLOCK
ISRO_QFN16_4.00 0.65 1.50 x 0.40 1.50 2.50 4.00 0.9
DRIVER (INTERSIL)
• Dimensions are in mm
General Instruction: Dimension A is PTH allowable area, if the device has metallic cap at the bottom no PTH is
allowed under device.
144
30 mil Pitch, HMC Device,
Part No: HMC 244G16(HITTITE MICROWAVE CORP.)
ISRO_CQFP16_380
Lib. No P LL x LW A B G Part No Height
ISRO_ CQFP16_380 30 120 x 20 160 260 380 HMC 244G16 65
Note:
• Metal Base bottom, Area A is to be connected to PCB RF ground.

• Dimensions are in mil
145
50 mil Pitch, CLCC Package,
Part No: ICL 3232E(INTERSIL),
ISRO_CLCC20_336
Lib. No P B G LL x LW Part No. Height
ICL3232E (5962-
ISRO_CLCC20_ 336 As per Drawing 100
0620707Q2A)
Note:
• Vias and traces are not allowed below the device (Flush mounted device).
• Dimension are in mil.
146
50 mil Pitch, CLCC Package,
Part No: UC1806L(TEXAS INSTRUMENTS),
ISRO_LCC20_320
ISRO_LCC20_ 320 As per Drawing UCL1806L 80
Note:
147
0.50mm Pitch, QFN Device,
Part No:TPS75003 (TEXAS INSTRUMENTS),
ISRO_QFN20_4.45
ISRO_QFN20_ 4.45 As per Drawing TPS75003
Note:
• Dimension are in mm.
148
50 mil Pitch, CQFJ Device,
Part No:PE9704,PE83336(PEREGRINE SEMICONDUCTOR)
ISRO_CQFJ44_670
Lib. No P LL x LW A B G Part No. Height
PE9704,
ISRO_CQFJ44_ 670 50 140 x 35 430 530 670 113
PE83336
Note:

• Pin no 1 in top middle & in anticlock wise direction.
149
0.50 mm Pitch, CQFJ Device,
Part No: DS90C241IVS & DS90C124IVS
ISRO_CQFJ48_10.60
Lib. No. P LL x LW A B G Part No. Height

DS90C241IVS, 1.2
ISRO_CQFJ48_10.60 0.50 3.00 x 0.33 5.10 7.60 10.60
DS90124IVS-SERDES
• Dimensions are in mm.
150
50 mil Pitch, CQFP Device,
Part No: ACT5028
ISRO_CQFP52_1116
ISRO_CQFP52_1116 50 120 x 30 896 996 1116 ACT5028 100
Note:
• Dimensions are in mils.

151
0.50 mm Pitch, QFP Device,
Part No: AFE AD9995
ISRO_QFP56_8.80
ISRO_QFP56_8.80 0.50 2.00 x 0.33 4.3 6.80 8.80 AFE AD9995 1.00
Note:
• Dimension are in mm .
• Package Style : Lead Frame Chip Scale Package (LFCSP)
152
0.50 mm Pitch, QFP Device,
Part No: DS90UR124(NATIONAL SEMICONDUCTOR)
ISRO_QFP64_13.60

DS90UR124-
ISRO_QFP64_13.60 0.50 3.00 x 0.33 8.10 10.60 13.60 VEC64A- 1.2
DESERIALIZER
• Dimension are in mm.
153
50 mil Pitch, QFP Device,
Part No: WS 512K32(G1U)1(WHITE ELE. DESIGNS CORP.)
ISRO_QFP68 _970
ISRO_QFP68_970 50 110 x 30 760 860 970 WS512K32(G1U)1 140
Note:
• Device has metallic cap at the bottom PTH/Traces are not allowed under the device.
• Dimensions are in mil.
• Pin no 1 in top middle & in anticlockwise direction.
154
Part No: 512Kx32 SRAM UT9Q512K32E
ISRO_QFP68 _1140
ISRO_QFP68_1140 50 120 x 30 920 1020 1140 UT9Q512K32E- SRAM 206
Note:
• The device has metallic cap at bottom PTH/Traces are not allowed under Device
155
Part No: ADC-TS 8388(ATMEL)
ISRO_QFP68 _1056

TS8388B
ISRO_QFP68_1056 50 120 x 40 836 936 1056 137
(ATMEL)
Note:

156
Part No: MA 31751
ISRO_CQFP68_1110
ISRO_CQFP68_1110 50 120 x 30 890 990 1110 MA31751 109
Note:

157
0.635 mm Pitch, PQFJ Device,
Part No: A54SX32A/RT54SX32AFPGA(ACTEL)
ISRO_PQFJ84_22.31

A54SX32A,
ISRO_PQFJ84_22.31 0.635 3.00 x 0.385 16.81 19.31 22.31 RT54SX32AFPGA 2.4
(ACTEL)
158
Part No: MA 31750/RTX2010RH
ISRO_CQFP84_1310

MA31750,
ISRO_CQFP84_1310 50 120 x 30 1090 1190 1310 107
RTX2010RH

159
50 mil Pitch, CQFJ Device,
Part No: 3DDP 96-165 HSS & 48KX16DPRAM
ISRO_CQFJ84_1300

3DDP96-165 HSS,
ISRO_CQFJ84_1300 50 160 x 35 1040 1140 1300 48KX16 DPRAM 486
(3D plus )
160
50 mil Pitch, MQFP Device,
Part No: DPRAM-67025 (8KX16)
ISRO_ MQFP84 _1310
DPRAM-67025
ISRO_MQFP84_1310 50 120 x 30 1090 1190 1310 105
(8KX16)
161
1.27 mm Pitch, CQFP Device
Part No: HMC-64Channel Analog Multiplexer (CEL)
ISRO_CQFP92 _57.41
Lib. No P LL x LW B G Part No.
64-CHANNEL ANALOG
ISRO_CQFP92_ 57.41 1.27 3.00 x 0.86 As per Drawing
MULTIPLEXER
162
25 mil Pitch, CQFP Device
Part No: SUMMIT LXE/DXE (592F 9466311 VYC)
ISRO_CQFP100_1510

(SUMMIT LXE/DXE)
ISRO_CQFP100_1510 25 120 x 18 As per Drawing 130
5962F 9466311 VYC
163
0.50 mm Pitch, CQFP Package
Part No: C8051F120 (SILICON LABORATORIES)
ISRO_CQFP100_16.80

C8051F120
ISRO_CQFP100_16.80 0.50 3.00 x 0.33 11.30 13.80 16.80 1.20
(SILICON LAB.)
164
Part No:ADC08D1520(NATIONAL SEMI)
ISRO_CQFP128_23.83

ADC08D1520
ISRO_CQFP128_23.83 0.5 3.00 x 0.30 18.33 20.83 23.83 (NATIONAL 3.4
SEMICONDUCTOR)
165
Part No: RT1425A FPGA (ACTEL)
ISRO_CQFP132_1110A

RT1425A-
ISRO_CQFP132_1110A 25 120 x 18 890 990 1110 Without Heat 118
sink, Cavity up
166
Part No: CC1-1/2, CC2/3/4, MA28140
ISRO_CQFP132_1110B

CC1-1/2,
104
ISRO_CQFP132_1110B 25 120 x 18 890 990 1110 CC2/3/4,
MA28140
Note:

• Pin no 1 in top middle & in clock wise direction.
167
Part No: DSG-01/02/06
ISRO_CQFP132_1110C

ISRO_CQFP132_1110C 25 120 x 18 890 990 1110 DSG-01/02/06 104
Note:

168
Part No: ACTEL1280(RH & RT) FPGA
ISRO_CQFP172_1340
ACTEL1280 -RH
ISRO_CQFP172_1340 25 120 x 18 1120 1220 1340 127
&RT (FPGA)
169
Part No: RAD-PAK-SEI
ISRO_CQFP172_1310
ISRO_CQFP172_1310 25 120 x 18 1090 1190 1310 RAD-PAK-SEI 168
170
Part No: HUFF ASIC
ISRO_CQFP196_1510

HUFF ASIC (HUFF MAN
ISRO_CQFP196_1510 25 120 x 18 1290 1390 1510 CODER) without Heat 104
Sink
171
Part No: 81102 G0FS
ISRO_CQFP196_36.62
ISRO_CQFP196_36.62 0.635 3.00 x 0.385 31.08 33.62 36.62 81102 GOFS 3.05
172
0.50 mm Pitch, CQFP Device-CQ208
Part No: 54SX-S, RTAX250S (ACTEL)
ISRO_CQFP208_33.21
RT54SX-S,
ISRO_CQFP208_33.21 0.5 3.00 x 0.33 27.67 30.21 33.21 2.67
RTAX250S
173
25 mil Pitch, CQFP Device- CB228
Part No: XQV600 (XILINX)
ISRO_CQFP228_1710

XQV600
ISRO_CQFP228_1710 25 120 x 18 1490 1590 1710 130
( XILINX)
174
Land Pattern Geometry for 240 Pins, 0.50mm Pitch,
PQFP Device: PQ/PQG/HQ/HQG240
Part No: FPGA (XILINX)
ISRO_PQFP240_34.39
FPGA
ISRO_PQFP240_34.39 0.50 2.50 x 0.33 29.39 31.89 34.39 4.10
(XILINX)

• Approved for Air Borne projects only.
175
20 mil Pitch,CQFP Device
Part No: 5962-99b01,KM10A (ASIC-1), DACP (ASIC-2),
AIHS (ASIC-3),PSKDMBS (ASIC-10)
ISRO_CQFP256_1620
5962-99B01, KM10A(ASIC-1),
DACP (ASIC-2), AIHS
ISRO_CQFP256_1620 20 120 x 13 1400 1500 1620 130
(ASIC-3), PSKDMBS(ASIC-10)-
(AEROFLEX)
176
20 mil Pitch, MQFP Device
Part No: DCT ASIC,TSC21020 DSP(TEMIC)
ISRO_MQFP256_1620

DCT ASIC
ISRO_MQFP256_1620 20 120 x 13 1400 1500 1620 125
(TEMIC)
Note:

• Pin no in clock wise direction.
177
0.50 mm Pitch, CQFP Device-CQ256
Part No: RT54SX-S, RTAX2000S (ACTEL)
ISRO_CQFP256_40.00

RT54SX-S,
ISRO_CQFP256_40.00 0.5 3.0 x 0.33 34.50 37.00 40.00 RTAX2000S- 2.69
Cacity up
Note:

• For Cavity up Pin no. are in anticlockwise direction.
178
Part No: RTAX 1000S/2000S (ACTEL)
ISRO_CQFP352_52.00
ISRO_CQFP352_52.00 0.5 3.0 x 0.33 46.5 49.00 52.00 RTAX1000S/2000S 2.89
Note:

• For Cavity up Pin no. are in anticlock wise direction.
179
DUAL FLAT PACK ICs
Land Pattern Geometry for 8 Pins

25 mil Pitch, SOIC Package
Part No: ADP 3336(ANALOG DEVICES)
ISRO_CFP8_200
Lib. No P LL x LW B G Part No. Height
ADP 3336 (ANALOG

ISRO_CFP8_200 25 80 x 18 120 200 43
Devices)
Note:

• Device body length = 120 mil.
180
50 mil Pitch, SOIC Package,
Part No: MOCD223-M (FAIRCHILD)
ISRO_CFP8_224

MOCD223-M
ISRO_CFP8_224 50 80 x 40 144 224 143
(FAIRCHILD-QML)
Note:
• Controlling dimensions are in mil.

• Device body length = 202 mil
181
50 mil Pitch, CFP Device,
Part No: IS9 705RH-Q-8
ISRO_CFP8_452
ISRO_CFP8_452 50 120 x 40 332 452 IS9-705RH-Q-8 115
Note:
• Controlling dimension are in mil.

182
1.27 mm Pitch, SOIC Package,
Part No: AT45DB041 (ATMEL)
ISRO_CFP8_6.40

AT45DB041
ISRO_CFP8_6.40 1.27 2.0 x 1.0 4.40 6.40 1.75
(ATMEL)
Note:
• Controlling dimensions are in mm

• Device body length = 5.05 mm
183
Part No: PE9311, PE9301, PE9312, PE9313 (PEREGRINE SEMI.)
ISRO_MFP8_365

PE9311, PE9301,
ISRO_MFP8_365 50 170 x 30 195 365 PE9312, PE9313 70
(PEREGRINE)
Note:
• Controlling dimension are in mil

• Bottom of the device is metallic
184
50 mil Pitch, Device: WG10A/W10A,
Part No: LM158QML, DS16F95 (NATIONAL SEMI.)
ISRO_CFP10_400

LM158QML, DS16F95
ISRO_CFP10_400 50 120 x 30 280 400 80
(NATIONAL SEMI.)
Note:

185
Part No: M11X1041 (AEROFLEX METELICS)
ISRO_CFP10_840

M11x1041 (AEROFLEX
ISRO_CFP10_840 100 120 x 40 720 840 175
METELICS)
Note:
186
1.27 mm Pitch, CFP Device,
Part No: RHFL 4913 (ST MICROELECTRONIC)
ISRO_CFP14_7.90

RHFL4913 (ST MICRO
ISRO_CFP14_7.90 1.27 3.0 x 0.76 4.90 7.90 2.34
ELECTRONICS)
Note:
• Controlling dimensions are in mm.

• Device body length = 9.95 mm.
187
Part No: RCA RH 4000 SERIES
ISRO_CFP14_390A

RCA RH 4000
ISRO_CFP14_390A 50 190 x 30 200 390
SERIES
Note:
188
50 mil Pitch, Device: WG14A,
Part No: LM124 WG(NATIONAL SEMI.)
ISRO_CFP14_390B

LM124A
ISRO_CFP14_390B 50 100 x 30 290 70
390 (NATIONAL SEMI.)
Note:
• Controlling dimensions are in mil

• Device length is 390 mil
189
50 mil Pitch, CFP Device: W14B,
Part No: 54AC00, 54ACT00, 54F14
ISRO_CFP14_412
54AC00, 54ACT00, 54F14 80

ISRO_CFP14_412 50 120 x 30 292 412
(NATIONAL SEMI.)
Note:

• Device body dimension 385x 252 mil.
190
50 mil Pitch, CFP Device: K14.A,
Part No: 54HCT00/04/08/32, 54ACT74,
54LVCH244 (INTERSIL/NATIONAL/EQC)
ISRO_CFP14_500
54HCT00/04/08/32, 54ACT74, 54LVCH244

ISRO_CFP14_500 50 120 x 40 380 500 115
(INTERSIL/ NATIONAL/ EQC)
Note:
• Controlling dimension are in mil.

• Device body length is 390 mil.
191
100 mil Pitch, Flat Pack Device,
Part No: DTC 5729.16(Temex), 18092G-1 to 12(PDI)
ISRO_CFP14_1046

DTC 5729.16(Temex), 18092G-1 to
ISRO_CFP14_1046 100 120 x 40 926 1046 522
12(PRECISION DeviceS INC.)
Note:

• Pin 8 physically does not exist as per catalog. In view of this, additional support to the device on PCB must
be provided. The support options are
(a) Araldite AV138H998 on two width sides prior to soldering of pins.
(b) Metallic ‘C’ clamp plate with 2.5mm hole & approved hardware & torque value.
(c) Lacing prior to soldering of pins
• 810MIL sq size ground pad is required below the device body.
• Device body length is 811 mil
192
Part No:VMF-2E-500/78458, IQF-2E SERIES, (MERRIMAC)
ISRO_CFP14_1200
VMF-2E-500/78458, IQF-2E,
ISRO_CFP14_1200 100 120 x 80 1080 1200 160
(MERRIMAC)
Note:

• Device body length is 810 mil
193
Part No: 26C32
ISRO_PFP16_256

ISRO_ PFP16_256 50 80 x 40 176 256 26C32 (TEXAS INST.) 69
Note:

• Device body length is 394mil
• Approved for Airborne projects only
194
50 mil Pitch, WG16A Device,
Part No: LM 2941WG, ADC128S102 QML
ISRO_CFP16_390

LM2941WG, ADC128S102
ISRO_CFP16_390 50 100 x 30 290 390 80
(NATIONAL SEMI.)
Note:

195
Part No: 54HCTS157MS,54F157
ISRO_CFP16_380

54HCTS157MS,
ISRO_CFP16_380 50 180 x 30 200 380
54F157
196
50 mil Pitch, K16.A CFP Device,
Part No: DS90LV031AW-QML, DS90LV032AW-QML, UT54LVD8032LV/31LV, LVDS
DS90C31/32, HS-26C31RH, HS-26CT32RH, HS-91825_ARH-Q, 54HTC138/39, CD4051/94/14/49,
54LVDS 031 LV/032LV, UT54ACS109, AD7872RPFE, ISL7457SRH
ISRO_CFP16_425

DS90L V031AW-QML, DS90LV032AW-QML,
LVDSDS90C31/32, UT54LVD8032LV/31LV,
HS26C31RH, HS26CT32RH, HS91825ARHQ,
54HCT138/39,CD4051/94/14/49
ISRO_CFP16_425 50 120 x 30 305 425
(INTERSIL/NATIONAL/EQC), 54LVDS 031 LV/032LV
(TEXAS INS.), UT54ACS109 (RADHARD MSI LOGIC),
AD7872RPFE(ANALOG Device), ISL7457SrH
(INTERSIL)
Note:

• Height of device =130 mil
197
50 mil Pitch, W16A CFP Device,
Part No: 26LV32,54AC/54ACT157
ISRO_CFP16_430

ISRO_CFP16_430 50 120 x 30 310 430 26LV32, 54AC/54ACT157 (NATIONAL) 80
Note:

198
Part No: M54HC4050, 54HCT138, RHFL4913
ISRO_CFP16_10.97

M54HC4050(ST),
54HC138,
ISRO_CFP16_10.97 1.27 3.0 x 0.76 7.97 10.97 2.72
RHFL4913 (ST
ELECTRONICS)
Note:
• Controlling dimension are in mm

• Device body length = 9.94 mm
• RHFL4913 is metallic package
199
Part No: 54LVDS 031LV/032LV (TEXAS INS.)
ISRO_CFP16_460

54LVDS031LV/032LV
ISRO_CFP16_460 50 120 x 40 340 460 115
(TEXAS INS.)
Note:

200
25 mil Pitch, SSOP Device,
Part No: SP 3223B (SIPEX)
ISRO_PFP20_308

ISRO_PFP20_308 25 80 x 18 228 308 SP3223B (SIPEX) 78
Note:

• Device body length 289 mil
• Approved for Air Borne project only.
201
50 mil Pitch, PFP Device,
Part No: HI1573
ISRO_PFP20_380

HI1573
ISRO_PFP20_380 50 100 x 30 280 380 100
(HOLT INC.)
Note:
• Dimension are in mil

202
Part No: DS3232 (TEXAS INSTRUMENTS)
ISRO_CFP20_394

DS3232(TEXAS
ISRO_ CFP20_394 50 80 x 40 314 394 104
INSTRUMENTS)QML
Note:

203
50 mil Pitch, W20A CFP Device,
Part No: 54ACT244/245, 54F244, 54ABT244, 54ACTQ244/245,
54F240/241/244
ISRO_CFP20_425

54ACT244/245, 54F244 54ABT244,
ISRO_CFP20_425 50 120 x 30 305 425 54ACQ244/245, 54ACTQ244/245, 75
54F240/241/244 (NATIONAL)
Note:

204
Part No: 54HCT244/245 (ST MICRO/INTERSIL)
ISRO_CFP20_12.95
54HCT244/ 245
ISRO_CFP20_12.95 1.27 4.30 x 0.76 8.65 12.95 2.33
(ST MICRO/INTERSIL)
Note:
• Controlling dimension are in mm

• Device body length 12.044 mm
• As per MIL-STD-1835D package style is Ceramic, metal sealed, bottom brazed spider lead
205
50 mil Pitch, K20.A CFP Device,
Part No: 54HCT541/244/245/373 (INTERSIL/NATIONAL/EQC)
ISRO_CFP20_550
54HCT541/244/245/373
ISRO_CFP20_550 50 120 x 40 430 550 115
(INTERSIL/ NATIONAL/ EQC)
Note:

• Body length of device 540 mil.
206
Part No: UT63M143
ISRO_CFP24_760
ISRO_CFP24_760 50 120 x 30 640 760 UT63M143 130
Note:
207
Part No: M67204H,AT28C256 (ATMEL)
ISRO_CFP28_14.22

M67204H-
FIFO(ATMEL), 3.30
ISRO_CFP28_14.22 1.27 3.00 x 0.76 11.22 14.22
AT28C256-
COMM(ATMEL)
Note:
• Body length of device 18.80 mm.
208
50 mil Pitch,CFP Device,
Part No: HS1840, HS6664 RH, AD9814 ,AD768,AD1672-703F
ISRO_CFP28_650

HS1840, HS6664 RH,
ISRO_CFP28_650 50 120 x 30 530 650 AD9814, AD768, 115
AD1672-703F**
Note:

• Body length of device HS1840, HS6664RH, AD9814, AD768 is 740 mil
• **Body Length of AD1672-703F is 765 mil
209
Part No: 197A807-144T/C-32kx8PROM,LM32K/8 PROM
238A790 -214T 197A807-244T
ISRO_CFP28_660
197A807-144T/C-
238A790 -214T
ISRO_CFP28_660 50 120 x 30 540 660 197A807-244T 109
32KX8 PROM,
LM32K/8 PROM
Note:

• Body length of device 768 mil
210
50 mil Pitch, CFP Device,(HYBRID PACKAGE)
Part No: 143IB/1440B,112SSS, 114SSS,
115SSS, 361AF, 240OB
ISRO_CFP30_1290

143IB/ 144OB, 112SSS,
ISRO_CFP30_1290 50 120 x 30 1170 1290 103
114SSS, 115SSS, 361AF, 240OB
Note:

211
Part No: 256 MB MEMORY MODULE-(3D PLUS)3DD-256(SSR)
ISRO_CFP32_453

256MB MEMORY MODULE
ISRO_CFP32_453 50 160 x 24 293 453
(3D PLUS), 3DD-256(SSR)

• Trace width between pads 0.25 mm
• Trace to pad spacing 0.2 mm
212
Part No: EEPROM AS58C1001(128Kx8), AT28C010-12DK (ASI/ATMEL)
ISRO_CFP32_595

AS58C1001(128KX8),
ISRO_CFP32_595 50 120 x 30 475 595 150
AT28C010-12DK
Note:

• Body Length of device 830 mil.
213
Part No: CMOS EEPROM W28C256
(NORTHROP GRUMMAN CORPORATION)
ISRO_CFP32_754

CMOS EEPROM W28C256 (NORTHROP
ISRO_CFP32_754 50 120 x 40 634 754 120
GRUMMAN CORPORATION
Note:

214
Part No: 198A592-234T (198A-592-234T 128KX8 SRAM)
ISRO_CFP32_812

ISRO_CFP32_812 50 120 x 30 692 812 198A 592-234T 130
Note:

• Body Length of device 820 mil.
215
Part No: 182A 934-234T (LOCKHEED MARTIN) HX6256
ISRO_CFP36_790

182A 934-234T
ISRO_CFP36_790 25 120 x 18 670 790 HX6256 97
32K 8SRAM
Note:

216
Part No: UT 512K x 8 SRAM-UTMC
ISRO_CFP36_17.13

ISRO_CFP36_17.13 1.27 3.00 x 0.76 14.13 17.13 UT 512K x 8 SRAM-UTMC ---
Note:
• Dimension are in mm
217
Part No: UT9Q512E (AEROFLEX)
ISRO_CFP36_20.65
UT9Q512E - SRAM
ISRO_CFP36_20.65 1.27 3.00 x 0.76 17.60 20.60 3.30
(AEROFLEX)
Note:
• Body length of device 23.62 mm.
218
Part No: SRAM (128K x 8) (BAY SYSTEM)
ISRO_CFP40_924

SRAM (128K x 8)
ISRO_ CFP40_924 25 120 x 15 804 924 125
BAY SYSTEM
Note:

219
Part No: 190A325-134T, HX6228
ISRO_CFP40_935

190A325-134T,
ISRO_CFP40_935 25 120 x 18 815 935 125
HX6228
Note:

220
Part No: 16LVTH2244/2245, UT54LVDS217/218, 54ACT16244,
54ACTQ16245
ISRO_CFP48_540

16LVTH2244/2245,
UT54LVDS217/8,
ISRO_CFP48_540 25 120 x 18 420 540 170
54ACT16244,
54ACTQ16245
Note:

• Body length of device 16LVTH2244/2245 is 730 mil, UT54LVDS217/218 is 810 mil (TEXAS
INSTRUMENTS)
• Body length of device 54ACT16244, 54ACTQ16245 (NATIONAL SEMICONDUCTOR) is 640 mil
221
0.8 mm Pitch, SOP Device,
Part No: MMSD08256404S (3D PLUS)
ISRO_CFP54_11.08

MMSD08256404S- 2GB
ISRO_CFP54_11.08 0.8 5.08 x 0.46 6.00 11.08 7.75
SDRAM (3D PLUS)
Note:
• Trace width between pads 0.12 mm
• Trace to pad spacing 0.1mm
• Body length of device 24.20 mm
222
0.8 mm Pitch, SOP Device,
Part No: MMSR16001808S-CR (3D PLUS)
ISRO_CFP64_9.40

MMSR16001808S-CR
ISRO_CFP64_9.40 0.8 3.00 x 0.5 6.40 9.40 7.75
(3D PLUS)
Note:
223
Part No: BU61582/BU63825
ISRO_CFP70_1160
BU61582/
ISRO_CFP70_1160 50 120 x 30 1040 1160 215
BU63825
Note::

224
Part No: BU-63825FX/BU-61582F3-431Z
(DATA DEVICE CORPORATION)
ISRO_CFP70_1233

BU-63825FX & BU-61582F3-
ISRO_CFP70_1233 50 120 x 40 1113 1233 215
431Z(DATA Device CORP.)
Note:

225
0.50 mm Pitch, MFP Device,
Part No: 251A 172-417
ISRO_MFP84_30.23
251A 172-417
ISRO_MFP84_30.23 0.5 3.00 x 0.33 27.23 30.23 5.15
(SRAM MCM)
Note:
226
RELAY: E210/215 & EL210/215
No. of pins: 10
Relay mounting hole dia: 3.8mm Free Hole
Turrets Hole Dia. 1.6 (63); Pad Dia. 2.5 (100)
Sr. No. Lib. No Part No No. of Turrets

1 ISRO_E210/215 E210/215 10
2 ISRO_EL210/215 EL210/215 10
227
RELAY: E410/415 & EL410/415
No.OF PINS:16
Relay mounting hole dia: 3.8mm Free Hole
Turrets Hole Dia. 1.6 (63); Pad Dia. 2.54 (100)
No. of
Sr. No. Lib. No Part No
Turrets
1 ISRO_E410/415 E410/415 16
2 ISRO_EL410/415 EL410/415 16
228
RELAY:TO5 PACKAGE
Hole
Sr. No. Lib. No Type No. of Pins Pad Dia
Dia
1 ISRO_TO5R_8 TO5 8 0.8(31) 1.5(59)
2 ISRO_TO5R_10 TO5 10 0.8(31) 1.5(59)
Note: Tracks, Pads,Vias are not permitted under these devices on component side.
229
RELAY:GP250
RELAY TYPE: GP250 CODE 00
No. of Pad Hole

Sr. No. Lib. No Part No Height
Pins Dia Dia
2.0 1.0 12.5
1 ISRO_GP250_200 10 GP 250-720-E-00-26V
(79) (39) (98)
230
RELAY: GP250F
RELAY TYPE: GF250F CODE DB
No. of Hole
Sr. No. Lib. No Part No Pad Dia Height
Pins Dia
2.0 1.0 12.5
1 ISRO_GP250F_200 GP250-720-E-DB-26V 10
(79) (39) (98)
Relay mounting Hole Dia.: 3.2 mm Free Hole
231
RELAY: GP5
RELAY Type: GP5 CODE 00
No. of Pad
Sr. No. Lib. No Hole Dia Part No Height
Pins Dia
2.0 1.0 GP5-900-A-00-26V, 12.5
1 ISRO_GP5_200 8
(79) (39) GP5-700-A-00-26V (98)
232
RELAY: GP5F
RELAY Type: GP5F CODE DB
No. of Hole
Sr. No. Lib. No Pad Dia Part No
Pins Dia
2.0 1.0 GP5-900-A-DB-26V,
1 ISRO_GP5F_200 8
(79) (39) GP5-700-A-DB-26V
Relay mounting Hole Dia.: 3.2 mm Free Hole
233
RELAY: 3SBC
RELAY TYPE: 3SBC
No. of Pad Hole Part

Sr. No. Lib. No
Pins Dia Dia No
1 ISRO_3SBC_150 8 1.5 (59) 0.8 (31) 3SBC
234
SOLID STATE RELAY
Sr. No. Lib. No. LL x LW P B G Part No.
2.54 x 1.00 2.54 8.38 10.92 SCDO1CFY

1 ISRO_SCDO1CFY_430
(100 x 40) (100) (330) (430) (Teledyne)
Note: Pin No. 3 & 6 do not exist physically as per catalog.
235
CONNECTORS
NOMENCLATURE: STANDARD DENSITY FRB CONNECTOR
236
STANDARD DENSITY 90º BENT FRB CONNECTOR
Lib.. No. No. of Pins L A B D E/G F P/C

38.50 30.48 1.27 3.81 5.08 20.32 2.54
(1516) (1200) (50) (150) (200) (800) (100)
53.70 45.72 1.27 3.81 5.08 35.56 2.54
(2114) (1800) (50) (150) (200) (1400) (100)
69.00 60.96 1.27 3.81 5.08 50.80 2.54
(2717) (2400) (50) (150) (200) (2000) (100)
84.20 76.20 1.27 3.81 5.08 66.04 2.54
(3315) (3000) (50) (150) (200) (2600) (100)
99.5 91.44 1.27 3.81 5.08 81.28 2.54
(3917) (3600) (50) (150) (200) (3200) (100)
Note:
• Pad Dia is 1.50 (60)

• Hole Dia is 0.8 (32)
• M is Connector Mounting Free Hole Diameter -2.70 (106)
237
STANDARD DENSITY 90º BENT FRB CONNECTOR
No. of
Lib. No. L A B D/H E/G F P/C
Pins
ISRO_FRBSD72P/S_ 114.70 106.68 1.27 3.81 5.08 43.18 2.54
72 PIN
RA_4200 (4516) (4200) (50) (150) (200) (1700) (100)
ISRO_FRBSD84P/S_ 129.90 121.92 1.27 3.81 5.08 50.80 2.54
84 PIN
RA_4800 (5114) (4800) (50) (150) (200) (2000) (100)
ISRO_FRBSD96P/S_ 145.20 137.16 1.27 3.81 5.08 58.42 2.54
96 PIN
RA_5400 (5716) (5400) (50) (150) (200) (2300) (100)
ISRO_FRBSD120P/S_ 120 175.50 167.64 1.27 3.81 5.08 73.66 2.54
RA_6600 PIN (6909) (6600) (50) (150) (200) (2900) (100)
Note:
• Pad Dia is 1.50 (60)

238
STANDARD DENSITY STRAIGHT FRB CONNECTORS
No. of
Lib. No. L A B/G E F P/C
Pins
ISRO_FRBSD17P/S_ 38.50 30.48 1.27 5.08 20.32 2.54
17 PIN
ST_1200 (1516) (1200) (50) (200) (800) (100)
ISRO_FRBSD29P/S_ 53.70 45.72 1.27 5.08 35.56 2.54
29
ST_1800 (2114) (1800) (50) (200) (1400) (100)
ISRO_FRBSD41P/S_ 69.00 60.96 1.27 5.08 50.80 2.54
41
ST_2400 (2717) (2400) (50) (200) (2000) (100)
ISRO_FRBSD53P/S_ 84.20 76.20 1.27 5.08 66.04 2.54
53
ST_3000 (3315) (3000) (50) (200) (2600) (100)
ISRO_FRBSD65P/S_ 99.50 91.44 1.27 5.08 81.28 2.54
65
ST_3600 (3917) (3600) (50) (200) (3200) (100)
Note:
• Pad Dia is 1.50 (60)
• Height of the component is 8.05(317) for plug/ socket type connector
• Width (W) for plug 6.40 (252) and for socket 7.00 (276)
239
STANDARD DENSITY STRAIGHT FRB CONNECTORS
No. of
Lib. No. L A B/G H E F P/C
Pins
114.70 106.68 1.27 3.81 5.08 96.52 2.54
(4516) (4200) (50) (150) (200) (3800) (100)
129.90 121.92 1.27 3.81 5.08 111.76 2.54
(5114) (4800) (50) (150) (200) (4400) (100)
145.20 137.16 1.27 3.81 5.08 127.00 2.54
(5716) (5400) (50) (150) (200) (5000) (100)
175.50 167.64 1.27 3.81 5.08 157.48 2.54
(6909) (6600) (50) (150) (200) (6200) (100)
Note:
• Pad Dia is 1.50 (60)
• Height of the component is 8.05(317) for plug/ socket type connector
• Width (W) for plug 6.40 (252) and for socket 7.00 (276)
240
CONTACT ARRAGEMENT OF STANDARD DENSITY FRB CONNECTORS
241
PCB MOUNTABLE TWO ROWS STANDARD DENSITY(DAUGHTER BOARD)
90 DEG BENT CONNECTORS DE-CODING (KNB)
3401 016 01 B 01* MC/ML 33 00 33
*No. OF CONTACTS
01-17 PINS 04-53 PINS 07-84 PINS
02-29 PINS 05-65 PINS 08-96 PINS
03-41 PINS 06-72 PINS 10-120 PINS
242
ESSC PART No. FOR PLUG
No OF
Sr.No Lib. No.FOR PLUG* ESCC PART No MIL PART NUMBER
PINS
1 17 ISRO_FRBSD17P_RA_1200 340101601B01MC330033 D55302 162C17W
2 29 ISRO _FRBSD29P_RA_1800 340101601B02MC330033 D55302 162C29W
3 41 ISRO_ FRBSD41P_RA_2400 340101601B03MC330033 D55302 162C41W
5 65 ISRO _FRBSD65P_RA_3600 340101601B05MC330033 D55302 162C65W
Lib. No.FOR PLUG**
10 17 ISRO_ FRBSD17P_RA_1200 340101601B01ML720072
11 29 ISRO _FRBSD29P_RA_1800 340101601B02ML720072
Note:
• *Board thickness: 1.7-2.0 mm, for use on Daughter Board Pitch:1.27mm,Spill length: 3mm.
• **Board thickness: 2.4mm , for use on Daughter Board Pitch:1.27mm. Spill Length: 4mm.
• RA=Right angle Mounting, ST=Straight Mounting
• SD=Standard density, HD=high density
243
ESSC PART No. FOR SOCKET
Sr No OF Lib. No. FOR SOCKET
ESCC PART No MIL PART NUMBER
No PINS (Daughter Board)
1 17 ISRO_FRBSD17S_RA_1200 340101601B13FC360036 D55302 159D17W

Lib. No. FOR SOCKET
(Mother Board)
10 17 ISRO_FRBSD17S_ST_1200 340101601B13FD360036 D55302 159D17B
Note:
• Board Thickness:2.4mm, for use on mother board pitch:1.27mm.

• For different lead length please contact manufacturer.
• RA=Right angle Mounting, ST=Straight mounting
• SD=Standard density, HD=high density
244
NOMENCLATURE OF HIGH DENSITY FRB CONNECTOR
245
HIGH DENSITY 90º BENT FRB CONNECTOR
No. of
Lib. No. L A B D E F P/C/G
Pins
38.50 30.48 1.27 3.81 5.08 20.32 2.54
(1516) (1200) (50) (150) (200) (800) (100)
53.70 45.72 1.27 3.81 5.08 35.56 2.54
(2114) (1800) (50) (150) (200) (1400) (100)
69.00 60.96 1.27 3.81 5.08 50.80 2.54
(2717) (2400) (50) (150) (200) (2000) (100)
84.20 76.20 1.27 3.81 5.08 66.04 2.54
(3315) (3000) (50) (150) (200) (2600) (100)
99.50 91.44 1.27 3.81 5.08 81.28 2.54
(3917) (3600) (50) (150) (200) (3200) (100)
Note:
• Pad Dia is 1.50 (60)
• Hole Dia is 0.80 (32)
246
HIGH DENSITY 90º BENT FRB CONNECTOR
No. of
Lib. No. L A B D E/H F P/C/G
Pins
145.20 137.16 1.27 3.81 5.08 127 2.54
(5716) (5400) (50) (150) (200) (5000) (100)
160.40 152.40 1.27 3.81 5.08 142.24 2.54
(6315) (6000) (50) (150) (200) (5600) (100)
Note:
• Pad Dia is 1.50 (60)

• Hole Dia is 0.80 (32)
247
HIGH DENSITY STRAIGHT FRB CONNECTORS
No. of
Lib. No. L W A B E F P/G/C
Pins
38.50 7.00 30.48 1.27 5.08 20.32 2.54
(1516) (276) (1200) (50) (200) (800) (100)
53.70 7.00 45.72 1.27 5.08 35.56 2.54
(2114) (276) (1800) (50) (200) (1400) (100)
69.00 7.00 60.96 1.27 5.08 50.8 2.54
(2717) (276) (2400) (50) (200) (2000) (100)
84.20 7.00 76.20 1.27 5.08 66.04 2.54
(3315) (276) (3000) (50) (200) (2600) (100)
99.50 7.00 91.44 1.27 5.08 81.28 2.54
(3917) (276) (3600) (50) (200) (3200) (100)
Note:
• Pad Dia is 1.50 (60)

• Hole Dia is 0.80 (32)
• Height of component is 8.05 (317)
248
HIGH DENSITY STRAIGHT FRB CONNECTORS
No. of
Lib. No. L W A B E/H F P/C/G
Pins
145.20 7.00 137.16 1.27 5.08 127.00 2.54
(5716) (276) (5400) (50) (200) (5000) (100)
160.40 7.00 152.40 1.27 5.08 142.24 2.54
(6315) (276) (6000) (50) (200) (5600) (100)
Note:
• Pad Dia is 1.50 (60)

• Hole Dia is 0.80 (32)
249
CONTACT ARRAGEMENT OF HIGH DENSITY FRB CONNECTORS
ESSC PART No. FOR SOCKET
Sr. No No of PINS Lib. No.FOR SOCKET ESCC PART No
1 26 ISRO_FRBHD26S_ST_1200 340103901B0264430121
2 44 ISRO_FRBHD44S_ST_1800 340103901B0444430121
3 62 ISRO_FRBHD62S_ST_2400 340103901B0624430121
4 80 ISRO_FRBHD80S_ST_3000 340103901B0804430121
5 98 ISRO_FRBHD98S_ST_3600 340103901B0984430121
6 144 ISRO_FRBHD144S_ST_5400 340103901B1444430121
7 162 ISRO_FRBHD162S_ST_6000 340103901B1624430121
250
ESSC PART No. FOR PLUG
Sr. No No of PINS Lib. No.FOR PLUG ESCC PART No
1 26 ISRO_FRBHD26P_RA_1200 340103901B0265510110
2 44 ISRO_FRBHD44P_RA_1800 340103901B0445510110
3 62 ISRO_FRBHD62P_RA_2400 340103901B0625510110
4 80 ISRO_FRBHD80P_RA_3000 340103901B0805510110
5 98 ISRO_FRBHD98P_RA_3600 340103901B0985510110
6 144 ISRO_FRBHD144P_RA_5400 340103901B01445510110
7 162 ISRO_FRBHD162P_RA_6000 340103901B01625510110
RA=Right angle Mounting, ST=Straight Mounting

SD=Standard density, HD=high density
251
NOMENCLATURE OF D-Type CONNECTOR
252
STANDARD DENSITY 90º BENT D TYPE PLUG CONNECTOR with Brackets
Device
Lib. No. L W P A B C D E F G
Type
ISRO_SD-RA_ 9P_2B7N 30.81 15.60 2.74 24.99 1.37 2.84 11.52 7.01 10.96 1.42
9P_984 /2B9N (1213) (614) (108) (984) (54) (112) (454) (276) (432) (56)
ISRO_SD- 15P_2B7N 39.14 15.60 2.74 33.32 1.37 2.84 11.52 7.07 19.18 1.42
RA_15P_1312 / 2B9N (1541) (614) (108) (1312) (54) (112) (454) (278) (756) (56)
ISRO_SD- 25P_2B7N 53.04 15.80 2.76 47.04 1.38 2.84 11.74 6.96 33.1 1.42
RA_25P_1852 /2B9N (2088) (622) (109) (1852) (54.5) (112) (462) (274) (1304) (56)
ISRO_SD- 37P_2B7N 69.32 15.80 2.76 63.50 1.38 2.84 11.74 6.91 49.68 1.42
RA_37P_2500 /2B9N (2729) (622) (109) (2500) (54.5) (112) (462) (272) (1956) (56)
Note:
• Pad Dia is 1.70 (67)

• Hole Dia is 1.00 (39)
253
STANDARD DENSITY 90º BENT D TYPE PLUG CONNECTOR with Brackets
PLUG
Device
Type
ISRO_SD- 50P_2B7N/ 66.93 17.70 2.76 61.11 1.38 2.84 13.16 8.48 44.16 2.84
RA_50P_2406 2B9N (2635) (697) (109) (2406) (54.5) (112) (518) (334) (1739) (112)
Note:
• Pad Dia is 1.70(67)

• Hole Dia is 1.00(39)
254
STANDARD DENSITY 90º BENT D TYPE SOCKET CONNECTOR with Brackets
SOCKET
Device
Lib. No. L W P A B D C E F G
Type
ISRO_SD- 9S_2B7N 30.81 15.60 2.74 24.99 1.37 11.52 2.84 7.01 10.96 1.42
RA_9S_984 /2B9N (1213) (614) (108) (984) (54) (454) (112) (276) (432) (56)
ISRO_SD- 15S_2B7N 39.14 15.60 2.74 33.32 1.37 11.52 2.84 7.07 19.18 1.42
RA_15S_1312 /2B9N (1541) (614) (108) (1312) (54) (454) (112) (278) (756) (56)
ISRO_SD- 25S_2B7N 53.04 15.60 2.76 47.04 1.38 11.52 2.84 6.96 33.12 1.42
RA_25S_1852 /2B9N (2088) (614) (109) (1852) (54.5) (454) (112) (274) (1304) (56)
ISRO_SD- 37S_2B7N 69.32 15.60 2.76 63.50 1.38 11.52 2.84 6.91 49.68 1.42
RA_37S_2500 /2B9N (2729) (614) (109) (2500) (54.5) (454) (112) (272) (1956) (56)
Note:
• Pad Dia is 1.70 (67)

• Hole Dia is 1.00 (39)
255
STANDARD DENSITY 90º BENT D TYPE SOCKET CONNECTOR with Brackets
Device
Lib. No. L W P A B D C E F G
Type
ISRO_SD- 50S_2B7N 66.93 17.5 2.76 61.11 1.38 12.94 2.84 8.48 44.16 2.84
RA_50S_2406 /2B9N (2635) (689) (109) (2406) (54.5) (509) (112) (334) (1739) (112)
Note:
• Pad Dia is 1.70 (67)

• Hole Dia is 1.00 (39)
256
CONTACT ARRAGEMENT OF STANDARD DENSITY 90 DEGREE D-TYPE
CONNECTORS
ESSC PART No. FOR RIGHT ANGLE PLUG & SOCKET

No OF Lib. No. FOR RIGHT MIL PART
Sr No. ESCC PART NUMBER
PINS ANGLE PLUG & SOCKET NUMBER
1 9 ISRO_SD-RA_ 9P_984 M24308/24-49 340100101BDEM9PNMB2B7N
2 15 ISRO_SD-RA_15P_1312 M24308/24-50 340100101BDAM15PNMB2B7N
3 25 ISRO_SD-RA_25P_1852 M24308/24-51 340100101BDBM25PNMB2B7N
4 37 ISRO_SD-RA_37P_2500 M24308/24-52 340100101BDCM37PNMB2B7N
5 50 ISRO_SD-RA_50P_2406 M24308/24-53 340100101BDDM50PNMB2B7N
6 9 ISRO_SD-RA_9S_984 M24308/23-49 340100101BDEM9SNMB2B7N
7 15 ISRO_SD-RA_15S_1312 M24308/23-50 340100101BDAM15SNMB2B7N
8 25 ISRO_SD-RA_25S_1852 M24308/23-51 340100101BDBM25SNMB2B7N
9 37 ISRO_SD-RA_37S_2500 M24308/23-52 340100101BDCM37SNMB2B7N
10 50 ISRO_SD-RA_50S_2406 M24308/23-53 340100101BDDM50SNMB2B7N
Note:
• As per ESA/SCC standard lead length is 5mm & lead dia is 0.76mm
• SD=Standard density; RA= Right angle Mounting
257
STANDARD DENSITY STRAIGHT D TYPE PLUG CONNECTOR
PLUG
Device
Lib. No. L W P A B C E F G
Type
ISRO_SD-ST_ 30.81 12.55 2.74 24.98 1.37 2.84 7.01 10.98 1.42
9P_OL3
9P_984 (1213) (494) (108) (984) (54) (112) (276) (432) (56)
ISRO_SD- 15P_ 39.14 12.55 2.74 33.32 1.37 2.84 7.07 19.18 1.42
ST_15P_1312 OL3 (1541) (494) (108) (1312) (54) (112) (278) (756) (56)
ISRO_SD- 25P_ 53.04 12.55 2.76 47.04 1.38 2.84 6.96 33.12 1.42
ST_25P_1852 OL3 (2088) (494) (109) (1852) (54.5) (112) (274) (1304) (56)
ISRO_SD- 69.32 12.55 2.76 63.50 1.38 2.84 6.91 49.68 1.42
37P_0L3
ST_37P_2500 (2729) (494) (109) (2500) (54.5) (112) (272) (1956) (56)
Note:
• Pad Dia is 1.60 (63)

• Hole Dia is 0.90 (35)
258
STANDARD DENSITY STRAIGHT D TYPE PLUG CONNECTOR
PLUG
Device
Type
ISRO_SD- 66.93 15.37 2.76 61.11 1.38 2.84 8.48 44.16 2.84
50P_0L3
ST_50P_2406 (2635) (605) (109) (2406) (54.5) (112) (334) (1739) (112)
Note:
• Pad Dia is 1.60(63)

259
STANDARD DENSITY STRAIGHT D TYPE SOCKET CONNECTOR
SOCKET
Device
Type
ISRO_SD-ST_ 30.81 12.55 2.74 24.99 1.37 2.84 7.01 10.96 1.42
9S_OL3
9S_984 (1213) (494) (108) (984) (54) (112) (276) (432) (56)
ISRO_SD- 15S_ 39.14 12.55 2.74 33.32 1.37 2.84 7.07 19.18 1.42
ST_15S_1312 OL3 (1541) (494) (108) (1312) (54) (112) (278) (756) (56)
ISRO_SD- 25S_ 53.04 12.55 2.76 47.04 1.38 2.84 6.96 33.12 1.42
ST_25S_1852 OL3 (2208) (494) (109) (1852) (54.5) (112) (274) (1304) (56)
ISRO_SD- 69.32 12.55 2.76 63.50 1.38 2.84 6.91 49.68 1.42
37S_0L3
ST_37S_2500 (2729) (494) (109) (2500) (54.5) (112) (272) (1956) (56)
Note:
• Pad Dia is 1.60(63)

260
STANDARD DENSITY STRAIGHT D TYPE SOCKET CONNECTOR
SOCKET
Device
Type
ISRO_SD- 50S_ 66.93 15.37 2.76 61.11 1.38 2.84 8.48 44.16 2.84
ST_50S_2406 OL3 (2635) (605) (109) (2406) (54.5) (112) (334) (1739) (112)
Note:
• Pad Dia is 1.60(63)

261
CONTACT ARRAGEMENT OF STANDARD DENSITY STRAIGHT D-TYPE
CONNECTORS
PLUG SOCKET
ESSC PART No. FOR STRAIGHT PLUG & SOCKET

No of Lib. No. FOR STRAIGHT MIL PART
PINS PLUG & SOCKET NUMBER
1 9 ISRO_SD-ST_ 9S_984 M24308/23-7 340100101BDEM9SNMBOL3
2 15 ISRO_SD-ST_15S_1312 M24308/23-8 340100101BDAM15SNMBOL3
3 25 ISRO_SD-ST_25S_1852 M24308/23-9 340100101BDBM25SNMBOL3
4 37 ISRO_SD-ST_37S_2500 M24308/23-10 340100101BDCM37SNMBOL3
5 50 ISRO_SD-ST_50S_2406 M24308/23-11 340100101BDDM50SNMBOL3
6 9 ISRO_SD-ST_9P_984 M24308/24-7 340100101BDEM9PNMBOL3
7 15 ISRO_SD-ST_15P_1312 M24308/24-8 340100101BDAM15PNMBOL3
8 25 ISRO_SD-ST_25P_1852 M24308/24-9 340100101BDBM25PNMBOL3
9 37 ISRO_SD-ST_37P_2500 M24308/24-10 340100101BDCM37PNMBOL3
10 50 ISRO_SD-ST_50P_2406 M24308/24-11 340100101BDDM50PNMBOL3
ST=Straight mounting
SD=Standard density
Note:
• For OL3 termination modifier Standard Lead Dia:0.6±0.05mm

• For OL3 termination modifier Standard Lead Length: 4.15±0.2mm
262
263
HIGH DENSITY 90º BENT D TYPE PLUG CONNECTOR
PLUG
Lib. No. Device Type L W P A B C /G D E F

ISRO_HD-RA_
15P_1CON 1213 720 90 984 45 78 559 322 360
15P_984
ISRO_HD-
26P_1CON 1541 720 90 1312 45 78 559 316 720
RA_26P_1312
ISRO_HD-
44P_1CON 2088 728 90 1852 45 78 567 316 1260
RA_44P_1852
ISRO_HD-
62P_1CON 2729 728 95 2500 47.5 78 567 323 1900
RA_62P_2500
Note:
• Pad Dia is 1.50 (60)

• Hole Dia is 0.80 (32)
• All dimensions are in mil only.
264
HIGH DENSITY 90º BENT D TYPE PLUG CONNECTOR
PLUG
Device
Type
ISRO_HD- 78P_1DON
2635 815 95 2406 47.5 82 612 300 1805 41
RA_78P_2406 /1D9N
Note:
• Pad Dia is 1.50 (60)

• Hole Dia is 0.80 (32)
265
HIGH DENSITY 90º BENT D TYPE SOCKET CONNECTOR
Lib. No. Device Type L W P A B C/G D E F

ISRO_HD-RA_
15S_1CON 1213 720 90 984 45 78 559 322 360
15S_984
ISRO_HD-
26S_1CON 1541 720 90 1312 45 78 559 316 720
RA_26S_1312
ISRO_HD-
44S_1CON 2088 720 90 1852 45 78 559 316 1260
RA_44S_1852
ISRO_HD-
62S_1CON 2729 720 95 2500 47.5 78 559 320 1900
RA_62S_2500
SOCKET
Note:
• Pad Dia is 1.50 (60)

• Hole Dia is 0.80 (32)
266
HIGH DENSITY 90º BENT D TYPE SOCKET CONNECTOR
SOCKET
Device
Type
ISRO_HD- 78S_1DON
2635 807 95 2406 47.5 82 604 300 1805 41
RA_78S_2406 /1D9N

Note:
• Pad Dia is 1.50 (60)

• Hole Dia is 0.80 (32)
267
CONTACT ARRAGEMENT OF HIGH DENSITY D-TYPE CONNECTORS
PLUG SOCKET
ESSC PART No. FOR HIGH DENSITY RIGHT ANGLE SOCKET & PLUG
No of Lib. No. FOR RIGHT
PINS ANGLE SOCKET
1 15 ISRO_HD-RA_15S_984 340100102BDEM15SNMB1CON
2 26 ISRO_HD-RA_26S_1312 340100102BDAM26SNMB1CON
3 44 ISRO_HD-RA_44S_1852 340100102BDBM44SNMB1CON
4 62 ISRO_HD-RA_62S_2500 340100102BDCM62SNMB1CON
5 78 ISRO_HD-RA_78S_2406 340100102BDDM78SNMB1DON
Lib. No. FOR RIGHT
ANGLE PLUG
6 15 ISRO_HD-RA_15P_984 340100102BDEM15PNMB1CON
7 26 ISRO_HD-RA_26P_1312 340100102BDAM26PNMB1CON
8 44 ISRO_HD-RA_44P_1852 340100102BDBM44PNMB1CON
9 62 ISRO_HD-RA_62P_2500 340100102BDCM62PNMB1CON
10 78 ISRO_HD-RA-78P_2406 340100102BDDM78PNMB1DON
Note: RA=Right angle Mounting

HD=High density
268
HIGH DENSITY STRAIGHT D TYPE PLUG CONNECTOR
PLUG
Lib. No. Device Type L W P A B C /G E F
ISRO_HD-ST_15P_984 15P_ OL3 1213 494 90 984 45 78 322 360

ISRO_HD-ST_26P_1312 26P_ OL3 1541 494 90 1312 45 78 316 720
ISRO_HD-ST_44P_1852 44P_OL3 2088 494 90 1852 45 78 316 1260
ISRO_HD-ST_62P_2500 62P _OL3 2729 494 95 2500 47.5 78 323 1900
Note:
• Pad Dia is 1.60 (63)
• Hole Dia is 0.90 (35)
269
HIGH DENSITY STRAIGHT D TYPE PLUG CONNECTOR
PLUG
Lib. No. Device Type L W P A B C E F G

ISRO_HD- 78P_1DON
2635 605 95 2406 47.5 82 301 1805 41
ST_78P_2406 /1D9N
Note:
• Pad Dia is 1.60 (63)

• Hole Dia is 0.90 (35)
270
HIGH DENSITY STRAIGHT D TYPE SOCKET CONNECTOR
SOCKET
Lib. No. Device Type L W P A B C/G E F

ISRO_HD-ST_
15S_OL3 1213 494 90 984 45 78 322 360
15S_984
ISRO_HD-
26S _OL3 1541 494 90 1312 45 78 316 720
ST_26S_1312
ISRO_HD-
44S _OL3 2088 494 90 1852 45 78 316 1260
ST_44S_1852
ISRO_HD-
62S_OL3 2729 494 95 2500 47.5 78 323 1900
ST_62S_2500
Note:
• Pad Dia is 1.60 (63)

• Hole Dia is 0.90 (35)
271
HIGH DENSITY STRAIGHT D TYPE SOCKET CONNECTOR
SOCKET
Device
Type
ISRO_HD-
78S_OL3 2635 605 95 2406 47.5 82 300 1805 41
ST_78S_2406
Note:
• Pad Dia is 1.60 (63)

• Hole Dia is 0.90 (35)
272
CONTACT ARRANGEMENT FOR HIGH DENSITY D-TYPE CONNECTOR
PLUG SOCKET
ESSC PART No. FOR HIGH DENSITY STRAIGHT SOCKET & PLUG
Sr No OF Lib. No. FOR STRAIGHT
ESCC PART NUMBER
No. PINS SOCKET
1 15 ISRO_HD-ST_15S_984 340100102BDEM15SNMBOL3
2 26 ISRO_HD-ST_26S_1312 340100102BDAM26SNMBOL3
3 44 ISRO_HD-ST_44S_1852 340100102BDBM44SNMBOL3
4 62 ISRO_HD-ST_62S_2500 340100102BDCM62SNMBOL3
5 78 ISRO_HD-ST_78S_2406 340100102BDDM78SNMBOL3
Lib. No. FOR STRAIGHT
PLUG
6 15 ISRO_HD-ST_ 15P_984 340100102BDEM15PNMBOL3
7 26 ISRO_HD-ST_26P_1312 340100102BDAM26PNMBOL3
8 44 ISRO_HD-ST_44P_1852 340100102BDBM44PNMBOL3
9 62 ISRO_HD-ST_62P_2500 340100102BDCM62PNMBOL3
10 78 ISRO_HD-ST_78P_2406 340100102BDDM78PNMBOL3
Note: RA=Right angle

HD=High density
273
NOMENCLATURE OF MICRO-D CONNECTOR
274
MICRO-D 90º BENT PLUG & SOCKET
PLUG
SOCKET
No. of
Lib.. No. L W A B D E G P/C
Pins
35.31 11.81 29.21 1.27 3.18 9.53 3.81 2.54
(1390) (465) (1150) (50) (125) (375) (150) (100)
39.12 11.81 33.02 1.27 3.18 7.62 3.81 2.54
(1540) (465) (1300) (50) (125) (300) (150) (100)
42.93 11.81 36.83 1.27 3.18 5.72 3.81 2.54
(1690) (465) (1450) (50) (125) (225) (150) (100)
45.47 11.81 39.37 1.27 3.18 4.45 3.81 2.54
(1790) (465) (1550) (50) (125) (175) (150) (100)
51.82 11.81 45.72 1.27 3.18 3.81 3.81 2.54
(2040) (465) (1800) (50) (125) (150) (150) (100)
59.44 11.81 53.34 1.27 3.18 3.81 3.81 2.54
(2340) (465) (2100) (50) (125) (150) (150) (100)
Note:
• Pad Dia is 1.50(59)

• M is Connector Mounting Free Hole Diameter -2.40(94)
275
No. of
Lib.. No. L W A B/E D G P/C
Pins
ISRO_MD51P/S_ 51 47.63 14.35 40.64 1.27 3.18 3.81 2.54
RA_1600 (1875) (565) (1600) (50) (125) (150) (100)
Note:
• Pad Dia is 1.50(59)

276
PLUG
SOCKET
No. of
Lib.. No. L W A B/E D G P/C
Pins
ISRO_MD100P/S_ 70.60 19.43 63.50 1.27 5.72 3.81 2.54
100
RA_2500 (2780) (765) (2500) (50) (225) (150) (100)
Note:
• Pad Dia is 1.50(59)

• Mounting hole is in-line with pin no-1 in Y direction
277
CONTACT ARRANGEMENT FOR MICRO-D RIGHT ANGLE CONNECTOR
Sr No. No of PINS Lib. No. FOR PLUG Lib. No. FOR SOCKET
1 9 ISRO_MD9P_RA_1150 ISRO_MD9S_RA_1150
Note: MD=Micro Density, RA=Right angle Mounting
278
MICRO-D STRAIGHT PLUG & SOCKET
PLUG
SOCKET
No. of
Lib.. No. L W A B/G E P/C
Pins
35.31 7.82 29.21 1.27 9.53 2.54
(1390) (308) (1150) (50) (375) (100)
35.31 7.82 29.21 1.27 5.72 2.54
(1390) (308) (1150) (50) (225) (100)
42.93 7.82 36.83 1.27 5.72 2.54
(1690) (308) (1450) (50) (225) (100)
44.20 7.82 38.10 1.27 3.81 2.54
(1740) (308) (1500) (50) (150) (100)
51.82 7.82 45.72 1.27 3.81 2.54
(2040) (308) (1800) (50) (150) (100)
59.44 7.82 53.34 1.27 3.81 2.54
(2340) (308) (2100) (50) (150) (100)
Note:
• Pad Dia is 1.50(59)

279
PLUG
No. of
Lib.. No. L W A B E P/C
Pins
57.64 8.92 50.8 1.27 3.81 2.54
(2270) (351) (2000) (50) (150) (100)
Note:
• Pad Dia is 1.50(59)

280
No. of
Lib.. No. L W A B/G E P/C
Pins
ISRO_MD100P/S_ 82.55 11.68 71.12 1.27 3.81 2.54
100
ST_2800 (3250) (460) (2800) (50) (150) (100)
Note:
• Pad Dia is 1.50 (59)

• Hole Dia is 0.80 (31)
281
CONTACT ARRAGEMENT FOR MICRO-D STRAIGHT CONNECTOR
No of
Sr No. Lib. No. FOR PLUG Lib. No. FOR SOCKET
PINS
1 9 ISRO_MD9P_ST_1150 ISRO_MD9S_ST_1150
282
Contributors
Task team:
Thomas John,VSSC
M. M.Vachhani, SAC
G. Jayaprasad, IISU
R. Saravanan, VSSC
M. P. James, ISAC
Co-opted members:
Archana D. Bhatt, SAC
Rangalakshmi, ISAC

ISRO PAX 301 Rev1

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ISRO PAX 301 Rev1

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ISRO-PAX-301

Issue 3, April 2013

Design Requirements for

ISRO Reliability Standards

Directorate of Systems Reliability and Quality, ISRO Headquarters, Bangalore

2 DIMENSIONS AND TOLERANCES FOR LAND PATTERNS 03

6 ELECTRICAL DESIGN FACTORS 27

7 DESIGN OUTPUT GENERATION 36

8 INSPECTION OF PCB LAYOUTS 42

10 Consideration for Generation of Land Pattern Designs 58

11 LAYOUT DESIGN PROCESS CERTIFICATION PLAN 62

12 TERMS AND DEFINITIONS 65

13 CURRENT CARRYING CAPACITY IN PULSED MODE OPERATIONS 71

14 HIGH SPEED PCB DESIGN GUIDELINES 72

15 RIGID FLEX PCB DESIGN GUIDELINES 83

SMD CAPACITORS 111

SMD DIODES 128

SMD INDUCTORS 130

DUAL IN-LINE PACKAGE ICS 139

DUAL FLAT PACK ICS 180

NOMENCLATURE: STANDARD DENSITY FRB CONNECTOR 236

STANDARD DENSITY 90º BENT FRB CONNECTOR 237

STANDARD DENSITY STRAIGHT FRB CONNECTORS 239

NOMENCLATURE OF HIGH DENSITY FRB CONNECTOR 245

HIGH DENSITY 90º BENT FRB CONNECTOR 246

HIGH DENSITY STRAIGHT FRB CONNECTORS 248

NOMENCLATURE OF D-TYPE CONNECTOR 252

STANDARD DENSITY 90º BENT D TYPE PLUG CONNECTOR 253

STANDARD DENSITY 90º BENT D TYPE SOCKET CONNECTOR 255

STANDARD DENSITY STRAIGHT D TYPE SOCKET CONNECTOR 260

HIGH DENSITY 90º BENT D TYPE PLUG CONNECTOR 264

HIGH DENSITY 90º BENT D TYPE SOCKET CONNECTOR 266

HIGH DENSITY STRAIGHT D TYPE PLUG CONNECTOR 269

HIGH DENSITY STRAIGHT D TYPE SOCKET CONNECTOR 271

MICRO-D 90º BENT PLUG & SOCKET 275

MICRO-D STRAIGHT PLUG & SOCKET 279

Figure 2 Schematic symbol for polarized capacitor 09

Figure 3 Recommended conductor routing styles. 19

Figure 4 Orientation of Component identification 23

Figure 5 Surface mount passive leadless device component and footprint 60

Figure 6 Single-ended Transmission Lines 72

Figure 7 Surface Microstrip 73

Figure 8 Coated Microstrip 73

Figure 9 Differential Transmission line 73

Figure 11 Differential traces in Microstrip & Stripline configuration 77

Figure13 Illustrative example of CCGA footprint 86

Figure 14 Illustrative examole of BGA footprint 87

Table 1 Applicable documents 01

Table 2 Symbols used in schematic drawing 11

Table 3 Schematic drawing header 14

Table 4 PCB design process traveler card 14

Table 5 Design Rules for Layout Design 15

Table 6 Buried via pairs 16

Table 7 PCB Layout Data Sheet 21

Table 8 Color of identification marks 22

Table 9 Component identification symbols in the Layout 24

Table 10 Hole and Pad identification requirements 25

Table 11 Current carrying capacity of conductor 27

Table 12 Conductor spacing requirements 28

Table 13 List of components that require additional support 29

Table 14 Types of turrets placement requirements ( in Mils) 30

Table 15 Spacing requirements between turrets & coils/transformers 31

Table 16 Identification codes to be mentioned in component list 33