Thesis - Calibration Techniques For Digitally Assisted Nyquist-Rate ADCs

Research Collection
Doctoral Thesis
Calibration Techniques for Digitally Assisted Nyquist-Rate ADCs
Author(s):
Fateh, Schekeb
Publication Date:
2016
Permanent Link:
https://doi.org/10.3929/ethz-a-010655420
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ETH Library
Calibration Techniques for Digitally Assisted
Nyquist-Rate ADCs
DISS. ETH NO. 23227
Calibration Techniques for

Digitally Assisted
Nyquist-Rate ADCs
A thesis submitted to attain the degree of

DOCTOR OF SCIENCES of ETH ZURICH
(Dr. sc. ETH Zurich)
presented by
SCHEKEB FATEH
MSc ETH EEIT
born on April 23rd, 1983
citizen of Biel/Bienne BE, Switzerland
accepted on the recommendation of
Prof. Dr. Qiuting Huang, examiner

Prof. Dr. Christoph Studer, co-examiner
2016
Dedicated to my family.
“The garden of the world
has no limits,
except in your mind.”
Rumi
Acknowledgements
First of all, I would like to express my gratitude to my advisor,

Prof. Dr. Q. Huang. His continuous support, intelligent guidance,
stimulating discussions, and patience throughout the course of this
challenging research were invaluable to the work presented in this
thesis, and I am very grateful to him for providing an outstanding
research environment at the Integrated Systems Laboratory (IIS).
At the same time, I would like to express my gratitude to my co-
advisor, Prof. Dr. C. Studer, who kindly agreed to act as an external
co-examiner of my dissertation. His interest in my work and his
comments during our discussions led to numerous improvements of
this thesis.
My very special thanks go to Prof. Dr. L. Benini, Prof. Dr. A. Burg,
and Prof. Dr. H. Kaeslin for numerous fruitful discussions.
I owe special thanks to Dr. J. Treichler, P. Schönle, G. Rovere,
M. Safi, M. Rashid, and Dr. T. Burger for proofreading this thesis.
Many thanks also go to my former colleagues at work, in particu-
lar R. Blattmann, Dr. C. Benkeser, Dr. T. Christen, Dr. Y. Chen,
Dr. P. Greisen, C. Keogh, Dr. P. Meinerzhagen, Dr. C. Martelli,
Dr. D. Seethaler, F. Schulthess, Dr. C. Senning, and R. Ulrich.
Special thanks also go to Advanced Circuit Pursuit (ACP) for
prototyping the ASICs being essential for my research. This includes
my colleagues working there, in particular Dr. F. Bürgin, Dr. J. Chen,
Dr. Y. Chen, Dr. T. Dellsperger, Dr. I. Kouchev, D. Riha, Dr. J. Ro-
gin, and Dr. D. Tschopp.
Moreover, I would like to thank the staff members of the IIS and
the Design Zentrum (DZ), namely A. Feigin, C. Wicki, H. Gisler,
F. Kunz, N. Felber, F. Gürkaynak, and B. Muheim, for the excellent
vii
viii ACKNOWLEDGEMENTS
maintenance of the infrastructure. Special thanks also go to M. Lanz

for bonding my ASICs.
Many thanks also go to my present colleagues of the Analog and
Mixed-Signal and the Digital Circuits and Systems Design Groups
for their friendship and support, in particular L. Bettini, S. Belfanti,
P. Bunjaku, X. Han, T. Kleier, H. Kröll, D. Luu, L. Wu, C. Roth,
B. Sporrer, S. Altorfer, B. Weber, D. Bellasi, M. Gautschi, C. Keller,
M. Schaffner, M. Mühlberghuber, P. Vogel, P. Hager, Dr. A. Bar-
tolini, L. Cavigelli, Dr. A. Magno, Dr. A. Marongiu, A. Pullini, and
D. Palossi. I owe special thanks to C. Haller, E. Plank, A. Bakanova,
B. Malesevic, and F. Heitz for the administrative work during my
time at IIS.
Moreover, I would like to thank my colleagues of the Micrel Lab at
the university of Bologna, in particular S. Benatti, F. Casamassima,
Dr. B. Milosovic, M. Tomasini, and Dr. E. Farella.
It is also my pleasure to express my thanks to my colleagues and
friends, specially E. Auger, C. Sidler, N. Häuptli, S. Serov, A. Güzel,
P. Lüthi, J. Biveroni, K. Sartori, J. Ong, D. Juric, A. Di Carlo,
A. Kyburz, W. Liu, A. Barresi, and A. Zuberbühler, for all the support
and unforgettable discussions.
In addition, I would like to express my gratitude to my family
for supporting my studies and encouraging me to pursue this career.
Many thanks to my parents and my siblings for all their help. Special
thanks go also to my family living in the Netherlands for all their sup-
port. In particular, I also owe many thanks to my wife for the support
and motivation along this journey. I would like to dedicate this thesis
to my family for their love, patience, support, and understanding since
they allowed me to spend most of the time on this thesis.
In addition, I would like to express my gratitude to B. Steiger,
E. Füger, C. Amstutz, H. Sahli, C. Koch, and A. Mastantuoni for all
their help and support in my past.
Finally, I appreciate the contributions to my research from the
following students: N. Agianniotis, and C. Zhang. I would like to
express my gratitude also to the students working part-time in the
analog Lab, in particular D. Burri, N. Brun, F. Glaser, and F. Huang.
They allowed me to concentrate on my research while taking over my
other duties at the IIS.
ix
This project has been partially funded by Nano-Tera.ch, which is

financed by the Swiss Confederation and scientifically evaluated by
Swiss National Science Foundation (SNSF).
Zurich, May 23, 2016 Schekeb Fateh

Abstract
In recent years, the energy efficiency of ADCs has been continuously

increasing due to the advances in integrated circuit technologies, cir-
cuit and architecture innovations, novelties in digital calibration, as
well as improved CAD tools. With faster transistors in CMOS, the
trend is to move in particular to higher sampling rates. CMOS is
not only interesting because of the ease of combination of analog and
digital circuits on the same substrate but also because of the extensive
range of intellectual property (IP) available.
As digital circuits fully benefit from the CMOS technology scaling
due to improved transition frequencies of transistors, they are also
less sensitive to noise, supply and process variations, compared to
their analog counterparts. The use of these scaled transistors with
minimum channel length and minimum oxide thickness to implement
analog functions, adversely affects parameters relevant to analog de-
sign. Achieving high linearity, high sampling rate, and high dynamic
range, with low supply voltages and low power dissipation is a major
challenge in designing analog circuits.
The technology scaling benefits of digital circuits are exploited
in the presented ADC implementations in this thesis in order to re-
duce the complexity of ADCs in the analog domain and to enhance
the precision of the converters using digital circuit techniques. For
this reason, different digitally-assisted calibration and correction tech-
niques are analyzed throughout this thesis which improve the energy
efficiency of ADCs compared to the uncalibrated ones and the most
effective ADCs are implemented in CMOS. This thesis focuses on
Nyquist-rate high-speed ADC architectures with emphasis on suc-
cessive approximation register (SAR) and folding ADCs. The SAR
xi
xii ABSTRACT
ADC is more deeply considered due to its amenability to technology

scaling and its relevance to research and industry nowadays using
deep sub-micron technologies available. The folding ADC proves to
be interesting in research due to its fast conversion bandwidth and low
latency nature. However, the different circuit techniques discussed
for both chosen architectures can be adopted to other ADCs as well.
During the course of this thesis, two prototypes of digitally-assisted
SAR ADCs and a folding converter were implemented in a 130 nm
CMOS technology.
Two different prototypes of a 14 bit sub-radix-2 SAR ADC are
presented in a 130 nm CMOS technology employing a redundant seg-
mented capacitor array with merged capacitor switching scheme. An
optimized non-uniform clocking scheme is proposed that reduces the
conversion time by more than 50 % compared to a traditional clocking
scheme. A perturbation-based least-mean square (LMS) start-up cal-
ibration has been implemented directly on-chip to correct capacitor
mismatch and enhance the effective resolution by more than 10 dB.
The first chip prototype achieves 71.1 dB SNDR (11.5 bit) at 2 MS/s
with a power consumption of 0.92 mW. These properties make it suit-
able as an alternative solution to Σ∆ ADCs in cellular systems. The
second prototyped SAR ADC is reconfigurable and achieves an ENOB
of 12.9 bit at a sampling rate of 286 kHz with a FoM of 59 fJ/conv.
Using non-subtractive dither, the achievable ENOB is enhanced to
13.5 bit. In particular for battery-powered biomedical applications,
the resolution and signal bandwidth of the implemented ADC can be
adapted to the needs of the application to avoid power wastage.
Measurement results of the fabricated folding ADC reveals a mea-
sured peak INL of 15.33 LSB which is reduced to 2.34 LSB after cal-
ibration. The peak DNL of 1.76 LSB is reduced to 1.56 LSB, respec-
tively. The ASIC realization spans a silicon-area of 2.86 mm2 and
achieves 9.6 ENOB while running at 150 MHz. A FoM of 2.8 pJ/conv is
achieved in practice which is competitive to other Nyquist-rate ADCs
of similar precision and signal bandwidth coverage published by the
solid-state circuits community.
The measurement results obtained from the prototyped ASICs
show the effectiveness of digital calibration in practical Nyquist-rate
converter implementations.
Zusammenfassung
Die Energieeffizienz von Analog-Digital Wandlern (ADC) hat sich in

den letzten Jahren stetig verbessert aufgrund der Fortschritte der
Fabrikationstechnologien, der Schaltungsinnovationen, der komplexen
Kalibrationstechniken, sowie der verbesserten CAD-Tools. Mit Hilfe
der immer schneller und kleiner werdenden Transistoren, geht der
Trend in ADC Schaltungsentwurf in Richtung höherer Abtastraten.
Die geeignete Technologie, die für die Entwicklung der heutigen Schal-
tungen in Frage kommt, ist CMOS und zwar nicht wegen der einfach
zu platzierenden analogen und digitalen Schaltungen auf dem glei-
chen Siliziumsubstrat, sondern auch deshalb, weil eine umfangreiche
Anzahl von Schaltungen in CMOS mit der Technologie mitgeliefert
werden, die für den Entwurf von komplexen Systemen unerlässlich
sind.
Digitale Schaltungen profitieren vermehrt von der Skalierung der
modernen CMOS Technologien, weil sie weniger empfindlich auf elek-
tronisches Rauschen und Prozessschwankungen reagieren im Vergleich
zu den analogen Schaltungen. Die Verwendung der skalierten Tran-
sistoren für den Entwurf analoger Schaltungen bringt jedoch Her-
ausforderungen mit sich. Die Abnahme der Versorungsspannung der
Transistoren in modernen CMOS Technologien erschwert den Entwurf
hochauflösender ADCs, weil sich der analoge Signaldynamikbereich
proportional mit der Versorgungsspannung reduziert. Somit ist das
Signal-zu-Rausch Verhältnis (SNR) des Wandlers durch die Versor-
gungsspannung limitiert. Die Skalierung der CMOS Technologie kann
aber auch für den Entwurf analoger Schaltungen von Nutzen sein, vor-
allem wenn sie digital kalibriert werden. Die digitale Kalibrationslogik
xiii
xiv ZUSAMMENFASSUNG
kann in skalierten Technologien sehr effizient implementiert werden.

In dieser Arbeit wird die Wichtigkeit der digitalen Kalibrationsschal-
tungen hervorgehoben, die mit der Korrektur des Wandlers ebenfalls
dessen Energieeffizienz verbessern. Vorallem wird der Schwerpunkt der
Arbeit auf die sogenannte SAR und Folding Wandler Architekturen
gelegt. Der SAR ADC profitiert nicht nur von den beschleunigten
digitalen Schaltungen, sondern auch von der Skalierung der Transis-
toren in analogen Schaltungen und geniesst deshalb viel Ansehen in
der Forschung und der Industrie. Der Folding basierter Wandler ist
ebenfalls von grosser Interesse für die Forschung, weil damit grosse
Abtastraten bei geringer Verarbeitungslatenz erreicht werden. In die-
ser Arbeit werden verschiedene Wandlerimplementierungen in 130 nm
CMOS Technologien diskutiert.
Die Umsetzung zweier Prototypen eines redundanten 14 bit SAR
ADCs wird gezeigt. Ein innovatives Taktschema wurde für den ADC
entworfen, damit die Zeit für die analog-digital Wandlung um mehr als
50 % verkürzt wird. Eine auf LMS basierte Kalibrationsmethode wird
auf dem selben Chip implementiert, um die Fabrikationsungenauig-
keiten digital zu korrigieren. Durch die Kalibration wird eine Verbes-
serung der effektiven Auflösung um mehr als 10 dB erreicht. Der erste
fabrizierte SAR ADC Prototyp erreicht 71.1 dB SNDR (11.5 bit) bei
2 MS/s und verbraucht dabei eine Leistung von 0.92 mW. Der Wandler
ist ein geeigneter Kandidat für den Einsatz in Mobilfunksysteme.
Der zweite Prototyp ist rekonfigurierbar und erreicht eine effektive
Auflösung von 12.9 bit bei einer Abtastrate von 286 kHz mit einem
FoM von 59 fJ/conv. Durch Dithering wird die effektive Auflösung auf
13.5 bit erhöht. Dieser Wandler ist für batteriebetriebene und biomedi-
zinische Anwendungen gedacht, wobei die Auflösung und Signalband-
breite des Wandlers während der Laufzeit einer Anwendung angepasst
werden können, um unnötigen Leistungsverbrauch zu reduzieren.
Der Folding Wandler erreicht 9.6 ENOB, wobei der ADC bei einer
Taktrate von 150 MHz optimal operiert. Der Chip braucht 2.8 pJ/conv
und liefert ähnliche Präzision und Bandbreite wie andere kürzlich
publizierte Wandler, aber mit einem weniger komplexen Schaltungs-
aufbau.
Die Messergebnisse der Prototypen in dieser Arbeit zeigen die
Effektivität der digitalen Kalibration in praktischen Wandler Imple-
mentierungen.
Contents
Acknowledgements vii
Abstract xi
Zusammenfassung xiii
1 Introduction 1
1.1 ADC characterization . . . . . . . . . . . . . . . . . . 3
1.1.1 Transfer characteristic of ADCs . . . . . . . . . 3
1.1.2 Static characterization of ADCs . . . . . . . . . 5
1.1.3 Dynamic characterization of ADCs . . . . . . . 7
1.1.4 Figure-of-merit (FoM) . . . . . . . . . . . . . . 8
1.2 Background . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.1 Typical fields of application . . . . . . . . . . . 10
1.2.2 Analog-to-digital conversion . . . . . . . . . . . 11
1.2.3 Amplitude quantization limitations . . . . . . . 12
1.2.4 Time quantization limitations in ADCs . . . . 14
1.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3.1 Research focus . . . . . . . . . . . . . . . . . . 17
1.4 Thesis goals . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5 Chapter organization . . . . . . . . . . . . . . . . . . . 20
2 Nyquist-Rate ADC Architectures 23

2.1 Nyquist criterion . . . . . . . . . . . . . . . . . . . . . 24
2.2 Classification of Nyquist-rate ADCs . . . . . . . . . . 24
2.3 Single-reference ADC architectures . . . . . . . . . . . 25
xv
xvi CONTENTS
2.3.1 Successive-approximation register ADC . . . . 27

2.3.2 Algorithmic ADC . . . . . . . . . . . . . . . . . 30
2.3.3 Pipeline ADC . . . . . . . . . . . . . . . . . . . 31
2.4 Multi-reference ADC architectures . . . . . . . . . . . 32
2.4.1 Flash ADC . . . . . . . . . . . . . . . . . . . . 32
2.4.2 Interpolating flash ADC . . . . . . . . . . . . . 34
2.4.3 Folding ADC . . . . . . . . . . . . . . . . . . . 37
2.4.4 Two-step ADC . . . . . . . . . . . . . . . . . . 43
2.4.5 Subranging ADC . . . . . . . . . . . . . . . . . 43
2.5 High-bandwidth Nyquist-rate ADCs . . . . . . . . . . 45
3 Implications of Static Error Sources on Nyquist-Rate

ADCs 47
3.1 Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.1.1 Random mismatch . . . . . . . . . . . . . . . . 48
3.1.2 Systematic mismatch . . . . . . . . . . . . . . . 50
3.2 Performance metrics . . . . . . . . . . . . . . . . . . . 51
3.3 Impact of mismatch on the reference generation circuit 51
3.3.1 Mismatch in a reference ladder . . . . . . . . . 52
3.3.2 INL errors in non-ideal resistive ladders . . . . 53
3.3.3 DNL errors in resistive ladders . . . . . . . . . 54
3.4 Impact of capacitor mismatch on SAR ADCs . . . . . 55
3.4.1 INL errors in SAR ADCs . . . . . . . . . . . . 57
3.4.2 DNL errors in SAR ADCs . . . . . . . . . . . . 58
3.5 Impact of mismatch on flash ADCs . . . . . . . . . . . 58
3.5.1 Offset in differential pairs . . . . . . . . . . . . 59
3.5.2 INL errors in flash ADCs . . . . . . . . . . . . 60
3.5.3 DNL errors in flash ADCs . . . . . . . . . . . . 61
3.6 Generalized quantizers . . . . . . . . . . . . . . . . . . 62
3.6.1 Process of ideal quantization . . . . . . . . . . 62
3.6.2 Process of non-ideal quantization . . . . . . . . 64
3.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . 66
4 Digital Calibration and Post-Correction 67

4.1 Relevance of digital calibration techniques in ADCs . . 68
4.2 LUT based post-correction . . . . . . . . . . . . . . . . 69
4.2.1 Operation principles . . . . . . . . . . . . . . . 69
4.2.2 Addressing function . . . . . . . . . . . . . . . 71
CONTENTS xvii
4.2.3 Estimation function . . . . . . . . . . . . . . . 73

4.3 Redundancy . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3.1 Redundancy in beta-expansion . . . . . . . . . 75
4.3.2 Beta-expansion in SAR ADCs . . . . . . . . . . 77
4.4 Digital self-trimming circuits . . . . . . . . . . . . . . 78
4.4.1 Working principle . . . . . . . . . . . . . . . . 80
4.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . 81
5 A 14 bit SAR ADC with On-Chip Digital Calibration 83

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 83
5.2 Architecture of Prototype I . . . . . . . . . . . . . . . 85
5.2.1 Capacitor array . . . . . . . . . . . . . . . . . . 85
5.2.2 Unity capacitor Cu . . . . . . . . . . . . . . . . 87
5.2.3 Flexible clocking scheme . . . . . . . . . . . . . 88
5.2.4 Comparator design . . . . . . . . . . . . . . . . 89
5.3 Architecture of Prototype II . . . . . . . . . . . . . . . 90
5.3.1 Noise reduction techniques . . . . . . . . . . . 92
5.3.2 Flexible capacitor array . . . . . . . . . . . . . 93
5.3.3 Reconfigurable clocking scheme . . . . . . . . . 94
5.4 Digital calibration and post-correction . . . . . . . . . 96
5.4.1 Perturbation injection . . . . . . . . . . . . . . 96
5.4.2 Calibration algorithm . . . . . . . . . . . . . . 98
5.5 Measurement results of Prototype I . . . . . . . . . . . 100
5.6 Measurement results of Prototype II . . . . . . . . . . 102
5.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . 109
6 A 150-MS/s 11-bit Folding ADC with 9.6 ENOB 111

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 111
6.2 Folding ADC architecture . . . . . . . . . . . . . . . . 113
6.3 Integration of the analog core . . . . . . . . . . . . . . 114
6.3.1 Track-and-hold (T/H) circuit . . . . . . . . . . 114
6.3.2 Pre-amplification stage . . . . . . . . . . . . . . 118
6.3.3 Reference generation circuit . . . . . . . . . . . 120
6.3.4 Cascaded folding and interpolation technique . 121
6.3.5 Comparators . . . . . . . . . . . . . . . . . . . 124
6.3.6 Calibration DAC . . . . . . . . . . . . . . . . . 125
6.4 Digital core . . . . . . . . . . . . . . . . . . . . . . . . 128
6.4.1 Bubble error correction circuit . . . . . . . . . 128
xviii CONTENTS
6.4.2 Encoder logic . . . . . . . . . . . . . . . . . . . 128

6.4.3 Digital calibration and post-correction . . . . . 130
6.5 Measurement results . . . . . . . . . . . . . . . . . . . 132
6.6 Conclusion and outlook . . . . . . . . . . . . . . . . . 135
6.6.1 Conclusion . . . . . . . . . . . . . . . . . . . . 135
6.6.2 Outlook . . . . . . . . . . . . . . . . . . . . . . 136
7 Summary, Conclusion, and Outlook 139

7.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . 141
7.3 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . 142
A Power Contributors in SAR ADCs 145

A.1 Performance metrics . . . . . . . . . . . . . . . . . . . 146
A.2 Dynamic comparator . . . . . . . . . . . . . . . . . . . 147
A.3 Digital logic of the SAR ADC . . . . . . . . . . . . . . 148
A.4 Reference buffer . . . . . . . . . . . . . . . . . . . . . . 149
A.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . 155
B Impact of Mismatch on MOS Differential Pairs 157

B.1 Input-referred offset voltage Vos . . . . . . . . . . . . . 157
B.2 Variance of the input-referred offset voltage Vos . . . . 160
C Mismatched Channels in Time-Interleaved ADCs 161
D Non-Ideal Quantizers 163

D.1 Impact of DNL errors on SNR in non-ideal quantizers 163
D.2 Impact of INL errors in quantizers . . . . . . . . . . . 165
E Notation and Acronyms 167

Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Bibliography 171
Curriculum Vitae 191

Chapter 1
Introduction
The demand for high-speed and high-resolution Nyquist-rate analog-

to-digital converters (ADCs) has increased in recent years, driven
by the analog-to-digital conversion specifications for wireless com-
munication devices. Modern wireless standards such as the IEEE
802.11ac and the 3GPP LTE-A [1, 2] require energy-efficient analog-
to-digital conversion techniques to meet the demands of data rates
up to 100 MS/s and effective resolutions of around 12 bit. Similarly,
future wireline communication and broadcasting systems extend their
signal constellations (up to 4K-QAM) to increase data throughput [3,
4], such as in case of 10 – 100 Gb/s Ethernet, next-generation cable
modem, and ultra-high definition TV (UHDTV) standards. All these
communication applications demand for medium-resolution, low-cost,
low-power, and high-bandwidth integrated circuits (ICs) [5, 6].
ADCs build the interface between the analog and digital domains
and are critical components in communication devices since their con-
version linearity and noise performance affect the overall performance
of the underlying systems. In recent years, the energy efficiency of
ADCs has been continuously increased [7, 8] due to the advances
in integrated circuit technologies, circuit and architecture innova-
tions, novelties in digital calibration, as well as improved computer-
aided design (CAD) tools. With faster transistors the trend is to
move in particular to higher sampling rates which allows every new
generation of communication devices to achieve higher data rates
1
2 CHAPTER 1. INTRODUCTION
and more functionality on the same chip area for better quality-of-
service. To manage the increasing complexity of these communication
application-specific integrated circuits (ASICs), system-on-chip (SoC)
design concepts providing integrated solutions are highly suited there-
fore [9]. The most appropriate technology for the design of SoCs is
complementary metal-oxide semiconductor (CMOS) not only because
of the ease of combination of radio frequency (RF), analog, and digital
circuits on the same substrate but also because the extensive range of
intellectual property (IP) available.
As digital circuits fully benefit from the CMOS technology scaling
due to enhanced transition frequencies of transistors, they are also less
sensitive to noise, supply, and process variations, compared to their
analog counterparts [10]. The use of these scaled transistors with
minimum channel length and minimum oxide thickness to implement
analog functions, adversely affects parameters relevant to analog de-
sign. Achieving high linearity, high sampling rate, and high dynamic
range, with low supply voltages and low power dissipation is a major
analog design challenge.
This thesis focuses on Nyquist-rate high-speed ADC architectures
used in communication systems or applications with similar require-
ments with emphasis on successive approximation register (SAR) and
folding ADCs. The SAR ADC is more deeply considered in this
thesis due to its amenability to technology scaling, and accordingly
its relevance to research and industry nowadays using the deep sub-
micron CMOS technologies available. The folding ADC proves to
be interesting for industrial applications due to its fast conversion
bandwidth and low latency nature.
The technology scaling benefits of digital circuits are exploited in
the presented ADC implementations in this thesis in order to reduce
their complexity in the analog domain and enhance their precision
using digital circuits. For this reason, different digitally assisted cal-
ibration and correction techniques are analyzed which improve the
energy efficiency of ADCs and the most effective ones are implemented
in CMOS.
This chapter starts with the introduction of the key performance
metrics describing the process of analog-to-digital conversion. In order
to characterize ADCs thoroughly, a number of terms commonly used
to describe their performance are defined to establish a consistent and
1.1. ADC CHARACTERIZATION 3
relevant set of metrics for this thesis. For a more comprehensive set
of definitions, the reader is referred to [11]. The research motivation
is discussed followed by the thesis goals. The chapter ends with the
organization of the thesis.
1.1 ADC characterization

In the literature [7, 12–14], there are two different methods for char-
acterizing the ADC performance, i.e., static and dynamic charac-
terizations. Static characterizations are expressed in terms of in-
tegral nonlinearity (INL) and differential nonlinearity (DNL). They
both analyze the DC or low-frequency behavior of the ADC. AC or
high-frequency characteristics of the ADC, e.g., bandwidth limitations
and electronic noise, are considered in the dynamic measures. In
the dynamic characteristics, the (low-frequency) static errors are also
included.
The IEEE standard 1241 on the terminology and test methods for
ADCs [11] provides a consistent set of definitions and test methods
for ADCs. All measurements done in the course of this thesis are
compliant to the ones described in the IEEE standard 1241. Before
discussing ADC specific performance metrics, the transfer character-
istic and corresponding definitions are introduced.
1.1.1 Transfer characteristic of ADCs

Fig. 1.1 illustrates a typical transfer characteristic curve of an ideal
3-bit ADC with the corresponding definitions according to [15]. Along
the x-axis, a set of reference voltages mark equidistant code transition
levels where the ideal straight line is quantized in 23 code bins and
mapped accordingly to digital codes along the y-axis denoted as Dout .
Code transition level

The analog input at which the transition between two digital output
codes takes place is defined as code transition level
Tl ∀ l ∈ 0, . . . , 2Nres − 1,
D out ideal straight

line
111
110
code transition
101 level T2
100
011
010
midcode code bin
001
bin value TM,3 width W7
000 Vin
V0 V1 V2 V V4 V5 V6 V7 V8
3
V FS
Figure 1.1: Typical transfer characteristic curve of an ideal 3-bit ADC.
as depicted in Fig. 1.1. To target a resolution of Nres bit, 2Nres equidis-

tant code transition levels are necessary.
Code bin width
The difference between two code transition levels determines the ana-
log voltage range which is mapped to a digital output code and is
referred to as the code bin width
Wl = Tl+1 − Tl ∀ l ∈ 0, . . . , 2Nres − 1,
as depicted in Fig. 1.1. In an ideal ADC, all code bin widths are
equally sized.
Least significant bit (LSB)

The voltage VLSB is the analog equivalent of the least-significant bit
(LSB) and determines the nominal code bin width. It can be calcu-
lated using the full-scale signal range VFS according to
VFS
VLSB = .
2Nres
Midcode bin value

The analog input value
Tl−1 + Tl
TM,l = ∀ l ∈ 0, . . . , 2Nres − 1,
2
determining the center of the code bin width is denoted as midcode
bin value. The ideal midcode bin value TI,l lies on the (ideal) straight
line (with no distortions) as illustrated in Fig. 1.1.
1.1.2 Static characterization of ADCs

The DNL and INL definitions of an ADC described in this section
illustrate the static characterization of ADCs. Offset and gain error
of the transfer characteristic curve of the ADC are also static charac-
terizations. Their definitions are omitted here as they do not mainly
limit the performance of ADCs; further details can be found in [7].
Differential nonlinearity (DNL)

Fig. 1.2 illustrates the definition of DNL on a sample transfer char-
acteristic curve including static errors. DNL is the difference between
the actual and the nominal code bin width VLSB as
Tl+1 − Tl
DNLl = −1 ∀ l ∈ 0, . . . , 2Nres − 1. (1.1)
VLSB
An error |DNLl | < 1 VLSB guarantees a monotonic transfer function

and no missing codes will appear at the output of the converter, i.e.,
if the input voltage is swept over its dynamic range, all digital output
D out
ideal INL4 = -VLSB/4
111 non-ideal
110
101
100
011 DNL4 = VLSB/2
010 DNL3 = -VLSB/2
001 DNL2 = 0
000 Vin
V0 V1 V2 V V4 V5 V6 V7 V8
3
Figure 1.2: Transfer characteristic curve of a 3-bit ADC with static

errors: differential nonlinearity (DNL) and integral nonlinearity (INL)
resulting from the decision level errors are labeled accordingly.
code combinations will appear at the output of the ADC. Monotonic-

ity is a necessary condition to make the transfer characteristic of an
ADC correctable. An error DNLl = 0, ∀l, typically belongs to an ideal
ADC.
Integral nonlinearity (INL)
INL is the deviation in the LSB of the actual transfer characteristic

curve from an ideal one. The INL of a non-ideal transfer characteristic
curve is illustrated in Fig. 1.2. A mathematical definition of INL
follows as:
l−1
TM,l − TI,l X
INLl = = DNLi , (1.2)
VLSB i=1
where TI,l is the ideal and TM,l the measured midcode bin value of an
ADC.
ADCs are usually specified by their maximum DNL and INL [16]
according to
DNLmax = max DNLl

l∈0,...,2Nres −1
INLmax = max INLl .

l∈0,...,2Nres −1
1.1.3 Dynamic characterization of ADCs

The dynamic characterization of an ADC is performed by measuring
the ADC with a sinusoidal input (with average signal power Psignal ).
Mathematically, the sine wave has a single power spectral component.
At the output of the ADC, non-idealities of the converter (noise and
distortion) can be measured. The average noise power is denoted as
Pnoise distributed over the Nyquist signal bandwidth while the average
power spectral components characterizing the harmonic distortion are
represented by the vector Pdist with M entries. Only a set of M
harmonic components with a significant portion of harmonic distor-
tion energy1 is considered in the following computations of the met-
rics signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR),
signal-to-noise-and-distortion ratio (SNDR), effective number of bits
(ENOB), total-harmonic-distortion ratio (THD), and figure-of-merit
(FoM) which will be explained here with more details.
Signal-to-noise ratio (SNR)
The SNR is the ratio between the average signal power Psignal and the
average noise power Pnoise , excluding harmonic distortions:

Psignal
SNR = 10 log10 . (1.3)
Pnoise
1 Unless specified otherwise, the set is composed of the strongest nine harmonics
M = 9 [11].
Spurious-free dynamic range (SFDR)

The SFDR is the ratio between the average signal power Psignal and
the strongest from the distortion components Pdist of the ADC:
 
Psignal
SFDR = 10 log10  . (1.4)
max (Pdist,i )
i∈1,...,M
Signal-to-noise-and-distortion ratio (SNDR)

The SNDR is the ratio between the average signal power Psignal and
the sum of all noise and harmonic distortion components:
!
Psignal
SNDR = 10 log10 PM . (1.5)
Pnoise + i=0 Pdist,i
Effective number of bits (ENOB)

The ENOB indicates the number of bits that are effectively resolved
by an ADC with the measured SNDR and can be approximated as:
SNDR − 1.76 dB
ENOB ≈ . (1.6)
6.02 dB
For the derivation of (1.6) see [7].
Total harmonic distortion (THD)

The THD is the ratio between the sum of all harmonic distortion
components’ power and the average signal power.
PM !
i=0 Pdist,i
THD = 10 log10 . (1.7)
Psignal
1.1.4 Figure-of-merit (FoM)

There exist different definitions for the FoM of an ADC. Throughout
this thesis, the following most common definition of the FoM is used:
P
FoM = , (1.8)
2ENOB · 2fNyquist
2
10
1
10
0
10
FoM [pJ/conv]
−1
10
−2
10
Pipeline
SAR
10
−3 Two−Step
Subranging
Flash
−4 Folding
10
500 350 250 180 130 90 65 40 28
technology generation [nm]
Figure 1.3: FoM versus technology of Nyquist-rate ADCs implemented

in CMOS technology and published at ISSCC from 2000 to 2014 [17].
The dashed line shows the impact of the supply voltage reduction with
the CMOS technology scaling on the FoM.
where P is the power dissipated in the ADC which covers the Nyquist
band fNyquist . Not the nominal resolution but instead the ENOB is
considered in the calculation of the FoM. The FoM has the dimension
of energy per sample conversion [J/conv.]. An efficient ADC design
aims to minimize the FoM. Solely relying on the FoM to compare the
performance of different ADCs requires caution. There is no common
definition of how the power dissipation P of an ADC is measured in
practice, and there is a particularly low consensus on where to draw
the line between the ADC core and auxiliary circuits. This makes
the comparison between different ADC architectures using the FoM
challenging.
A semi-logarithmic plot with an overview on Nyquist-rate con-
verters published in ISSCC proceedings since the year 2000 is shown
in Fig. 1.3, where ADC implementations in various CMOS technolo-

gies are plotted against the FoM. This illustration exhibits a trend
in decreasing energy per sample conversion versus more advanced
technologies. The trend of FoM reduction does not only depend on
decreasing the supply voltage, but also on reducing the parasitics of
CMOS technologies per se and new innovations in circuit design [7].
Especially high effort is made in the research of SAR ADCs, where
almost no static current consumption is required within typical CMOS
realizations (if excluding the power consumption of input and ref-
erence buffers). These ADCs also make perfect use of technology
scaling [18–21] where the digital power consumption is reduced and
operating speed is enhanced.
The ADC designs presented throughout this thesis are optimized
to minimize the FoM. In particular, correcting the ENOB of converters
digitally helps to reduce the FoM. Pipelining techniques for accelera-
tion of digital circuits combined with intelligent clock gating [10] are
essential to achieve efficient implementation of calibration and cor-
rection circuits. For these reasons, digital calibration and correction
circuits for medium- to high-resolution ADCs can be implemented
efficiently compared to to their analog counterparts and do not limit
the Nyquist band of the underlying converter.
1.2 Background
1.2.1 Typical fields of application
ADCs in wireless communications
Analog-to-digital conversion in RF transceivers impose special con-
straints on ADCs, especially in the design of advanced software-defined
multi-standard receivers. The linearity and SNR of the sampled signal
by the ADC plays a crucial role in determining the quality of the
digital baseband signal, such as the bit error rate [22]. One of the
main devices in the signal chain of a software-defined RF receiver
which limits the receiver performance, is the ADC. Calibration of
static errors in the ADC of these receivers is a must to fulfill the
requirements dictated by these multi-standard transceivers which re-
quire the integration of a highly complex communication modem to
1.2. BACKGROUND 11
analog digital
Vin (t) Dout [kTs]

ADC
Nres
Figure 1.4: Overview of the analog-to-digital conversion process.
achieve higher data rates with improved quality-of-service, low power

dissipation, and lower cost per chip. In order to minimize power
consumption, certain Nyquist-rate converters are preferable to be used
in wireless communications, such as Σ∆ or SAR ADCs.
ADCs in multi-channel biomedical devices
Efficiently operating multi-channel biomedical devices share a single

ADC between their channels in a time-interleaved manner in order
to reduce power and silicon area. An analog multiplexer drives the
input of the ADC. In order to design a flexible ADC for multi-channel
biomedical devices, not only a high data rate is favorable to maximize
the number of multiplexed analog channels but also a one-to-one map-
ping between its analog input and digital output (memoryless transfer
characteristic as it is the case for Nyquist-rate ADCs) to associate each
sample unambiguously to the correspondent channel. For this reason,
Nyquist-rate ADCs are the favorable converter architectures for the
design of multi-channel biomedical devices. ADCs with memory, e.g.,
Σ∆ based converters due to integration, have to properly settle after
switching the input channel. Typically, this costs some extra samples
and makes these memory-based architectures inefficient to be used in
multi-channel biomedical devices.
1.2.2 Analog-to-digital conversion

ADCs represent the interface between the analog and digital domains
as shown in Fig. 1.4. The converter has a real-valued input signal
Vin (t) (within a predefined voltage range) which is continuous in time
4
supply voltage [V]
0
1000 700 500 350 250 180 130 90 65 45 32 22 14
technology generation [nm]
Figure 1.5: The reduction tendency of the supply voltage in depen-

dence of mainstream sub-micron CMOS technology nodes [23].
and amplitude. The analog-to-digital conversion step performs quan-

tization in time and amplitude. The analog input signal Vin (t) is
sampled with a sampling frequency of fs Hz. For every time instant
kTs , where Ts = 1/fs is the sampling period and k the sample index,
the analog input is resolved in a time-discrete output Dout [kTs ] from a
finite quantization alphabet of the dimension 2Nres . The digital output
Dout [kTs ] ∈ {0, 1}Nres is a vector with entries Dout [kTs ] ∈ {0, 1} and
dimension Nres .
In practice, both the sampling and amplitude quantization pro-
cesses experience physical limitations as discussed in the following.
1.2.3 Amplitude quantization limitations

Advanced CMOS technologies offer relatively small and fast transis-
tors to build complex mixed-signal SoCs. These deep sub-micron
transistors with reduced supply voltage (compared to prior technology
generations) are the preferred switching devices when building low-
cost and low-power digital signal processors. The reduction trend of
the supply voltage in dependence of the mainstream CMOS technolo-
gies2 is shown in Fig. 1.5.
2 According to the technology trend targets 2013 of semiconductor industry
association (SIA) [23], a 14-nm transistor has a minimum supply voltage of only
0.86 V.
1.2. BACKGROUND 13
The reduced supply voltage in modern sub-micron CMOS tech-

nologies reduces the analog signal swing and potentially the available
SNR in analog circuits. Moreover, the ratio between the average power
of the analog signal and the noise generated in active and passive
analog circuit components limits among others the precision of the
analog system. As a common sense, the realization of high SNR ADCs
in advanced CMOS technologies is challenging due to the fact that the
supply voltage is continuously reduced with each scaled technology
node.
The SNR (see also (1.3)) of a sinusoidal signal in a simple analog
sampling system as shown in Fig. 1.6 is given by
1 VFS 2

average signal power 2
VDD
SNR = = 2 2
< ,
average noise power kB T /Cs 8kB T /Cs
where kB denotes the Boltzmann constant, T is the temperature of

the system expressed in Kelvin, Cs is the sampling capacitance, and
VFS < VDD is the full-scale signal range. The circuit samples an analog
signal Vin (t) and stores the result in a storing element until the next
sampling instant. This operation is periodic and rather performed on
voltages than currents. Storing a voltage on a capacitor is easier in
practice than a current in an inductor [7].
A reduced supply voltage VDD requires a larger sampling capac-
itance Cs in order to maintain the same SNR value for the desired
accuracy in the illustrated sampling system in Fig. 1.6. This, how-
ever, leads to a decrease of the desired sampling bandwidth which is
determined by the cut-off frequency of the time quantizer as
1
fc = ,
2πRCs
where R is the on-resistance of the sampling switch S1 in Fig. 1.6.

A certain settling time Ts is required for the sampling capacitor Cs
to be loaded with sufficient precision. The settling error of the charge
for the sampling capacitor is defined to be

t
ss = exp − ∀t ∈ {0, Ts }, (1.9)
RCs
time quantization amplitude quantization
kTs+e
Dout(kTs )
encoder
S1
Vin(t) ~ sampler
Cs quantizer
analog-to-digital converter
Figure 1.6: Time and amplitude quantization processes in an ADC.

For a given bandwidth ∆f a noise power of 4kB T ∆f is dissipated in
the on-resistance R of switch S1 and the input Vin is sampled at the
time instant kTs + e with the sampling uncertainty described by the
variable e. Amplitude quantization is only performed in the quantizer.
where the settling error ss is maximum at t = 0 and requires a certain

settling time Ts to achieve the desired precision. The settling error ss
reduces, the larger the settling time Ts gets. As can be seen from (1.9),
a larger sampling capacitor Cs needs more settling time Ts in order to
achieve the same precision.
1.2.4 Time quantization limitations in ADCs

A semi-logarithmic overview plot of Nyquist-rate ADCs recently pub-
lished at ISSCC is illustrated in Fig. 1.7 where the ENOB is plotted
versus the Nyquist bandwidth. This illustration shows a trade-off
between bandwidth and resolution. It can be seen from this illus-
tration, that certain ADC architectures are meant to maximize the
Nyquist bandwidth (see Sec. 2.4 for more details), e.g., flash or folding,
while others are designed to target higher resolutions (see Sec. 2.3).
This medium- to high-resolution category includes SAR and pipeline
ADCs.
The aperture jitter is the sample-to-sample variation of the sam-
pling clock. It imposes an upper limitation in the bandwidth-resolution
trade-off. Fig. 1.6 illustrates the source of aperture jitter. Consider a
sine wave Vin (t) = A sin (2πfin t) that is sampled at the time instant
1.3. MOTIVATION 15
t = kTs + e for k ∈ Z and assume that the variable e is a random

process uncorrelated with Vin (t). The term Ts = 1/fs denotes the
sampling period. The root mean square (RMS) value of e is denoted
as erms . The SNR is limited by the variable erms according to
SNR = −20 log (2πfin erms ) . (1.10)
The derivation of (1.10) can be found in [24]. As shown in Fig. 1.7, the
aperture jitter sets an upper limit to the resolution of high-bandwidth
ADCs. In practice, this limitation in converters is known as the
bandwidth-resolution trade-off.
An aperture jitter of 0.5 ps rms3 (marked as a red dashed line
in Fig. 1.7) caused by noise of the sampling clock (see Fig. 1.6) limits
the overall SNR of the ADC.
1.3 Motivation
Achieving the optimal trade-off between sampling rate and resolution
for a given ADC architecture represents the key design problem for
practical implementations in advanced CMOS technologies. An ab-
straction of the bandwidth-resolution trade-off is depicted in Fig. 1.8,
where static and dynamic performance limiters and challenges are
illustrated separately. The diagrams show the performance limitations
of ADCs in both extreme edges of the Nyquist bandwidth. The static
performance of an ADC provides an understanding of the converter
behavior for a DC or a low-frequency input signal. The AC or dy-
namic performance of the ADC is essential in order to understand the
characteristics of the converter for high-frequency input signals (close
to the Nyquist frequency).
The static performance, as shown in Fig. 1.8 a), is primarily lim-
ited by the settling error of switched-capacitor (SC) based analog
circuits. The more settling time is available the better the effective
resolution becomes [25]. The settling behavior in SC circuits rep-
resents a bandwidth-resolution trade-off. Analog as well as digital
circuits benefit from scaled transistors and continuously decreasing
3 A clock jitter of 0.5 ps rms is assumed in the illustration Fig. 1.7 because
there are VCOs available on the market with similar jitter performance, e.g.,
CDCE62002 from TI.
2
10
Pipeline
SAR
1
10 Two−Step
Subranging
0 Flash
10
Folding
Jitter = 0.5 ps rms
Nyquist bandwidth [GHz]
−1
10
−2
10
−3
10
−4
10
−5
10
−6
10
2 4 6 8 10 12 14
effective number of bits (ENOB)
Figure 1.7: ENOB versus bandwidth of Nyquist-rate ADCs imple-

mented in CMOS technology published at ISSCC from 2000 to 2014
[17]. The dashed line marks an aperture jitter of 0.5 ps.
parasitic capacitance in terms of settling and operating bandwidth.

CMOS scaling does not only accelerate circuits but also show an
improved mismatch behavior in practice. The resolution of analog
circuits is enhanced due to improved mismatch in deep sub-micron
technologies (see Sec. 3.1). Novel analog-to-digital conversion tech-
niques increasingly use the advantages of digital signal processing for
energy-efficient operation. Thus in practice, these ADCs are known to
be digitally calibrated and corrected to compensate for systematic and
random mismatches of transistors. New innovations in calibration and
correction circuits are necessary to substitute the increase in power
consumption that would compensate the accuracy loss while keeping
the operating bandwidth constant. Thus, there are several ways in
practice how the static performance of ADCs is improved.
The dynamic performance of ADCs, as depicted in Fig. 1.8 b),
faces also different challenges in practice. The aperture jitter, as
1.3. MOTIVATION 17
static performance dynamic performance

conversion conversion
bandwidth bandwidth
settling aperture jitter
limitation limitation
CMOS scaling
CMOS scaling
power increase power increase
calibration
resolution resolution
a) b)
Figure 1.8: The bandwidth-resolution trade-off for advanced CMOS

technologies’ a) static and b) dynamic performance.
already discussed in Sec. 1.2.4, builds a bandwidth-resolution trade-off

for the dynamic performance of analog circuits. Apart from that,
innovations in analog signal processing techniques are essential to
ensure robustness against electronic noise (which is the main perfor-
mance limiter of precise analog circuits) and other undesired dynamic
interferences for targeting medium to high resolutions. In certain
cases, an increase of power consumption helps to suppress electronic
noise, e.g., when using operational amplifiers.
CMOS scaling improves the conversion bandwidth of ADCs while
scaling of the supply voltage reduces the analog signal swing and
accordingly the SNR (see Sec. 1.2.3). For this reason, scaling of
transistors has a negative impact on the dynamic performance of high
precision ADCs.
The design of medium- to high-resolution ADCs is challenging in
deep sub-micron CMOS and interesting for research. Therefore, one
main focus of this thesis is to study the design of robust and efficient
ADCs implemented in deep sub-micron CMOS.
1.3.1 Research focus

The main research in this thesis focuses on Nyquist-rate ADCs with
dedicated on-chip calibration circuitry to compensate for static errors
control feedback
Vin (t) Draw [kTs] digital

Dout [(k+d)Ts]
ADC core
Nint signal processing Nres
ADC chip
Figure 1.9: System overview of a digitally assisted Nyquist-rate ADC.
and thus, to improve their overall circuit performance and to reduce

their silicon area. Special effort is made on digital post-correction
techniques where the term post-correction indicates that digital cor-
rection is performed on an already converted signal.
The system overview of the implemented ADC architectures is
shown in Fig. 1.9. The input of the realized ADC chip is defined
to be analog and time continuous which is denoted as Vin (t). The
resolved raw data at the output of the ADC (which is defined to
be Draw [kTs ]) is sampled at time-instants kTs for all k ∈ Z. The
raw data experiences distortions which are primarily of static nature
and need to be corrected digitally. For this reason, a digital signal
processing block with a delay of d ≥ 0 conversion cycles is provided on-
chip to control the calibration processes interacting with the normal
conversion mode of the ADC core in order to run post-correction
algorithms. A control feedback path is provided from the digital signal
processing block to the ADC core to guide the analog circuit properly
during the calibration mode. The corrected ADC output is defined to
be Dout [kTs ]. The internal resolution of the ADC Nint can be larger or
equal to the nominal resolution Nres of the ADC to create redundancy
and simplify the requirements on the correction circuitry.
The analog-to-digital conversion algorithm runs in the ADC core.
Conceptually the simplest conversion algorithm is performed in the
flash ADC [7]. Flash ADCs achieve high conversion rates due to
their fully parallel architecture (see Sec. 2.4.1). The disadvantage
of these converter types is the exponential growth of power con-
sumption and sampling capacitance with the increase in resolution.
1.4. THESIS GOALS 19
In order to overcome these shortcomings, folding and interpolating

circuit techniques are used to reduce the number of comparators and
lower the sampling capacitance (see Sec. 2.4.3). Folding and inter-
polating ADCs employ a parallel architecture consisting of open-loop
folding amplifiers, which is a prerequisite for fast conversion, since
the high-bandwidth benefits of modern CMOS technologies can be
optimally exploited [26]. A drawback of this architecture is its limited
accuracy due to its non-linear behavior, which is directly related
to the matching characteristics of transistors. Averaging, which is
a promising approach to alleviate the matching requirements and
digitally assisted calibration techniques can be applied to compensate
for non-linearity errors [27, 28].
Another candidate of conversion algorithm which can easily achieve
high conversion bandwidths is the pipeline ADC (see Sec. 2.3.3). Also
this ADC needs to be calibrated in practice to target a medium
resolution.
As seen in Fig. 1.7, SAR ADCs also achieve high conversion band-
widths in deep sub-micron technologies. These types of ADCs resolve
their analog input successively, and share therefore most of the used
hardware (see Sec. 2.3.1). However, medium- to high-resolution SAR
ADCs need also to be properly calibrated in order to correct technol-
ogy dependent capacitor mismatch.
In this thesis, two SAR ADC prototypes and a folding converter
were implemented in 130-nm CMOS technology. While the first pro-
totype of the SAR ADC covers a signal bandwidth of 2 MHz and
achieves an effective resolution of more than 11 bit, the second proto-
type resolves an ENOB of 13.5 bit using dithering at a sampling rate
of 286 kHz.
The implemented folding converter covers roughly 100 MHz of sig-
nal bandwidth at an effective resolution of over 9 bit. Different calibra-
tion methods are analyzed and implemented for the CMOS converter
architectures in order to show their efficiency in practice.
1.4 Thesis goals

The thesis focuses on the following topics:
1. The static error sources originating from the underlying CMOS

process are analyzed in the desired Nyquist-rate ADC architec-
ture and digitally assisted calibration methods are developed
therefore to maximize the effective resolution. In particular,
digital post-correction algorithms are studied to approach the
corrected output of the converter to the one of an ideal con-
verter. The studied post-correction algorithms are implemented
for the SAR and folding ADCs, which can also be transferred
to other Nyquist-rate ADC architectures. Hybrid calibration
techniques [27, 29] operating in the analog as well as digital
domains are not excluded from being implemented in practice.
2. Off-line post-correction is not addressed in this thesis even though

different state-of-the-art ADCs published so far [20, 28] perform
it to operate low power. The post-correction circuits are im-
plemented on chip for the prototypes presented in this thesis in
order to get a precise number for their power consumption.
3. The Nyquist bandwidth of the ADCs is optimized for the desired

CMOS technology. All ADC realizations in the course of this
thesis are implemented in 130-nm CMOS technology.
4. Digitally assisted mixed-signal ASICs are implemented in prac-

tice to illustrate the successful compensation of analog imper-
fections. Robustness to analog limitations originating from the
reduced supply voltage, mismatch, nonlinearity of the transis-
tors in saturation, and electronic circuit noise is essential in the
design of the realized ADCs in order to increase their yield.
5. The achievable FoM is improved for the ADC realizations in a

way that is comparable to other state-of-the-art converter im-
plementations published in [20, 28–33]. The impact of digitally
assisted calibration techniques is shown on the FoM of the ADC.
1.5 Chapter organization

The rest of this thesis is organized as follows.
1.5. CHAPTER ORGANIZATION 21
Chapter 2 discusses different Nyquist-rate ADC architectures. A

thorough understanding of these ADCs is essential for the course of
this thesis. However, a detailed study of all Nyquist-rate ADCs would
go beyond the scope of this work which is why the SAR and the
folding ADCs are explained in detail. The SAR ADC is more deeply
considered in this thesis due to its amenability to technology scaling.
The folding ADC proves to be interesting in research and industry due
to its fast conversion bandwidth and low latency nature. However, the
different circuit techniques discussed for both chosen architectures can
be also adopted for other Nyquist-rate ADCs.
Chapter 3 describes the nature of device mismatch and its impact on

the overall performance of ADCs. Assuming that device parameters
are well-known for a given CMOS technology, the influence of device
mismatch on different ADC architectures is analyzed mathematically
to derive measures for the static performance of ADCs. This study
gives an understanding in how to correct the digital output of these
converters in practice. The chapter ends with the analysis of basic
ideal and non-ideal quantizers representing medium to high-resolution
and mathematically complex ADC architectures.
Chapter 4 describes different calibration techniques to compensate
for static errors which originate from fabrication imperfections as
discussed in Chap. 3. A background on the well established digitally
based calibration techniques is provided. The largest field of digitally
based calibration techniques is the look-up table (LUT) based post-
correction technique which is described in detail in this chapter. To
compensate for all sources of errors, post-correction is unfortunately
not sufficient in practice. It is transparent to missing codes. Re-
dundancy in combination with digital post-correction recovers also
missing codes. This technique is used in the implemented SAR ADC
prototypes described in Chap. 5. Since redundancy cannot be built
easily in folding ADCs, a digital post-correction algorithm is optimized
for folding ADCs and successfully implemented in CMOS as described
in Chap. 6.
Chapter 5 describes the realization of two different prototypes of a

14 bit sub-radix-2 SAR ADC in 130-nm CMOS technology employ-
ing a redundant segmented capacitor array with a merged capacitor
switching scheme. An optimized non-uniform clocking scheme is pro-

posed that reduces the conversion time by more than 50 % compared
to traditional clocking schemes for the same sampling capacitance.
A perturbation-based least-mean-square (LMS) start-up calibration
technique has been implemented directly on-chip to correct capacitor
mismatch and to enhance the effective resolution by more than 10 dB.
Both prototypes show the effectiveness of digitally-assisted calibration
and correction techniques in practice.
Chapter 6 describes the implementation of a digitally calibrated
folding ADC in 130-nm CMOS technology. The data converter is
designed to target a resolution of 11 bit. A start-up calibration tech-
nique including post-correction is applied in the proposed converter
architecture to compensate for static non-linearity errors. The cor-
rection algorithm improves the precision of the ADC while enhancing
the SNDR and SFDR by around 15 dB and 20 dB, respectively. A
FoM of 2.8 pJ/conversion is achieved in practice which is competitive
to other folding ADCs of similar precision and signal bandwidth cov-
erage published by the research community, but with a less complex
converter circuit.
Chapter 7 provides a summary, conclusion, and outlook of the open
problems of the thesis.
Chapter 2
Nyquist-Rate ADC
Architectures
In this chapter the Nyquist-rate ADC architectures commonly em-

ployed in high performance systems are discussed. These converters
can be broadly classified in architectures requiring a single reference
voltage referring to the zero-reference, and architectures with multiple
reference voltages. Integrating, SAR, algorithmic, and pipeline ADCs
belong to the first category, while flash, folding, two-step, and sub-
ranging ADCs are part of the latter class.
A thorough understanding of these ADC architectures is essential
for the course of this thesis. However, the detailed study of all listed
Nyquist-rate ADCs would go beyond the scope of this work and
for this reason from both categories, i.e., single- and multi-reference
ADCs, a promising candidate is chosen as a representative of its class.
In particular, the focus of this thesis is on the SAR and the folding
converter architectures. The reader is referred to the literature for an
exhaustive treatment of the matter, e.g., [7, 12, 34].
The SAR ADC is more deeply considered in this thesis due to
its amenability to technology scaling and, accordingly its relevance to
research and industry nowadays using the deep sub-micron CMOS
technologies available. The folding ADC proves to be interesting
in research due to its fast conversion bandwidth and low latency
23
24 CHAPTER 2. NYQUIST-RATE ADCS
nature. However, all circuit techniques discussed for both chosen

architectures can also be adopted to other Nyquist-rate ADCs as well.
Hybrid ADCs, i.e., combinations of different converter architectures
contributing each to the same converted signal, are not considered in
this thesis. In particular, time-interleaved ADCs are also not discussed
in this work.
2.1 Nyquist criterion

The sampling nature of Nyquist-rate ADCs places a physical lim-
itation on the bandwidth of the input signal to ensure a lossless
reconstruction of the sampled signal. The Nyquist criterion states
that a bandwidth-limited signal is uniquely determined by its samples
only if it is sampled at a frequency fs which is more than twice as large
as the Nyquist bandwidth fin [35–37]:
fs > 2fin . (2.1)
In practice, anti-aliasing filters are used in front of ADCs to restrict

the bandwidth of the analog input signal to satisfy the sampling
theorem (2.1) in the band of interest.
The following section gives an overview over Nyquist-rate ADCs
employed in high-performance systems.
2.2 Classification of Nyquist-rate ADCs

Before the era of deep sub-micron CMOS technologies, Nyquist-rate
ADCs were grouped in three categories and ordered according to
their conversion rates in slow, medium, and fast architectures [34,38].
This classification was done as a consequence of the required clock
cycles necessary to resolve an analog input signal. However, with the
development of deep sub-micron technologies, this commonly used
classification rapidly changed in literature. Since some ADC archi-
tectures scale better in CMOS than others [5], a classification with
respect to conversion cycles or simply sampling frequency fs is not
the best choice anymore.
2.3. SINGLE-REFERENCE ADCS 25
Table 2.1: Classification of Nyquist-rate ADCs.

single-reference multi-reference
integrating flash
SAR folding
ADC architecture
algorithmic subranging
pipelined two-step
In this work, a different classification is used which takes the

minimum number of required single-ended reference voltages into ac-
count as illustrated in Tbl. 2.1. For the mapping of analog signals
into quantized digital equivalents, reference nodes are essential, as for
example in daily life, physical distances are measured with a ruler and
each distance is labeled with a quantized number with the dimension
expressed in meters. The scaled labels on the ruler in this case serve
as reference nodes.
While single-reference Nyquist-rate ADC architectures, i.e., inte-
grating, SAR, algorithmic, and pipelined ADCs can be built requiring
a single reference voltage, multi-reference ADCs need complex refer-
ence generation circuitries to provide a set of equidistant reference
voltages. The amount of references and the choice of the reference
generation circuit is decided based on the underlying conversion algo-
rithm and the resulting ADC architecture.
As will be illustrated in the later chapters, the calibration and
correction of Nyquist-rate ADCs highly depend on the underlying
conversion algorithm and correspondingly on the number of necessary
reference voltages. For this reason, a classification taking the number
of reference voltages into account is essential for the purpose of this
thesis.
2.3 Single-reference ADC architectures

Providing a single reference voltage for an ADC simplifies the ref-
erence generation circuitry at the cost of a complexity increase in
the conversion algorithm. The mapping of an analog signal to its
3Vref
Vref
2Vref
Vref
0
Vref
Vref
0
0
0
Figure 2.1: Ruler with a single reference Vref with respect to the zero-
reference marked as 0 measuring a physical distance. Measurement is
performed iteratively in multiple steps.
quantized digital equivalent results in a mathematical search problem.

Equivalently in daily life, a ruler with a single reference node Vref with
respect to the zero-reference as illustrated in Fig. 2.1 needs 2Nres − 1
attempts to measure a physical distance of length Vref · 2Nres . This
measurement is equivalent to a linear search problem targeting a
resolution of Nres bit.
In literature, this linear conversion algorithm is commonly em-

ployed in the integrating ADC architecture [39]. The linear search,
however, is slow for high resolutions Nres and therefore not usable in
medium- to high-bandwidth sampling systems. For this reason, any
further discussions on integrating ADCs are skipped in this thesis.
A binary search is more attractive for practical and efficient high-

speed applications as it requires only Nres different measurement steps
for targeting a resolution of Nres bit. Mathematically, if the signum
function sgn(.) is defined to yield +1 for a positive and -1 for a negative
number, Vref being the reference voltage, and Vi+1 the analog residue
of the (i + 1)th iteration cycle, then the binary search can be written
using recursion as
Vref
Vi+1 = Vi − sgn (Vi ) i ∀ i ∈ 1, 2, . . . , Nres (2.2)
| {z } 2
Dout,i [kTs ]
with V1 = Vin [kTs ]. Through the binary search conversion algorithm,

the analog input is successively quantized to finer precisions. The
analog input is resolved successively by a factor (or radix) of 2 and
the reference voltage is adjusted accordingly to perform conversion on
smaller residues of the analog input.
The described recursion formula (2.2) can be translated into a con-
verter architecture commonly known as SAR ADC. The decision made
by the signum function (denoted as Dout,i [kTs ] in (2.2)) corresponds
to the digital output of the SAR ADC. A detailed discussion on the
SAR architecture follows in Sec. 2.3.1.
Instead of dividing the reference voltage by a factor of 2 as in (2.2),
the recursion formula can also be modified to
Vi+1 = 2Vi − sgn (Vi ) Vref ∀ i ∈ 1, 2, . . . , Nres (2.3)
| {z }
Dout,i [kTs ]
with V1 = Vin [kTs ]. In this case, the reference voltage Vref is sub-
tracted from the analog input signal and the resulting analog residue
is rescaled to again fit the signal range. This recursion formula be-
longs to the conversion algorithm of the algorithmic (or cyclic) ADC.
The decision made by the signum function (denoted as Dout,i [kTs ]
in (2.3)) again corresponds to the digital output of the algorithmic (or
cyclic) ADC. A detailed discussion on the algorithmic ADC follows
in Sec. 2.3.2.
Unfolding the architecture of the algorithmic ADC results in the
pipeline ADC which is discussed in subsection 2.3.3.
2.3.1 Successive-approximation register ADC

The successive approximation technique employs the recursive bi-
nary search algorithm as described in (2.2). The algorithm approxi-
mates the sampled analog input voltage successively through a feed-
back loop. A general block level schematic of the ADC is illustrated
Vin (t) Vin [kTs]

S/H Dcomp,i Dout [kTs]
SAR
Vref A
D
Figure 2.2: Block diagram of a SAR ADC [14].
in Fig. 2.2. To perform the recursive conversion algorithm, the ADC

requires four main circuit components, namely a sample-and-hold
(S/H), a comparator, a digital SAR logic, and a digital-to-analog
converter (DAC) circuit.
The S/H circuit in Fig. 2.2 samples the analog input signal Vin (t)
and holds Vin [kTs ] until the next sampling instant. During the hold
phase of the S/H circuit, the comparator performs comparisons. De-
pending on the comparison result Dcomp,i , a new DAC input for the
(i + 1)-th conversion cycle is calculated and adjusted over the feed-
back. The feedback approximates the sampled input signal Vin [kT s]
successively with cumulative combinations of the terms Vref /2i for
the i-th conversion cycle.
The first conventional charge redistributing SAR ADC was pub-
lished by J. L. McCreary and P. R. Gray in 1975 [40,41] and is depicted
in Fig. 2.3 a). A typical characteristic of the convectional capacitor
array is that the input signal Vin (t) is sampled on the bottom plate of
the capacitor array.
In recent years, the research interest in SAR ADCs has rapidly
increased because of its low power consumption and its amenability to
technology scaling [18–20,42]. Recently published SAR ADCs achieve
MSample/s to GSample/s data rates [21]. In principle, SAR ADC
cores are designed with no static current consumption (if reference
generation circuitry is excluded). A detailed analysis of the power
contributors in SAR ADCs can be found in App. A. The merged
capacitor switching scheme is used in here for further discussions and
VGND Vtop Dcomp,i Dout [kTs]

SAR
8C u 4C u 2C u Cu Cu
Vref
VGND
a) Vin (t)
Vin (t) Vtop Dcomp,i Dout [kTs]

SAR
+Vref
Vcm
b) -Vref
Figure 2.3: a) Conventional SAR ADC block diagram [40]. b) Detailed

block diagram of the merged capacitor switching method based SAR
ADC [14].
is illustrated in Fig. 2.3 b). It requires a positive and a negative

−
reference voltage (denoted as Vref
+
and Vref ) and is intended for fully
differential applications.
The factorization of the reference voltage Vref by a factor of 2 is
done through the binary weighting of the unity capacitor Cu . Using a
merged capacitor switching scheme during sampling in the SAR ADC
all capacitors are connected to the common-mode voltage Vcm and a
total charge of
res −1
NX
Qsamp = Cu (Vin − Vcm ) + 2i Cu (Vin − Vcm ) (2.4)
i=0
is stored in the capacitor array. During conversion, the digital SAR

logic is active which controls the switches of the weighted capacitors.
The capacitors are switched depending on the comparator output
Dcomp,i for the i-th conversion cycle and the total charge can be
computed according to
Qconv = Cu (Vtop − Vcm )

res −1
NX
+ 2i Cu Vtop + (−1)Dcomp,i Vref . (2.5)

i=0
Due to charge conservation Qsamp = Qconv in (2.4) and (2.5) and

assuming Vcm = 0, the sampled analog signal Vin [kTs ] is successively
approximated during conversion as
res −1
NX
Vref
Vtop = Vin − (−1)Dcomp,i 2i Cu , (2.6)
2Nres Cu i=0
which is equivalent to the recursive formula in (2.2).

As can be seen in (2.6), the effective resolution of the SAR ADC
is primarily limited by the imperfections of the unity capacitor (see
Sec. 3.4).
2.3.2 Algorithmic ADC

In this subsection, basic concepts of the algorithmic (or cyclic) conver-
sion are discussed [43, 44]. Equivalent to the SAR ADC, the algorith-
mic converter resolves its analog input recursively as shown in (2.3).
An overall block level diagram of the converter is depicted in Fig. 2.4.
Vin (t)
Dcomp [kTs]
S/H 2 S/P
Dcomp [kTs]
- +Vref
+ - Vref
Figure 2.4: Block diagram of the algorithmic (or cyclic) ADC [43].
The illustrated algorithmic ADC samples its analog input Vin (t)
using the S/H circuit. Before a comparison is performed, the sampled
signal is multiplied by a factor of 2. The comparator output decides
on the sign of the reference voltage, which is subtracted from the
amplified signal. A serial-to-parallel (S/P) interface is used in order to
store the comparator output Dcomp [kTs ] during conversion and build
the parallel ADC output Dout [kTs ].
Due to its iterative structure, the algorithmic converter needs only
a few active circuit elements [45], i.e., an amplifier and a comparator.
The amplifier is shared in a SC circuit realization to perform different
subtasks in the algorithmic ADC. It is used to sample the input signal
Vin (t) on a capacitor, multiply it by a factor (or radix) of 2, and
subtract a positive or negative reference voltage from it. A dedicated
comparator circuit is used to resolve the output of the SC circuit.
The limitation of the circuit is given by the design of the am-
plifier [45–48]. For high-linearity and high-speed operation, the ADC
needs to provide high open-loop gain and signal bandwidth. However,
both requirements increase the power consumption of the amplifier
and make it inefficient compared to other Nyquist-rate ADCs.
Moreover, the ADC is not necessarily amenable to technology
scaling, since the intrinsic gain of transistors decreases in some new
technology generations [49]. For this reason, it is challenging to
design a high-gain amplifier in a deep sub-micron technology which is
required in this ADC architecture. The signal swing is also relatively
small due to supply voltage limitations (see Sec. 1.2.3). The converter
is more susceptible to circuit noise due to a reduced signal swing.
2.3.3 Pipeline ADC

Unfolding the architecture of the algorithmic (or cyclic) ADC (which
is discussed in Sec. 2.3.2) results in the pipeline ADC. In this ADC
architecture, each conversion cycle [7] is processed in a separate stage
as illustrated in Fig. 2.5. Each stage of the pipeline ADC consists
in general of a S/H, a low-resolution ADC, a DAC, an adder, and a
residue amplifier with an open-loop gain A. As each stage holds its
sampled value during the analog signal processing, the ADC operates
in a pipelined fashion. A digital encoder takes the output of the
single stages, and computes the output of the ADC which is denoted
-
S/H ADC DAC + A
Vin (t)
stage 1 stage 2 stage Nres
Dout [kTs]
digital encoder
Figure 2.5: Blocklevel schematic of the pipeline ADC.
as Dout [kTs ]. The pipeline ADC can be designed to target high signal
bandwidths at medium precision [13, 31, 50–58].
2.4 Multi-reference ADC architectures

Multi-reference ADC architectures need a set of equidistant reference
voltages to digitize an analog signal. Equivalent to a ruler using
an equidistant set of references referring to the zero-reference which
instantly measures a physical distance as illustrated in Fig. 2.6, this
ADC architecture type profits also from the simplicity of its conver-
sion algorithm. The sampled analog signal at the input is compared
directly with a parallel set of reference voltages and its output is
generated within the same conversion cycle.
The simplest multi-reference architecture is the flash ADC which is
discussed in Sec. 2.4.1. However, as the number of reference voltages
and comparators increases exponentially with the targeted resolution,
other more advanced multi-reference architectures are studied. These
architectures are known as the folding, two-step, and sub-ranging
ADCs which are discussed in the following subsections.
2.4.1 Flash ADC

The ADC architecture that achieves the largest conversion rate with
the lowest latency is the flash ADC [59–63]. The block level schematic
2.4. MULTI-REFERENCE ADC ARCHITECTURES 33
3Vref
Vref 2Vref 3Vref

2Vref
Vref
0
Figure 2.6: Ruler with multiple reference with respect to the zero-
reference marked as 0 in order to perform a single measurement to
quantize a physical distance.
of the flash ADC is shown in Fig. 2.7 a), and in b) the corresponding
transfer characteristic is depicted. The reason why the flash ADC
achieves the highest conversion rate lies in the architecture of the
converter. For each quantized code level, a separate comparator is
used which compares the input voltage Vin (t) against a reference
voltage from the set {Vref,0 , Vref,1 , . . .}. A thermometer to binary
encoder is required at the output of the flash ADC to convert the
resulting thermometer code generated by the parallel set of 2Nres − 1
comparators. The conversion latency of the flash ADC ideally equals
one clock cycle.
The flash ADC is limited to a resolution of 4-8 bit since overall
power dissipation, silicon area, number of voltage references, and input
capacitance seen by Vin (t) increase exponentially with the nominal
resolution Nres of the converter. A power-hungry input buffer is
required to drive the resulting capacitive load at the input of the
comparators for higher resolutions.
Different techniques are exploited in literature [61,63,64] to reduce
the input capacitance seen by Vin (t). Among others, the interpolation
technique is a first attempt to do so which is discussed in the next
section. Interpolation, however, does not help to decrease the number
of comparators.
Vin (t) Vin (t)
termometer to binary encoder

Vref,...
Vref,2
reference generator
Vout [kTs]
Dout [kTs]
Vref,1 t
Vref,1
Vref,0
Vref,0
a) b)
Figure 2.7: a) Architecture of the flash ADC. b) Transfer characteris-

tic of the flash ADC. The voltage Vout [kTs ] is the analog representation
of the digital output Dout [kTs ]
2.4.2 Interpolating flash ADC
Although a flash converter offers fast conversion rates with the lowest
latency due to its fully parallel design, it has the disadvantages of a
high power consumption and input capacitive load as the number of
references and comparators increases exponentially with the nominal
resolution Nres . In order to reduce the number of reference voltages,
a circuit technique called interpolation [60] can be used which is
depicted in Fig. 2.8.
Interpolation is a mathematical method to create new equidistant
data points within the range of a set of known data points, which is
demonstrated in Fig. 2.8 a). A commonly used circuit technique to
implement interpolation is shown in Fig. 2.8 b). The interpolation
factor NI defines the number of newly created equidistant points.
Mathematically, the interpolation function can be expressed as

k
Vint,k = A Vdiff,bk/NI c + ∆Vdiff k = 0, 1, 2, . . . ,
NI
where ∆Vdiff = Vdiff,1 − Vdiff,0 .

pre-amplification stage
Vint
Vdiff,0 Vdiff,1
Vdiff,1 Vin (t) - Vint
0 1 2 3 interpolation
Vin (t) Vref,1 NI = 3
Vdiff,0
Vref,0 Vref,1 -
Vref,0
a) b)
Figure 2.8: a) Transfer characteristic of the interpolation circuit with

NI = 3. New data points (marked as 1 and 2) are constructed from
known data points (marked as 0 and 3). b) Block diagram of a circuit
which performs the interpolation technique.
In practice, a pre-amplification stage is used in combination with

the interpolation circuit to create residues between the analog in-
put denoted as Vin (t) and the set of reference voltages. The pre-
amplification stage is not only used to create the residues, but also to
improve the settling in the interpolation circuit [65] which is commonly
built by passive components, e.g., resistors and/or capacitors. The
output of the pre-amplifier is zero when Vin (t) equals its associated
reference voltage, otherwise the pre-amplifier saturates either in the
positive or negative direction.
As shown in Fig. 2.8 a), additional zero-crossings (marked with
the numbers 1 and 2) are created in the interpolation circuit using
the existed ones (marked with the numbers 0 and 3). Zero crossings
are relevant in analog circuits because comparators can be used to
detect them.
The most common scheme implementing interpolation in prac-
tice consists of resistive dividers to generate new equidistant data.
However, this is not the only way to perform interpolation. Other
alternative schemes are active [66–68], current [69–71], and capacitive
interpolation [64, 72]. The basic advantages of resistive interpola-
tion against other schemes is the relatively low power consumption,
its ability to be easily combined with averaging, and the fact that
a monotonic transfer characteristic is always guaranteed [65]. The
averaging technique is commonly used with resistive interpolation
consisting of an integrating resistor network between amplifiers to
pre-amplifiers interpolation comparators

& averaging
Vin (t) V -
diff,N-1 V-
int,2N-1
+-
Vref,N-1 A V +
diff,N-1 V+
int,2N-1
-+

R R
reference generator
Vdiff,1
- R R Vint,2
-
+- Dout [kTs]
Vref,1 A
-+ Vdiff,1
+
Vint,2
+
R R -
Vint,1
Vint,1
+
Vdiff,0
- R R Vint,0
-
+-
Vref,0 A Vdiff,0
+
Vint,0
+
-+
Figure 2.9: Resistive interpolation technique employed in an interpo-

lating flash ADC with an interpolation factor NI = 2.
improve the overall DNL of the ADC. After averaging, the outputs of
the amplifiers are highly correlated which results in an improvement
of DNL. In general, additional resistors are added to the resistive
interpolation circuitry to perform averaging with no effect on power
dissipation or input capacitance. The reader is referred to [73] to find
further information on the averaging technique.
The interpolation technique can be used to redesign the conven-
tional flash ADC more efficiently. Compared to the conventional
flash ADC studied in Sec. 2.4.1, the interpolating flash converter (as
depicted in Fig. 2.9) requires besides comparators and a reference gen-
eration circuitry, also a pre-amplification and an interpolation stage.
In the interpolating flash ADC, the only important information for
quantization are the locations of zero crossings at the pre-amplifier
output, since those denote the transition between the digital code
levels.
The interpolating technique reduces the high input capacitive load
of the flash ADC by the interpolation factor NI . Consequently, fewer
0 1 NF 2 NF 57 NF 58 NF 59 NF
a) 12
11 12 1
60
10 2
NF = 12 9 45 15 3
8 4
30
7 5
b) c) 6
Figure 2.10: a) Monotonically ascending line with minute information.

b) Folding of the monotonically ascending line by a factor NF = 12.
c) Folding of minute information by a factor of NF = 12 on a clock
display.
reference voltages and pre-amplifiers are needed. However, the num-

ber of comparators still increases exponentially with the nominal reso-
lution Nres . One possible solution to mitigate this problem is discussed
in Sec. 2.4.3 when the folding technique is introduced.
2.4.3 Folding ADC

The folding circuit technique was first proposed in [74] and is used
in folding ADCs primarily to reduce the complexity of the underlying
analog circuitry which is based on the parallel structure of the flash
converter [16,26–28,75–79]. The working principle of the folding ADC
can be explained using the illustration in Fig. 2.10.
To assign time information to the course of the day, a set of
references is required for measurement as depicted in Fig. 2.10 a).
Expressing the time information only in minutes requires an analog
clock display with a confusingly large amount of reference nodes rep-
resenting each minute of the day. This would be the equivalent of a
flash type converter measuring the time. However, instead of using a
quantization levels
coarse
flash ADC
Ncoarse
digital encoder
Vin (t) Dout [kTs]
Nres 2 Ncoarse
residue fine
folding flash ADC
Nfine
2 Nfine
a) b) Vin
Figure 2.11: a) Two-step (coarse and fine) approach of the conversion

problem. b) Transfer characteristic of the two-step approach.
single clock hand to represent time information, the references can be

neatly arranged using minute and hour clock hands to measure the
time. The minute information is folded by the number of references
used to represent hours (a folding factor of NF = 12) as shown
in Fig. 2.10 b) and c). This folding of references on a clock display
is only possible because the fine quantization of the time, i.e., the
minute information, is repetitive for each hour, and the overall time
information is monotonically ascending for each day.
The transfer characteristic of an ADC is also monotonically in-
creasing. The folding technique, equivalent to the intuitive representa-
tion of time information, can be efficiently implemented as an ADC ar-
chitecture. The principle of the folding ADC is shown in Fig. 2.11 a).
The converter architecture consists of a coarse and a fine quantizer
(minute and hour hand) as depicted in Fig. 2.11 b). In the folding
ADC the coarse and fine quantization are performed simultaneously.
A dedicated encoder circuit is used in practice to combine fine and
coarse information in the digital domain.
The analog residue (fine information) quantized by the flash con-
verter is generated by the folding circuit which has a transfer charac-
teristic shown in Fig. 2.12 a). The conceptual transfer function is not
steady and for this reason, its generation is challenging in practice.
Therefore, practical implementations of folding ADCs use the steady
residues
Vin
a)
residues
Vin
b)
residues
Vin
c)
Figure 2.12: a) Conceptual transfer function of a folding circuit [65].

b) Steady transfer function. c) Steady transfer function including
high-frequency limitations.
transfer function illustrated in Fig. 2.12 b). The difference of the

transfer function to the one in Fig. 2.12 a) is considered in the encoder
of the folding ADC. Since active analog circuits are bandwidth limited
in practice, the sinusoidal signal shape as depicted in Fig. 2.12 c) is
realizable with folding circuits. Note, that only the linearity around
the zero crossings is significant for correct operation of the converter.
The conversion rate of the converter is maintained high due to the
parallel operation of the two quantizers. In general, only
Ncomp = 2Ncoarse + 2Nfine − 2 2Nres
comparators are used in the folding converter.

In addition to the folding technique, interpolation can be used
to reduce the number of necessary references. As can be seen from
the enduring discussions, multiple stages (cascading) of folding and
interpolation operations can increase the nominal resolution of the
-
Vin (t) Ifold
0 1 0 1
Vref,1
I +
fold
r e sid u e
Vref,3 - Vin (t)
Ifold+ - Ifold
Vref,5 Vref,1 Vref,3 Vref,5

a) b)
Figure 2.13: a) Folding amplifier realized with three operational

transconductance amplifiers resulting in a folding factor of NF = 3.
b) Transfer characteristic of the folding circuit.
converter efficiently compared to the flash converter and the number

of comparators Ncomp can be minimized by intelligent concatenation
of the stages [28], i.e., by building a cascaded folding and interpolating
topology.
Folding technique
The analog residue signal required in the folding ADC is generated

by the folding circuit illustrated in Fig. 2.13 a), with the transfer
characteristic shown in Fig. 2.13 b). The analog residues are obtained
from the input signal subtracted by a set of references.
A folding factor NF = 3 can be realized with three operational
transconductance amplifiers. The linearity of the amplifiers is less
critical and only their zero crossings are important for the fine quan-
tization. The folding factor NF is defined as the number of zero
crossings in the transfer characteristic of the folding circuit. Folding
helps to reduce the number of comparators, but not the amount of
references. Interpolation techniques are used in practice to reduce the
number of references as well, which will be explained in the following.
Vin (t)
Vref,0 folding Vfold,0 Dout,0 [kTs]
0000
1000
1100
1110
1111
1111
0111
0011
0001
0000
0000
Dout [kTs]
1000
1100
1110
Vref,2 amplifier
Vref,4
Vintr,00 Dout,1 [kTs]
Vin
Vintr,01 Dout,2 [kTs] Vfold,1

Vfold,0
Vref,1 folding Vfold,1 Dout,3 [kTs]

Vref,3 amplifier Vref,0 Vref,2 Vref,4
Vref,5 Vref,1 Vref,3 Vref,5
a) b)
Figure 2.14: a) Folding and interpolation with NF = 3 and NI = 3. b)

Transfer characteristic of the folding and interpolation circuits. The
digital output Dout [kTs ] represents the decisions of the comparators.
Interpolation techniques in folding ADCs
As already discussed in Sec. 2.4.2 in the context of flash ADCs, where

the interpolation technique is applied to reduce the number of refer-
ence voltages and pre-amplifiers by the interpolation factor denoted
as NI , this technique can also be applied in folding ADCs. As shown
in Fig. 2.14 a), additional resistors are introduced at the output of
the folding amplifiers. The basic advantages of resistive interpolation
against other schemes is the relatively low power consumption and its
ability to be easily combined with averaging [28].
The interpolation effect of the folded signals can be seen in the
transfer characteristic of the circuit shown in Fig. 2.14 b). Additional
zero crossings are generated in order to reduce the amount of folding
amplifiers, reference voltages, and pre-amplifiers. The transfer char-
acteristic of adjacent folding circuits must be linear around the zero
crossings to avoid systematic deviations of zero crossings, in particu-
lar, when folding circuits experience gain mismatch. For this reason,
a small folding factor NF is desirable in practice if high linearity is
required in the converter [77].
residue
Vfold,1 Vin
Vref,0
Vref,3 folding Vfold,1 Vref,0 Vref,3 Vref,6
Vref,6 Nf = 3 Vfold,2 Vin
Vref,1
Vref,4 folding Vfold,2 folding Vout Vref,1 Vref,4 Vref,7
Vref,7 Nf = 3 Nf = 3 Vfold,3 Vin
Vref,2
Vref,2 Vref,5 Vref,8
Vref,5 folding
Vref,8 Nf = 3 Vfold,3 Vout Vin
a) b)
Figure 2.15: a) Cascaded folding circuit with Nf = 9. b) Transfer

characteristic of the cascaded folding circuit.
Cascaded topology
A large folding factor NF developed in a single-stage folding circuit

reduces the number of comparators at the cost of an increased capac-
itive load at the output of the folding circuits. Thus, a large folding
factor limits the analog bandwidth. A large interpolation factor NI
increases the resistive load and thus decrease the analog bandwidth
as well. A cascaded topology helps to improve the efficiency of the
folding ADC instead of increasing the folding and interpolating factors
at the front-end of the circuit.
The cascaded topology consists of multiple folding and interpo-
lating stages connected in series. This circuit technique helps to
increase the resolution of the converter by building multiple folding
and interpolating stages [26] with minimum folding and interpolating
factors (see Fig. 2.15 a)). The total number of zero crossings is in-
creased by the resulting folding and interpolation factors of all stages
as illustrated in Fig. 2.15 b). The analog bandwidth is relatively
enhanced compared to a single stage folding and interpolating ADC
with high folding and interpolation factors.
2.4.4 Two-step ADC

The exponential growth of reference voltages, power consumption,
and silicon area makes the medium resolution flash ADC unusable for
low-power applications. In literature, also other circuit techniques are
investigated which differ from the folding ADC discussed in Sec. 2.4.3.
An analog-to-digital conversion technique which reduces the num-
ber of reference voltages and comparators is illustrated in Fig. 2.16
and is called two-step ADC [80, 81]. After the analog input Vin (t) is
sampled, a coarse ADC generates a rough approximation Vcoarse [kTs ]
of the sampled input Vin [kTs ]. In a second processing step, the sam-
pled analog signal is subtracted from the rough approximation, and
the resulting residue is quantized by a fine ADC. The coarse infor-
mation Dcoarse [kTs ] and the fine information Dfine [kTs ] are combined
in the digital domain to build the output of the ADC. Since this
architecture employs a DAC and a subtraction operation, stringent
linearity requirements should be upheld in both circuit elements. This
architecture type operates also at a low bandwidth compared to the
flash ADC because a new sampling step can only be performed after
the coarse and the fine comparisons have both settled.
2.4.5 Subranging ADC

Instead of using a highly linear DAC and subtraction operation as
it is the case in the two-step ADC, there also exists the possibility
to perform a coarse comparison on the sampled input signal Vin [kTs ]
and adjust the reference voltages used in the fine ADC afterwards
-
Vin (t) Vin [kTs] Dcoarse [kTs] Vcoarse [kTs]
S/H coarse ADC DAC +
Dfine [kTs] Vfine [kTs]

fine ADC
Figure 2.16: Block diagram of a two-step ADC.

Vin (t) Vin [kTs] Dcoarse [kTs]

S/H coarse ADC
Vref,coarse
reference generator
Dout [kTs]
encoder
Dfine [kTs]
BUF fine ADC
BUF
MUX
Vref,fine [kTs]
Figure 2.17: Blockdiagram of the subranging ADC.
such that the sampled input signal lies in the range of the gener-
ated references Vref,fine [kTs ]. A switching matrix then connects the
quantizer which is responsible to resolve the fine information to the
appropriate subrange of the reference. A digital encoder combines
the coarse Dcoarse [kTs ] and fine Dfine [kTs ] thermometer codes [82–86].
This slightly modified circuit is called the subranging ADC and is
depicted in Fig. 2.17. The switching matrix which connects the ap-
propriate subrange of the reference voltages to the ADC is denoted as
MUX in the illustrated block level diagram in Fig. 2.17.
For performance reasons, the latency of the coarse quantizer must

be kept low, because its decision has to be known before the signal
dependent reference set Vref,fine [kTs ] is adjusted in the switching ma-
trix. Then, the quantizer responsible for the fine information can start
to resolve the sampled input Vin [kTs ]. However, to ensure matching
of inputs and reference voltages between both quantizers, the same
reference ladder should be used for both quantization steps. For this
reason, the reference generation circuit ends up to be complex in terms
of number of switching elements. To increase the efficiency of the
converter, pipelining techniques can be applied. Digital and analog
buffers denoted as BUF in the illustration, can be introduced in the
signal chain of the converter to store the signal correspondingly.
2.5. HIGH-BANDWIDTH NYQUIST-RATE ADCS 45
Table 2.2: Recently published high-bandwidth Nyquist-rate ADCs in

JSSC.
SAR pipelined flash folding subranging
[21] [87] [63] [88] [86]
year of publication 2013 2013 2013 2010 2014
technology [nm] 32 40 90 90 65
sample rate [GHz] 1.2 2.1 4.1 2.7 1.0
resolution [bit] 8 9 6 6 6
power cons. [mW] 3.1 240 76 50 9.9
FoM [pJ/conv.] 0.034 0.43 0.625 0.47 0.278
2.5 High-bandwidth Nyquist-rate ADCs

Recently published high-bandwidth Nyquist-rate ADCs in the journal
of solid-state circuits (JSSC) are summarized in Tbl. 2.2 where the
designed prototypes are fabricated in nowadays different deep sub-
micron CMOS technologies. The listed Nyquist-rate ADCs can all be
seen as state-of-the-art high-bandwidth designs. All listed Nyquist-
rate ADC implementations achieve sampling rates in the gigahertz
region and target low resolutions due to the bandwidth-resolution
trade-off in ADCs (described in Sec. 1.3). Digital calibration and
correction circuits improve the FoM of all listed Nyquist-rate ADCs.
The SAR ADC reported in [21] achieves the lowest FoM compared
to the other listed Nyquist-rate ADCs. The extreme efficiency in
this architecture is achieved through the low power consumption in
the ADC core. As discussed in Sec. 2.3.1, except of the reference
generation circuitry, no static power is consumed in this converter.
High bandwidth is achieved in the reported SAR ADC implementation
through two alternate comparators that are asynchronously clocked
and a redundant capacitive DAC which tolerates settling errors. The
reported SAR ADC is implemented in a 32 nm CMOS technology.
In literature, no publication is found on high-bandwidth algorith-
mic ADCs. As discussed in Sec. 2.3.2, the limitation of the converter
architecture is given by the design of the iteratively used amplifier,
specially when using deep sub-micron technologies with relatively
small intrinsic gain of transistors and supply voltages. For these

reasons, a power-efficient design of the amplifier is challenging when
using deep sub-micron technologies.
However, as described in Sec. 2.3.3, unfolding the iteratively used
architecture of the algorithmic converter leads to the pipelined ADC,
which is a well suited candidate for high-bandwidth operation. The
pipelined ADC described in [87] resolves 9 bit and achieves a FoM
of 0.43 pJ/conversion. A digital error correction technique is imple-
mented in the pipelined ADC for correcting dynamic errors. It uses a
digital low-pass filter which operates directly on the different pipelined
stages.
As expected from the discussion in Sec. 2.4.1, the highest con-
version rate is achieved by the flash ADC if compared to all other
Nyquist-rate ADCs in Tbl. 2.2. The proposed flash ADC achieves
4.1 GS/s. The implementation details of the state-of-the-art flash
ADC is reported in [63]. Interpolation techniques are used in the
ADC prototype in order to reduce the input capacitance of all com-
parators driven by the track-and-hold (T/H) circuit and thus reducing
its overall power consumption. The resolution of the flash ADC is,
however, limited to 6 bit.
The folding ADC reported in [88], achieves a better FoM compared
to the flash ADC. The proposed ADC performs an on-chip background
calibration technique to compensate for the large mismatch of the
cascaded folding stages used in the converter architecture. The folding
ADC is designed to target 6 bit of resolution.
The sub-ranging converter reported in [81] resolves also 6 bit, but
consumes less power compared to the other multi-reference ADCs.
The separation in coarse and fine quantizers, and dedicated buffer-
ing/pipelining as discussed in Sec. 2.4.5, improves the power efficiency
of the subranging ADC in practice.
A high-bandwidth two-step ADC implementation is also missing
in literature. As discussed in Sec. 2.4.4, this architecture type is
bandwidth limited compared to other multi-reference ADCs because
a new sampling can only be performed, after the coarse and the fine
comparisons are done. A parallelization of the coarse and the fine
quantizers is not feasible for this type of converter architecture.
Chapter 3
Implications of Static
Error Sources on
Nyquist-Rate ADCs
This chapter discusses static errors which originate from device mis-
match and their impact on the performance of ADCs. Following
the studies on single- and multi-reference converters from Chap. 2,
the influence of mismatch on reference voltage generation circuits is
further analyzed. Assuming that device parameters are well known
for a given CMOS technology, the influence of device mismatch on
different ADC architectures is analyzed in great detail. This study
gives an understanding in how to correct the output of these converters
in practice. The chapter ends with the analysis of basic ideal and non-
ideal quantizers and derives measures to characterize the conversion
quality of ADCs. It provides methods for analyzing medium- to
high-resolution and mathematically complex converter architectures.
3.1 Mismatch
The modeling and understanding of a CMOS process helps to de-
rive parameters to express the behavior of electrical components, i.e.,
47
48 CHAPTER 3. STATIC ERROR SOURCES
transistors, resistors, and capacitors. The resulting device parameters

either consist of measurable currents and voltages or of derived model
parameters such as threshold voltages, transconductance, resistances,
and capacitances [89]. The technology dependent parameters deter-
mine the performance of all analog ICs.
The design of precise analog circuits requires a thorough under-
standing of the matching characteristics of commonly used compo-
nents available in CMOS. Mismatch is the process describing time-
independent random variations in identically designed physical com-
ponents which are closely placed on silicon and is greatly discussed in
literature [90–92].
The sensitivity of data converters to mismatch increases with the
specifications on their resolution [5]. In particular, the trend towards
reduced supply voltages in deep sub-micron technologies (see Chap. 1)
increases the relevance of mismatch. Even a few millivolts of offset
given by mismatch between transistors can result in ADCs with re-
duced yield (see [92]). The large sensitivity of converters to mismatch
demands for a precise estimate of device parameters (see Sec. 3.6.2) as
well as the design of calibration algorithms to correct time-independent
random variations.
In literature, it is common to differentiate between random and
systematic sources of mismatch [93]. Both are discussed in this sec-
tion.
3.1.1 Random mismatch

Random mismatch originates from imperfections in fabrication, such
as lithographic edge roughness [94], random dopant fluctuations [95,
96], or grain boundary effects [97, 98]. In the following, mismatch
occurring in commonly used CMOS components, i.e., transistors, re-
sistors, and capacitors is further discussed.
CMOS transistor mismatch

The mismatch of two identical and closely placed transistors has been
extensively studied in literature [92], and it primarily depends on the
device area. The threshold voltage difference ∆VTH and the current
factor difference ∆β are the dominant influences of mismatch that are
3.1. MISMATCH 49
5
σ (∆ VT H )
2 250 nm
130 nm
1 65 nm
32 nm
0
0 0.5 1 1.5 2
1/ √ W L
Figure 3.1: Standard deviation σ (∆VTH ) of the threshold voltage VTH

over the square root of transistor area [8].
present in an imperfectly matched pair of CMOS transistors. These

random differences between transistors have a normal distribution
with zero mean and a variance [99], which is a function of a technology-
dependent proportionality constant AVTH and the device area given
by W and L. The variances of the threshold voltage ∆VTH and the
current factor difference ∆β are given as
A2VTH
σ 2 (∆VTH ) = (3.1)
WL
and
∆β A2β

σ 2
= . (3.2)
β WL
There is little correlation between the threshold voltage difference

∆VTH and the current factor difference ∆β in practice and hence,
they are assumed to be statistically independent throughout this work.
Fig. 3.1 illustrates the technology-dependent proportionality constant
AVTH for several industrialized CMOS processes in relation to tran-

sistor area. Transistor matching improves with thinner oxides [90–92]
in advanced sub-micron technologies.
Resistor mismatch
Different types of resistors can be realized with CMOS processes.
Among others the n-well as well as the polysilicon resistance are
commonly used to build resistive elements [100]. For resistors, the
mismatch is described as a random variable with a normal distribution
of zero mean and variance
∆R A2R

σ 2
= , (3.3)
R WR LR
where WR and LR are the dimensions of the resistor and AR is the
technology-dependent matching constant.
Capacitor mismatch
Capacitive elements with reliable electrical characteristics are real-
ized as metal-insulator-metal (MIM) and metal-oxide-metal (MOM)
capacitors in CMOS technology processes [100]. However, MOS ca-
pacitors (MOSCAPs) have a variable capacitance value dependent on
the region of operation of the underlying MOS transistor, and are
therefore not recommended for the design of precise analog circuits.
The random mismatch of MIM and MOM capacitors can be de-
scribed similar to the one of resistors. The mismatch of capacitors
is described as a random variable with a normal distribution of zero
mean and variance
∆C A2C

σ 2
= , (3.4)
C WC L C
where WC and LC are the dimensions of the capacitor and AC is the
matching constant that again is technology dependent.
3.1.2 Systematic mismatch

When designing medium- to high-resolution ADCs, it proves essential
to pay attention to the symmetry of layout, specially in matching
3.2. PERFORMANCE METRICS 51
of highly sensitive circuit elements [93]. For this reason, systematic

analog layout practices include the use of dummy devices for providing
similar environment also on the boundary of a layout, the use of sym-
metric layouts to cancel CMOS process gradients, and maintaining
the same current directions [101–103].
In the following sections, it is assumed that the random mismatch
dominates over the systematic one. Hence, a symmetric and proper
layout of the analog circuitry is presumed.
3.2 Performance metrics

As discussed in Sec. 1.1, there are static and dynamic measures for
describing the DC and AC performance of ADCs. DNL and INL
belong to the former while SNR, SFDR, SNDR, and THD are part
of the latter group. All measures discussed so far are of practical
interest to measure the precision of ADCs and to describe the quality
of the resolved digitized output. However, these measure can also
be of practical use during the design of ADCs. Before the ASIC
is sent out for fabrication, technology dependent parameters can be
used to derive performance measures beforehand. Accordingly, the
mathematically derived measures can serve to optimize the mixed-
signal sampling system and enhance its overall performance.
In the following sections, the impact of static errors on ADCs
is expressed in terms of static measures, i.e., DNL and INL. These
measures are used to derive mathematical expressions for the SNDR
and the ENOB of ADCs. Since the SNDR and equivalently the ENOB
are more than sufficient to determine the overall performance of an
ADC and especially to calculate its FoM, a mathematical expression
for the SNDR based on DNL and INL [16,25] is provided in Sec. 3.6.2.
3.3 Impact of mismatch on the reference

generation circuit
ADCs that require multiple equidistant reference voltages suffer from
mismatch between their passive components. Passive components are
necessary in the design of a reference generation circuit. Indeed, the
Vref mismatched
R+ΔRM
references Vref
Vref,M-1
Vref,M-1
R+ΔRM-1 Vref,M-2 Vref,M-2
σ INL M/2
σ INL M/2-1
...
σ INL M/2-2
Vref,1
Vref,1
R+ΔR1 Vref,0
Vref,0
R+ΔR0 ideal
references
VGND VGND Vid,0 Vid,1 ... Vid,M-1
a) b)
Figure 3.2: a) Block diagram of a mismatched resistive ladder. b)

Transfer characteristic curve of the mismatched resistive ladder where
the generated reference voltages Vref,k are plotted against the ideal
ones denoted as Vid,k . The standard deviation of INL, labeled as
σINL , is also plotted to illustrate the expected maximum INL error in
the resistive ladder.
resulting generated reference voltages are statically disturbed, i.e.,

they are superimposed with a set of static errors that are randomly
distributed over the passive components.
In this section, the effect of component mismatch is studied on
a simple reference ladder circuit which generates a set of equidistant
reference voltages. The reference ladder consists of resistive electrical
components. The loss in precision due to mismatched components is
expressed in terms of INL and DNL measures.
3.3.1 Mismatch in a reference ladder

The simplest way to generate an equidistant set of multi-reference
voltages is to use a resistive ladder as shown in Fig. 3.2 a). The refer-
ence voltages at both ends of the resistive ladder (denoted as Vref and
VGND ) are assumed to be ideal. The ladder consists of M resistors to
3.3. REFERENCE GENERATION CIRCUITRY 53
generate the references required for an equivalent blog2 (M )c-bit flash

ADC. Under ideal circumstances, i.e., no imperfection in fabrication,
the reference voltages can be expressed as
Vref
Vid,k = (k + 1)R k = 0, . . . , M. (3.5)
(M + 1)R
The accuracy of the resistor ladder is determined by the matching

characteristics between closely spaced resistors of the ladder [104].
Assume that each resistor Rk has an associated error ∆Rk due to
mismatch such that
Rk = R + ∆Rk k = 0, . . . , M,
where the errors ∆Rk are independently and identically distributed

with a standard deviation of σR = AR / (WR LR ). The resulting
reference voltages Vref,k [28, 104] can be expressed as
k
!
Vref X
Vref,k = PM (k + 1) · R + ∆Ri . (3.6)
(M + 1) · R + i=0 ∆Ri i=0
The expression in (3.6) shows that static errors of resistive ele-

ments accumulate along the ladder. Since static errors are assumed
to be independently and identically distributed with a finite variance,
the central limit theorem [105] states, that the probability distribution
of the sum approaches a normal distribution with a finite variance.
3.3.2 INL errors in non-ideal resistive ladders

Using the expression in (3.6) and assuming the ideal reference voltages
as given in (3.5), the INL can be calculated using (1.2) as follows:
INLk = Vref,k − Vid,k

" k M
#
Vref X k+1 X
= ∆Ri − ∆Ri . (3.7)
M + 1 i=0
PM
(M + 1)R + i=0 ∆Ri i=0
PM
With the assumption (M + 1)R i=0 ∆Ri and (M 1) which
holds for a long reference ladder used in medium- to high-resolution
multi-reference ADCs, the equation in (3.7) can be simplified to
" k M
#
Vref X k+1 X
INLk ≈ ∆Ri − ∆Ri . (3.8)
M + 1 i=0 M + 1 i=0
The standard deviation of INL for all generated reference voltages can
be calculated from (3.8) as
r n o
2 2
σINLk = E |INLk | − E {|INLk |}
s
k+1

Vref σR
= k 1− , (3.9)
M +1 R M +1
where E {.} denotes the expectation operator.

The standard deviation σINLk is statistically more informative than
the set INLk for all reference voltages. By setting the derivative
of (3.9) to zero, it can be shown that the maximum variance of INL
is at the code word M/2 which is also illustrated in the transfer
characteristic curve in Fig. 3.2 b).
Mathematically seen from (3.9), a relatively short resistor ladder is
favorable in practice. However, for medium- to high-resolution ADCs
long resistive ladders are imperative, e.g., an 8-bit flash ADC needs 28
reference voltages. Resistive interpolation, as described in Sec. 2.4.2,
is a commonly used technique to reduce the number of references used
in multi-reference ADCs and to shorten the length of the resistive
ladder.
3.3.3 DNL errors in resistive ladders

The DNL error in a non-ideal resistor ladder can be calculated from
the results found for the INL in (3.7) as follows:
DNLk = INLk − INLk−1
−1
" M
#
Vref ∆Rk 1 X ∆Ri
= + . (3.10)
M +1 R M + 1 i=0 R
3.4. MISMATCH IN SAR ADCS 55
The standard deviation of the DNL can be calculated analogously to

the one of the INL as
r n
2
o Vref σR
σDNL = E |DNLk | ≈ , (3.11)
M +1 R
where (M 1) is assumed in order to derive an appropriate approx-
imation for medium- to high-resolution ADCs.
As can be seen from the calculations of the standard deviation of
the INL and the DNL in (3.9) and (3.11), the linearity of a multi-
reference ADC connected to the reference ladder is distorted due
to mismatch between resistors. A first corrective action during the
design phase of the reference generation circuit can be performed by
proper sizing of resistors in order to reduce their mismatch and corre-
spondingly the resulting nonlinearity to an acceptable limit. Also, a
proper layout of the resistor ladder is essential to minimize systematic
mismatch and to generate precise reference voltages [93].
A common approach to reduce the impact of mismatch on the
reference ladder can be undertaken by connecting Vref,M/2−1 to an
accurate voltage buffer as it is already done with both ends of the
resistor ladder. This trick can also be done to other nodes of the
ladder to reduce the described static errors. The additional buffer,
however, increases the power consumption of the reference generation
circuit.
3.4 Impact of capacitor mismatch on SAR

ADCs
As already discussed in Sec. 2.3.1, the SAR ADC, as a representative
of single-reference ADCs, experiences capacitor mismatch. The im-
pact of capacitor mismatch on the performance of the SAR ADC is
analyzed and expressed in terms of INL and DNL in this section. For
the following nonlinearity calculations, the 2-bit SAR ADC illustrated
in Fig. 3.3 is considered. In order to simplify the equations, similar
to [106] each capacitor Ci is modeled as the sum of nominal (or unity)
capacitor Cu as
Ci = 2i · Cu + δi i = 0, . . . , Nres − 1.
Vin (t) Vtop Dout [kTs]

SAR
C2 C1 C0 C0 Dcomp,i
=4C u+δ 2 =2C u+δ 1 =Cu+δ 0 =Cu+δ 0
+Vref
Vcm
-Vref
Figure 3.3: Block diagram of a non-ideal 2-bit SAR ADC which

includes mismatch between the array capacitors.
The static errors δi in the capacitors Ci originates from the unity

capacitors. These errors are independent and identically distributed
random variables. The error term δi has a zero mean and a variance
of
n o
2
E |δi | = 2i σ02 , (3.12)
√
with σ0 = AC / WC LC .
For the k-th sampled ADC input, the term Dcomp,i ∈ {0, 1} rep-
resents the comparator decision for bit i. The ideal quantized analog
output voltage Vid [kTs ] of a binary weighted capacitor array with a
nominal resolution Nres bit can be formulated according to (2.6) as
Vid [kTs ] = Vin [kTs ] − Vtop [kTs ]
res −1
NX
Vref
= (−1)Dcomp,i 2i Cu . (3.13)
2Nres Cu i=0
Considering mismatch between capacitor, the analog output volt-
age Vout [kTs ] in (3.13) can be modified to
res −1
NX
Vref
Vout [kTs ] = (−1) Dcomp,i
2i
+

N −1
C u δ i ,
2Nres Cu + i=0
P res
δi i=0
which is simplified to
res −1
NX
Vref
Vout [kTs ] ≈ (−1)Dcomp,i 2i Cu + δi , (3.14)

2N res Cu i=0
3.4. MISMATCH IN SAR ADCS 57
PNres −1
assuming 2Nres Cu i=0 δi . Compared to the output of an
ideal SAR ADC in (3.13), all conversions of the non-ideal converter
in (3.14) are cumulatively disturbed by the mismatch of the same Nres
capacitors. Consequently, only the mismatch of the Nres capacitors
needs to be calibrated in practice. This observation is in contrast to
multi-reference architectures, e.g., in a flash ADC, the input-referred
offset of all 2Nres − 1 comparators needs to be calibrated in order to

enhance its effective resolution (see Sec. 3.5).
3.4.1 INL errors in SAR ADCs

The INL for the k-th digital code in the SAR ADC can be calculated
from (3.14) as
res −1
NX
Vref
INLk = Vout [kTs ] − Vid [kTs ] = (−1)Dcomp,i δi , (3.15)
2Nres Cu i=0
similar to [107] where INL is derived for a segmented capacitor array.

The variance of the INL can be written with (3.15) as
2 Nres −1
Vref σ02 X
2
= E |INLk |2 = 2N (−1)Dcomp,i 2i .

σINL
2 res Cu2 i=0
The variance σINL2

of the SAR ADC is dependent on the weighting
of the capacitor array. Assuming that the biggest change in INL
is expected [107] when the largest binary weighted capacitor in the
SAR ADC core is switched from the negative to the positive reference
voltage1 , leads to a standard deviation of
√
2Nres −1 σ0
σINL,max = Vref . (3.16)
2Nres Cu
Reducing INL errors leads to linearity improvements in ADCs. In or-
der to make the INL smaller than half of a LSB (INL ≤ Vref /2Nres +1 ),
the following requirement should be fulfilled:
√
Cu ≥ 2σ0 2Nres −1 .
1 The largest change in INL is expected from the code 0111 . . . 111 to
1000 . . . 000.
The requirements on the size of Cu changes with the resolution Nres of

the ADC. While in the design procedure of a low resolution SAR ADC,
the unity capacitor Cu is small-sized which is favorable in terms of
operating bandwidth, medium- to high-resolution SAR ADCs require
innovative calibration techniques to suppress the effect of mismatch.
3.4.2 DNL errors in SAR ADCs

The DNL in the SAR ADC can be calculated from the INL in (3.15)
as
DNLk = INLk − INLk−1
res −1
NX
Vref
= δ i (−1) Dcomp,i [kTs ]
2Nres Cu i=0
res −1
NX
Vref
− δ i (−1) Dcomp,i [(k−1)Ts ]
. (3.17)
2Nres Cu i=0
From (3.17) the standard deviation of the DNL follows as

√
2Nres − 1 σ0
σDNL = Vref . (3.18)
2Nres Cu
In order to target a DNL smaller than half of a LSB, the following
requirement should be fulfilled:
p
Cu ≥ 2σ0 2Nres − 1.
The size of Cu needs to increase with the resolution Nres . Increasing
the size of Cu , however, is not a practical solution to design medium-
to high-resolution SAR ADCs. Big capacitors decrease the signal
bandwidth of the converter. For realizing efficient SAR ADCs, again
calibration of capacitor values in the array is essential in practice.
3.5 Impact of mismatch on flash ADCs

A detailed analysis of the flash ADC is a necessity in practice to under-
stand the impact of mismatch on transistors and resistors in multi-
reference ADCs. All multi-reference converter architectures consist
3.5. IMPACT OF MISMATCH ON FLASH ADCS 59
Vref Vin (t) Vos,M-1

R+ΔRM Vref,M-1

R+ΔRM-1
Vos,1 Dout [kTs]
Vref,1
R+ΔR1 Vos,0
Vref,0
R+ΔR0
VGND
Figure 3.4: Component mismatch in a flash ADC.
of a comparison stage similar, if not equivalent, to the structure

embedded in the flash ADC. Particularly in the folding converter,
both the coarse and fine quantizers are based on the flash ADC.
The flash converter as described in Sec. 2.4.1 consists of a set of
parallel comparators which compares the input signal against refer-
ence voltages. These comparators are subject to an input-referred off-
set due to mismatch between their input pair transistors. As already
discussed in Sec. 3.3, the flash converter also suffers from mismatch
in its reference generation circuit which mainly consists of a resistor
ladder. The reference voltages are distorted statically by mismatched
resistors. A block diagram of the non-ideal flash ADC is depicted
in Fig. 3.4.
3.5.1 Offset in differential pairs

A major accuracy limitation in flash-based ADCs originates from
mismatch in the input pair of pre-amplifiers and comparators. The
derivation of the input-referred offset due to mismatch can be found
in App. B.1. The variance of the input-referred offset of a differential

pair [28] is given by
2
∆β ∆RL

ID
σ (Vos ) = σ (∆VTH ) +
2 2
σ 2
+σ 2
,
gm β RL
where ID is the drain current and gm the transconductance of the

input pair transistors. The term ID /gm gives an indication on the
operating region of transistors and decides on the overall performance
of analog circuits [108]. The offset is also partially determined by the
operating region of transistors.
For CMOS transistors operating in saturation, the mismatch of the
threshold voltage VT dominates over the current factor β mismatch,
and the resistor matching is also much better than the transistor
equivalent. Therefore, the standard deviation of the input-referred
offset of a differential pair can be simplified to
AV
σ (Vos ) ≈ σ (∆VTH ) = √ TH .
WL
Reducing the input-referred offset in differential pairs, requires the

increase of transistor size. Enlarging the area of the input pair tran-
sistors, however, translates into larger parasitic capacitors at their
inputs and leads to settling limitations.
3.5.2 INL errors in flash ADCs

The sources of nonlinearity in a flash ADC are shown in Fig. 3.4. The
INL of the flash ADC can be formulated as
" k M
#
Vref X k+1 X
INLk = ∆Ri − ∆Ri + Vos,k ,
M + 1 i=0 M + 1 i=0
where the first term in the equation originates from the reference
ladder given in (3.7) and the latter denotes the offset of the k-th
comparator.
3.5. IMPACT OF MISMATCH ON FLASH ADCS 61
The standard deviation of the INL can be calculated assuming that

mismatch in the reference ladder is statistically independent from the
one in the comparators as
s 2
k+1

Vref σR
σINL = k 1− + σ 2 (Vos ). (3.19)
M +1 R M +1
The maximum σINL can be found for k = M/2 where the reference
generation circuit experiences the largest accumulated mismatch.
3.5.3 DNL errors in flash ADCs

The DNL of the non-ideal flash converter can be formulated [104]
equivalent to (3.10) as
−1
M
!
Vref ∆Rk 1 X ∆Ri
DNLk = + + Vos,k − Vos,k−1 .
M +1 R M + 1 i=0 R
The standard deviation of DNL in a flash ADC can be calculated

assuming again that the mismatch in the reference generation circuit
is statistically independent from the one in the comparators and the
offset of the comparators are also statistically independent from each
other as
s 2
Vref σR
σDNL = + 2σos
2 . (3.20)
M +1 R
Since the standard deviation σos is directly dependent on the size of

transistors, increasing the dimensions of transistors solves the offset
problem partially. The offset voltage does not scale linearly with the
transistor area. The area needs to be quadrupled to halve the offset
at the input of comparators. An increase of transistor area does not
come for free. The power consumption of the converter needs to be
increased to a level such that settling errors do not dominate in the
performance of the ADC. Larger transistors demand for higher power
consumption. However, calibration can improve the performance of
these ADCs without the need of excessive power consumption and
area increase.
sampler quantizer
Dout(kTs )
encoder
Vin(t)
Figure 3.5: Basic operations of an ADC.
3.6 Generalized quantizers

In this section, a more general approach is shown to model the analog-
to-digital conversion process mathematically and to describe the per-
formance of generic ADCs in practice. Limits are derived for the
achievable maximum SNR and SNDR. The mathematical expressions
are essential in particular to understand beforehand the performance
limitations of generic medium- to high-resolution ADCs.
As illustrated in Fig. 3.5, the ADC can be broken down in two ba-
sic operations, namely sampler and quantizer. Dedicated S/H circuits
are used in practice to provide high performance sampler solutions
before amplitude quantization is performed. However, building high
performance quantizers is challenging in practice.
The main objective of this section is to find an analytical ex-
pression for the performance of the quantization process with respect
to mismatch. Since quantization is the basic function of all generic
ADCs, in a first attempt, an analytical performance metric is found
for the ideal quantization process. In the following, also the non-ideal
quantizer is studied and corresponding performance metrics are found
equivalently.
3.6.1 Process of ideal quantization

The transfer characteristic of the ideal and uniform quantizer is shown
in Fig. 3.6. The step size ∆y is commonly referred to as least signifi-
cant bit (LSB) since a change in the input signal level of one step size
∆x results in the change of one LSB in the binary coded output.
3.6. GENERALIZED QUANTIZERS 63
Q (w)
Δx
ξ (w)
Δy
Δy/2
w w
-3 Δx /2 - Δx /2 Δx /2 3 Δx /2
a) b)
Figure 3.6: a) Transfer characteristic curve of an ideal quantizer with

∆x = ∆y . b) Quantization error ξ(w) as a function of quantizer input
w.
Quantization introduces an error signal into the digital data stream,

denoted as ξ(w), which is simply the difference between the input w
and the output of the quantizer Q(w) as
ξ(w) = w − Q(w). (3.21)

The quantization error is shown in Fig. 3.6 b). The error is peri-
odic and has a maximum magnitude of ∆y .
The ideal quantization noise power can be calculated for ∆ =
∆x = ∆y according to
∆2
Z ∆/2
Pq = P (e) · ξ 2 dξ = , (3.22)
−∆/2 12
where ξ is considered as a random variable that is uniformly dis-
tributed between −∆/2 and ∆/2. The analog input is in the middle
of the code bin (see Sec. 1.1.1).
The average signal power (assuming a full-scale sinusoidal signal
as input) can be calculated for an Nres -bit ADC as
1 2
Ps = 2Nres −1 ∆ . (3.23)
2
With (3.22) and (3.23), the SNR follows as:

3 2Nres

Ps
SNR = = 10 log 2
Pq dB 10
2
= 6.02 · Nres + 1.76 dB. (3.24)
The required SNR to resolve Nres bit in the ADC has been calculated
in (3.24). In order to resolve a nominal resolution of Nres = 12 bit for
example, the ADC needs to achieve 74 dB of SNR.
3.6.2 Process of non-ideal quantization

The non-ideal quantizer is characterized by its DNL and INL errors,
which are both described by their probability density functions with
zero mean and standard deviations
σDNL ≥ 0 and σINL ≥ 0.
In the ideal quantizer, the standard deviations of INL and DNL

errors equal zero (σDNL = σINL = 0). As discussed in [16], the SNR
of quantizers is solely defined by their DNL and its distortion is
completely determined by their INL. For this reason, the impact of
DNL on the SNR and of INL on the overall SNDR are discussed in
the following.
Impact of DNL on quantizer SNR

To analyze the influence of DNL on the SNR of a non-ideal quan-
tizer, it is assumed, that two neighboring digital code words influence
each other when an error σDNL 2
≥ 0 is present between them [25].
The mathematical derivation of the total noise power due to DNL is
performed in App. D and is given as
∆2
PDNL = 1 + 3σDNL
2
(3.25)

.
12
However, missing codes (see Sec. 1.1.2) are neglected in this model.
Fig. 3.7 illustrates how the SNR is degraded with the DNL. A DNL
of ∆ results in 6 dB loss in SNR from the maximum achievable SNR
given in (3.24) for the ideal converter.
3.6. GENERALIZED QUANTIZERS 65
0
−2
−4
−6
SNR [dB]
−8
−10
−12
−14
0 ∆ /2 ∆ 3∆ /2 2∆ 5∆ /2 3∆
σ DNL
Figure 3.7: SNR degradation due to DNL errors. A DNL = ∆ results

in 6 dB SNR loss.
There exist also other mathematical models for the SNR degrada-
tion due to DNL with similar results [16] as well. The SNR can be
calculated taking the total noise power due to DNL into consideration
from (3.25) as

Ps
SNR = 10 log10
Pq + PDNL
= 6.02 · Nres + 1.76 dB − 10 log10 1 + 3σDNL
2
(3.26)

.
The expression in (3.26) shows that calibration methods only com-
pensating for INL errors, do not improve the SNR degradation caused
by the remaining DNL errors.
SNDR degradation due to mismatch

The results derived in App. D lead to an expression for the achievable
maximum SNDR of general non-ideal quantizers. The SNDR can be
calculated as

Ps
SNDR = 10 log10
Pq + PDNL + PINL
= 6.02 · Nres + 1.76 dB
− 10 log10 1 + 3σDNL
2
+ 12σINL
2
(3.27)

.
As seen in (3.27), the SNDR of a generic ADC is mainly limited by its

INL errors which dominate over the DNL. This information is essential
in practice when designing calibration methods for ADCs. Primarily,
the INL of the ADC must be corrected. However, the correction of
INL is not sufficient to achieve the maximum ENOB in the ADC. To
target the maximum achievable resolution in a quantizer, also DNL
errors needs to be corrected. Calibration and correction methods for
this purpose are discussed in Chap. 4.
3.7 Summary
For low-resolution ADCs, static errors from non-idealities in CMOS
fabrication processes are relatively insignificant. The higher the re-
quired precision, the more relevant the compensation of these errors
become. While certain error sources can be avoided by intelligent
design techniques, e.g., reasonable sizing of resistors to diminish the
effect of resistor mismatch, some others still remain and degrade the
accuracy of the underlying converter.
In this chapter, formulas for INL and DNL of a non-ideal SAR
ADC has been derived. In order to understand the source of static er-
rors in folding ADCs which consists of two sub-flash ADCs responsible
for resolving coarse and fine information, the flash ADC is analyzed
in detail. In order to understand general medium- to high-resolution
ADCs, a non-ideal quantizer is analyzed. The gathered results from
this analysis conclude that calibration and correction methods (which
are the subject of Chap. 4) are essential in practice to improve the
efficiency of such converters.
Chapter 4
Digital Calibration and

Post-Correction
This chapter focuses on calibration and correction techniques to com-

pensate for static errors in Nyquist-rate ADCs. The chapter starts
providing a background on well-established digitally-based calibration
techniques for Nyquist-rate ADCs. From the described digital calibra-
tion techniques, the three most promising candidates are studied for
the implementation in SAR and folding ADCs.
The largest field of digitally based calibration techniques is the
LUT based post-correction approach which is described here in detail.
However, many modern ADCs utilize a combination of calibration
and redundancy. Redundancy differs fundamentally from calibration.
Through redundancy the precision is preserved in the analog domain
of the ADC [109,110]. This can be achieved for example by increasing
the internal resolution of the ADC. A thorough discussion on redun-
dancy in single-reference ADCs is also provided in this chapter.
The chapter ends with the study of digital trimming/tuning of
analog circuits, which requires relatively less hardware resources to
be implemented in multi-reference ADCs if compared to redundancy.
Redundancy uses more analog information in the digital domain. For
this reason, redundancy implemented in multi-reference ADCs re-
quires a large number of additional comparators to increase the analog
67
68 CHAPTER 4. CALIBRATION AND POST-CORRECTION
precision at their outputs. Increasing the number of comparators leads

to an increase in power consumption and silicon area. For this reason,
redundancy is not suitable for multi-reference ADCs.
In literature, also analog calibration techniques exist to correct
static errors, e.g., auto-zeroing [28]. However, the discussion on pure
analog calibration techniques goes beyond the scope of this thesis.
4.1 Relevance of digital calibration tech-

niques in ADCs
The performance of ADCs is adversely affected by CMOS technology
scaling, specially if taking the reduction of supply voltage and the
low intrinsic gain of transistors into account. Hence, calibration and
correction techniques are essential to compensate for static errors
in modern CMOS processes. First attempts to correct component
mismatch in ADCs were performed by costly laser trimming [111]. In
addition to conventional laser trimming techniques, on-chip write-once
erasable programmable read only memory (EPROM) based methods
were reported in the past to correct mismatch [50]. Rapidly, efficient
digital trimming of mismatch and post-correction algorithms replaced
the correct-once methods with success as described in [112].
Nowadays, the research activities are likely motivated by Moore’s
Law [56] which states that digital circuits become smaller, more com-
plex, and power efficient. In literature, good design examples can
be found for all digitally calibrated Nyquist-rate single- and multi-
reference ADCs. Calibration circuits tend to move more into the digi-
tal domain where digitally-assisted calibration techniques trade digital
circuits for precision. For single-reference ADCs, efficient digitally
assisted algorithms have been used to estimate capacitor mismatch in
particular for SAR ADCs that has been published in [14,19,20,42,112].
Capacitor mismatch and finite amplifier gain in algorithmic (or cyclic)
ADCs have also been corrected digitally as reported in [113]. Also
the quality of digitized signals in pipeline ADCs have been improved
through calibration as described in [51–55, 57, 58].
For multi-reference converters, digitally assisted offset compen-
sation techniques have been reported for flash ADCs [59, 62]. The
4.2. LUT BASED POST-CORRECTION 69
Dref [kTs]
finite-state estimation
machine (FSM)
addressing LUT
Dlut[(k+d-1)Ts]
Vin (t) Draw [kTs] Dout [(k+d)Ts]
ADC core
Nint Nres
Figure 4.1: Digitally assisted calibration and post-correction tech-

nique based on a LUT. A dedicated FSM is necessary for the
controlling of the calibration process.
concept of digital trimming has been recently reported in a folding

ADC [27] where amplifier offset in the pre-amplification stage of the
converter has been tuned such to become negligible. Basic digital cali-
bration techniques for offset compensation in folding ADCs have been
reported in [28, 76, 77]. Digitally corrected two-step and subranging
converters have been published in [86, 114, 115].
In the following, different calibration techniques are studied which
are aimed at correcting Nyquist-rate ADCs.
4.2 LUT based post-correction

To achieve sufficient static accuracy in medium- to high-resolution
ADCs, calibration and post-correction based on a LUT [116–118] is
the frequently proposed method in literature which is discussed in the
following.
4.2.1 Operation principles

The basic idea of the LUT-based post-correction method is shown
in Fig. 4.1. In this digitally-controlled calibration circuit, the raw
output Draw [kTs ] of the ADC with internal resolution Nint is corrected
in the digital domain. In the illustration the LUT has two different
inputs. During calibration, the raw output Draw [kTs ] of the ADC is
used in the estimation function to train the LUT such that the LUT
entries required for post-correction improve the overall performance of
the calibrated converter. During normal operation, post-correction is
running in the background. In this mode of operation, the raw data is
used to find an optimal LUT entry using the addressing function. The
output of the LUT, denoted as Dlut [kTs ], is used to perform on-line
correction on the sampled raw data. A dedicated FSM is used to
control the calibration and post-correction processes. The calibration
is performed either as a fore- or a background process [28]. Foreground
calibration is either run during power-up of the ADC or on demand
(if an update of LUT entries is necessary due to on-chip temperature
variations). Background calibration trains the entries of the LUT in
the background and is transparent to the normal ADC operation.
After the calibration has completed, i.e., when the entries of the
LUT have been well trained, post-correction is performed. The output
of the LUT is either added to or replaced by the raw data Draw [kTs ]
in order to build the corrected output of the ADC [116, 119] which
has nominal resolution Nres and is denoted as Dout [kTs ] in Fig. 4.1.
During post-correction, the digital output samples of the ADC are
optimized using the entries of the LUT such that the overall linearity
of the converter is improved as shown in Fig. 4.2. Through post-
correction, non-linearity errors (expressed in INL) are minimized.
However, the code transition levels (see Sec. 1.1 for the definition) in
the transfer characteristic curve of Fig. 4.2 are not modified digitally.
If the amount of analog information in the digital domain is limited
through missing granularity of digital codes, i.e, Nint = Nres , then
DNL errors cannot be corrected digitally. The LUT based calibration
technique is transparent to missing codes of the ADC. It is advan-
tageous in practice to design the ADC such that Nint > Nres (by
enhancing the internal resolution of the ADC or adding redundancy
in the quantizer circuit), in order to correct also DNL errors as well
(see Sec. 4.3 for more details). The introduction of redundancy in the
ADC reduces the probability of missing code occurrences. As stated
in Sec. 3.6.2, the maximum ENOB of the ADC can only be acquired
if INL as well as DNL errors are corrected.
4.2. LUT BASED POST-CORRECTION 71
Dout [kTs]
Draw [kTs]
Dout [kTs]
before calibration
after calibration
Vin (t)
Figure 4.2: LUT based post-correction where the raw output of the
ADC (denoted as Draw [kTs ]) is replaced by the trained LUT entries
with Nint = Nres . The corrected output of the ADC is denoted as
Dout [kTs ].
4.2.2 Addressing function
During post-correction, if using the raw output Draw [kTs ] of the ADC
to address the LUT entries, an addressing function is required to
search for the best candidate Dlut [kTs ] to be corrected with. The
addressing function in this case is not only used during calibration
to train the LUT but also decides on the performance of the post-
correction. In order to express the performance of the post-correction
properly, an error measure is needed to decide on the optimal LUT
entry Dlut [kTs ] which depends on Draw [kTs ].
Most commonly used error measures are based on the distance

between the output of the post-correction function and the ideal (non-
disturbed) ADC output Dideal [kTs ]. The absolute error measure is
defined as follows:
|Dout [kTs ] − Dideal [kTs ]| .
In practice, however, the resolved data of the ADC is noisy and should
be described statistically. Therefore, the addressing function in the
post-correction circuit needs to find an optimal LUT entry according
to the minimal mean-squared error defined as
n o
2
D̂lut,opt [kTs ] = arg min E |Dlut [kTs ] − Dideal [kTs ]| ,
Dlut [kTs ]
in case if Draw [kTs ] is directly replaced with the optimal LUT output
as
Dout [kTs ] = D̂lut,opt [kTs ].
If the output is built by summation of Draw [kTs ] and D̂lut,opt [kTs ],

then the addressing function needs to find the optimal LUT entry
according to
n o
2
D̂lut,opt [kTs ] = arg min E |Dlut [kTs ] + Draw [kTs ] − Dideal [kTs ]|
Dlut [kTs ]
and the output of the ADC is corrected as

Dout [kTs ] = D̂lut,opt [kTs ] + Draw [kTs ].
Depending on the architecture of the ADC, it is favorable for certain
types of converters to compress the data stored in the LUT, i.e., only
the distance
|Draw [kTs ] − Dideal [kTs ]|
is stored in the LUT. An arithmetic computation unit is provided to
add the LUT entry to the raw output of the ADC on the fly. Storing
only the distance with reduced word size is desired in practice, when
the LUT is big, i.e., its address space is relatively large. LUTs with a
small address space can store the corrected output directly. Then the
arithmetic computation unit is not required anymore.
4.3. REDUNDANCY 73
4.2.3 Estimation function

The main task of the estimation function is to update the entries of the
LUT during calibration such that the LUT can optimally be trained
for post-correction. This function can either be run at start-up in a
foreground calibration or as a background process in order to update
the LUT continuously.
When running calibration during power-up, the estimation func-
tion needs a reference sequence at its input to train the entries of
the LUT. It is important to design the calibration routine carefully
such that the post-correction circuitry is not biased towards a specific
calibration reference signal. Otherwise, the ADC is well optimized to
resolve signals with similar probability density function.
Indeed, the entries of the LUT must be trained using a calibration
reference sequence with a uniform probability density function (e.g.,
a stochastic reference signal) to yield unbiased results [118, 120, 121].
One possible implementation of the reference based estimation func-
tion is discussed in Chap. 6 which applies a reference sequence with a
uniform probability density function.
Running the estimation function in the background means that
the converted raw signal of the ADC is continuously used to train the
LUT. A possible solution of the reference-less estimation function is
discussed in Chap. 5.
4.3 Redundancy
Many modern ADCs utilize a combination of calibration and redun-
dancy [20, 122] in their architecture. Redundancy differs from cal-
ibration in the sense that errors in the analog are corrected in the
digital domain through preservation of the analog precision [109,110].
Redundancy in the ADC architecture is often required to make certain
calibration techniques work at all.
The combination of redundancy with post-correction (as discussed
in Sec. 4.2) is powerful in a sense that the granularity of the transfer
characteristic of the ADC is increased through the introduction of
redundant information in the digitized analog signal. In this case,
Dout [kTs]
Draw [kTs]
Dout [kTs]
before calibration
after calibration
Vin (t)
Figure 4.3: LUT based post-correction where the raw output of the
redundant ADC (denoted as Draw [kTs ]) is corrected by the trained
LUT entries. The corrected output of the ADC is denoted as
Dout [kTs ]. Compared to Fig. 4.2, also transition levels between the
digital codes are corrected due to redundancy.
post-correction not only corrects the code levels, but also the transi-
tion levels between the codes as shown in Fig. 4.3.
Including redundancy in the converted signal comes unfortunately
not for free. Still, some ADC architectures benefit more from it than
others. In particular, single-reference ADCs following an iterative
search algorithm to perform their conversion algorithm (as described
in Sec. 2.3) can simply be modified to implement redundancy. This
will be explained in Sec. 4.3.1.
In literature, many forms of redundant single-reference ADCs have
been reported. Sub-radix-2 weighted SAR ADCs [20, 123] explore
redundancy based on the beta-expansion as explained in Sec. 4.3.1.
Other redundant SAR conversion principles are used in [124, 125].
4.3. REDUNDANCY 75
Cyclic ADCs, i.e., algorithmic or pipeline converters, using beta-

expansion are proposed in [126].
Multi-reference converters require multiple comparators to provide
redundancy in the digital output of the converted analog signal [109,
127]. The reason why redundancy has limited use in multi-reference
architectures comes with the increase in power consumption and sili-
con area with the introduced redundant comparators. For this reason,
other techniques than redundancy are employed for multi-reference
ADCs to make them better calibratable. One of these techniques is
discussed in Sec. 4.4.
4.3.1 Redundancy in beta-expansion

A first attempt to introduce redundancy in single-reference ADCs is
discussed in the following. As reported in [128], beta-expansion [129]
contains redundancy. It can be used to implement efficient single-
reference ADCs that are less sensitive to component non-idealities.
The quantized analog input signal V̂in of a single-reference ADC
with nominal resolution Nres is expressed as
N
Xres
V̂in = Vref bi 2−i , (4.1)

i=1
with bi ∈ {−1, 1} denoting the i-th decision of the iteratively resolved

output and |Vin | ≤ Vref . The radix used in here is 2.
In order to analyze the effect of redundancy on the ADC, the
information content or entropy of the ADC is calculated. The entropy
according to [130] is expressed for a generic quantizer as
2NX
res −1
H=− pj log2 pj ,
j=0
with probability of occurrence pj for each digital output code j.

Assuming that all digitized outputs of the single-reference ADC

with radix 2 have the uniform probability pj = 1/2Nres , the informa-
tion content of the quantizer can be obtained as
2NX
res −1
1 1
H=− log2 Nres = Nres , (4.2)
j=0
2Nres 2
which states that the quantizer resolves Nres bit of information.

According to the beta-expansion [129], the quantized analog input
in (4.1) can also be reformulated as
M
X
V̂in = Vref bi β −i , (4.3)
i=1
with bi = {−1, 1}, 1 < β ≤ 2, and β denoting the so-called sub-binary

radix. Instead of resolving the analog input in binary conversion
cycles, a sub-binary radix (smaller than 2) is used in order to digitize
the signal. Indeed, the sub-binary radix needs more conversion cycles
to achieve equivalent precision.
The information content for the sub-binary radix based on beta-
expansion can be computed similar to the binary quantizer in (4.2)
as
M
βX −1
1 1
H=− log2 M = M log2 (β). (4.4)
j=0
βM β
As can be seen in (4.4), the higher the number of cycles M per

conversion, the more information is generated. Implementing an ADC
using the beta-expansion in (4.3) can be of great interest if an increase
of information content is desired at the output of the ADC and in
order to create redundancy. However, the introduction of a sub-binary
radix to create redundancy requires M > Nres cycles per conversion
to resolve the analog signal, which is dependent on the value of the
chosen sub-binary radix (β < 2). To express the relationship between
the number of cycles M per conversion, the sub-binary radix β, and
the targeted nominal resolution Nres of the redundant ADC, the in-
formation content in (4.2) is set equal to (4.4) as
Nres ≤ M log2 (β),
4.3. REDUNDANCY 77
which states, that a small sub-binary radix β is compensated by a large

cycle M per conversion to achieve the same amount of information
created by the non-redundant radix-2 architecture. The amount of
redundancy depends on how much smaller the sub-binary radix β is
compared to the binary radix [110].
4.3.2 Beta-expansion in SAR ADCs

The radix-2 SAR ADC generates one bit information per conversion
cycle while always relying on the fact that the comparator decision
is correct [131]. However, slow settling or non-binary weighting of
the capacitor array due to mismatch lead to wrong decisions in the
successive approximation algorithm. In practice, redundancy enables
the correction of wrong decisions made by the comparator.
In a redundant conversion algorithm, the iterative binary succes-
sive approximation of (2.2) is modified to
Vref
Vi+1 = Vi − sgn (Vi ) i = 1, 2, . . . , M (4.5)
| {z } β i
Dout,i [kTs ]
with the sub-binary radix 1 < β ≤ 2, the reference voltage Vref , the
analog residue Vi+1 of the (i + 1)th iteration cycle, and V1 = Vin [kTs ].
The decision made by the signum function (denoted as Dout,i [kTs ]
in (4.5)) corresponds to the digital output of the SAR ADC.
Due to the smaller amount of information per conversion cycle
given by the sub-binary radix β, a full analog-to-digital conversion
requires more than Nres cycles to achieve a resolution of Nres bits
which is denoted as M and given by the relation

Nres
M= .
log2 β
The redundancy can be built directly in the capacitor array of the

SAR ADC. The redundant search algorithm improves the dynamic
performance of the ADC and the settling speed. A certain level of
settling error can be tolerated in the ADC. The output of the ADC
can be recovered during post-correction through redundant digital
information available at the output of the converter.
VDD
- +
Iout RL RL Iout
- +
Vout Vout
Vos
- M1 M2 +
Vin Is Vin
Rs
- +
Ical Ical
Figure 4.4: Implementation of input-referred offset trimming circuit

in a fully differential transconductance amplifier [132].
Static accuracy requirements, e.g., capacitor matching, are not re-

laxed through redundancy. Thus, calibration of the capacitor weights
is still essential in practice.
4.4 Digital self-trimming circuits

Since redundancy cannot be efficiently implemented in multi-reference
ADCs, e.g., flash and folding converters, there are also other methods
to improve the performance of an analog circuit. Since mismatch
is time-independent (excluding temperature variations), digital trim-
ming/tuning of analog circuits can improve the static precision of
ADCs by adding additional circuit complexity in the analog domain
which is digitally controlled [16, 28, 30, 132]. Correcting static errors
in the analog domain is equivalent to trimming the offset of amplifiers
or comparators such that their input-referred offset is negligible.
In Fig. 4.4, a slightly modified fully differential transconductance
amplifier is shown where a separate tail current source for each dif-
ferential branch is used. A source degeneration resistor Rs is inserted
between the differential branches. The tail current sources in this
VDD
- +
Iout RL RL Iout
- +
Vout Vout
Vos
Vcm
M1 M2
Is
SA
- Rs +
Ical Ical
Din[N-1] Din[N-1] Din[0] Din[0]

Din
... VGND VDD
4.4. DIGITAL SELF-TRIMMING CIRCUITS
2 N-1 Iu 2 N-2 Iu 2 N-3 Iu Iu 2 N-1 Iu

VGND
Figure 4.5: Block diagram of a tunable fully differential transconductance amplifier including digital
successive approximation (SA) logic in the feedback to approximate the input-referred offset voltage
Vos [132].
79
transconductance amplifier are digitally programmable. During cal-

−
ibration, the currents Ical
+
and Ical are tuned such that the overall
input-referred offset of the amplifier approximates zero. With this
digitally assisted trimming technique, the offset of the amplifier is
compensated by the voltage drop over the degeneration resistor Rs .
4.4.1 Working principle

A detailed block diagram of the digitally tunable transconductance
amplifier is depicted in Fig. 4.5 where its inputs are shorted and
connected to a common analog ground denoted as Vcm and its output
is sensed with a comparator during calibration.
The tunable tail current sources are built with a unity current
source Iu . A set of N binary weighted tail current sources are provided
to be controlled digitally and represent an N -bit DAC. Digital ad-
justing of tail current sources is performed such that binary weighted
−
currents are added/subtracted to the branch currents Ical +
and Ical .
The value of Iu must be chosen properly such that the compensated
offset becomes negligibly small and does not influence the linearity of
the amplifier when used in a medium- to high-resolution ADC.
A successive approximation (SA) logic is used to evaluate the
output of the comparator and search for the value of the analog offset
voltage Vos . The output of the SA adjusts the tunable tail current
sources of the amplifier.
Tunable transconductance amplifiers or comparators are in par-
ticular interesting for ADC architectures where their performance is
mainly limited by offset. Especially, multi-reference ADCs are relying
on this technique as reported in [16, 27, 28]. The advantage of the
digital trimming technique is that power consumption of the ADC
employing this technique is not increased. During start-up, the digi-
tally implemented SA logic can be activated to search for the correct
values of the tail current sources in order to compensate for mis-
match. In particular, multi-reference ADCs built of cascaded stages
profit from digital trimming, e.g., cascaded folding and interpolating
ADCs [27]. In these architectures, the critical stages of the ADC can
be equipped with tunable analog circuits while the remaining stages
can still be corrected using a LUT based post-correction technique.
4.5. CONCLUSIONS 81
An implementation of the described method for a medium-resolution

ADC is reported in Chap. 6.
A disadvantage of the digital trimming technique, however, is the
increasing routing complexity from the SA logic to the adjustable
tail current sources. The noise contributed by the adjustable tail
current sources on both branches of Fig. 4.5 are independent of each
other. These noise sources have a bigger impact on the overall noise
performance of the amplifier compared to a simple (non-adjustable)
differential pair. In the simple differential pair, the tail current noise
can be see as common mode disturbance which is canceled in a fully
differential circuit configuration. The noise contribution of adjustable
tail current sources can be seen as another disadvantage of the digital
trimming technique.
4.5 Conclusions
This chapter focuses on the three most promising techniques, i.e., the
LUT-based post-correction approach, redundancy, and digital trim-
ming, in order to correct static errors in an ADC. The LUT-based
post-correction approach trains the LUT entries during calibration
and uses the trained LUT to correct the raw output of the ADC.
The combination of redundancy and post-correction is powerful
in a sense that the granularity of the ADC transfer characteristic is
increased through redundant information in the digital output. For
this reason, post-correction can also be able to correct the transition
levels between the codes. Redundancy combined with a LUT based
post-correction technique is used in the implemented SAR ADC which
is described in Chap. 5.
While single-reference converters widely use redundancy in their
architectures, multi-reference ADCs require additional comparators
to preserve the analog precision. Digital trimming is used instead in
these architectures. A digital post-correction algorithm is optimized
for folding ADCs and implemented in CMOS as described in Chap. 6.
Chapter 5
A 14 bit SAR ADC with

On-Chip Digital
Calibration
5.1 Introduction
In this chapter1 , two different prototypes of a 14-bit sub-radix-2 SAR
ADC are presented in a 130-nm CMOS technology [14, 133] employ-
ing a redundant segmented capacitor array with a merged capacitor
switching scheme [134]. An optimized non-uniform clocking scheme
is proposed that reduces the conversion time by more than 50 %
compared to a traditional clocking, for the same sampling capacitance.
A perturbation-based LMS start-up calibration and post-correction
technique [135] has been implemented directly on chip to correct the
mismatch of capacitors digitally and enhance the effective resolution
by more than 10 dB.
The prototyped ASICs are denoted as Prototype I and II through-
out this chapter. Prototype I achieves 71.1 dB SNDR (11.5 bit) at
1 A part of the material presented in this chapter is an excerpt from S. Fateh
et al., “A Reconfigurable 5-to-14 bit SAR ADC for Battery-Powered Medical

Instrumentation,” TCAS I, © 2015 IEEE.
83
84 CHAPTER 5. A 14 BIT SAR ADC
2 MS/s with a power consumption of 0.92 mW. At 4 MS/s, the con-

verter achieves 65.5 dB SNDR (10.6 bit) with a power consumption
of 1.78 mW. The converter does not require a reference sequence to
perform calibration. Instead, it uses the input signal of the converter
to measure/estimate its capacitor weights. Since the SAR ADC is
scalable with CMOS technology, it is a suitable alternative solution
to Σ∆ based ADCs in mobile communications.
In prototype II, the non-uniform clocking scheme is extended to
be reconfigurable that renders the SAR ADC energy efficient over a
wide range of resolutions and signal bandwidths [136]. In particular
for battery-powered biomedical applications, the resolution and signal
bandwidth of the ADC have to be adapted to the needs of an appli-
cation to avoid power wastage. For this reason, the capacitor array
of Prototype I is redesigned in order to be highly flexible, allowing
capacitors to be disconnected from the array for applications requiring
lower resolutions. A typical application could be a multi-channel,
multi-functional, and battery-powered medical instrumentation. Pro-
totype II uses a resistor ladder based reference sequence generation
circuit to perform calibration. Since the input of the converter, i.e.,
biopotential signals in medical instrumentation, have small ampli-
tudes, they are not well dedicated to serve as a calibration reference.
Besides calibration also other digital resolution enhancement tech-
niques, such as non-subtractive dither [137], majority voting [138],
and oversampling are implemented on chip to improve the accuracy
of the SAR ADC. The converter is as accurate as required for a desired
application and is able to remain in a reset state where no power is
consumed in the ADC core in order to minimize the overall power
consumption. The overhead given by the reconfigurability in the ADC
is minimal in the digital domain (if compared to protoype I) with the
exception of few logic gates in the analog domain to provide additional
switches for disabling capacitors when targeting lower resolutions.
Reconfiguration in the ADC is essential in biomedical applications to
enhance the lifetime of the battery. The proposed ADC can be tuned
to operate at ultra low-power to only fulfill minimal specifications on
the signal quality, e.g., when awaiting activity or a specific pattern in
the biopotential signals. The system, however, is able to recover full
performance if required, e.g., when activity or the specific pattern is
detected. Measurements of the fabricated reconfigurable SAR ADC
5.2. ARCHITECTURE OF PROTOTYPE I 85
show an ENOB of 12.9 bit at a sampling rate of 286 kHz with a FoM of
59 fJ/conversion. Using non-subtractive dither, the achievable ENOB
of prototype II is enhanced to 13.5 bit.
In the following sections, the cores of the SAR ADC in both
prototypes are discussed in more details.
5.2 Architecture of Prototype I

The fully-differential schematic of the implemented SAR ADC core
in Prototype I is depicted in Fig. 5.1. It consists of a capacitive
DAC, a 1 bit dynamic comparator, a SAR control logic and a digital
calibration unit. The segmented 14-bit capacitor array employs the
merged capacitor switching scheme proposed in [134]. The calibration
circuit in Protoype I can either be run at start-up while updating its
capacitor values after power-up, or as background calibration.
The input signal is directly sampled onto the comparator input
by means of a bootstrapped [139] sampling switch Ssample . In order
to tolerate up to ±6 σ capacitor mismatch without affecting linearity
and to avoid missing codes, redundancy is introduced directly into
the capacitor array by sub-radix-2 weighting of the single capacitors
(see Sec. 4.3). The negative and positive voltage references have
been chosen as V− ref = 0.2 V and Vref = 1.0 V respectively in the 1.2 V
+
implementation, leading to a maximum input signal swing of 1.6 VPP .

The frequency of the global clock in the SAR ADC is denoted as
fclk . The synchronous high speed clock is used in the digital domain
of the ADC to derive the clock phases in order to control the analog
switches of the capacitor array using integer numbers of cycles of the
global clock. The sampling frequency of the SAR ADC is denoted as
fs and is derived from the global clock too.
5.2.1 Capacitor array

The power consumption in a SAR ADC core is mainly dominated
by the comparator and the SAR logic (when excluding the reference
buffers). Details on the comparator are discussed in Sec. 5.2.4.
The capacitor array in the SAR ADC is based on the principle
of charge redistribution in the condition of preserved total charge
86
s sample
+
Vin
-
LSB-Array MSB-Array Vin
+
Vref
Vcm Dout
-
Vref
s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s 10 s 11 s 12 s 13 s 14 s 15 sp
C att
s rst Cu C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C 10 C 11 C 12 C 13 C 14 C 15 Cp
+ digital
b in
SAR calib.
- unit
s rst Cu C0 C1 C2 C3 C4 C5 C6 C7 C att C8 C9 C10 C11 C12 C13 C14 C15 Cp
s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s 10 s 11 s 12 s 13 s 14 s 15 sp
+
Vref
Vcm
-
Vref Perturbation
Capacitors
T sample
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40/0
Normal
Sampling S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 rst
Conversion
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Sampling S15 & + Pert. S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Calibration
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80/0
Mode
Input Regeneration S15 & - Pert. S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 rst
Figure 5.1: Schematic of the 14-bit sub-radix-2 SAR ADC core used in Prototype I with merged capacitor
switching scheme (top) and corresponding timing diagram (bottom).
CHAPTER 5. A 14 BIT SAR ADC
(top-plate). Thus, the original, sampled voltage, can be restored by

resetting all bottom-plate switches to their intial state. This enables
perturbation injection during calibration. In order to prevent any
charge accumulation on floating nodes, all capacitors are reset once
per conversion to the common-mode voltage. All capacitors in the
LSB and most-significant bit (MSB) arrays are integer multiples of
the unity capacitor Cu , which facilitates the layout of the capacitor
array and also helps to reduce the systematic mismatch.
In the realized SAR ADC, a 14-bit differential segmented capaci-
tor array [140] with 8 LSB and 8 MSB capacitors is designed with
a merged capacitor switching scheme [134]. For better immunity
to capacitor mismatch, a non-binary weighted sub-radix-2 ratio ca-
pacitor array is implemented to build redundancy in the resolved
digital output of the ADC (see Sec. 4.3). The SAR approximation
steps are slightly lower due to redundancy than in case of binary
search and a full conversion requires 17 cycles. Redundancy ensures
a correct approximation of the sampled voltage to zero in presence
of mismatched capacitors. This prevents missing codes and preserves
linearity. Furthermore, redundancy allows incomplete settling and
thus can reduce conversion time although it increases the number of
comparisons and approximation steps [136].
5.2.2 Unity capacitor Cu

The proper choice of the unity capacitor size gives a trade-off between
capacitor mismatch, converter bandwidth, and thermal noise [14].
The larger the size of the unity capacitor, the smaller the relative
capacitor mismatch becomes (see (3.4)). However, an increased value
of the unity capacitor Cu leads to a larger RC constant which reduces
the sampling rate of the converter and increases its power consump-
tion. Moreover, a larger unity capacitor requires more silicon area to
be occupied and therefore increases the chip fabrication costs.
Assume that the capacitor array is designed such to be immune to
about 3 % capacitance mismatch (covering 6 σ capacitance mismatch).
Matching and thermal noise considerations led to the choice of a total
sampling capacitance of Cs =11 pF divided into 50 fF unit elements.
This results in a maximum achievable SNR of 86 dB in the capacitor
array.
C15 C7
C14 C6
C15
C13 C5
C12 C4
C11 C3
C10 C2
C9 C1
C8 C0
CP C att
Figure 5.2: Single-ended capacitor array with an area of 120×230 µm2 .

The white space at the edges of the capacitor array denotes dummy
capacitors. In Prototype II, certain dummy capacitors are used to
generate the non-subtractive dithering sequence.
In order to reduce the systematic mismatch (see Sec. 3.1.2) of the

capacitor array, the layout structure depicted in Fig. 5.2 is chosen
such that the routing overhead to connect the capacitors to the rest
of the ADC circuit is minimized as well.
5.2.3 Flexible clocking scheme

The bandwidth of high-precision SAR ADCs is usually limited by
the settling behavior of the voltage at the input of the comparator,
which in turn is determined by the sampling capacitance and the on-
resistance Rsw of the switches. A conventional N -bit capacitor array
requires at least N identical cycles for a single conversion. However, as
the voltage on the capacitor array reduces by the radix β ≤ 2 at each
conversion step, the settling time for a given settling error ε scales as
well according to
−
Tsettl = Cs Rsw · log V+ ref − Vref / (εβ) .

The allotted time can be for instance reduced by about 30 % every

3 steps for a resolution of 12 bit. Fortunately, redundancy allows
the converter to tolerate even a larger settling error as described
in Sec. 4.3. Therefore, the allocated time can be reduced even more
- +
Vm clk Vm
- +
Vin M1 M2 Vin
clk
VDD
+ -
Vout Vout
VGND
Figure 5.3: Schematic of the double-tail latch [136].
aggressively. The bottom half of Fig. 5.1 shows the timing diagram
of the proposed SAR ADC. One complete normal conversion (i.e.,
calibration is off) allocates 6 clock cycles (Tsample ) for sampling of the
input, 3 cycles for the second phase, and 2 for each of the remaining
15 phases. The conversion time can be dramatically reduced by
employing a decreasing number of cycles, at the price of an increased
complexity in the clocking circuitry. The internal clock is set to
fclk = 160 MHz in order to achieve a fs = 4 MS/s sampling rate. In
practice, the maximum affordable clock frequency limits the scaling
of the allotted time to the first two phases only. Note that the
same 14-bit capacitor array would require 17 Tsample cycles to perform
one conversion with a uniform clocking scheme, whereas it needs
6.7 Tsample cycles in the proposed design. Therefore, the conversion
speed more than doubles with the proposed approach.
5.2.4 Comparator design

A high-bandwidth fully-dynamic double-tail latch (DTL) composed
of a pre-amplifier and an output latch has been chosen as comparator
ADC core
bootstrap capacitor array comparator
switch (sub-radix-2, 16 caps)
data
Vin(t)
correction
SAR
serial output test interface

...
BS-driver
calibration
Vref_int
+
Vref
+
Vcm_int
Vcm -
Vref_int memory
memory
Vref- config.
...
controlling
reference buffers SPI
6-bit
R-ladder DAC digital circuitry
Figure 5.4: Architectural level block diagram of Prototype II. The

memory contains both registers used by the calibration circuit and
for the configuration of the analog and digital circuits [136].
[141–143], and is depicted in Fig. 5.3. The dynamic pre-amplifier

together with the inverter provides a limited gain (∼10) that reduces
the input-referred offset of the regenerative stage, allowing the use
of small and fast transistors in the latter. Furthermore, it reduces
the kick-back noise of the latch from propagating backwards into the
capacitor array. A single clock signal (clk) is sufficient to control the
reset (clk = 0 V) and the latch phase (clk = 1.2 V).
5.3 Architecture of Prototype II

This section describes the architecture details of Prototype II as illus-
trated in Fig. 5.4. The SAR ADC core consumes only dynamic power
and consists of a capacitor array, a comparator, and a SAR logic.
The positive, negative, and common-mode references are buffered on
chip where details on the implementation of the buffers can be found
in [136]. In Prototype I, the reference buffers were missing on chip.
5.3. ARCHITECTURE OF PROTOTYPE II 91
dithering
Dcomp,i Vin (t) capacitor Dcomp,i
+ array +
*
σ02 average decision
by N
Vin (t) capacitor array with Dcomp,i

* dithering capacitors
σ02
a) N b)
Figure 5.5: a) The impact of majority voting on comparator noise. b)

Generation of a dithering sequence directly in the capacitor array of
the SAR ADC.
A 6-bit resistor ladder DAC enables autarkic calibration, which is

crucial when the ADC is used in a system which does not guarantee
a sufficiently conditioned input signal at start-up when calibration is
enabled. Compared to Prototype I, the converter cannot be run in a
background calibration mode. In particular, the LMS based start-up
calibration is not well-suited for acquiring biopotential signals that
have a signal component with small amplitude superimposed to a
slowly moving large offset. Thus, the LMS based start-up calibration
imposes only two conditions to the input signal during calibration:
a coverage of the input signal range which ensures that all capac-
itors of the array toggle. Thus, there are no constraints on the
linearity and the noise level of the reference signal. Indeed, circuit
noise can be beneficial in this case since it increases the amount of
distinguishable input values, which allows for a fairly simple circuit
realization. Details on the circuit implementation of the resistor
ladder DAC can be found in [136]. During calibration, a triangular
wave is generated by the resistor ladder. The step size and input range
of the calibration sequence can be controlled over serial peripheral
interface (SPI). Reference buffers, a calibration circuitry, a resistor
ladder DAC, and a SPI interface are implemented on-chip and serve
as auxiliary circuitry to the SAR ADC core.
MSB Capacitor Array LSB Capacitor Array
Perturbation Capacitors
sample
... 1.25C0 ...
input 8 caps, 9 caps,

3C0 103C0 ... C0 60C0 ...C0
sub-radix-2 sub-radix-2
... ...
...
C0
8 caps,
C0 C0 C0 C0 0.2C0 ... 1.2C0
uniformly distr.
...
Attenuation Capacitor
Vref−
Vcm
Vref+
Dithering Capacitor Array
Figure 5.6: Detailed schematic of the capacitor array in Prototype II.

The sub-radix-2 split-array design of Prototype I is extended featuring
a dithering array to further enhance the resolution of the SAR
ADC [136].
5.3.1 Noise reduction techniques

The SAR ADC offers a highly flexible conversion algorithm which
supports noise reduction techniques. A first method to reduce com-
parator noise in SAR ADCs is majority voting [33,144]. The drawback
of majority voting is, however, the slight increase of conversion time.
In biomedical sampling systems, where the sampling frequency is rel-
atively low, indeed the conversion time overhead is negligible. For this
reason, majority voting is implemented in Prototype II, to minimize
the noise of the comparator in order to enhance the resolution of the
converter. A block diagram of the majority voting implementation is
shown in Fig. 5.5 a). Assuming that the input-referred noise variance
of the comparator equals σ02 . Majority voting uses N comparison

outputs of the comparator and makes a decision based on the majority
of the multiple comparisons. The consequence of majority voting is
that the input-referred noise variance of the comparator is reduced by
the comparison factor N . Since the noise is less critical for the first bit
cycles (MSBs), majority voting is only performed for the LSBs. The
number of votes for the LSBs can be optimized during measurements.
To further enhance the resolution of Prototype II, non-subtractive
dither [137] is added to the sampled signals. Fig. 5.5 b) shows its
implementation. Basically, non-subtractive dither allows oversam-
pling of an already sampled signal by slightly modulating the latter
from conversion to conversion with a zero-mean pseudo-random signal.
Similar to real oversampling, this virtual oversampling results in a
quantization noise reduction, but in contrast to the former not in
a reduction of the sampled kT /C thermal noise. The advantage
of dithering is that it can easily be realized in practice by adding
additional small capacitors in the array of the SAR ADC as shown
in Fig. 5.2, in order to add a small perturbation to the sampled signals.
5.3.2 Flexible capacitor array

The capacitor array used in Prototype II is slightly modified compared
to the one used in Prototype I and is illustrated in Fig. 5.6. Matching
and thermal noise considerations led to the choice of a total sampling
capacitance Cs =14.9 pF, divided into Cu =70 fF unity capacitors with
σCu =0.38 %. This results in a theoretical upper SNR of 87.6 dB which
is limited by thermal noise. Quantization noise clearly dominates and
lowers the theoretical SNR to 85.3 dB for conventional conversions.
In the presented implementation, a deterministic dither sequence
of 8 levels is injected to the capacitor array after sampling [33, 144].
The array is extended with additional capacitors, while a simple dig-
ital counter generates the desired dither sequence. The dither range
is set to approximately 1.2 LSB. Dithering is particularly interesting
for sub-radix-2 SAR ADCs since the redundant capacitor weighting
allows to repeat just the last few conversion steps. Thus, real over-
sampling would dramatically increase the overall power consumption
while virtual oversampling affects it only marginally.
in regeneration: change of stat

e
- perturbation polarity
configuration
- dither weight & polarity
clk cycle
sample configuration
Figure 5.7: Illustration of the implemented highly configurable clock-

ing scheme. The radial axis represents different possible configurations
for the various FSM states and sub-states (angular axis). Each
state (except for reset/regeneration) is divided in two independently
configurable sub-states: the settling time and the number of compar-
isons (to reduce the impact of comparator thermal noise by majority
voting). Each rectangle corresponds to one clock cycle. The yellow
marked path illustrates a sample configuration. The innermost white
segment represents the 0-cycle option, i.e., skipping a certain state
and thus disconnecting a certain capacitor from the array. The
reset/regeneration state is not only used to reset the ADC after a
conversion is done, but also to regenerate the sampled analog signal
in case of perturbation or dithering injection [136].
5.3.3 Reconfigurable clocking scheme

The flexible clocking scheme of Prototype I represents the basis of the
clocking scheme in Prototype II. It is extended with additional digital
logic in order to allow reconfigurability. For a given application, the
clocking scheme can be well optimized due to a highly configurable
implementation, which is visualized in Fig. 5.7. The settling time for
each conversion step can be set individually over the SPI interface as
an integer multiple of clock cycles in the range of 1-32. In order to
a) cycles: 0 9 12 15 17 19 21 23 25 27
settling:
comparison:
reset:
states: sampling MSB
cycles: 29 31 33 35 37 39 45 55 0
settling:
comparison:
reset:
states: LSB
b) cycles: 0 3 6 8 10 12 14 16 0
settling:
comparison:
reset:
states: sampling MSB MSB-5
Figure 5.8: a) Timing diagram of Prototype II to achieve highest

resolution without dithering and b) a resolution of 6 bit. Each square
corresponds to one clock cycle. A conversion always starts with
sampling and ends with a capacitor array reset. If necessary, the
ADC is able to stay for more than one clock cycle in the reset state.
Achieving highest resolution in the ADC requires majority voting
which corresponds to consecutive comparisons and comparator resets
in the LSBs of the ADC [136]. Both the comparator and capacitor
array resets are listed in the same row but in different colors.
optimize the converter for a specific application, the ADC is tuned

externally during measurements to find the optimal circuit settings.
Comparator noise can be mitigated by majority voting: an odd num-
ber of comparisons in the range 1-5 can be set for each conversion
step individually. While fine-tuning of the settling time for the most
significant conversion steps can increase the performance, majority
voting is only effective for the least significant conversion steps.
The timing diagrams for two different resolution settings are given
in Fig. 5.8. For higher resolutions, N = 17 SA steps is performed in
56 clock cycles. Majority voting is activated for the last two LSBs to
reduce noise. Configuring the ADC for a resolution of 6 bit requires

for example 17 clock cycles.
5.4 Digital calibration and post-correction

In the SAR ADC implementation, N = 17 capacitors are used due
to redundancy and need to be estimated in the digital domain. The
achievable resolution of the ADC, however, is mainly limited by the ac-
curacy of the capacitor weight measurement/calibration (see Sec. 3.4
for more details). The finite precision of the capacitor weights adds
to the quantization noise of the SAR ADC. Since the output of the
ADC is built by a +1/-1 weighted sum of all capacitor weights, the
overall quantization error also sums up. The necessary precision to
which the single capacitor weight must be known, is
V,tot
V = √ ,
Nres
where V,tot = LSB/2 is the total allowed quantization error, and Nres
the nominal targeted resolution [14]. For this reason, the estimation
of capacitor weights must have higher precision than the ADC.
The capacitor mismatch in the array of the SAR ADC is corrected
by means of the perturbation-based algorithm proposed in [20], which
has been implemented on chip in both ADC prototypes to avoid the
need for costly off-chip computations. A block diagram of the digital
calibration and LUT-based post-correction unit is shown in Fig. 5.9.
Its principle of operation is similar to the split-ADC calibration [145].
Instead of splitting the original ADC into two identical ones, it makes
perfect use of positive and negative perturbation injection to acquire
two digital output codes from the same input signal.
5.4.1 Perturbation injection

The implementation of the calibration algorithm requires that an
analog offset is injected into the sampled signal in order to generate
two different digital output codes from the same input. This is ac-
complished with a minimum overhead of two additional perturbation
capacitors Cp in the capacitor array that can be connected to either
Area Distribution: Digital Calibration and LUT based Post-Correction Unit
LUT LMS Update
Δd,k
os k
Other wk [0]
Memory Capacitor Weight &
19%
30% LMS Error Update
...
LMS Correction
21%
Correction + 2Δ d,k
+
5.4. DIGITAL CALIBRATION
wk [16] − Dout
30% Dout 17 Dout + − ek
+ −
−1 Dout −
+
+ b k [n]
bin + a k [n]
...
−
−
- b k [n] 1 Dout
a k = b +k _ b −k
Figure 5.9: Top-level block diagram of the digital calibration and LUT-based post-correction unit and
area distribution of the main building blocks relative to the total digital area.
97
12.5
12.0
11.5
1.8 bit
resolution [bit]
11.0
10.5
10.0
9.5
9.0 after calibration
before calibration
8.5
10 20 30 40 50 60 70 80 90 100
unity capacitance [fF]
Figure 5.10: Fixed-point Matlab simulation of the SAR ADC resolu-
tion versus unity capacitance before and after calibration using 1000
Monte Carlo simulations. The learning factors have been chosen equal
to µw = 2−8 and µd = 2−1 , respectively [136].
the positive or the negative reference voltage. The timing diagram

of a complete conversion in calibration mode is shown at the bottom
of Fig. 5.1. In addition to the original 6 sampling cycles, two times 34
cycles are required to convert twice the same input to which a positive
and a negative perturbation ∆a have been added. Additional 6 cycles
are used between the positive and negative perturbation injection
to regenerate the analog sample by reconnecting all switches to the
analog common-mode ground.
5.4.2 Calibration algorithm

Since the capacitor array is not binary weighted, the two generated
output codes are converted to binary according to
N
X −1
Dout [kTs ] = wi [kTs ] (2bi [kTs ] − 1) ∀k ∈ Z,
i=0
5.4. DIGITAL CALIBRATION 99
where bi is the i-th digit of the non-binary output code, N = 17 is

the number of SAR iterations required to resolve each sample, and
wi is the i-th bit weight of the capacitor array. If all weights of the
array were exactly known, the difference between the two output codes
would be identical to twice the digital representation ∆d of the analog
offset. An error can therefore be defined as
−
e[kTs ] = Dout
+
[kTs ] − Dout [kTs ] − 2∆d [kTs ].
As long as the LMS error e[kTs ] is not zero, the calibration algorithm
updates the values of the capacitor weights in a LUT trying to min-
imize the LMS of the error signal, according to the update equation
system as
w[(k + 1)Ts ] = w[kTs ] − µw e[kTs ]a[kTs ]

∆d [(k + 1)Ts ] = ∆d [kTs ] − µd e[kTs ].
The learning factors µd and µw determine the convergence speed and

the precision of the updated weights. Since the input needs to be
sampled twice, we calibrate the capacitor array during start-up and
disable the calibration in normal operation to recover full speed and
to save power. It takes about 5000 samples before the LMS error
fulfills |e[kTs ]| ≤ 0.1 LSB, which is equivalent to a convergence time
of 2.5 ms at 2 MS/s. With smaller learning factors which can be
adjusted through the SPI interface of the converter chip, the LMS
is able to estimate the capacitor values with higher precisions and
convergence times. The robustness and stability of the LMS loop is,
thus, ensured by the ability to tune the learning factors. When start-
up calibration is finished with the estimation of the capacitor weights,
post-correction starts to operate in the background and corrects the
output of the ADC digitally.
The achievable resolution of the calibrated SAR ADC has been
evaluated using Matlab Monte-Carlo simulations for different unit
capacitor values, and is shown in Fig. 5.10. Capacitor mismatch is
based on the technology data of the employed 130 nm CMOS. Each
calculated point in the plot represents the average of 1000 independent
simulations with a calibration time of 105 samples. A random (up to
±6 σ) offset on each capacitor has been added to simulate the effect of
Table 5.1: Performance summary of Prototype I.
Sampling Rate
2 MS/s 4 MS/s
Technology 130 nm 1P8ML 1.2 V CMOS

Peak SNR [dB] 72.7 66
SFDR [dB] 79.5 85
Peak SNDR [dB] 71.1 65.5
ENOB [bit] 11.5 10.6
Power [mW] 0.92 1.78
FOMa [fJ/conv] 160 286
a
FOM = Power/ 2 BW 2 ENOB

capacitor mismatch. Thermal noise is added to the samples, whereas

the comparator noise is neglected in this analysis.
In Prototype I, a unity capacitor value of 50 fF has been chosen as a
good trade-off between precision and bandwidth. The LMS based dig-
ital calibration improves the resolution by about 11 dB (1.8 ENOB).
Prototype II has a unity capacitor of 70 pF.
The digital calibration unit measures 0.156 mm2 corresponding to
28.4 kGE (one gate equivalent GE corresponds to a 2-input drive-1
NAND gate) in both prototyped ADC implementations and consumes
around 70 % of the total power (when excluding the power consump-
tion of the reference buffers).
5.5 Measurement results of Prototype I

The proposed 14-bit SAR ADC has been fabricated in a 130-nm
1P8ML mixed-signal CMOS technology with MiM-capacitor option
and a single 1.2-V supply. The chip micrograph is shown in Fig. 5.11
a). The ASIC measures 0.33 mm2 , 47 % of which is occupied by
the on-chip digital calibration and the LUT based post-correction
5.5. MEASUREMENT RESULTS OF PROTOTYPE I 101
control
USB
board
to PC
DTL
Digital
417 µm
Capacitor
SAR Calibration
Array
Unit test board LVDS
clock
signal input
input
798 µm DUT
a) b)
Figure 5.11: a) Chip micrograph of Prototype I. b) DUT controlled

over USB from PC where resolved digital data is transferred through
LVDS back to the PC.
unit. The measurement setup is shown in Fig. 5.11 b) where the

device under test (DUT) is controlled over USB from PC and the
control board is connected through SPI with the DUT. The digitized
output of the SAR ADC is transferred over a low-voltage differential
signaling (LVDS) port back to the PC to be further analyzed. The
fully differential analog input and the clock signal are connected to
the test board through shielded cables.
The impact of the calibration algorithm on the output spectrum

at 2 MS/s with a 60 kHz sinusoidal input is presented in Fig. 5.12
a). After the correct bit weights in the capacitor array have been
identified, an improvement of 9.3 dB on the SNR and 11.3 dB on
the SNDR are observed. Finally, the dynamic performance as a
function of the input frequency for a full-scale input at 4 MS/s is
shown in Fig. 5.12 b). The converter consumes 0.92 mW at 2 MS/s
and 1.78 mW at 4 MS/s, corresponding to a FoM of 160 fJ/conv and
286 fJ/conv respectively. The degradation of FoM in the 4 MS/s
operation mode is mainly given by the fact, that no reference buffers
are implemented on chip, and the reference voltages are disturbed
over the inductance of the bonding wires and thus limit the overall
dynamic performance of the ADC, in particular when the sampling
frequency is increased.
Table 5.2: Comparison to state-of-the-art ADCs with medium

resolution.
Proto-
[146] [20] [147]a
type I
Architecture SAR SAR Σ∆ SAR
Technology 130 nm 130 nm 90 nm 130 nm
Resolution [bit] 10 12 12 14
Sampling Rate [MS/s] 12 22.5 4 4
SFDR [dB] 62.5 90.3 87 85
Peak SNDR [dB] 50.9 71.1 63.2 65.5
Power [mW] 0.32 3 8 1.78b
FOM [fJ/conv] 95 51.3 1200 286b
Calibration no off-chip - on-chip
a
UMTS mode
b
Including power consumption of the on-chip digital correction unit
Compared to [147] in UMTS mode, Prototype I achieves the same

resolution at 4.5 times lower power consumption and 50 % of the sili-
con area, which vindicates the employment of digitally calibrated SAR
ADCs in wireless receivers. The ADC performance is summarized
in Tbl. 5.1. Finally, Tbl. 5.2 shows a comparison with state-of-the-art
ADCs targeting similar bandwidths. It is worth to stress the fact
that the reported power consumption includes the digital LUT based
post-correction unit which is active during normal operation.
5.6 Measurement results of Prototype II

Prototype II has also been fabricated in a 130 nm 1P8ML mixed-
signal CMOS technology with MiM-capacitor option and a single 1.2-
V supply. The chip micrograph is shown in Fig. 5.13. The converter
measures 0.42 mm2 , 52 % of which is occupied by the on-chip digital
unit and about 14 % by the capacitor array.
The static performance of Prototype II is depicted in Fig. 5.14.
Peak INL and DNL are reduced from 9 LSB and 2 LSB respectively
5.6. MEASUREMENT RESULTS OF PROTOTYPE II 103
0
Before calibration:
power [dB] −20 SNDR=59.8dB, SFDR= 67.6dB, THD= −62.4dB
−40 After calibration:
−60 SNDR=71.1dB, SFDR= 79.5dB, THD= −76.2dB
−80
−100
−120
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
a) frequency [MHz]
95
SFDR
90 SNDR
85
80
dB
75
70
65
60
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
b) frequency [MHz]
Figure 5.12: a) Measured output spectrum of Protoype I before (grey)

and after (black) calibration at 2 MS/s with a 60 kHz input (8192
points FFT). b) Measured dynamic performance vs. input frequency
at 4 MS/s for a full-scale input. Note that the input frequencies were
imposed by external bandpass filters which are employed to remove
harmonics from the signal source.
before calibration, to 0.7 LSB and 0.6 LSB after calibration. Thus, the
calibration not only corrects INL but also take care on DNL errors.
The LSB in here is referred to a 14-bit integer number.
Fig. 5.15 shows the ENOB versus Nyquist bandwidth where sev-
eral measurements of the SAR ADC have been collected at different
converter clock frequencies fclk . Since the power consumption in the
digital domain is dominant and proportional to the clock frequency,
the signal bandwidth that meets the specification for a given appli-
cation scenario can be optimized by pre-scaling of fclk . Furthermore,
a slower clock frequency relaxes the settling time of the capacitor
870 µm
Cal
Reference Cor ibra
Buffers rect tion
LVDS Drivers
DTL ion
525 µm
Me
Capacitor mo
SAR ry
Array
Digital
Logic SPI
R-Ladder DAC
Figure 5.13: Chip micrograph of Prototype II with the most important

sub-circuits marked. The digital circuitry is roughly divided in its
main building blocks [136].
array, allowing to reduce the static power consumption of the reference

buffers. The ADC covers a Nyquist bandwidth of more than 1 MHz
when running at fclk = 64 MHz at an ENOB of 12.6 bit. The Nyquist
bandwidth can be extended to 2 MHz (fclk = 64 MHz), when the
accuracy of the ADC is tuned to 9.2 bit by disabling capacitors in the
array. The Nyquist bandwidth has been increased in this measure-
ment because the ADC is only permitted to enter the reset state for
one clock cycle such that a new conversion can start immediately (see
Fig. 5.8 for further explanation).
Fig. 5.16 shows the uncalibrated and calibrated output spectra

at 286 kS/s with no dither. A SNDR of 79.1 dB can be achieved
in practice which corresponds to an ENOB of 12.9 bit. The SAR
ADC core consumes 130 µW at 16 MHz with 92 µW in the digital
and 38 µW in the analog domain, respectively. Enabling dithering by
injecting a zero-mean pseudo random sequence to the signal results
in the spectrum shown in Fig. 5.17. With an oversampling factor of
4 and fclk = 16 MHz, the achieved ENOB is 13.5 bit.
10
INL [LSB] [min: -0.72, max: 0.53]
5
0
0.5
−5
-0.5
−10
0 1000 2000 3000 4000 5000 6000 7000 8000
digital code
4
[min: -0.39, max: 0.58]
DNL [LSB]
2
0
0.5
−2
−4 -0.5
0 1000 2000 3000 4000 5000 6000 7000 8000
digital code
Figure 5.14: Measured INL and DNL of Prototype II before (grey)

and after (black) calibration. The inset highlights maximum INL and
DNL [136].
In Tbl. 5.3, the performance comparison of Prototype II with other

recently published medium- to high-resolution SAR ADCs is summa-
rized. The ADC implementations proposed in [32, 148, 149] achieve
high sampling rates above 40 MS/s but are nevertheless interesting in
this comparison due to their targeted resolution of above 13 bit. To
achieve the desired accuracy, the SAR ADC in [149] applies noise-
shaped dithering generated by a Σ∆-modulator. Additional capac-
itors are used in the MSB array to increase the SNR and in the
LSB array to correct settling errors and to improve the SNR by
averaging. The SAR ADC prototype in [33] uses a 14 bit capacitor
array segmented into 4 bit unary MSB and 10 bit binary LSB sections.
Similar to [138], the ADC performs multiple comparisons for majority
voting. In order to increase its resolution, non-subtractive dither
combined with oversampling is applied, similar to Prototype II, as well
14
13 4) fclk = 64 MHz
Pcore = 540 μW
12
11
10
ENOB
9
2) fclk = 16 MHz
8 Pcore = 130 μW
7 1) fclk = 8 MHz
Pcore = 65 μW
3) fclk = 32 MHz
6 Pcore = 260 μW
5
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Nyquist bandwidth [MHz]
Figure 5.15: ENOB versus Nyquist bandwidth trade-off of Proto-

type II. Measurement results generated for the prototype operated
at different clock frequencies: 1) fclk = 8 MHz, 2) fclk = 16 MHz, 3)
fclk = 32 MHz, and 4) fclk = 64 MHz. The power consumption of the
SAR ADC core, denoted as Pcore , scales with fclk [136].
Figure 5.16: Measured output spectrum of Prototype II before (grey)

and after (black) calibration without dithering with a 1.6 Vpp input
signal at 1.98 kHz [136]. (220 points FFT).
Figure 5.17: Measured output spectrum of Prototype II before (grey)

and after (black) calibration with dithering with a 1.6 Vpp input signal
at 1.98 kHz [136]. (218 points FFT).
as chopping to cancel out noise and distortion. The SAR ADC imple-
mentation in [150] consists of a 13-bit capacitor array with redundant
elements. The comparator runs in one of the two different modes, i.e.,
a low-power mode and an offset-compensated high-resolution mode.
In contrast to Prototype II which uses all digital output codes of the
ADC during start-up calibration to train its LUT, only some special
output codes are used to perform the calibration procedure. When
enabling the dithering sequence, Prototype II achieves similar ENOB
as reported in [148], and the implementation outperforms all other
SAR ADCs in Tbl. 5.3 by at least 0.8 ENOB.
Most of the published ADCs are not reconfigurable and therefore

optimized to achieve a certain resolution for a constant Nyquist band-
width and power consumption. For this reason, their FoMs are well
optimized. However, they are not able to trade power consumption
for resolution as it is the case in Prototype II. The power consumption
in Prototype II is reduced by 70 % when lowering the resolution from
14 down to 5 bit. The ADC consumes 130 µW at 12.9 ENOB and
37 µW at 5.9 ENOB. The maximum achievable ENOB versus sampling
frequency fs for Prototype II is illustrated in Fig. 5.18 where dithering
is disabled.
108
Table 5.3: Comparison of Prototype II with recently published medium- to high-precision SAR
ADCs [136].
ISSCC’07 JSSC’13 ISSCC’13 ISSCC’14 ISSCC’15 Proto-
[148] [32] [149] [33] [150] type II
Resolution [bit] 14 14 13 14 13 14
Power [µW] 66’000 31’100 4’200 1.37 46 130
Technology [nm] 130 65 90 65 40 130
ENOB [bit] 13.5 11.6 11.5 12.8 10.4 12.9 13.5
Sampling freq. [MS/s] 40 80 50 0.128 6.4 0.286 0.072
FOM [fJ/conv.] 143 125 28.7 5.4 5.5 59 156
SNR [dB] 85 71.4 72 80 64.1 79.3 83.9
SFDR [dB] - 88.6 84 87.1 81.9 95.0 96.8
SNDR [dB] 83 71.3 71 79.1 64 79.2 82.9
Dithering - no yes yes no no yes

CHAPTER 5. A 14 BIT SAR ADC
5.7. CONCLUSIONS 109
13
12
ENOB
11
10
9
0 0.5 1 1.5 2 2.5
sampling frequency [MHz]
Figure 5.18: Measured ENOB versus sampling frequency fs of

Prototype II.
5.7 Conclusions
In this chapter, two prototypes of a 14-bit sub-radix-2 SAR ADC

has been reported in 130-nm CMOS, employing an optimized non-
uniform clocking scheme that reduces the conversion time by more
than 50 % compared to a conventional scheme. A digital perturbation-
based start-up calibration technique is implemented entirely on chip
to correct the capacitor mismatch digitally and enhance the effective
resolution of the SAR ADC by more than 10 dB. Prototype I achieves
an ENOB of 11.5 bit at 2 MS/s and 10.6 bit at 4 MS/s. It cover
a wide range of applications, in particular applications in wireless
communications (GSM, Bluetooth, GPS, or UMTS).
The non-uniform clocking scheme of Prototype I has been extended
to be reconfigurable that renders Prototype II energy efficient over a
wide range of resolutions and signal bandwidths. The capacitor array
of Prototype I has been redesigned to be highly flexible, allowing ca-
pacitors to be disconnected from the array for biomedical applications
requiring lower resolutions. Reference buffers have been provided on
chip to deliver clean reference signals to Prototype II. Oversampling,
non-subtractive dither, majority voting, and several other options can
be controlled over SPI to further increase the resolution of the ADC.
Prototype II achieves an ENOB of 12.9 bit at 286 kS/s and 13.5 bit
when applying dithering. The converter covers a wide range of po-
tential biomedical applications ranging from EEG and ECG to EMG
and beyond.
Chapter 6
A 150-MS/s 11-bit
Folding ADC with
9.6 ENOB
6.1 Introduction
This chapter details the design procedure of a 150-MS/s 11-bit folding

ADC implemented in 130-nm CMOS technology. A novel start-up cal-
ibration technique with a LUT based post-correction circuit is directly
implemented on chip to compensate for static non-linearity errors.
The LUT based post-correction circuit improves the accuracy of the
ADC while enhancing the SNDR and SFDR by around 15 dB and
20 dB, respectively. The ADC achieves 9.6 ENOB at low frequencies
and 9.1 ENOB at Nyquist. It consumes 287 mW from a 1.2-V supply
and occupies a silicon area of 1.74 mm2 . A FoM of 2.8 pJ/conversion
is achieved in practice which is competitive to other folding ADCs
of similar precision and signal bandwidth coverage published by the
research community.
111
112
Analog Core Digital Core

11
Bandgap Calibration Logic
1 Dout [kTs]
SC-Integrator Clock
T/H
1
Vin(t) Coarse Fine
VT/H[kTs] 27 Quantizer Quantizer 144
54 18 36 12 48 16
Reference Pre- Averaging & Folding Averaging & Folding Averaging & Folding Averaging &
Ladder amplifier Interpolation Amplifier Interpolation Amplifier Interpolation Amplifier Interpolation
Npre = 27 Nint,0 = 2 Nfold,1 = 3 Nint,1 = 2 Nfold,2= 3 Nint,2= 4 Nfold,3 = 3 Nint,3 = 9
Figure 6.1: Architecture of the 11-bit digitally-calibrated folding ADC.

CHAPTER 6. A 150-MS/S 11-BIT FOLDING ADC
6.2. FOLDING ADC ARCHITECTURE 113
6.2 Folding ADC architecture

The overall architecture of the proposed 11-bit digitally-calibrated
folding ADC is shown in Fig. 6.1. The converter is supplied from a
1.2 V source. A 2.5 V supply voltage is also provided to operate the on-
chip bandgap circuit. The differential input range of the converter is
1 Vpp and the time-discrete binary output vector Dout [kTs ] represents
the 11-bit digital representation of the analog input voltage Vin (t).
A T/H circuit samples Vin (t) at discrete time instants kTs (for all
k ∈ Z) and isolates the input of the ADC from the capacitive load seen
at the input of the pre-amplification stage. The variable Ts denotes
the sampling period of the ADC. Bootstrapped switches equivalent to
the ones reported in [139] are used at the input of the T/H circuit to
minimize on-resistance variations dependent on Vin (t).
The sampled time-discrete analog signal VT/H [kTs ] is subtracted
from Nref = 27 reference voltages in the pre-amplification stage and
results in amplified analog residue signals. The reference voltages
provided to the pre-amplification stage are generated by a reference
ladder consisting of 28 identical resistors. High-speed voltage buffers
are provided on-chip to target operating rates above 150 MS/s. A
small folding factor (Nfold = 3) is chosen for all folding amplifiers in
the prototyped converter in order to achieve high-speed conversion
rates. The cascaded folding and interpolating stages are the dominat-
ing speed limiters in folding ADCs but make the complexity of the
11-bits converter manageable for CMOS integration if compared to a
generic flash ADC of similar precision.
A total folding factor of Nfold,tot = 27 is distributed over three
folding stages. Resistive interpolation and averaging are introduced
at the output of each amplification stage with a total interpolation
factor of Nint,tot = 144. They reduce substantially the number of
pre- and folding amplifiers. The intersection between the analog and
digital domain is built by coarse and fine comparator stages in the
analog domain, and a digital post-correction logic samples the output
of the comparators in the digital domain.
In the digital domain, both binary output codes from the coarse
and fine comparators are combined by the digital post-correction cir-
cuit and are forwarded off chip by high-speed LVDS drivers. A digital
start-up calibration and LUT based post-correction logic is provided
114 CHAPTER 6. A 150-MS/S 11-BIT FOLDING ADC
φ2
bootstrapped φ1
φ1 Cs φs Ts
Vin (t)
Vout [kTs]
φs A
CL φ2
a) b)
Figure 6.2: a) Flip-around T/H circuit. b) Timing diagram of the

clock phases used in the flip-around T/H circuit.
on chip which control a SC-integrator in the analog domain to generate

the required calibration sequence.
A dedicated clock generator circuit is provided in the digital do-
main which generates all necessary clock phases used in the con-
verter. To complete the discussion of the single-chip folding con-
verter implementation, also a low-noise bandgap circuit is provided
on chip. The bandgap circuit provides digitally tunable bias currents
for optimizing the operating region of the analog core. The digitally
tunable bias currents are connected to on-chip register banks that
are controlled externally over a SPI interface. Optimizing the CMOS
bias points externally allows improvements in the accuracy-bandwidth
trade-off [99].
6.3 Integration of the analog core

In the following subsections, analog design details of the folding ADC
are discussed.
6.3.1 Track-and-hold (T/H) circuit

The functionality of the T/H circuit can be explained using the flip-
around T/H depicted in Fig. 6.2. For the sake of simplicity, the
presented T/H circuit is illustrated single-ended. In practice, the de-
signed T/H circuit is fully-differential which achieves a better rejection
6.3. ANALOG CORE 115
bootstrapped φ1
channel1
φ2 channel2
φ1 φ1
C s1 φ2 MUX
φ1 φs Ts
φs
Vin (t)
Vout [kTs]
φ2 A φ2
φ2 C s2
φ1
a) b)
Figure 6.3: a) Double-sampling flip-around T/H as described in [152].

b) Timing diagram of the clock phases that support the double-
sampling technique.
of common-mode noise and high-frequency power supply variations

compared to the single-ended variant.
A bootstrapped sampling switch equivalent to the one reported
in [139] is used at the input of the T/H circuit to reduce signal
dependent charge injection and improve the linearity of the switch.
During the tracking mode (ϕ1 = 1 and ϕ2 = 0), the sampling ca-
pacitor Cs is loaded to Vin [kTs ] while the operational amplifier with
finite gain A is in idle state. In hold mode (ϕ1 = 0 and ϕ2 = 1)
the capacitor Cs is isolated from the input and switched into the
feedback path of the operational amplifier. The voltage over the
sampling capacitance Cs remains constant (denoted as Vout [kTs ]) such
to be processed by a subsequent analog circuit during hold mode.
In agreement with the charge conservation, the clock phases ϕ1 and
ϕ2 must be non-overlapping. An additional early clock phase ϕs is
provided for supporting bottom-plate sampling as described in [151].
Double-sampling technique
Since the overall capacitive load CL at the input of the Npre = 27

preamplifiers of the folding ADC are relatively high (about 7 pF), the
double-sampling technique is used in the flip-around T/H circuit to
extend the available settling time of the T/H circuit while reducing
the power consumption of the operational amplifier. The power con-

sumption Pamp of the amplifier can be characterized by
Pamp = Itot VDD ∝ SR CL VDD , (6.1)
where Itot is the total current consumption of the amplifier, VDD the
power supply, SR the slew rate, and CL the output capacitive load.
The proposed double-sampled flip-around T/H circuit is shown
in Fig. 6.3. The operational amplifer is shared in a time-interleaved
fashion between the two parallel signal channels. While the input
Vin (t) is sampled passively into the sampling capacitor Cs1 (ϕ1 =
1 and ϕ2 = 0), the sampling capacitor Cs2 holds the previously
sampled signal Vout [(k−1)Ts ] while being connected in feedback of the
amplifier. In the next phase, the roles of the channels are exchanged
and with this technique the operational amplifier is kept occupied
in both clock phases such that its SR and power consumption Pamp
are both relaxed by a factor of two in (6.1). The saving in power
consumption and relaxed SR in the analog domain comes unfortu-
nately not for free. Firstly, additional switches are required to build a
multiplexer (denotes as MUX in Fig. 6.3 a)) and to isolate both signal
channels from each other. The generation of the additionally required
clock phases adds more complexity to the clock generator circuit. In
particular, the input of the pre-amplification stage needs also to be
designed such to support two different signal channels.
Since the proposed double-sampled circuit has two parallel signal
channels, process mismatch resulting in slightly different capacitor
values Cs1 and Cs2 introduces static errors which result in different
channel gains. Mismatch in the channel gains modulates the ampli-
tude of the signal |Vin (t)| with a square wave at half of the sampling
frequency, which is seen as an image of the signal spectrum centered
at the Nyquist frequency. Gain mismatch in the two channels is com-
pensated by a low-complexity digital LMS based estimation algorithm
as described in [153]. Details on the LMS algorithm can be found
in App. C. Since both channels in the proposed double-sampling flip-
around T/H circuit are connected to the same operational amplifier,
they see the same input-referred offset voltage. For this reason no
distortion due to different offset voltages is expected for the integrated
double-sampling flip-around T/H circuit.
VDD
VBP M5 M6
M7
VCM φ2 φ1 φ2 φ1 VCM
A
+ - C2 C1 C2
Vin (t) Vin (t) M8 M9
M1 M2 - + VBN φ2 φ1 φ2 φ1 VBN
Vout [kTs] Vout [kTs]
Vc [kTs]
M10 M11 C2 C1 C2
A VCM φ2 φ1 φ2 φ1 VCM
Vc [kTs]
M3 M4
a) VGND b)
Figure 6.4: a) Gain boosted folded cascade. b) SC-CMFB configura-

tion with symmetric loading of the differential-mode loop [154].
However, timing-skew in the clock signals of the parallel channels

leads to non-uniform sampling, which is, in general, challenging to
be corrected digitally. The timing-skew is a result of unmatched
propagation delays of the clock generator circuit to the switches. To
prevent timing-skew to disturb the sampling process, the proposed
double-sampling T/H circuit in Fig. 6.3 is designed to be timing-skew
insensitive. A single sampling switch is shared in the T/H circuit
between both analog sampling channels while the multiplexer MUX
decouples the channels from each other. To avoid systematic timing
errors during sampling, the sampling pulse ϕs is derived from the same
clock source.
The operational amplifier in the T/H circuit has a gain-boosted

folded cascode topology as shown in Fig. 6.4 a). The differential
amplifier is supplied by VDD = 1.2 V and biased by the voltage VBN
and VBP . Since the fully-differential amplifier requires a well-defined
and precise output common-mode Vc [kTs ] in the double-sampling flip-
around T/H circuit during both clock phases (sample and hold mode),
a time-discrete symmetric SC-CMFB has been designed in this work
and shown in Fig. 6.4 b). In the symmetric CMFB circuit, the total
loading of the differential loop is for both phases equivalent to Ctot =
C1 + C2 .
+
Vout [kTs] φ2
+
C s,2 φ2
Vin (t) Vout [kTs] +
VR,N φ1 φ1 channel2
T/H pre
- φ2
VR,N pre φ1 φ1
VR,T VR,N pre − Va,Npre [kTs] -
φ2
a Vout [kTs] - φ2 -
C s,2 VR,N pre [kTs]
+
A
reference Vout [(k-1) Ts] φ1
+ φ1 +
VR,N pre [kTs]
C s,1
voltage +
VR,Npre φ2 φ2
Va,2 [kTs]
generator VR,2 −
a - φ1 φ2
VR,Npre φ2
channel1
-
VR,B Va,1 [kTs] Vout [(k-1) Ts] φ1 -
C s,1 φ1
VR,1 −
a
Figure 6.5: Details on the implementation of the pre-amplification

stage where the reference voltages are subtracted from the output
of the T/H circuit. A zoom in the subtraction operation shows the
implemented two channels required for the double-sampled T/H cir-
cuit. The channels are designed fully differential and a corresponding
open-loop amplifier is used to drive the subsequent analog sub-circuits.
The main advantage of the time-discrete CMFB over the time-

continuous circuits found in literature is that they impose no restric-
tions on the maximum allowable differential input signal, have no
additional parasitic poles in the common-mode loop, are highly linear,
have no static power consumption, and are highly recommended for
precise SC applications. The only disadvantage of the SC-CMFB
circuit is that it increases the load capacitance driven by the common
operational amplifier. Therefore, the amplifier requires a slightly
higher unity-gain bandwidth.
Simulation results for the 130-nm CMOS technology show, that the
AC response of the optimized gain-boosted OTA achieves a unity-gain
bandwidth of 1.1 GHz for CL = 7 pF load capacitance. An open-
loop DC gain of A = 77.3 dB, a phase margin of 76.4◦ , and a power
consumption of 19.2 mW for a supply voltage of VDD = 1.2 V are
further achieved.
6.3.2 Pre-amplification stage

In order to understand the working principle of the pre-amplification
stage as well as its cooperation with the other circuit elements in the
converter, the front-end of the folding ADC is shown on the left-hand

side of Fig. 6.5 where one out of Npre preamplifiers (in the grey box)
is chosen and discussed in more details. The preamplifier in question
is connected with the output of the T/H circuit denoted as Vout [kTs ]
from which the reference voltage VR,N is subtracted.
The generated residues from the subtraction represent zero cross-
ings defined as follows:
Va,N (kTs ) = Vout (kTs ) − VR,N k ∈ 0, 1, 2, . . . , (6.2)
which can easily be detected by comparators. The comparator is a

zero crossing detector and its digital output level only depends on
whether it has a negative or positive input voltage.
However, creating precise residue signals requires precise time-
continuous analog circuits which are power hungry for high-bandwidth
applications. For this reason, the power-efficient SC circuit depicted
on the right-hand side of Fig. 6.5 is implemented in practice to gen-
erate the required residues in the folding ADC.
Since the T/H circuit is designed with double-sampling capabil-
ities, analogously the input stage of the preamplifier supports two
different signal channels which are completely decoupled from each
other. The pre-amplification stage runs with twice of the sampling
frequency used in the T/H stage.
Before a conversion is performed in the ADC, the input of the
first channel in the preamplifier is connected with the corresponding
first T/H output channel. When the T/H circuit is in hold mode, the
operational amplifier in the pre-amplification stage is in reset state
to cancel remaining charge in the parasitic capacitance at the input
of the amplifier. The charge is transferred during hold mode to the
−
capacitors {Cs0+
, Cs0 }. In the next clock cycle, the input of the pre-
amplification stage is connected to the reference voltages such that a
subtraction is performed in order to generate the residues.
The operational amplifier in the preamplifer is a simple differential
pair (as shown in Fig. 6.6 a) and its most relevant design parameters
are the offset voltage, DC gain, settling speed, and parasitic input
capacitance. A preset switch is added at the output of the differential
pair with the reset phase ϕreset in order to improve the settling time
in the cascaded structure of the converter [28].
VDD VDD
Cc
RL RL
φreset M1 M2 VR,T
+ -
Vout (t) Vout (t) R0
R1
M5
R0 Rc
M3 M4 R2 VCM,2
R0
+ - Vref
Vin (t) Vin (t) Cc
M1 M2
Cc R0
Rc R0 VR,B
Iss
M3
VCM,1
a) VGND b) VGND
Figure 6.6: a) Pre-amplifier and b) reference generation circuits.
In the proposed pre-amplification stage, the simulated current

consumption of a preamplifier is 0.57 mA and the standard deviation
of the offset voltage is σ(Vos ) = 2.39 V. The gain of the preamplifier
is AV = 2.30 and its 3-dB bandwidth is 1.71 GHz.
6.3.3 Reference generation circuit

Reference voltages required for the operation of the folding ADC
are generated by an on-chip resistor ladder. However, the top and
bottom reference voltages of the ladder, denoted as VR,T and VR,B are
connected to a large off-chip capacitor. The external capacitor relaxes
the requirements on bandwidth of the reference buffer, because the
low output impedance of the reference buffers is mainly provided by
the large off-chip capacitor. This implementation is a slow reference
buffer approach which is described in [28, 155].
Large variations due to systematic and random mismatch from
the fabrication process need adjustment of the unity resistors in the
ladder (see Sec. 3.3). There exists different ladder topologies which
are less sensitive to variations and a corresponding design solution is

shown in Fig. 6.6 b).
The proposed resistive ladder consists of 28 unity resistors with
the value R0 . In this circuit topology, the voltage difference between
the top VR,T and the bottom reference VR,B equals
56R0 W2
VR,T − VR,B = Vref
R2 W1
with W1 and W2 properly sized to form a PMOS current mirror.
Since the resistors R0 , R1 , and R2 are realized with the same
resistor type, their resistance variations across process, corners, and
temperature cancel each other. To avoid excessive ringing from the
inductance of bonding wires, small compensation resistors and capaci-
tors denoted as Rc and Cc are added to the circuit. The common-mode
voltages VCM,1 and VCM,2 have to be tuned externally in order to
adjust VR,B and VR,T .
6.3.4 Cascaded folding and interpolation technique

In order to reduce the complexity of the medium-resolution folding
ADC, the cascaded folding and interpolation technique is employed.
Fig. 6.7 a) shows the implementation of the cascaded structure where
folding and interpolating stages alternate in a way such to minimize
the required number of comparators and reference signals for a given
nominal resolution Nres in the folding ADC [28]. The analog signal
processing performed in the cascaded structure is shown in Fig. 6.7
b)-c).
Cascading of folding amplifiers can be described as follows: A set
of folding circuits generating non-redundant folded residues of the
order Nfold of similar form but phase shifted can be connected to
build a cascade structure of folders in order to increase the number of
zero crossings in the resulting folded signal. This cascaded folding
technique increases the resolution of the ADC without drastically
increasing the number of comparators.
In practical CMOS realizations, a folding circuit is built by cross-
connecting the outputs of an odd number of differential pairs. The
implemented folding circuit is shown in Fig. 6.8. In the presented
folding circuit, only one differential amplifier is active (in its linear
N pre Va (t)
Va (t)
-Va,n-1 (t) -Va,n+1 (t) -Va,n+3 (t)
1 1 1 1 1 1 Va,n-2 (t) Va,n (t) Va,n+2 (t)
122
.. .
interpolation interpolation interpolation
N int,0 N int,0 N int,0 Vin (t)
0
Vint,0 (t)
b) VR,n-2 VR,n-1 VR,n VR,n+1 VR,n+2 VR,n+3
N fold,1 N fold,1 N fold,1
folding folding folding folding folding folding Vint,1 (t)

.. .
1 1 1st level
1
of folding and
interpolation interpolation interpolating interpolation
N int,1 N int,1 N int,1
Vin (t)
Vint,1 (t) 0

.. .
folding and folding and 2nd level folding and

c)
of folding and
interpolation interpolation interpolating
interpolation
Dout [kTs]
Dout,Nres -1[kTs]
Vint,2 (t)
Dout,Nres -2[kTs]
.. . Dout,Nres -3[kTs]
3rd level
folding and folding and of folding and
folding and
interpolation interpolation interpolating interpolation
.. .

Vint,4 (t)
N int,4 N pre
Dout,1 [kTs]
coarse and fine comparators Dout,0 [kTs]
N res
a) Dout [kTs] d)
Figure 6.7: a) Cascaded folding and interpolation circuit overview where Va (t) is the pre-amplification
CHAPTER 6. A 150-MS/S 11-BIT FOLDING ADC
stage output. b) The output of the pre-amplification stage versus Vin (t). c) The output of the first
folding and interpolating stage Vint,1 (t). d) The digital output of the folding ADC.
output stage
VDD
VB VB VB VB
M3 M4 M3 M4 M3 M4 M5 M6
VC
M1 M2 - +
M1 M2 - M1 M2 - M7 M8
+ + Vin,2 (t) Vout
Vin,0 (t) Vin,0 (t) Vin,1 (t) Vin,1 (t) Vin,2 (t) -
(t) +
Vout (t)
Iss Iss Iss RL RL
VGND
Figure 6.8: Folding circuit with a folding factor of Nfold = 3. The

circuit is biased with the bias voltages denoted as VB and VC , and
the tail current source Iss . The voltages VB and VC are derived from
the bandgap output voltage. The output stage converts the sum of
currents at its input into the differential output voltages Vout
+
(t) and
−
Vout (t).
region) at any time: the one with the input voltage close to its
reference voltage. All other amplifiers are in saturation. The con-
tribution of the remaining even numbered saturated amplifiers to
the overall transfer function is canceled out. For this reason, the
folding factor must always have an odd order. The folding circuit
in the first stage of the cascaded structure (with Nfold = 3) has a
DC gain of 2.85 in 130 nm CMOS and its input-referred offset equals
1.10 mV. Since analog signals at the input of the folding stages of
the cascaded structure are pre-amplified, the design requirements for
them are relaxed.
The interpolation technique is detailed in Sec. 2.4.2 and is used
to create additional zero crossings without requiring additional ref-
erence voltages and pre-amplifiers. Thus, the layout area, the input
capacitance, and the power consumption are reduced. The interpo-
lation factor Nint is used to denote the order of interpolation. Using
the notation of the interpolation factor, the number of zero-crossings
generated through the interpolation circuit is Nint − 1.
The interpolation technique is implemented in practice with a re-
sistive ladder consisting of Nint passive resistive elements between two
consecutive amplifiers. In practice, the settling speed of the converter
is limited by the interpolation factor Nint . Hence, the interpolation

factor decides not only on operating speed of the converter, but also
sets an upper limit to the value of the resistive elements. The resistive
interpolation is used here over the other interpolation techniques be-
cause it can easily be combined with the averaging technique. Details
on the averaging technique can be found in [28].
6.3.5 Comparators
Since analog signals at the input of both (coarse and fine) comparators
are pre-amplified, the requirements on their input-referred offsets are
relaxed. However, kick-back noise [7] is considered in the design of the
static comparators. The required silicon area for both comparators
must be minimized during design, because a set of 144 fine and 28
coarse comparators are used in the 11-bit folding architecture.
The coarse comparator used in the folding architecture is depicted
in Fig. 6.9 and the fine comparator in Fig. 6.10. Both comparator
circuits are composed of a differential pair (M1 -M2 ), current mirrors,
an RS latch, and a reset switch M11 . Depending on the common-mode
voltage at the input of the comparator, either a PMOS or an NMOS
differential input pair is chosen [28].
Both comparators operate periodically in two different states, a
reset phase (φreset active), and a regeneration phase. During the reset
phase, the CMOS transistor M11 which is controlled by φreset shorts
the output nodes of the comparator and removes the previous logic
state. In this state, however, the comparator senses the differential
analog input voltage. The gain during the reset phase is approxi-
mately given by
gm7 gm1 Ron

Av ≈ ,
gm5 1 − gm9 Ron
where Ron is the on-resistance of the reset switch.

To eliminate the positive feedback in the comparators, the follow-
ing criterion must be fulfilled across all process corners and tempera-
ture ranges
gm9 Ron < 1.

VDD
M5 M7
M6 M8
+
φreset Dout [kTs]
+
M1 M2 -
Vin (t) Vin (t)
M11
-
IB Dout [kTs]
M9 M10
φsample
VGND
Figure 6.9: Block diagram of the coarse comparator.
The RS latch is used to store the output of the comparator during

regeneration phase of the comparator (φsample = 1). Once the output
is stored in the latch, the comparator goes back to the reset state.
The implementation of the coarse comparator in 130 nm CMOS
technology results in 6.75 mV offset voltage, were 2.96 mV is input-
referred with a gain of Av = 0.59, and an overdrive time of 207 ps.
The expected regeneration time is 433 ps. A single coarse comparator
consumes 96 µW.
The fine comparator is designed such to permit an offset voltage
of 3.58 mV where 85.9 µV is the input-referred offset voltage with a
gain of Av = 0.57. The input-referred offset of the fine comparator is
much lower than the one of the coarse comparator since the signal at
the input of the fine comparator is amplified by the cascaded folding
and interpolating stages. The overdrive time of the fine comparator
is 304 ps and the regeneration time 597 ps. A single fine comparator
consumes 120 µW of power.
6.3.6 Calibration DAC

The calibration algorithm used in the folding ADC requires a ramp-
shaped reference signal at the input of the converter in order to learn
VDD
VBP
M4 M9 M10
VCP +
M3 φreset Dout [kTs]
M11
- +
Vin (t) Vin (t) VCN
M1 M2 M7 M8
-
Dout [kTs]
VBN
M5 M6 φsample
VGND
Figure 6.10: Block diagram of the fine comparator.
and to correct the transfer characteristic of the converter. During

calibration, shortly after power-up, the transfer characteristic curve of
the ADC is stored in a LUT which is accessed by the post-correction
algorithm in order to correct the static non-linearity errors of the
ADC.
Usually, a digitally controlled low-bandwidth and precise DAC is
used to generate the desired training sequence for calibration [27]. The
precision of the DAC should, however, be higher than the resolution
of the underlying folding ADC, otherwise the transfer characteristic
of the ADC is distorted systematically by the calibration DAC. The
design of precise DACs is challenging in practice and its silicon area
increases exponentially with the resolution.
The simplest method to generate a ramp-shaped analog signals
is depicted in Fig. 6.11 a). This analog circuit is implemented with
passive components. The number of generated training points for
calibration, however, is directly proportional to the number of unity
resistors R0 . Thus, a large number of training points results in a highly
complex reference ladder circuit. Systematic and random mismatch
in the reference ladder (see Sec. 3.3) also limit the precision of the
LUT based post-correction algorithm.
VDD Cf
R0 φn
Rin φ2
Vin
φn-1 Vramp [kTs]
R0
R0 CL
VCM
φ2 Vramp [kTs] b)
R0 φ1 Cf
φ1 Cin φ2
R0 φ0 Vin φ2
Vramp [kTs]
R0 φ2e φ1e
CL
VGND VCM
a) c)
Figure 6.11: a) Passive ramp generation circuit. b) Active ramp

generation circuit. c) SC-based ramp generation circuit.
An improved analog circuit that generates a precise ramp signal

is illustrated in Fig. 6.11 b) which represents an integrator [151]. The
output of the integrator is defined as
Vin
Vramp (t) = − kTs k = 0, 1, 2, . . . , (6.3)
Rin Cf
where Vin is a constant voltage and the slope of the ramp is con-
trolled through the ratio Vin / (Rin Cf ). In order to flatten the slope
of the ramp such to increase the amount of training points during
calibration, either the constant input voltage Vin or the product of the
passive elements Rin Cf must be kept small. Since it is challenging to
generate the slope of the ramp with high accuracy due to mismatch
in capacitive and resistive elements, this solution is skipped in this
work.
For the calibration of the folding ADC, the discrete-time counter-
part of the active ramp generation circuit can be used as illustrated
in Fig. 6.11 c) with its output defined as
Cin
Vramp [kTs ] = Vramp [(k − 1)Ts ] − Vin [(k − 1)Ts ] . (6.4)
Cf
The slope of the time-discrete ramp generation circuit is controlled

by the ratio of capacitors Cin /Cf . A symmetric layout of capacitors
ensures that the ratio Cin /Cf is sufficiently precise and the overall
mismatch between both capacitors is negligibly small for achieving
the required linearity in the ADC.
6.4 Digital core

In the following subsections, the design details of the main digital
building blocks of the folding ADC are discussed.
6.4.1 Bubble error correction circuit

Different types of thermometer-to-binary decoders are well known in
literature, e.g., the read-only memory (ROM), folded Wallace tree,
ones-counter, and the MUX-based decoder [156, 157]. The simplest
decoder is the ROM based. All others require a tremendous amount
of hardware complexity. The ROM based solution uses the output of
the comparators to address a ROM.
High-speed ADCs create erroneous bits in the thermometer code,
so called bubbles or sparkles which appear due to different causes
in the ADC, i.e., metastability, offset, crosstalk, and bandwidth lim-
itation of the comparators [158, 159]. Single bubble errors can be
corrected using 3-input NAND gates which remove errors in the ther-
mometer code. The solution proposed by [59] is illustrated in Fig. 6.12
and implemented in the folding ADC.
6.4.2 Encoder logic

A dedicated encoder logic is required after bubble error correction to
combine the outputs of the coarse and fine comparators denoted as
Dcoarse and Dfine to Dout . Besides calculating the uncalibrated output
of the converter, the encoder logic is also able to correct offset errors
in Dcoarse . Without error correction in the encoder logic, an error in
the coarse comparators causes Dfine to go out of range, which results
in missing codes as illustrated in Fig. 6.13 a).
6.4. DIGITAL CORE 129
Vin 0
0
Vref,6
Vin 0
0
Vref,5
Vin 0
0
Vref,4
Vin 0
1
Vref,3
Vin 1
0
Vref,2
Vin 0
0
Vref,1
Vin 1
0
Vref,0
Dout,2 = 1 Dout,1 = 0 Dout,0 = 0

Edge
Detection ROM
Figure 6.12: Thermometer-to-binary decoder with bubble error

correction capability. It senses more than two consecutive bits to
detect bubbles [59]. A zero between two consecutive ones at the output
of the comparators is successfully corrected.
In order to avoid missing codes, redundancy is introduced by

adding an additional comparator to the coarse quantizer [77]. As
a result, the final output code does not face discontinuity but at the
cost of additional digital circuit complexity and an additional coarse
comparator. The encoder implementing the described correction al-
gorithm is shown in Fig. 6.13 b).
Dcoarse 0 1 2 3
Dfine 0 M-1 0 M-1 0 M-1 0 M-1
missing codes
a) Draw 0 M-1 M 2M-1 2M 3M 4M-1
Dcoarse 0 1 2 3 4 5 6 7
Dfine,0 M-1 0 M-1 0 M-1 0 M-1
Dfine,1 M-1 0 M-1 0 M-1 0 M-1 0
b) Draw 0 M-1 M 2M-1 2M 3M-1 3M 4M-1
Figure 6.13: a) Encoding without error correction where Draw is

the uncorrected output of the folding ADC. An offset in the coarse
comparator output results in missing codes. b) Error correction with
an additional coarse comparator is employed to create redundancy
and to be able to correct the input-referred offset of comparators.
6.4.3 Digital calibration and post-correction

A block level diagram of the digital calibration and post-correction
circuit is depicted in Fig. 6.14. The start-up calibration of the fold-
ing ADC requires a reference sequence, which is ramp shaped and
generated with the integrator circuit described in Sec. 6.3.6. After
the transfer characteristic of the ADC is stored in the LUT (which
is realized with random-access memory), post-correction is performed
on the digital raw output Draw of the ADC. An addressing function
is used to store the ramp-shaped data correctly in the LUT. During
post-correction, the calibration logic performs a binary search on the
distorted transfer function in order to find an appropriate closest-
distance candidate for Draw , whose address is the corrected output
Draw[(k-1)Ts]
moving
Dfine [kTs] average
encoder 1 entry
LUT
6.4. DIGITAL CORE
Dcoarse [kTs] Draw[kTs] addressing

function address
LUT based post-correction
Dout[kTs] fine linear 2 entries coarse 16 entries

9 entries
binary interpolation binary
search 9x eearch
address address
address
Figure 6.14: Block diagram of the implemented start-up calibration and its corresponding LUT based
post-correction circuit.
131
Dout . The addressing function is used during post-correction in order

to find the 16 candidates of the LUT which have the closest distance to
Draw . The described correction algorithm has the disadvantage that
the circuit complexity and memory requirements increase exponen-
tially with the resolution Nres of the ADC. To this end, the last ana-
log signal processing stage in the cascaded folding and interpolating
structure in Fig. 6.7 is designed to be a resistive interpolation circuit
expanding the transfer characteristic of the folding ADC linearly by
a factor of 9. This trick allows to store only a subset of the transfer
characteristic curve in the LUT. Linear interpolation in the digital
domain is deployed to reconstruct the transfer characteristic from the
subset stored in the random-access memory (RAM). Monotonicity of
the ADC allows focusing the binary search only on a sub-region of the
transfer characteristic (16 entries interpolated by a factor of 9). To
keep the complexity of the correction logic low, the search algorithm is
decomposed into coarse, interpolation, and fine stage. During coarse
binary search, the two closest neighbors of Draw needs to be found for
interpolation. After interpolation, the fine binary search is performed
to find Dout . Additionally, a moving average algorithm is provided to
run the SC integrator more than once during start-up to mitigate the
effects of thermal noise.
6.5 Measurement results

In the prototyped folding ADC, all analog and digital functions, in-
cluding calibration DAC and static non-linearity correction circuit, are
integrated on a core area of 1.74 mm2 . The measured INL is shown
in Fig. 6.16. The uncalibrated peak INL of 15.33 LSB is reduced to
2.34 LSB after calibration. The uncalibrated peak DNL of 1.76 LSB
is reduced to 1.56 LSB, respectively. In the left hand-side of Fig. 6.15,
the dynamic performance measurements of the folding ADC before
and after calibration are presented. A chip micrograph is shown
on the right hand-side. Fig. 6.17 shows the measured performance
at 150 MS/s in comparison to higher operating speeds. The ADC
achieves 9.6 ENOB at Nyquist frequency while running at 150 MS/s.
The FoM changes slightly from 2.8 to 2.9 pJ/conv when operating at
180 MS/s. The power consumption increases proportionally with the
0 ENOB = 6.84 bit
−20
before SFDR = 48.0 dB
calibration SNR = 55.6 dB
−40 THD = -43.1 dB
SC-Integrator
−60 Bandgap Track and Hold
−80
Amplitude (dB)
−100
SPI CLK
& Ladder
−120
Coarse
0 10 20 30 40 50 60 70 Quant.
Frequency (MHz)
0
1.69 mm
ENOB = 9.25 bit Cascaded Folding &
−20 after SFDR = 67.4 dB Calibr.
Averaging &
6.5. MEASUREMENT RESULTS
calibration SNR = 58.5 dB Logic

−40 THD = -62.2 dB Interpolation
−60 Fine Quantizer
RAM
−80
Amplitude (dB)
Bubble Error Correction
−100
−120
0 10 20 30 40 50 60 70
Frequency (MHz) 1.69 mm
Figure 6.15: Left: Measured output spectrum of a sinusoidal input signal at 60.123 MHz and 150 MHz
sampling frequency. Right: Chip micrograph of the implemented folding ADC in 130 nm CMOS
technology.
133
Table 6.1: ADC measurement results and comparison.
ESSCIRC’07 JSSC’09 This

[160] [27] work
Sampling rate [MHz] 200 1000 150

CMOS technology [nm] 130 180 130
Power consumption [mW] 195 1260 a
287b
ADC core area [mm ] 2
1.82 – 1.74
Die area [mm ] 2
3.24 49 c
2.86
Supply [V] 1.2 1.8 1.2/2.5d
SNRe[dB] – 57.4 60.6
SFDRe[dB] 63.6 – 69.7
THD [dB]
e
– – -65.3
ENOB [bit]
e
8.6 9.2 9.6
FoM [pJ/conv] 3.2 2.3 2.8
a
Power consumption per ADC channel
b
LVDS driver not included
c
Two ADCs present on same die
d
2.5 V supply for bandgap required
e
Sinusoidal input at 10 % of Nyquist frequency
15
10 before calibration
INL [LSB]
5
0
−5 after calibration
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Digital Output Dout
Figure 6.16: INL measurement before and after calibration at a

sampling frequency of 150 MHz.
6.6. CONCLUSION 135
9.5 59
9 56
8.5 53
SNDR [dB]
ENOB [bit]
8 50
10.123 MHz 20.123 MHz 40.123 MHz 60.123 MHz 80.123 MHz 99.123 MHz
7.5 47
100.123 kHz 150 MS/s, 287 mW, 2.8 pJ/conv
7 44
180 MS/s, 294 mW, 2.9 pJ/conv
6.5 41
210 MS/s, 300 mW, 3.2 pJ/conv
0 10 20 30 40 50 60 70 80 90 100
Input Frequency [MHz]
Figure 6.17: Measured ENOB versus input frequency.
sampling frequency. While operating at 210 MS/s, the ADC achieves

9.1 ENOB at low and 8.5 ENOB at Nyquist frequency with an FoM
of 3.2 pJ/conversion.
The measured characteristics of the ADC running at 150 MHz and
calibrated at 30 MHz sampling frequency are summarized in Tbl. 6.1.
Compared to [160], the prototyped folding ADC in this work achieves
better effective resolution and FoM. The folding ADC presented in [27]
uses analog pipelining techniques in the cascaded folding and interpo-
lating structure in order to achieve a sampling frequency of 1 GS/s.
Also a high precise DAC is implemented on-chip to generate the
reference training sequence for the calibration algorithm. The ADC
in [27] achieves similar effective resolution as in this work but with
slightly improved FoM and higher circuit complexity.
6.6 Conclusion and outlook

6.6.1 Conclusion
A 150-MS/s 11-bit digitally-calibrated folding ADC has been pre-
sented in this chapter which is prototyped in 130-nm CMOS technol-
ogy. A new start-up calibration with a LUT based post-correction
technique is described to compensate for static non-linearity errors
which mainly limit the precision of the folding ADC. The ADC de-
livers 9.6 ENOB at low and 9.1 ENOB at Nyquist frequency, consum-
ing 287 mW from a 1.2-V supply, while occupying a silicon area of
1.74 mm2 . The LUT based post-correction algorithm implementation
improves the precision of the ADC while enhancing the SNDR and
SFDR by around 15 dB and 20 dB, respectively. A FoM of 2.8 pJ/conv
is achieved in practice which is competitive to other folding ADC of
similar precision and signal bandwidth coverage published in litera-
ture.
Measurement results of the fabricated folding ADC reveals a mea-
sured peak INL of 15.33 LSB which is reduced to 2.34 LSB after cal-
ibration. The peak DNL of 1.76 LSB is reduced to 1.56 LSB, respec-
tively. While the peak INL is reduced by 13 LSB, the DNL does not
experience a similar large drop. A disadvantage of the LUT based
post-correction method, however, is that it mainly corrects the static
nonlinearity errors of the ADC, thus the INL.
6.6.2 Outlook
As already discussed in this chapter, the LUT based post-correction
algorithm improves the precision of the ADC while enhancing the
SFDR by 20 dB. This fact can also be seen in the measurement results
from the INL which is improved by of around 13 LSB after calibration.
Since the DNL (and accordingly the SNR) of the ADC did not improve
much because missing codes cannot be recovered in the digital domain
due to the large offset in the pre-amplification stage, the future of
this work must focus on hybrid calibration techniques [132] in order
to reduce the impact of offset and missing codes. Unfortunately, the
LUT based post-correction technique is transparent to missing codes.
The hybrid calibration technique discussed in Sec. 4.4 and pro-
posed here, uses digital tunable amplifiers in the pre-amplification
stage of the folding converter. The block diagram of the tunable
preamplifier is shown in Fig. 4.5. The architecture of the 11-bit folding
and interpolating ADC is illustrated in Fig. 6.18, where the LUT
based post-correction technique is combined with the hybrid calibra-
tion method [132].
Once the pre-amplification stage is calibrated, the LUT based
post-correction circuit is initialized such to run in the background
Analog Core Digital Core
27 NDAC 11
Bandgap Calibration Logic
1 Dout [kTs]
SC-Integrator
T/H
1
Clock
VT/H[kTs]
6.6. CONCLUSION
Vin(t) Coarse Fine

27 Quantizer Quantizer 144
54 18 36 12 48 16
digitally tunable
Reference Pre- Averaging & Folding Averaging & Folding Averaging & Folding Averaging &
Ladder amplifier Interpolation Amplifier Interpolation Amplifier Interpolation Amplifier Interpolation
Npre = 27 Nint,0 = 2 Nfold,1 = 3 Nint,1 = 2 Nfold,2= 3 Nint,2= 4 Nfold,3 = 3 Nint,3 = 9
Figure 6.18: Architecture of the 150-MS/s 11-bit digitally calibrated folding ADC which is extended with
a digitally tunable pre-amplification stage.
137
−20 SNR = 66.3 dB CLK track & hold

bandgap
SFDR = 78.2 dB SC-integr. reference gen.
SNDR = 65.0 dB
−40 ENOB = 10.5 bit digitally tunable
Amplitude (dB)
preamplifiers
1.90 mm
−60 coarse comparators
cascaded
folding &
−80 averaging &
interpolation
−100 digital fine comparators
calibr.
LVDS driver
0 20 40 60 80 100 120 140
Frequency (MHz)
1.85 mm
Figure 6.19: Left: Cadence AMS simulation results of the 11-bit

folding ADC performing a hybrid calibration technique. Right: Chip
micrograph of the implemented folding ADC in 130-nm CMOS.
and correct the remaining offset of the folding stages. As shown

in the left-hand side of Fig. 6.19, about 10.5 ENOB is achieved in
Cadence AMS simulations which is close to the quantization noise of
the converter. The power consumption increase of the ADC due to
the introduced tunable preamplifiers is expected to be negligible. A
chip micrograph with the desired extensions in the layout is shown in
the right-hand side of Fig. 6.19. The additionally introduced circuit
complexity increases the chip area by 20 %. A working realization of
the folding ADC employing the hybrid calibration technique is yet to
be fabricated and measured.
Chapter 7
Summary, Conclusion,
and Outlook
7.1 Summary
The trend in the IC industry for higher integration which is highly
motivated by Moore’s law, makes the advanced mainstream CMOS
technologies to offer relatively small and fast transistors. These sub-
micron transistors with reduced supply voltage compared to prior
technology generations, are the preferred switching devices when build-
ing cheap and low-power digital computing hardware. As digital
circuits fully benefit from CMOS scaling, also partly due to the re-
duced supply voltage which directly improves their power efficiency,
the supply voltage, however, directly decreases the available SNR in
analog circuits.
The two most fundamental parameters of data converters are the
sampling frequency fs , at which the analog input signal is sampled,
and the resolution Nres , which determines the minimum analog in-
put to be resolved and its digital counterpart. The ADCs simi-
larly experience an increase in sampling rate due to technology scal-
ing. However, achieving high resolution in ADCs remains challenging.
In this thesis, the technology scaling benefits of digital circuits are
exploited in Nyquist-rate ADCs. Digitally assisted calibration and
139
140 CHAPTER 7. SUMMARY, CONCLUSION, AND OUTLOOK
post-correction techniques are considered, in order to improve the

resolution of Nyquist-rate ADCs. In particular, calibration techniques
improving the static performance of converters are discussed. To this
end, calibration and post-correction algorithms are developed and
optimized for the SAR and folding ADCs. Corresponding very large
scale integration (VLSI) architecture results of the converters and
analysis of associated performance/complexity trade-offs demonstrate
the effectiveness of digital post-correction in practical Nyquist-rate
sampling systems.
Digitally calibrated 14 bit SAR ADC in 130 nm CMOS

Two different prototypes of a 14 bit sub-radix-2 SAR ADC employing
a redundant segmented capacitor array are presented. Redundancy
combined with LUT based post-correction directly implemented on
chip, corrects capacitor mismatch in the converter and enhances its
resolution by more than 10 dB. The realization of the ADC shows the
effectiveness of digitally assisted calibration techniques in practice.
Prototype I consumes 0.92 mW at 2 MS/s and 1.78 mW at 4 MS/s,
resulting in a FoM of 160 fJ/conversion and 286 fJ/conversion. The
implementation achieves uncalibrated 59.6 dB (9.6 bit) and calibrated
71.1 dB (11.5 bit) SNDR at 2 MS/s and uses the input signal of the
converter to measure/estimate the capacitor weights digitally. The
converter is a suitable alternative solution to Σ∆ based ADCs in
mobile communications.
Prototype II has been designed for battery-powered biomedical
devices. In battery-powered medical instrumentation, the resolution
and signal bandwidth of ADCs has to be adapted to the needs of
the application to avoid power wastage. For this reason, a recon-
figurable 5-14 bit SAR ADC is implemented in 130-nm CMOS. The
proposed flexible ADC can be tuned to operate ultra low-power to
only fulfill minimal specifications on the signal quality, e.g., when
awaiting activity or a specific pattern in a biomedical signal. The
system, however, is able to recover full performance if required, e.g.,
when activity or the specific pattern is detected. Measurements of the
calibrated chip show an ENOB of 12.9 bit at a sampling rate of 286 kHz
with a FoM of 59 fJ/conversion while consuming 130 µW. Lowering the
resolution from 14 to 5 bit, the power consumption is reduced by 70 %.
7.2. CONCLUSION 141
Using non-subtractive dither in combination with post-correction, the

converter resolves a maximum achievable ENOB of 13.5 bit.
A 1.2 V 150 MS/s 11 bit folding ADC with 9.6 ENOB

The implemented folding converter targets a resolution of 11 bit at
150 MS/s. A digitally assisted start-up calibration technique is em-
ployed in the converter to compensate for static non-linearity er-
rors. The post-correction algorithm improves the precision of the
converter while enhancing the SNDR and SFDR by around 15 dB and
20 dB, respectively. A FoM of 2.8 pJ/conversion is achieved in prac-
tice which is competitive to other folding ADCs of similar precision
and sampling rate. The ADC achieves uncalibrated 6.8 ENOB and
calibrated 9.6 ENOB at low and 9.1 ENOB at Nyquist frequency. It
consumes 287 mW from a 1.2 V supply while occupying a silicon area
of 1.74 mm2 .
7.2 Conclusion
The measurement results obtained from the prototyped ASICs show
the effectiveness of digital calibration techniques in practical Nyquist-
rate converter implementations. For the SAR ADC, the resolution
is enhanced by more than 10 dB in Prototype I. A LMS-based learn-
ing algorithm is implemented on-chip to estimate the weights of the
capacitor array and correct static errors. LMS has the advantage
that the requirements on the calibration reference signal are relaxed
such that Prototype I is calibrating in the background, i.e., without
using a calibration reference at all. Prototype II uses a non-precise
reference ladder in order to generate a triangular shaped calibra-
tion reference signal. The ADC only stores about Nres capacitor
weights in the LUT to perform post-correction. Redundancy in the
implemented single-reference ADCs suppresses missing codes in their
transfer characteristic curves and makes post-correction more robust.
Unfortunately, digital post-correction algorithms with no redundancy
are transparent to missing codes.
In order to achieve maximum resolution, i.e., the converter is
only limited by quantization noise, the LUT based post-correction
142 CHAPTER 7. SUMMARY, CONCLUSION, AND OUTLOOK
algorithm in Prototype II is extended with digital noise reduction

techniques such as non-subtractive dither, oversampling, and majority
voting. While digital calibration compensates for static errors, noise
reduction techniques improve the noise performance of the ADC.
Measurement results of Prototype II show that the effective resolution
of the converter is only limited by quantization noise after calibration
and digitally applicable noise reduction techniques.
The results of the prototyped SAR ADC implementations show
not only the effectiveness of digital calibration techniques but also
how easily single-reference converters can be extended with digitally
based noise reduction techniques.
The realization of a 1.2 V digitally calibrated folding ADC shows
the efficiency of post-correction in multi-reference ADCs. The ADC
has a differential input voltage range of 1 Vpp . The proposed start-up
calibration deploys an area-efficient SC integrator as a reference source
to provide calibration vectors required in the static non-linearity cor-
rection algorithm, instead of using a high resolution DAC [27] where
silicon area increases exponentially with resolution Nres . The 11-bit
multi-reference ADC stores about 256 calibration values in the LUT to
perform post-correction. Compared to the single-reference SAR ADC
implementation, the multi-reference folding ADC requires a much
larger LUT. The proposed low-complexity post-correction algorithm
improves the precision of the folding ADC while enhancing the SNDR
and SFDR by around 15 dB and 20 dB, respectively.
7.3 Outlook
The remaining research topics for digitally calibrated Nyquist-rate
ADCs are outlined in the following two paragraphs.
Theory and algorithms
• Digitally based correction methods to minimize the occurrence

of missing codes in the transfer characteristic curve of the folding
ADC (equivalent to redundancy in SAR ADCs) is an open topic
and needs to be further analyzed.
7.3. OUTLOOK 143
• Time-interleaving of ADCs is a new research topic of practical

relevance in order to enhance the sampling bandwidth of ADCs.
Instead of designing a highly complex multi-reference ADC to
cover a relatively high signal bandwidth, multiple low-complex
and power-optimized single-reference ADCs can be run in a
time-interleaved manner. A detailed complexity analysis and
a comparison of a multi-reference ADC with a time-interleaved
single-reference ADC in terms of power efficiency and silicon
area is still an open topic.
• A detailed analysis and implementation of post-correction tech-
niques for all other types of Nyquist-rate ADCs besides the SAR
and folding converters is an open topic in this thesis.
Circuit implementation aspects

• While improvements in resolution are reported for all imple-
mented converters in this thesis, their sampling rates are rel-
atively low, in particular in the SAR ADC prototypes. The
folding ADC achieves a sampling rate of over 150 MS/s, while
both SAR ADC prototypes achieve sampling rates between 2-
4 MS/s in the 130-nm technology. The implementation of the
SAR ADC in a modern sub-micron technology, e.g., 28 or 14-nm
CMOS, also remains an open topic in order to analyze the speed
improvements of SAR ADCs due to technology advancement.
• A detailed analysis of pipeline techniques in the cascaded struc-
ture of the folding ADC architecture is an open research topic
that is of practical relevance.
• A working realization of a folding ADC employing a hybrid
calibration technique is yet to be fabricated and measured.
Appendix A
Power Contributors in
SAR ADCs
The literature on SAR ADCs [42, 134, 161–164] partly claims, that
the capacitor array and its switching scheme has a large impact on
the power consumption of the SAR ADC. In order to prove this
assumption, these publications compare the dissipated energy in the
capacitor array using a highly optimized switching scheme in par-
ticular with the conventional converter published in [40] which in
most of the cases serves as a reference design. As conventional, the
firstly published capacitor array in [40] is denoted which is shown
in Fig. A.1). Since the conventional SAR ADC was implemented in
a technology using a supply voltage of VDD = 5 V, its architecture
is typically single-ended. A high dynamic range can be achieved in
practice through the relatively high supply voltage. The conventional
switching scheme of the SAR ADC uses a single reference voltage Vref
referred to ground (VGND ) to perform its conversion algorithm.
This appendix, however, disproves partly the assumption which
claims that the power consumption of the SAR ADC mainly depends
on the capacitor array and its switching scheme, and shows that
the research should focus more in realizing low-power and low-noise
reference generation circuits for SAR ADCs. Therefore, the power
145
146 APPENDIX A. POWER CONTRIBUTORS IN SAR ADCS
VGND Vtop Dcomp,i Dout [kTs]

SAR
Vref
VGND
Vin (t)
Figure A.1: Block diagram of the conventional 3-bit SAR ADC.
contributors of the conventional SAR ADC, i.e., the power consump-

tion of the dynamic comparator, digital logic, reference and input
buffer are considered in more details. As will be shown, the generation
of reference signals dominate the power consumption of SAR ADCs
for moderate-to-high signal bandwidths.
A.1 Performance metrics

The efficiency of the SAR ADC can either be defined as energy per
sample Es [10] or as power consumption P in Watt. The relationship
between energy Es and power dissipation P is defined as
P
Es = .
fs
For circuit elements consuming dynamic power, i.e., their power con-
sumption tend to increase proportionally with the sampling frequency
fs , it is desirable to consider the energy per sample Es which is
independent of the sampling frequency fs .
The overall SNR of the SAR ADC can be formulated as
2
1 Vin,pp
2 2
SNR = , (A.1)
σ2buf + σ2comp + σ2ref + σ2quant
where σ2buf is the noise variance of the input buffer, σ2comp the noise
variance of the comparator, σ2ref the noise variance of the reference
A.2. DYNAMIC COMPARATOR 147
Cc Cc
Figure A.2: Simplified block diagram of the dynamic comparator in

the SAR ADC where the positive feedback loop is illustrated. The
decision of the comparison is stored in the capacitors Cc .
buffer, and σ2quant the quantization noise variance of the ADC. The
2
term (0.5Vin,pp ) /2 corresponds to the average power of a full-scale
sinusoidal signal. The derivation of (A.1) can be done similar to (3.24).
The achievable nominal resolution Nres of the ADC is related to the
SNR [7] according to
SNR − 1.76
Nres = . (A.2)
6.02
In the following calculations, it is assumed that static nonlinearity
errors are corrected off-line and therefore, the ADC is not limited by
them. The converter is also optimized to improve its noise perfor-
mance. Flicker noise is also neglected based on the assumption that
the SAR ADC is operated at moderate sampling frequency fs .
In the following, the impact of noise on the comparator, digital
logic, and reference buffer are considered in more details. Further dis-
cussion on quantization noise, however, can be found in App. D. Cir-
cuit techniques improving the quantization noise of the SAR ADC, i.e.,
non-subtractive dither and majority voting, are discussed in Chap. 5.
A.2 Dynamic comparator

Fig. A.2 illustrates a simplified block diagram of the dynamic com-
parator. The two inverter in the loop represent the positive feedback
loop of the comparator. The size of capacitor Cc needs to be chosen
such to achieve the desired SNR which depends on the nominal res-
olution Nres of the converter. Assuming that the comparator is only
allowed to contribute 1/4 of the overall noise in (A.1), the SNR can
be simplified to
2
1 Vin,pp
2 2
SNR = ,
4σ2comp
with σ2comp = kB T /Cc . The noise performance of the dynamic com-

parator is mainly limited by thermal noise.
The energy required in the dynamic comparator can be formulated
as
Ecomp = Nres Cc VDD

2
2
VDD
= 32Nres SNR 2 kB T,
Vin,pp
where Nres bit are resolved for a sampled input signal. The power
consumption of the latch at the output of the dynamic comparator
is neglected in here since it is technology dependent (due to the wire
and parasitic capacitance of the latch) and does not contribute much
to the overall power consumption of the comparator, in particular for
ADCs with moderate-to-high resolutions.
A.3 Digital logic of the SAR ADC

A simplified block diagram of the SAR digital logic is shown in Fig. A.3.
It consists of a shift register with Nres cascaded registers, a FSM, and
buffers to drive the parasitic capacitors of the switches in the capacitor
array. The size and power consumption of the digital SAR logic
increases with the resolution Nres of the ADC. The average energy
dissipated to process a sampled signal [10] can be formulated as
K(Nres )
X αk
Edigital = VDD
2
Ck ,
2
k=1
where αk denotes the activity of node k and K (Nres ) is the set of nodes
where charge is transferred and it depends on the resolution Nres of
the ADC. However, the node capacitors Ck of the digital circuit do
A.4. REFERENCE BUFFER 149
CLK shift register
IN OUT
D Q D Q D Q D Q
FSM
clock phases for the capacitor array

...
Figure A.3: Simplified block diagram of the digital successive approx-

imation register (SAR) logic.
not have to fulfill any noise requirements. They mainly depend on the
CMOS technology (wire and parasitic capacitors) and decreases with
the on-going miniaturization of transistors.
Since the average energy dissipated in the digital logic of the
SAR ADC is technology dependent and negligibly small compared
to the other circuit elements of the converter, further analysis and
discussions on the power consumption in the digital logic are skipped
in this thesis.
A.4 Reference buffer
In order to simplify the power analysis of the reference buffer, a

simplified model of the buffer is shown in Fig. A.4 a). Fig. A.4 b)
illustrates a differential pair with active load which can be a simplified
amplifier topology used to design the reference buffers.
VDD
Vref M3 M4
A
Vout
Cu Cu 2Cu 4Cu
M1 M2
+ -
Vin Vin
Iss
a) b)
Figure A.4: a) Block diagram of a reference buffer connected to a 2-bit

capacitor array [165]. b) Differential pair with active load as amplifier
in the reference buffer.
DC gain of the amplifier in the reference buffer

The finite DC gain A of the amplifier has an impact on the preci-
sion of the closed-loop transfer function of the reference buffer shown
in Fig. A.4 a) with the feedback factor β = 1. The gain error factor ζ
caused by the finite DC gain A can be approximated as
Aβ β=1 1
ζ =1− ≈ .
1 + Aβ A
Requiring for example a gain error factor ζ of 1 %, demands for an

open-loop DC gain of A = 40 dB. The differential pair with active
load shown in Fig. A.4 b) is used for illustration purposes since it
has a simple architecture to be analyzed analytically. The complex-
ity of more advanced amplifier architectures demands for numerical
analysis.
The DC gain of the amplifier, however, highly depends on the
underlying CMOS technology. As CMOS technology continues to
evolve, its supply voltage is scaled more aggressively relative to the
threshold voltage which has remained almost constant [104]. The
inherent gain of transistors, however, is dropped with the development
of newer technologies. Classical techniques to achieve high DC gain

by vertically stacking (cascoding) of transistors is not possible in
sub-micron technologies, since the available signal swing is limited
by the reduced supply voltage. In order to achieve high DC gain in
practice, horizontal cascading is used instead. Advanced single-stage,
e.g., telescopic and folded cascode [166], or multi-stage amplifiers can
be used, if a higher DC gain is required in the amplifier of the reference
buffer.
Noise in the reference buffer

Assuming that the reference buffer shown in Fig. A.4 a) is only al-
lowed to contribute 1/4 of the overall noise in (A.1), the SNR can be
reformulated as
2
1 Vin,pp
2 2
SNR = , (A.3)
4σ2ref
where σ2ref is the input-referred noise variance of the amplifier. The

noise performance of the amplifier is mainly limited by thermal noise.
Using the simple differential pair with active load shown in Fig. A.4
b) as amplifier architecture in the reference buffer, its input-referred
noise variance [167] can be approximated as
2
σ2ref = 8kB T ∆f (1 + gm3 )
3gm{1,2}
gm3 1 2
≈ 8kB T ∆f, (A.4)
3gm{1,2}
where gm3 /gm{1,2} is minimized in the design in order to optimize the

noise performance of the buffer. The bandwidth of the buffer must be
at least Nres times higher than the sampling frequency of the ADC,
i.e., ∆f = Nres fs . The reference buffer needs to settle during each bit
cycle of a conversion. Setting (A.4) in (A.3) results in
512 SNR
gm{1,2} = kB T Nres fs .
3 Vin,pp
2
The power consumption of the buffer can be formulated as

Pref,noise = Iss gm{1,2} VDD , (A.5)

where Iss gm{1,2} is determined by the transconductance gm{1,2} of

the input pair transistors.
Settling characteristics of the reference buffer

The settling time of the amplifier is another critical design parameter
besides the noise performance. As seen in Fig. A.4 a), the maximum
load capacitor to be charged and discharged for each sampled input
signal equals to
CL = 2Nres Cu , (A.6)
where the unity capacitor Cu is mainly determined by the thermal
noise considerations of the sampling in the capacitor array in order to
resolve Nres bit.
The linear settling time of the amplifier is much longer than its
slewing time [165, 167]. During slewing time, the amplifier slews to
around 90 % of the desired output voltage. The linear settling (small-
signal operation) steers afterwards the output voltage to minimize
the settling error of the amplifier ss to an appropriate level. The
bandwidth of the amplifier mainly determines the settling time in
the linear settling region. The cross-over between the slewing and
linear settling regions cannot be determined precisely and for this
reason, 30% of the total settling time is allocated for slewing and
70 % for linear settling in here [165]. The slew rate of the amplifier
can therefore be formulated as
Iss Vref /2
SR = = , (A.7)
2CL 0.3Ts
where the largest change in voltage is expected to be Vref /2 for the
largest capacitor CL in the array which is defined in (A.6). The re-
quirements on the power consumption during slewing of the amplifier
can accordingly be calculated using (A.7) as
Vref CL
Pref,slew = Iss VDD = VDD . (A.8)
0.3Ts
The linear settling region of the amplifier also dictates a require-

ment for the power consumption of the amplifier. The required set-
tling time in this region increases with the desired resolution Nres of
the ADC. The settling error ss of the amplifier during linear settling
can be defined as
VFS
ss = exp (−t/τ ) < , (A.9)
2Nres +1
where τ = 1/ (2πfug β) is the time constant, fug is the unity-gain
frequency, and VFS is the full scale range of the ADC. It is assumed
here that in the ADC, the settling error of the amplifier is smaller
than LSB/2. An expression for the unity gain bandwidth fug of the
amplifier can be formulated as
log(ξ) gm{1,2}
fug = − = . (A.10)
2π0.7Ts 2πCL
An expression for the transconductance gm{1,2} of the differential pair
transistors using (A.9) and (A.10) can be calculated as
log(VFS /2Nres +1 )
gm{1,2} = − CL .
0.7Ts
The power consumption of the buffer can be derived from the expres-
sion
Pref,settl = Iss gm{1,2} VDD . (A.11)

Depending on the resolved resolution Nres and the sampling frequency

fs of the ADC, the power consumption of the amplifier in the reference
buffer can be dominated by either noise, slewing or settling require-
ment, and must be optimized using (A.5), (A.8), and (A.11) as
Iref = max (Iref,noise , Iref,slew , Iref,settl ) .

Nres ,fs
Transconductance-to-current ratio gm /Ids

The important parameter to calculate the power consumption of the
reference buffer in (A.5) and (A.11) is the transconductance gm{1,2}
of the input-pair transistors of the amplifier [166].
small large
W/L g m / Ids [V-1] W/L
5 10 15 20
strong inversion weak inversion
poor current efficiency 2 / ( g m Ids ) [V] good current efficiency
425m 225m 175m 125m
Figure A.5: Transistor current efficiency gm /Ids for a differential pair

with active load designed in 130-nm CMOS technology and simulated
in Cadence Spectre. The tail current source equals Iss = 1 mA and the
length of the input pair transistor is set to L = 500 nm. The width W
of the input-pair transistor is tuned accordingly to move from strong
to weak inversion.
The transconductance-to-current ratio gm /Ids represents the in-

put voltage of the transistor to the output current transformation
efficiency. The relationship of gm /Ids is shown in Fig. A.5 for the
differential pair used in the reference buffer. In order to analyze
transistors for both weak and strong inversion region of operation as
well as in moderate inversion region in between, an accurate transistor
model is required.
The current consumption of the reference buffer for the three

analyzed design requirements, i.e., noise, slewing, and settling, is
depicted in Fig. A.6. In these simulations, the input pair is considered
to operate in strong inversion in order to get the worst case current
consumption. For low resolution ADCs, the current consumption of
the reference buffer is determined by the slewing requirement of the
amplifier. For higher resolutions, however, the power consumption for
the linear settling requirement dominates. The sampling frequency is
set to fs = 200 kHz in this simulation which is comparable to the
results presented in Chap. 5.
A.5. CONCLUSIONS 155
−3
10
−4
a) b)
10
current consumption [A]
−5
10
−6
10
Iref
−7 Iref,noise
10
I
ref,settl
I
ref,slew
−8
10
8 9 10 11 12 13 14
resolution Nres [bit]
Figure A.6: Simulated current consumption of the reference buffer

where the three analyzed requirements, i.e., noise, slewing, and
settling, are illustrated. Two cross-sections are highlighted: a) The
current consumption of the amplifier given by the slewing requirement
dominates for below Nres = 9.4 bit. For higher resolutions the current
consumption given by the linear settling dominates. b) The minimum
allowed unity capacitor C0 is limited to 1 fF in the simulations. This
is the reason why the slope of the curve changes at around 12.8 bit.
A.5 Conclusions
The power consumption of the main power contributors in the SAR

ADC are depicted in Fig. A.7. As expected, the power consumption
of the reference buffer dominates in the SAR ADC if compared to the
dynamic comparator. However, in practical ADC applications more
reference buffers might be necessary, i.e., also for the common-mode
and negative reference voltages, which increase the power consump-
tion of the reference buffers by another factor of 2-3.
The analysis and evaluation of the input buffer in the ADC can
be performed similar to the reference buffer. Since the input buffer
also consists of an active circuit element (i.e., the amplifier) which
consumes static power, it is expected that the input buffer shows sim-
ilar power performance like the reference buffer. A detailed analysis
−3
10
−4
10
power consumption [W]
−5
10
−6
10 Pref
P
comp
−7
10
8 9 10 11 12 13 14
resolution Nres [bit]
Figure A.7: Simulated power consumption in the conventional SAR

ADC. The sampling frequency is set to fs = 200 kHz.
of the input buffer is skipped in this thesis. These results show, how-
ever, that the optimization of the switching scheme in the capacitor
array has less impact on the overall power consumption of the SAR
ADC which is mainly dominated by the reference buffers. Thus, the
research on SAR ADCs should focus more on the generation of low
power reference generations circuits instead, e.g., duty cycling of the
reference buffers [136] to lower the power consumption of SAR ADCs.
Appendix B
Impact of Mismatch on
MOS Differential Pairs
B.1 Input-referred offset voltage Vos

The impact of mismatch on a simple differential pair is shown in three
different steps. The block diagram of the differential pair is depicted
in Fig. B.1. Firstly, the threshold voltage mismatch is considered.
The impact of resistor and current factor mismatches are studied in
the further steps.
The structure of the simple differential pair is essential to be stud-
ied in practice because it builds the analog front-end of preamplifiers
as well as comparators in ADCs.
Mismatch of threshold voltage

The following equation
∆VTH
VTH,{1,2} = VTH ±
2
describes the mismatch of the threshold voltage VTH for the input-pair
transistors M1 and M2 . All other components are assumed to be ideal
for the moment.
157
158 APPENDIX B. MISMATCH IN MOS DIFFERENTIAL PAIRS
VDD +
Vout - Vout
-
-
I out I
+
out
RL Iss
RL1 RL2
- +
Vout Vout
+ -
+
Vin M1 M2 Vin
-
Vin - Vin
-RL Iss
Iss
a) b)
Figure B.1: a) Block diagram of a simple differential pair. b) transfer

characteristic curve of a simple differential pair.
The current in the branches of the differential pair can be calcu-

lated as
2
∆VTH

β
Iout =
+
VGS − VTH −
2 2
2
∆VTH

β 2
= (VGS − VTH ) 1 −
2 2 (VGS − VTH )
and
2
∆VTH

− β 2
Iout = (VGS − VTH ) 1 + ,
2 2 (VGS − VTH )
assuming both transistors of the input pair operating in the saturation
region. Taking the difference of the currents in both branches, and
assuming that the difference ∆iout is relatively small, its second-order
Tailor approximation leads to
−
∆iout = Iout
+
− Iout
∆VTH

Iss
= . (B.1)
2 VGS − VTH
B.1. INPUT-REFERRED OFFSET VOLTAGE VOS 159
The input-referred offset voltage Vos can be derived from (B.1) as
∆vout

Vos = = ∆VTH , (B.2)
A0 vin =0
where the gain of the differential pair is A0 = gm RL and the small-

signal output voltage is given by ∆vout = ∆iout RL . The transconduc-
tance gm of a transistor operating in saturation is defined as
Iss
gm = .
2 (VGS − VTH )
Load resistor mismatch

In the following, it is assumed that the load resistors RL , as illustrated
in Fig. B.1, experience mismatch. Thus, the load resistors can be
described as
∆RL
RL,{1,2} = RL ± ,
2
while considering all other electrical parameters of the differential pair
to be perfectly matched for the moment. The small-signal output
voltage of the amplifier is given as
− Iss
∆vout = Vout
+
− Vout = ∆RL .
2
The effect of the mismatched resistors on the input-referred offset
voltage Vos can be calculated as
∆vout VGS − VTH ∆RL

Vos = = . (B.3)
A0 vin =0 2 RL
Current factor mismatch

Consider that the transistors M1 and M2 at the input of the differential
pair are mismatched according to
1 ∆W

W W
= ± .
L {1,2} L 2 ∆L
160 APPENDIX B. MISMATCH IN MOS DIFFERENTIAL PAIRS
The small-signal output voltage ∆vout can be expressed as

Iss ∆ (W/L)
∆vout = RL .
2 (W/L)
With β = µn Cox W L being the current factor of an NMOS transistor,

the input-referred offset voltage Vos can be calculated for the differ-
ential pair (shown in Fig. B.1) as
(VGS − VTH ) ∆β
Vos = . (B.4)
2 β
B.2 Variance of the input-referred offset

voltage Vos
The impact of mismatch in a differential pair leads to the input-
referred offset Vos and can be summarized using (B.2), (B.3), and
(B.4) as follows:
VGS − VTH ∆β ∆RL

Vos = −∆VTH + + .
2 β RL
Assume that the different sources of mismatch leading to the input-
referred offset voltage Vos are independent of each other and with
zero-mean. The following general expression can be formulated for
the variance of the input-referred offset voltage Vos of a CMOS based
differential pair
2
∆β ∆RL

VGS − VTH
σ 2 (Vos ) = σ 2 (∆VTH ) + σ2 + σ2 .
2 β RL
For the CMOS transistor operating in saturation, the mismatch of the
threshold voltage VTH dominates over the β mismatch. The matching
of resistors is much better than the one of transistors. Therefore, the
standard deviation of the input-referred offset Vos of a differential pair
can be simplified as
AV
σ (Vos ) ≈ σ (∆VTH ) = √ TH .
WL
Appendix C
Mismatched Channels in
Time-Interleaved ADCs
Assuming a time-interleaved sampling system consisting of a parallel

set of M time-interleaved ADCs as shown in Fig. C.1. The ADCs ex-
perience component mismatch due to fabrication imperfections. The
resulting gain and offset mismatches between the ADCs result in
static nonlinearity errors. A simple LMS based algorithm is proposed
to estimate the gain and offset mismatches between the channels
according to [153]. The algorithm compensates channel mismatch
during post-correction to enhance the linearity of the time-interleaved
sampling system. Assume the first channel as a reference channel.
Vin,0 (t) Dout,1 [(k+0)Ts]

ADC 0
Vin,1 (t) Dout,2 [(k+1)Ts] Dout [(k+i)Ts]

DEMUX
Vin (t)
MUX
ADC 1
Nres
...
Vin,M-1 (t) Dout,M [(k+M-1)Ts]

ADC M-1
Figure C.1: Blocklevel diagram of time-interleaved ADCs [168].
161
162 APPENDIX C. TIME-INTERLEAVED ADC
The other channels are corrected in accordance to the reference chan-

nel [168]. For this reason, LMS is used to minimize the error between
the reference (0) and the other (M − 1) channels. The gain and offset
of the different ADC channels can be modeled as
Dout [kTs ] = (1 + ∆Gi ) Vin [(kM + i) Ts ] + ∆Oi i = 0, 1, . . . , M − 1,
where ∆Gi is the difference in gain of the i-th channel to the reference
one. The term ∆Oi is the offset difference between the i-th channel
to the reference one. After estimating the gain Ĝi and offset Ôi for
the i-th channel, the output of the different time-interleaved channels
of the ADC can be corrected as
D̂out [(k + i)Ts ] = Ĝi [kTs ] · Dout [(k + i)Ts ] + Ôi [kTs ],
with Ĝ0 = 1 and Ô0 = 0.

The estimated gain Ĝi [kTs ] and offset Ôi [kTs ] for the i-th channel
are both varying with each new sample. The following recursive
equations can be derived using the LMS approach to correct the gain
and offset mismatch between the channels

Ôi [kTs ] = Ôi [kTs ] − µo D̂out [(k + i)Ts ] − Dout [kTs ]

Ĝi [kTs ] = Ĝi [kTs ] − µg D̂out [(k + i)Ts ] − |Dout [kTs ]| ,

where µo and µg are the learning factors of the LMS. The smaller
the learning factors, the slower the LMS will converge and the more
precise the estimation becomes.
In case, if the size of the learning factors µo and µg are not chosen
properly, the LMS might not converge. Also the choice of the input
signal Vin (t) for calculating the recursive LMS equations is important
in order to determine the stability of the algorithm. In practice, it
is preferable in terms of stability to use an input signal Vin (t) with
known statistical characteristics during start-up to estimate the gain
and offset of the channels.
Appendix D
Non-Ideal Quantizers
D.1 Impact of DNL errors on SNR in non-

ideal quantizers
In order to analyze the influence of DNL on the SNR of a non-
ideal quantizer [25], it is assumed, that two neighboring code words
influence each other when σDNL2
> 0. This model is shown in Fig. D.1
where two different quantizers are illustrated, i.e., a real and an ad-
justed one [16]. The adjusted quantizer is derived from the real one
such that all code centers between two adjacent transitions intersect
the ideal transfer characteristic curve resulting in INLi = 0 for the
ith code word. The DNLi is non-zero in the depicted model and
is identically, independent, and uniformly distributed within 2 LSBs
with the probability density function P (ξ) = 1/(2∆) and the variance
2
σDNL . The term ∆ determines the ideal code bin width.
Assuming statistical independence between digital output codes
due to DNL, the expected total error energy can be calculated as
res −1
2NX
(Z )
1 ∆/2(1+DNLi )
E {PDNL } = E P (ξ)ξ dξ
2
2Nres −1 i=0 −∆/2(1+DNLi )
res −1
2NX
(Z )
1 ∆/2(1−DNLi )
+ E P (ξ)ξ dξ
2
, (D.1)
2Nres −1 i=0 −∆/2(1−DNLi )
163
164 APPENDIX D. NON-IDEAL QUANTIZERS
Q (w)
real quantizer
adjusted quantizer
w
a)
ξ (w)
(1+DNLi) Δ/2
Δ
Δ/2
w
-Δ/2
-Δ
(1-DNLi) Δ/2
b)
Figure D.1: Influence of DNL on neighboring code words within an

interval of 2∆.
with the assumption that two adjacent code words share the same
DNL at the transition between them.
Computing the integral in (D.1) yields
∆2 ∆2

3 3
E {PDNL } = E (1 + DNL) + (1 − DNL)
24 24
∆2
= 1 + 3σDNL
2

.
12
D.2. IMPACT OF INL 165
ξ (w)
Δ INL i-2 Δ INL i-1 Δ INL i Δ INL i+1
Δ/2
w
-Δ/2
ideal quantizer
non-ideal quantizer
Figure D.2: Quantization error of a non-ideal quantizer.
D.2 Impact of INL errors in quantizers

The influence of INL errors is shown in Fig. D.2. As can be seen,
the error for the different codes is not anymore centered but instead
shifted by ∆INLj for the j-th INL value when assuming σINL > 0
for a non-ideal quantizer. This randomly-distributed shift of the
code centers can be modeled with a normal zero-mean distributed
probability density function with the variance ∆σINL as
1 ξ2

P (ξ) = √ exp − 2 .
2πσINL ∆ 2σINL ∆2
The probability density function is shown in Fig. D.3. The total

error energy can be computed according to
res −1
2NX ∞
1
Z
E {PINL } = E P (ξ)ξ dξ .
2
2Nres −1 i=0 −∞
Finding a solution for this integral is straightforward as it is the second

moment of the continuous function P (ξ). The n-th moment mn of a
real-valued and continuous function P (ξ) with zero mean is described
through the integral
Z ∞
mn = ξ n P (ξ)dξ.
−∞
166 APPENDIX D. NON-IDEAL QUANTIZERS
P (Δ)
1
√2π INL ∆
Δ
Δ INL
Figure D.3: Probability density function of INL errors.
Thus, the second moment for P (ξ) which is normally distributed,

yields
E {PINL } = ∆2 σINL
2
.
Appendix E
Notation and Acronyms
Symbols
AC mismatch constant of capacitor

AR mismatch constant of resistor
AVTH threshold voltage mismatch constant of transistor
Aβ current factor mismatch constant of transistor
Cs sampling capacitance
Dout resolved digital output
Draw resolved raw digital output
LC capacitor length
LR resistor length
L transistor length
Nres nominal resolution
T temperature
Ts sampling period
VDD supply voltage
VFS full-scale signal range
167
168 Acronyms
VLSB least-significant bit voltage

VGND ground voltage
VTH threshold voltage of CMOS transistors
Vin analog input voltage
WC capacitor width
WR resistor width
W transistor width
β current factor of CMOS transistor
fin frequency of input signal
fs sampling frequency
kB Boltzmann constant
Operators
|·| absolute value

d·e ceil: smallest integer value equal to or larger than argu-
ment
b·c floor: largest integer value equal to or smaller than
argument
si i-th entry of vector s
E {·} expectation operator
log2 base-2 logarithm
log10 base-10 logarithm
mod(·) modulo operator
sgn(·) signum operator
Acronyms
ADC analog-to-digital converter

Acronyms 169
ASIC application-specific integrated circuit
CAD computer-aided design

CMFB common-mode feedback circuit
CMOS complementary metal-oxide semiconductor
DAC digital-to-analog converter

DNL differential nonlinearity
DTL double-tail latch
DUT device under test
EPROM erasable programmable read only memory
FoM figure-of-merit
FSM finite-state machine
IC integrated circuit
INL integral nonlinearity
IP intellectual property
ISSCC international solid-state circuits conference
JSSC journal of solid-state circuits
LMS least-mean-square
LSB least-significant bit
LUT look-up table
LVDS low-voltage differential signaling
MIM metal-insulator-metal
170 Acronyms
MOM metal-oxide-metal
MSB most-significant bit
RAM random-access memory

RF radio frequency
RMS root mean square
ROM read-only memory
SA successive approximation
S/H sample-and-hold
S/P serial-to-parallel
SAR successive approximation register
SC switched-capacitor
SFDR spurious-free dynamic range
SNDR signal-to-noise-and-distortion ratio
ENOB effective number of bits
SNR signal-to-noise ratio
SoC system-on-chip
SPI serial peripheral interface
T/H track-and-hold
THD total-harmonic-distortion ratio
VLSI very large scale integration

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Curriculum Vitae
Schekeb Fateh received the M.S. degree in electrical engineering from

ETH Zurich, Switzerland, in 2009. In the same year, he joined the
Integrated Systems Laboratory (IIS) of ETH Zurich, where he was
pursuing his Doctor of Sciences degree. From 2009 to 2015, he was
working under the supervision of Prof. Dr. Q. Huang as a Research
Assistant at the IIS .
His research interests include the design of high-speed analog and
mixed-signal circuits and systems for wireless communications with
emphasis on analog-to-digital converters as well as the implementation
of multi-purpose, low-power, and miniaturized biomedical devices. He
received (jointly with Dr. Studer and Dr. Seethaler) the Swisscom
and ICTnet Innovations Award 2010 for the work on “VLSI Imple-
mentation of Soft-Input Soft-Output Minimum Mean-Square Error
Parallel Interference Cancellation”.
Since 2012, he has been leading a group of system and design
engineers in order to develop VLSI circuits and systems for wearable
biomedical devices where his research is funded by Nano-Tera.ch.
In 2015, he has started to work as a senior design engineer for the
high-tech company called Advanced Circuit Pursuit (ACP) AG which
is specialized on RF circuit design for mobile devices.
191
192 CURRICULUM VITAE
Publications
Theses:
[A] S. Fateh, “VLSI Implementation of Soft-Input Soft-Output Min-
imum Mean Square Error (MMSE) Parallel Interference Can-
cellation,” Master’s thesis, Dept. Information Technology and
Electrical Eng., ETH Zurich, Mar. 2009.
Journal papers:
[A] C. Studer, S. Fateh, and D. Seethaler, “ASIC Implementation of
Soft-Input Soft-Output MIMO Detection Using MMSE Parallel
Interference Cancellation,” IEEE Journal of Solid-State Circuits
(JSSC), vol. 46, no. 7, pp. 1754-1765, July 2011.
[B] C. Studer, S. Fateh, C. Benkeser, and Q. Huang, “Implemen-
tation Trade-Offs of Soft-Input Soft-Output MAP Decoders for
Convolutional Codes,” IEEE Trans. on Circuits and Systems I:
Regular Papers, vol. 59, no. 11, pp. 2774-2783, Nov. 2012.
[C] S. Benatti, B. Milosevic, F. Casamassima, P. Schönle, T. Burger,
S. Fateh, Q. Huang, and L. Benini, “A Versatile Embedded
Platform for EMG Gesture Recognition,” IEEE Trans. on Bio-
medical Circuits and Systems, 2015.
[D] S. Fateh, P. Schönle, L. Benini, G. Rovere, L. Benini, and
Q. Huang, “A Reconfigurable 5-14 bit SAR ADC for Battery-
Powered Medical Instrumentation,” IEEE Trans. on Circuits
and Systems I: Regular Papers, Oct. 2015.
Conference papers:
[A] C. Studer, S. Fateh, and D. Seethaler, “A 757 Mb/s 1.5 mm2
90 nm CMOS Soft-Input Soft-Output MIMO Detector for IEEE
802.11n,” Proc. of ESSCIRC, pp. 530-533, Sept. 2010.
[B] P. Schönle, F. Schulthess, S. Fateh, R. Ulrich, F. Huang, T. Bur-
ger, and Q. Huang, “A DC-Connectable Multi-Channel Biomed-
ical Data Acquisition ASIC with Mains Frequency Cancellation,”
Proc. of ESSCIRC, pp. 149-152, Sept. 2013.
193
[C] S. Benatti, B. Milosevic, F. Casamassima, P. Schönle, P. Bun-

jaku, S. Fateh, Q. Huang, and L. Benini, “EMG-Based Hand
Gesture Recognition with Flexible Analog Front End,” IEEE Bio-
medical Circuits and Systems Conf. (BioCAS), pp. 57-60, Oct.
2014.
[D] P. Schönle, P. Bunjaku, S. Fateh, and Q. Huang, “Modular
Multi-Sensor Platform for Portable and Wireless Medical In-
strumentation,” IEEE Biomedical Circuits and Systems Conf.
(BioCAS), pp. 165-168, Oct. 2014.
[E] S. Benatti, B. Milosevic, M. Tomasini, E. Farella, P. Schönle,
P. Bunjaku, G. Rovere, S. Fateh, Q. Huang, and L. Benini,
“Multiple Biopotentials Acquisition System for Wearable Appli-
cations,” Int. Joint Conf. on Biomedical Engineering Systems
and Technologies (BioSTEC), Jan. 2015.
[F] M. Tomasini, S. Benatti, F. Casamassima, B. Milosevic, S. Fateh,
E. Farella, and L. Benini, “Digitally Controlled Feedback for
DC Offset Cancellation in a Wearable Multichannel EMG Plat-
form,” Int. Conf. of the IEEE Engineering in Medicine and
Biology Society (EMBC), Aug. 2015.
[G] D. J. Mack, P. Schönle, S. Fateh, T. Burger, Q. Huang, and
U. Schwarz, “An Inexpensive, Head-Mounted, High-Sampling
Eye-Tracking System,” IEEE Biomedical Circuits and Systems
Conf. (BioCAS), Jun. 2015.
Live demonstrations, workshop papers, and extended ab-

stracts:
[A] P. Schönle, P. Bunjaku, S. Fateh, and Q. Huang, “Modular
Multi-Sensor Platform for Portable and Wireless Medical In-
strumentation,” IEEE Biomedical Circuits and Systems Conf.
(BioCAS), pp. 181, Oct. 2014.
[B] Q. Huang, R. Ulrich, P. Schönle, S. Fateh, F. Schulthess, and
F. Huang, “A Wireless ECG/EEG Module with Fully-Integrated
Multi-Channel Sensor Interface,” Stepping Stone Symposia Zur-
ich, Sept. 2012.

Thesis - Calibration Techniques For Digitally Assisted Nyquist-Rate ADCs

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Thesis - Calibration Techniques For Digitally Assisted Nyquist-Rate ADCs

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Calibration Techniques for Digitally Assisted Nyquist-Rate ADCs

Calibration Techniques for

A thesis submitted to attain the degree of

accepted on the recommendation of

Prof. Dr. Qiuting Huang, examiner

First of all, I would like to express my gratitude to my advisor,

maintenance of the infrastructure. Special thanks also go to M. Lanz

This project has been partially funded by Nano-Tera.ch, which is

Zurich, May 23, 2016 Schekeb Fateh

In recent years, the energy efficiency of ADCs has been continuously

ADC is more deeply considered due to its amenability to technology

Die Energieeffizienz von Analog-Digital Wandlern (ADC) hat sich in

kann in skalierten Technologien sehr effizient implementiert werden.

2 Nyquist-Rate ADC Architectures 23

2.3.1 Successive-approximation register ADC . . . . 27

3 Implications of Static Error Sources on Nyquist-Rate

4 Digital Calibration and Post-Correction 67

4.2.3 Estimation function . . . . . . . . . . . . . . . 73

5 A 14 bit SAR ADC with On-Chip Digital Calibration 83

6 A 150-MS/s 11-bit Folding ADC with 9.6 ENOB 111

6.4.2 Encoder logic . . . . . . . . . . . . . . . . . . . 128

7 Summary, Conclusion, and Outlook 139

A Power Contributors in SAR ADCs 145

B Impact of Mismatch on MOS Differential Pairs 157

C Mismatched Channels in Time-Interleaved ADCs 161

D Non-Ideal Quantizers 163

E Notation and Acronyms 167

Curriculum Vitae 191

The demand for high-speed and high-resolution Nyquist-rate analog-

1.1 ADC characterization

1.1.1 Transfer characteristic of ADCs

Code transition level

D out ideal straight

Figure 1.1: Typical transfer characteristic curve of an ideal 3-bit ADC.

as depicted in Fig. 1.1. To target a resolution of Nres bit, 2Nres equidis-

Code bin width

Least significant bit (LSB)

Midcode bin value

1.1.2 Static characterization of ADCs

Differential nonlinearity (DNL)

An error |DNLl | < 1 VLSB guarantees a monotonic transfer function

Figure 1.2: Transfer characteristic curve of a 3-bit ADC with static

code combinations will appear at the output of the ADC. Monotonic-

Integral nonlinearity (INL)

INL is the deviation in the LSB of the actual transfer characteristic

DNLmax = max DNLl

INLmax = max INLl .

1.1.3 Dynamic characterization of ADCs

Signal-to-noise ratio (SNR)

Spurious-free dynamic range (SFDR)

Signal-to-noise-and-distortion ratio (SNDR)

Effective number of bits (ENOB)

Total harmonic distortion (THD)

1.1.4 Figure-of-merit (FoM)

Figure 1.3: FoM versus technology of Nyquist-rate ADCs implemented

in Fig. 1.3, where ADC implementations in various CMOS technolo-

Vin (t) Dout [kTs]

Figure 1.4: Overview of the analog-to-digital conversion process.

achieve higher data rates with improved quality-of-service, low power

ADCs in multi-channel biomedical devices

Efficiently operating multi-channel biomedical devices share a single

1.2.2 Analog-to-digital conversion

where the settling error ss is maximum at t = 0 and requires a certain