Computer Organization PDF

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Computer Organization
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CS260 - Computer Organization JNTU World
Syllabus:
• Introduction: Function and structure of a computer,
computer Functional components of a
computer, Interconnection of components, Performance of a computer.
ld
• Representation of Instructions: Machine instructions, Operands, Addressing
modes, Instruction formats, Instruction sets, Instruction set architectures - CISC and
or
RISC architectures.
• Processing Unit: Organization of a processor - Registers, ALU and Control unit,

Data path in a CPU, Instruction cycle, Organization of a control unit - Operations of a
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control unit, Hardwired control unit, Microprogrammed control unit.
• Memory Subsystem: Semiconductor memories, Memory cells - SRAM and DRAM

cells, Internal Organization of a memory chip, Organization of a memory unit, Error
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correction memories, Interleaved memories, Cache memory unit - Concept of cache
memory, Mapping methods, Organization of a cache memory unit, Fetch and write
mechanisms, Memory management unit - Concept of virtual memory, Address
t
translation,
l ti H
Hardware
d supportt ffor memory management.t
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• Input/Output Subsystem: Access of I/O devices, I/O ports, I/O control mechanisms -
Program controlled I/O,
I/O Interrupt controlled I/O, I/O and DMA controlled I/O, I/O I/O interfaces
- Serial port, Parallel port, PCI bus, SCSI bus, USB bus, Firewall and Infiniband, I/O
peripherals - Input devices, Output devices, Secondary storage devices.
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References
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1. C. Hamacher, Z. Vranesic and S. Zaky, "Computer Organization", McGraw-
Hill, 2002.
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2. W. Stallings, "Computer Organization and Architecture - Designing for
Performance", Prentice Hall of India, 2002.
3. D. A. Patterson and J. L. Hennessy, "Computer Organization and Design -
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The Hardware/Software Interface", Morgan Kaufmann,1998.
4. J .P. Hayes, "Computer Architecture and Organization", McGraw-Hill, 1998.

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Computer Level Hierarchy
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or
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Program Execution
Translation: The entire high level program is translated into an
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equivalent machine language program. Then the machine language
program is executed.
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Interpretation: Another program reads the high level program
instructions one-by-one and executes a equivalent series of
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machine language instructions.
Program translation uses a collection of tools to perform the translation:

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Compiler: Translates high level language programs into a lower level
language often called object code.
Assembler: Translates assembly language instructions into object code.

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Linker: Combines collections of object code into a single executable

machine language program.

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or
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Computer System: Layers of Abstraction
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Application Program
or
Algorithms
Language
Software
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Hardware
IInstruction
t ti Set S t Architecture
A hit t
(and I/O Interfaces)
Microarchitecture
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Circuits
Devices
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From Theory to Practice
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In theory, computer can compute anything
that’s possible to compute
or
• given enough memory and time
In practice, solving problems involves
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computing
ti underd constraints.
t i t
• time
 weather forecast
forecast, next frame of animation
animation, ...
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• cost
 cell phone, automotive engine controller, ...
• power
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 cell phone, handheld video game, ...

Transformations Between Layers

How do we solve a problem using a computer?
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A systematic sequence of transformations between
layers of abstraction.
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Problem
Software Design:
choose algorithms and data structures
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Al
Algorithm
ith
Programming:
g g to express
use language p design
g
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Program
Compiling/Interpreting:
convert language to
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machine instructions
Instr Set
A hit t
Architecture

Deeper and Deeper…

Deeper
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IInstr
t Set
S t
or
Architecture
Processor Design:
choose structures to implement ISA
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Microarch
Logic/Circuit Design:
gates and low-level circuits to
implement components
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Circuits
Process Engineering & Fabrication:
develop and manufacture
lowest-level components
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Devices

Descriptions of Each Level
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Problem Statement
or
• stated using "natural language"
• may be ambiguous,
ambiguous imprecise
Algorithm
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• step-by-step
p y p procedure,
p , guaranteed
g to finish
• definiteness, effective computability, finiteness
Program
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• express the algorithm using a computer language
• high-level language, low-level language
Instruction Set Architecture (ISA)
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• specifies the set of instructions the computer can perform

• data types,
types addressing mode

Descriptions of Each Level (cont

(cont.))
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Microarchitecture
or
• detailed organization of a processor implementation
• different implementations of a single ISA
Logic Circuits
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• combine basic operations
p to realize microarchitecture
• many different ways to implement a single function
(e.g., addition)
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D i
Devices
• properties of materials, manufacturability
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Many Choices at Each Level
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Solve a system of equations
or
Gaussian Jacobi
Red-black SOR Multigrid
g
elimination iteration
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FORTRAN C C++ Java Tradeoffs:
cost
performance
Sun SPARC Intel x86 Compaq Alpha power
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(etc.)
Pentium II Pentium III AMD Athlon
Ripple-carry adder Carry-lookahead adder

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CMOS Bipolar GaAs

What’s Next
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Bits and Bytes
• How do we represent information using electrical signals?
Digital Logic
or
• How do we build circuits to process information?
Processor and Instruction Set
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• How do we build a p
processor out of logic
g elements?
• What operations (instructions) will we implement?
Assembly Language Programming
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• How do we use processor instructions to implement
algorithms?
• How do we write modular
modular, reusable code? (subroutines)
I/O, Traps, and Interrupts
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• How does processor communicate with outside world?

Structure and Function of a COMPUTER SYSTEM:
A computer isi a complex

l system; For analysis,
l i
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understanding and design - Identify the
hierarchical nature of most complex system.
system
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A hierarchical system
y is a set of interrelated
subsystems, each in turn, hierarchical in structure;
until at the lowest level we have elementary
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subsystems.
b t
The hierarchical nature of complex systems is

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essential to both their design and their description.
g
The designer need onlyy deal with a p
particular level
of the system at a time.
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At each
h level,
l l the
th system
t consists
i t off a sett off
components and their interrelationships.
The behavior at each level depends only

on a simplified, abstracted characterization of
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the system at the next lower level.
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At each level,, the designer
g is concerned
with structure and function:
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Structure: The
h way iin which
hi h the
h components are
interrelated.
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Function: The operation of each individual
component
p as p
part of the structure.
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Central Processing Unit (CPU) based CO
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or
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The organization of a simple computer with

one CPU and two I/O devices
There are four main functions of a computer:
• Data processing
i
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• Data storage
• Data movement
• Control
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MAIN STRUCTURAL BLOCKS/PARTS:
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Central
C t l Processing
P i Unit
U it (CPU):
(CPU) Controls
C t l the
th operation
ti off
the computer and performs its data processing functions.
Often simply referred to as processor.
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Main Memory: Stores data.
I/O: Moves data between the computer and its external

environment.
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System Interconnection: e.g. BUS for communication

among CPU, main memory, and I/O.
The major
j structural components
p of a CPU are:
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Control Unit (CU): Controls the operation of the
C
CPU andd hence
h the
h computer.
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Arithmetic and Logic Unit (ALU): Performs
computer’s data processing functions.
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Register: Provides storage internal to the CPU.
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CPU Interconnection:
I i communication
i i among the
h
control unit, ALU, and register.
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Structure - Top Level
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or
Peripherals Computer
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Central Main
Processing M
Memory
Unit
Computer
Systems
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Interconnection
Input
Output
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Communication
lines
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Structure - The CPU
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or
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Computer Arithmetic
Registers
g and
I/O Logic Unit
System CPU
Bus
Internal CPU
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Memory Interconnection
CPU
Control
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Unit

Structure - The Control Unit
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or
Control Unit
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CPU
Sequencing
q g
ALU Logic
Control
Internal
Unit
Bus
Registers and
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Registers Decoders
Of CU
Control
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Memory

• The First Generation: Vacuum Tube Computers

(1945 - 1953)
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– Atanasoff Berry
y Computer
p ((1937 - 1938))
solved systems of linear equations.
or
– John Atanasoff and Clifford Berryy of
Iowa State University.
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– Electronic Numerical Integrator and Computer Computer
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(ENIAC) byb John
J h Mauchly
M hl andd J. J Presper
P E k
Eckertat the
h UUniversity
i i
of Pennsylvania, 1946
– The IBM 650 first mass-produced computer. (1955). It was

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phased out in 1969.

p

• The Second Generation: Transistorized
Computers
p ((1954 - 1965))
– IBM 7094 (scientific) and 1401 (business)
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– Digital Equipment Corporation (DEC) PDP-1
PDP 1
– Univac 1100
or
– Control Data Corporation 1604
1604.
– . . . and many others.
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• The Third Generation: Integrated Circuit Computers (1965
- 1980)
– IBM 360
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– DEC PDP-8 and PDP-11
– Cray-1
y supercomputer
p p
• IBM had gained overwhelming dominance in the industry.
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– Computer manufacturers of this era were characterized as IBM

and the BUNCH (Burroughs, Unisys, NCR, Control Data, and
Honeywell). Downloaded From JNTU World (http://www.alljntuworld.in)
The von Neumann Model
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• The invention of stored program computers
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has been ascribed to a mathematician, John
von Neumann,
N who
h was a contemporary
t off
Mauchley and Eckert.
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• St
Stored-program
d computers
t have
h become
b
known as von Neumann Architecture
systems.
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• Today’s
Today s stored-program
stored program computers have the
following characteristics:
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– Three hardware systems:
y
• A central processing unit (CPU)
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• A main memory system
• An
A I/O system
The capacity to carry out sequential instruction

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processing.
g data path
A single p between the CPU and main
memory.
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This single path is known as the von Neumann

b ttl
bottleneck.
k
ld
or
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TU
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IAS (P
(Princeton)
i t ) computer
t model
d l by
b Von
V Neumann’s
N ’ group.

IAS computer consists of:
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- A main memory,
memory which stores both data and instructions.
instructions
or
- An arithmetic-logical
arithmetic logical unit (ALU) capable of operating on
binary data.
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- A control unit, which interprets the instructions in memory
and causes them to be executed.
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- Input
p and output
p (
(I/O)
/ ) equipment
q p operated
p by
y the
control unit.
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CPU Organization
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or
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The data path of a typical Von Neumann machine

machine.

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• This is a general
or
depiction of a von
Ne mann s
Neumann system:
stem
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• These computers
p
employ a fetch-
decode-execute
cycle to run
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programs as
follows . . .
JN

ld
• Th
The control
t l unit
it fetches
f t h the
th nextt instruction
i t ti from
f
memory using the program counter to determine where
or
the instruction is located.
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ld
• Th
The instruction
i t ti iis d
decoded
d d into
i t a language
l that
th t the
th ALU
can understand.
or
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ld
• A
Any ddata
t operands
d required
i d to
t execute
t the
th instruction
i t ti
are fetched from memory and placed into registers
or
within the CPU.
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ld
• Th
The ALU executes
t the
th instruction
i t ti and
d places
l results
lt in
i
registers or memory.
or
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TU
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IAS – Von Neumann (1952+)

• 1024 x 40 bit words ( = 5KB memory)
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– Binary number (2 (2’s
s complement)
or
– 2 x 20 bit instructions
• Set of registers (storage in CPU)
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– Memory y Buffer Register
g
– Memory Address Register
Addition time was 62
– Instruction Register
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microseconds and
the multiplication time
– Instruction Buffer Register was 713 microseconds.
– Program Counter
It was an asynchronous
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– Accumulator machine.
– Multiplier Quotient
Structure of IAS
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Central Processing Unit
Arithmetic and Logic Unit
Accumulator MQ
or
A ith ti & Logic
Arithmetic L i Circuits
Ci it
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Input MBR
Output Instructions
& Data Main
Equipment
Memory
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IBR PC
MAR
IR Control
Circuits
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Address
Program
g Control
Unit
Downloaded From JNTU World (http://www.alljntuworld.in) MQ - Multiplier/Quotient

Non-von Neumann Models
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• Conventional stored
stored-program
program computers have
undergone many incremental improvements over
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the years.
• These improvements include adding specialized
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buses floating
buses, floating-point
point units,
units and cache memories,
memories
to name only a few.
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• B
But enormous iimprovements iin computational
i l
power require departure from the classic von
Neumann architecture.
architecture
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• Adding processors is one approach.

DEC - PDP-8
PDP 8 Bus Structure
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or
Console Main I/O I/O
CPU Memory Module
Controller Module
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OMNIBUS
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The Omnibus - a backplane of undedicated slots;

Summary of hardware complexity
Vacuum tube - 1946-1957 ; Transistor - 1958-1964
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Small scale integration: 1965 ; Up to 100 devices on a chip
or
Medium scale integration: -1971; 100-3,000 devices on a chip
Large scale integration :1971-1977; 3,000 - 100,000 devices on a chip
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Very large scale integration: 1978 -1991; 100,000 - 100,000,000 devices on a chip
Ultra large scale integration : 1990s; Over 100,000,000

100 000 000 devices on a chip
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Multi-core
Multi core Architectures 2000s ; Over 10^9
10 9 devices on a chip
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Architecture vs. Organization
ld
or
Often used interchangeably – in book titles and as keywords.
keywords
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Thin line of difference – should be clear as we progress through
the course material.
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An instruction set is a list of all the instructions,
that a processor can execute.
ld
Typical Categories of Instructions:
• Arithmetic - add, subtract
or
• Logic - and, or and not
• Data - move,
move input
input, output
output, load and store
• Control flow - goto, if ... goto, call and return.
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An instruction set, or instruction set
architecture (ISA), is the part of the computer
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architecture related to programming, including the
native data types, instructions, registers,
addressing modes
modes, memory architecture
architecture, interrupt
and exception handling, and external I/O; also
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includes a specification of the set of opcodes

(machine language) - the native commands for a
particular processor. Downloaded From JNTU World (http://www.alljntuworld.in)
Computer System: Layers of Abstraction
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Application Program
or
Algorithms
Language
Software
W
Hardware
IInstruction
t ti Set S t Architecture
A hit t
(and I/O Interfaces)
Microarchitecture
TU
Circuits
Devices
JN

www.alljntuworld.in
Computer Architecture JNTU World
Logical aspects of system implementation as

seen by the programmer; such as, instruction sets
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(ISA) and formats, opcode, data types, addressing
modes and I/O.
or
Instruction set architecture (ISA) is different
from “microarchitecture”, which consist of various
W
processor
p ocesso des
design
g tec
techniques
ques used to implement
pe e t
the instruction set.
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Computers with different microarchitectures
can share a common instruction set.
For example, the Intel Pentium and the AMD

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Athlon implement
p nearly
y identical versions of the
x86 instruction set, but have radically different
internal designs. Downloaded From JNTU World (http://www.alljntuworld.in)
Computer architecture is the conceptual design
and fundamental operational structure of a computer

system It is a functional description of requirements
system.
and design implementations for the various parts of a
ld
p
computer.
It is the science and art of selecting and
or
interconnecting g hardware components
p to create
computers that meet functional, performance and cost
goals.
W
It deals with the architectural attributes like
physical address memory, CPU and how they should be
designed and made to coordinate with each other
TU
keeping the goals in mind.
Analogy:
l “building
“b ildi the
h d design i and d architecture
hi off
house” – architecture may take more time due to
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planning and then organization is building house by

bricks or by latest technology keeping the basic layout
and architecture of house
Downloaded From JNTU in mind.
World (http://www.alljntuworld.in)
Computer architecture comes before

computer organization.
organization
ld
Computer organization (CO) is how
or
operational attributes are linked together and
contribute
t ib t tot realise
li the
th architectural
hit t l
specifications.
W
CO encompasses all physical aspects of
computer systems
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e.g. Circuit design, control signals, memory types.
JN

Microarchitecture, also known as
Computer organization is a lower level, more
concrete and detailed, description of the system
ld
that involves how the constituent parts of the
system
t are interconnected
i t t d and
d how
h they
th
interoperate in order to implement the ISA.
or
W
The size of a computer's cache, for example, is
an organizational issue that generally has nothing
to do with the ISA.
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Another example: it is an architectural design
issue whether a computer will have a multiply
instruction. It is an organizational issue whether
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that instruction will be implemented by a special

multiply unit or by a mechanism that makes
repeated use of the add unit of the system.
Instruction Set Architecture (ISA) -

The Hardware-Software Interface
ld
 The most important abstraction of computer design
or
Application
pp Programs
Application
Operating System Software
W
Compiler
Instruction Set Architecture
Processor I/O System Interface between SW & HW
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Logic - gates, state machines, etc.
Hardware
Circuit - transistors, etc.
Layout - mask patterns, etc.

JN

Important Building Blocks
ld
 Microprocessor
or
 Memory
 Mass Storage (Disk)

W
TU
 Network Interface
JN

Typical Motherboard (Pentium III)

Power Conn.
Conn Floppy Conn
Conn. S Bridge
S.
ld
BIOS ROM
IDE Disk Conn.
or
Memory
AGP
W
Processor
PCI Cards
N. Bridge
TU
Rear Panel Conn.
AGP - Accelerated Graphics Port;

JN
PCI - Peripheral
p Component
p Interconnect;;
IDE – Integrated Drive Electronics;
BIOS - Basic input/output system
ld
or
W
TU
JN

Why design issues matter:
ld
- Cannot assume infinite speed and memory.
- Speed mismatch between memory and processor
or
- handle
h dl b bugs and
d errors (b
(bad
d pointers,
i t overflow
fl etc.)
t )
W
- multiple processors, processes, threads
- shared memory
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- disk access
- better performance with reduced power

JN

Enhancing Performance
(speed)
ld
• Pipelining
or
• On board cache
• On board L1 & L2 cache
• Branch prediction
W
TU
• Data flow analysis (in compilers)
• Speculative execution
JN

DRAM and Processor

Characteristics
ld
or
W
TU
JN

Typical I/O Device Data Rates
ld
or
W
TU
JN

Performance Analysis
N *S
A basic performance equation: T
ld
R
T – processor time required to execute a program (not total time used);
or
N - Actual number of machine instructions (including that due to loops);
S – Average No. of clock cycles/instruction;
W
R – Cycle/sec
y Earlier measures –
MIPS (Millions of Instructions per sec.)

TU
MFLOPS – Million floating point operations per sec.
CPI – Cycles
y p
per Instruction;;
IPC – Instructions per cycle = 1/CPI;

JN
Speedup = (Earlier execution time) / (Current execution time);

The Unix “time <a.out>” command gives:
“User CPU” time; “system (kernel) CPU” time and the “elapsed” real-time.
ld
g A:
e.g. 0.327u 0.010s 0:01.15; %-age
g elapsed
p time in CPU:
0.327  0.01
or
 0.45%
75
W
e.g.
g B: 90.7u 12.9s 0:12.39;; %-age
g elapsed
p time in CPU:
90.7  12.9
A better situation, for exploitation  65%
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of CPU time. 159
CPU execution
ti titime ffor a program =
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CPU clock cycles

 CPU clock cycles * clock cycle time
Clock rate
CPU execution time “for a program” =
CPU clock cycles

y
 CPU clock
l k cycles
l * clock
l k cycle
l time
ti
Clock rate
ld
CPU clock cycles = No. of instructions * Avg. clock cycles/instruction
n
CPU clock cycles   N i * CPI i
or
i 1
CPI = cycles/instruction; N – No. of instructions;
W
°CPU execution time for program
= Instruction Count x CPI x Clock Cycle Time
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Exec _ Time( A) 1 n
A better measure: Exec _ time   Timei
E _ Time
Exec Ti ( B) n i 1
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sec onds
d t ti ns clock
IInstructio l k cycle
l seconds
d
 * *
program program Instruction clock cycle
Performance - SPECS
• CPU
SPEC MPI2007 focuses on performance
ld
• Graphics/Workstations of compute intensive applications using
the Message-Passing Interface (MPI),
• MPI/OMP
which means these benchmarks
or
(Orthogonal Multi-Processor) emphasize the performance of:
• Java Client/Server
• computer processor (CPU),
• Mail Servers • number of computer processors,
W
• MPI Library,
• Network File System
• i ti
communication interconnect,
i t t
• Power • memory architecture,
• compilers, and
• SIP
• shared file system.
system
TU
(Session Initiation Protocol)
Not for Graphics, O/S and I/O.
• SOA
(Service Oriented Architecture)
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• Virtualization
• Web Servers
MPI2007 is SPEC's benchmark suite for evaluating MPI-parallel,

g point,
floating p , compute
p intensive performance
p across a wide range
g of cluster
and SMP (Symmetric multi-processing) hardware.
ld
CFP2006 is used for measuring
g and comparing
p g compute-intensive
p
floating point performance.
or
SPEC rating (ratio) = TR / TC;
TR = Running time of the Reference Computer;
W
TC = Running time of the Computer under test;
TU
1/ n
 n
SPEC    SPECi  Higher the SPEC score,
 i 1  better the performance
performance.
JN
n – No. of programs in the SPEC Suite.

Benchmark Language Application Area
104.milc C Quantum Chromodynamics
107.leslie3d Fortran Computational Fluid Dynamics CFD
ld
113.GemsFDTD Fortran Computational Electromagnetics
115.fds4 C/Fortran CFD: Fire dynamics simulator
or
121 pop2
121.pop2 C/Fortran Climate Modeling
122.tachyon C Graphics: Ray Tracing
W
126.lammps C++ Molecular Dynamics
127.wrf2 C/Fortran Weather Forecasting

TU
128.GAPgeofem C/Fortran Heat Transfer using FEM
129 tera tf
129.tera_tf Fortran 3D Eulerian Hydrodynamics
JN
130.socorro C/Fortran Molecular Dynamics
132.zeusmp2 C/Fortran Computational Astrophysics
137.lu Fortran Implicit CFD

From first to fifth/sixth generation systems, the following factors were

also
l taken
t k into
i t consideration,
id ti to
t improve
i the
th performance.
f
ld
- Reduced Power dissipation
- Reduced Space Area
or
- More increase in Speed and Registers (GPRs) for operation
- More memory size
W
- Use of Cache
- Set of cores on CPU

TU
- pipelining and special MMX hardware.
-
JN

Increase in CPU p
performance,, may
y come from three factors:
ld
• Increase in clock rate
• Improvement in processor design to lower CPI
or
• Compiler enhancements for lower average CPI
• Better memory organization
W
•
TU
JN

Key terminologies:
• Control Path
ld
• Microcontroller • ALU, FPU, GPU etc.
• CPU design • Pipelining
or
• Hardware description language • Cache
• Von-Neumann architecture • Superscalar
W
• Multi-core
M lti (
(computing)
ti ) • Out-of-order
Out of order execution
• Datapath • Register renaming

TU
• Dataflow architecture • multi-threading
• Stream processing • RISC, CISC
• Addressing Modes
JN
• Instruction-level parallelism (ILP)
• Vector processor • Instruction set

• SIMD, MIMD
• Flynn’s taxonomy
ld
• MMX instructions
or
•
W
TU
JN

ld
or
END of INTRO –
Lets start some calculations
W
- binary arithmetic
TU
JN

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• Processing Unit: Organization of a processor - Registers, ALU and Control unit,

• Memory Subsystem: Semiconductor memories, Memory cells - SRAM and DRAM

3. D. A. Patterson and J. L. Hennessy, "Computer Organization and Design -

4. J .P. Hayes, "Computer Architecture and Organization", McGraw-Hill, 1998.

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Translation: The entire high level program is translated into an

Program translation uses a collection of tools to perform the translation:

Assembler: Translates assembly language instructions into object code.

Linker: Combines collections of object code into a single executable

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Computer System: Layers of Abstraction

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From Theory to Practice

In practice, solving problems involves

 cell phone, handheld video game, ...

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Transformations Between Layers

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Deeper and Deeper…

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Descriptions of Each Level

• specifies the set of instructions the computer can perform

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Descriptions of Each Level (cont

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Many Choices at Each Level

Ripple-carry adder Carry-lookahead adder

CMOS Bipolar GaAs

• How does processor communicate with outside world?

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A computer isi a complex

The hierarchical nature of complex systems is

The behavior at each level depends only

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Central Processing Unit (CPU) based CO

The organization of a simple computer with

I/O: Moves data between the computer and its external

System Interconnection: e.g. BUS for communication

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Structure - Top Level

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Structure - The CPU

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Structure - The Control Unit

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• The First Generation: Vacuum Tube Computers

– The IBM 650 first mass-produced computer. (1955). It was

phased out in 1969.

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– Computer manufacturers of this era were characterized as IBM

The von Neumann Model

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The von Neumann Model

The capacity to carry out sequential instruction

This single path is known as the von Neumann

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IAS computer consists of:

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The data path of a typical Von Neumann machine