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Embedded System

(T.Y. EJ6G)
Lecture Notes
Prof. Jamdade Abhijit S.
Dnyanshree Institute of Engineering & Technology, Sajjangad Road,
satara.
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CONTENTS
1. Architecture of Microprocessor and Microcontroller

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1. Architecture of Microprocessor and Microcontroller
1.1 Architecture of Microcontroller 8051:
Address Bus – 16 bit
Data Bus – 8 bit
Control Signals – Memory Read, Memory Write, External
Enable, Program Store Enable, Address Latch Enable

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Memory Structure –
On-Chip Memory Internal RAM
Registers
1F

Bank 3
Four Register Banks
18
Each bank has R0-R7
17 Selectable by psw.2,3

Bank 2

10
0F

Bank 1

08
07 R7
06 R6
05 R5
04
03
R4
R3
Bank 0
02 R2
01 R1
00 R0
Bit Addressable Memory
2F 7F 78 20h – 2Fh (16 locations X 8-bits =
2E 128 bits)
2D
2C Bit addressing:
2B mov C, 1Ah
2A or
29 mov C, 23h.2
28
27
26
25
1A
24
10
23
0F 08
22
07 06 05 04 03 02 01 00
21
20
Special Function Registers

DATA registers

CONTROL registers
Timers
Serial ports
Interrupt system
Analog to Digital converter
Digital to Analog converter Addresses 80h – FFh
Etc.
Direct Addressing used to
access SPRs
Bit Addressable RAM

Figure 2-6
Summary
of the 8051
on-chip
data
memory
(RAM)
Bit Addressable RAM

Figure 2-6
Summary
of the 8051
on-chip
data
memory
(Special
Function
Registers)
ROM Memory Mapping
8051 Port 3 Bit Latches and I/O Buffers
Hardware Structure of I/O Pin

Read latch Vcc


TB2
Load(L1)

Internal CPU D Q P1.X


bus P1.X pin

Write to latch Clk Q M1

TB1
Read pin
Hardware Structure of I/O Pin
• Each pin of I/O ports
• Internally connected to CPU bus
• A D latch store the value of this pin
• Write to latch=1:write data into the D latch
• 2 Tri-state buffer:
• TB1: controlled by “Read pin”
• Read pin=1:really read the data present at the pin
• TB2: controlled by “Read latch”
• Read latch=1:read value from internal latch
• A transistor M1 gate
• Gate=0: open
• Gate=1: close
Writing “1” to Output Pin P1.X

Read latch Vcc


TB2
Load(L1) 2. output pin is
1. write a 1 to the pin Vcc
D Q
1 P1.X
Internal CPU
bus P1.X pin
0 M1
output 1
Write to latch Clk Q

TB1
Read pin
Writing “0” to Output Pin P1.X

Read latch Vcc


TB2
Load(L1) 2. output pin is
1. write a 0 to the pin ground
D Q
0 P1.X
Internal CPU
bus P1.X pin
1 M1
output 0
Write to latch Clk Q

TB1
Read pin
Reading “High” at Input Pin

Read latch Vcc 2. MOV A,P1


TB2 external pin=High
1. write a 1 to the pin MOV Load(L1)
P1,#0FFH

1 1 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
Reading “Low” at Input Pin

Read latch Vcc 2. MOV A,P1


TB2
1. write a 1 to the pin Load(L1) external pin=Low
MOV P1,#0FFH
1 0 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC
Port 0 with Pull-Up Resistors

Vcc
10 K

P0.0
DS5000 P0.1

Port
8751 P0.2
8951 P0.3
P0.4 0
P0.5
P0.6
P0.7
Interrupts
• Determine conditions that exists in internal or external circuits.

• Jumps on status of flags and port pins and responds to hardware signal interrupt that force
a program to call sub routine

• Software technique uses up processor time

• Interrupts take processor time only when action by the program is needed.

• Interrupts may be generated by internal chip operations or provided by external sources.

• Any interrupt can cause the 8051 to perform a hardware call to an interrupt handling
subroutine located at interrupt vector

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Five interrupt –
3 generated by automatically by internal operations.
2 interrupts are triggered by external signals provided by
circuitry that is connected to INT0 and INT1

Reset – An ultimate interrupt , Non mask able interrupt

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Timers
• Counting of external event – Counting frequency of pulse train.

• Generation of precise internal time delays between computer action

• Software tool for counting or timing keep processor occupied

• Relieve processor this Burdon timers are used – 2 16 bit up counters T0 &
T1

• Programmed to count internal clock pulses acting as timer

• Programmed to count external pulses as a counter


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Serial Data Input / Output
• Serial data communication circuit, uses SBUF to hold data.

• SCON – Controls Data communication.

• PCON – Controls data rate.

• Pin RXD(P3.0), TXD(P3.1) connect to serial data network.

• SBUF is physically two register, Write only hold data to be transmitted out
via TXD and read only holds received data from external sources via RXD

• Serial Data interrupt -


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