EXPERIMENT NO: 0

(RECAPUTULATION)

Date: __/__/____

TITLE: - Realization of Basic gates using Universal Logic gates (By NAND & NOR)

OBJECTIVES: - To realize the basic gates using Universal logic gates that is to verify the truth
tables of OR, AND, NOT, X-OR and X-NOR gates using NAND and NOR gates.

THEORETICAL APPROACH: - NAND and NOR gates have the important properties that using
only NAND or only NOR gates repeatedly one can get the logic functions of OR, AND, NOT, X-OR
and X-NOR gates. That is why they are called universal gates. NAND is a combination gate in which
a NOT gate follows an AND gate. NOR is also combination gate in which a NOT gate follows an OR
gate.

CIRCUIT DIAGRAM: -

NAND AS NOT:-

NAND AS AND:-

NAND AS OR:-

Page 19 of 57 
 
 
 

NAND AS X-OR:-

NAND AS X-NOR:-

NOR AS NOT:-

NOR AS OR:-

NOR AS AND:-

Page 20 of 57 
 
 
 

NOR AS X-OR:-

NOR AS X-NOR:-

DEVICES AND COMPONENTS USED IN THIS EXPERIMENT: –

DEVICES: - 1) Digital Bread board system 2) IC testing kit 3) Multimeter

COMPONENTS: - 1) 7400 (AND gate) 2) 7402 (NOR gate) 3) Connecting wires

RESULTS/EXPERIMENTAL OBSERVATIONS: -

1) Observation table for Basic gates using universal gates

INPUT OUTPUT
A B Y
LOGIC LED LOGIC LED LOGIC LED
STATE STATUS STATE STATUS STATE STATUS

1) Make similar tables for realization of NAND as AND, NOT, X-OR, X-NOR gates and
NOR as OR, AND, NOT, X-OR and X-NOR gate.

CONCLUSION: -

Page 21 of 57 
 
 
 

Give technical conclusions. Restate the main objectives and how or to what degree they were
achieved. What principles, laws and/or theory were validated by the experiment? Describe some
applications of your results.

Page 22 of 57 
 
 
 

EXPERIMENT NO: - 1

Date: __/__/____

TITLE:- Design a Full Adder using basic gates and verify its output and design a Full Subtractor
circuit using basic gates and verify its output.
Aim: -

To realize half/full adder and half/full subtractor Using X-OR and basic gates

Apparatus Required: -

IC 7486, IC 7432, IC 7408, IC 7400, etc.

Procedure: -

1. Verify the gates.

2. Make the connections as per the circuit diagram.

3. Switch on VCC and apply various combinations of input according to truth table.

4. Note down the output readings for half/full adder and half/full subtractor sum/difference and the
carry/borrow bit for different combinations of inputs.

Circuit Diagram:-

Page 23 of 57 
 
 
 

Page 24 of 57 
 
 
 

Conclusion: -

Page 25 of 57 
 
 
 

EXPERIMENT NO: - 2(A)

Date: __/__/____

TITLE: - Design of a decoder circuit using basis gates

OBJECTIVES: - To design a 2-to-4 circuit using basic gates and verify its truth table.

THEORETICAL APPROACH: A decoder is a logic circuit that converts n-bits binary input code
into 2n output lines, such that each output line will be activated for only one possible combination of
inputs. In a decoder, the number of outputs is greater than the number of inputs. A general block
diagram of n-to-2n decoder is shown in the following figure

A 2-to-4 decoder has two input lines and 4output lines as Shown in the following figure.

Page 26 of 57 
 
 
 

The truth table of 2-to-4 decoder is shown in the following figure

ENABLE INPUTS OUTPUTS

EN A B D0 D1 D2 D3
0 0 0 1 0 0 0
0 0 1 0 1 0 0
0 1 0 0 0 1 0
0 1 1 0 0 0 1
1 X X 0 0 0 0

From the table the logic expression for the outputs can be written as

D0= (AB).EN

D1= (AB).EN

D2= (AB).EN

D3= (AB).EN

CIRCUIT DIAGRAM: -

Fig: - 2-to-4 Decoder Circuit

DEVICES AND COMPONENTS USED IN THIS EXPERIMENT: –

DEVICES: - 1) Digital Bread board system 2) IC testing kit 3) Multimeter

Page 27 of 57 
 
  
 

COMPONENTS: - 1) 7404 (NOT gate) 2) 7411 (3 I/P AND gate) 3) Connecting wires

RESULTS/EXPERIMENTAL OBSERVATIONS: -

Observation table for 2-to-4 line Decoder circuit

ENABLE INPUTS OUTPUTS

A B D0 D1 D2 D3
EN LED LOGIC LED LOGIC LED LOGIC LED LOGIC LED LOGIC LED LOGIC
STATUS STATE STATUS STATE STATUS STATE STATUS STATE STATUS STATE STATUS STATE

CONCLUSION: -

Page 28 of 57 
 
 
 

EXPERIMENT NO: - 2(B)

TITLE: - Design of a multiplexer circuit (MUX) using basis gates.

OBJECTIVES: - To design a 4:1 MUX using basic gates and verify its truth table.

THEORETICAL APPROACH: The term ‘multiplexer’ means many to one. Multiplexing is the
process of transmitting a large number of information over a single line. A MUX is a combinational
circuit that selects one digital information for several sources and transmits the selected information
on a single output line. The selection of input-to-output transfer path is controlled by a set of n select
lines or address lines. The relationship between this n address lines and m data lines is m=2n.

For a 4-to-1 MUX, there are 4 data inputs, 1 output and optionally there may be one enable input. The
function table of a 4-to-1MUX with active low enable (EN) input is shown in the following table

EANABLE SELECT INPUTS OUTPUTS

EN S1 S0 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 X X 0

From the table the logic equation for a 4-to-1MUX can be written as

Y= (S1S0I0+S1S0I1+S1S0I2+S1S0I3) EN

Here S1 and S0 are select inputs and I0, I1, I2 and I3 are the 4 data inputs.

Page 29 of 57 
 
 
 

CIRCUIT DIAGRAM: -

DEVICES AND COMPONENTS USED IN THIS EXPERIMENT: –

DEVICES: - 1) Digital Bread board system 2) IC testing kit 3) Multimeter

COMPONENTS: - 1) 7404 (NOT gate) 2) 7411 (3 I/P AND gate) 3) 7408 (2 I/P AND gate) 4)
7432 (2 I/P OR gate)

RESULTS/EXPERIMENTAL OBSERVATIONS: -

Observation table for 4:1 MUX circuit

SELECT
ENABLES INPUTS OUTPUT
INPUTS
EN S1 S0 I0 I1 I2 I3 Y

CONCLUSION: -

Page 30 of 57 
 
 
 

EXPERIMENT NO: - 3

Date: __/__/____

TITLE: - Realization of RS, JK, D Flip-flops using universal gates.

OBJECTIVES: - To design and verify the operations of RS, JK and D flip-flops using universal
logic gates.

THEORETICAL APPROACH: The logic circuits whose outputs at any instant of time depend not
only on the present inputs but also on the past outputs are called sequential circuits. In the sequential
circuits, the output signals are fed back to the input side. Thus an output signal is a function of the
present input signals and a sequence of the past signals i.e. the past output signals. So, to have a
sequential circuit, a storage device is required to know what happened in the past. The basic unit of
storage is the flip-flop.

SR Flip-Flop: The following figure shows the block diagram of an RS flip-flop using cross coupled
NAND gate. The truth table of RS flip-flop is given in the following table

Results

(PR) (CR) CLK(POSITIVE Sn Rn Qn(PRESENT Qn+1(NEXT STATE)

PRESET CLEAR LEVEL) STATE
1 1 1 0 0 0 0
1 1 1 0 0 1 1
1 1 1 0 1 0 0
1 1 1 0 1 1 0
1 1 1 1 0 0 1
1 1 1 1 0 1 1
0 0 1 1 1 X 1(Qn+1'=1)FORBIDDEN
1 1 0 X X 0 0(UNCHANGED)
1 1 0 X X 1 1(UNCHANGED)
0 1 1 X X 1 1 (PR) PRESET
1 0 1 X X 0 0 (CR) CLEAR
D Flip-Flop: The D (Delay) flip-flop uses a single data input and avoids the forbidden state of SR
flip-flop. It is used to provide single delay. The input information is transferred to the output at the
next clock pulse. The following figure shows the block diagram of a D flip-flop. The truth table of D
flip-flop is given in the following table

Page 31 of 57 
 
 
 

CLK(POSITIVE Qn(PRESENT Qn+1(NEXT

Dn
LEVEL) STATE STATE)
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
0 X 0 0(UNCHANGED)
0 X 1 1(UNCHANGED)

JK Flip-Flop: The uncertainty in the state of an SR flip-flop when S=1, R=1 can be eliminated by
converting it into a JK flip-flop. In case of JK flip-flop, when J=K=1, the flip-flop output toggles, i.e.
if Q=0, it switches to Q=1 and vice-versa. The block diagram and truth table of the JK flip-flop are
given below

Page 32 of 57 
 
 
 

CLK(POSITIVE Qn(PRESENT Qn+1(NEXT

Jn Kn
LEVEL) STATE STATE)
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1(TOGGLE)
1 1 1 1 0(TOGGLE)
0 X X 0 0(UNCHANGED)
0 X X 1 1(UNCHANGED)

The following table shows the operation of Preset and Clear inputs

INPUTS OUTPUT OPERATION

CLK PR CR Qn PERFORMED
NORMAL FLIP-
1 1 1 Qn+1
FLOP
0 0 1 1 PRESET
0 1 0 0 CLEAR
0 0 0 1(Qn'=1) FORBIDDEN

CIRCUIT DIAGRAM: - Circuit diagram of RS flip-flop

Page 33 of 57 
 
 
 

Circuit diagram of JK flip-flop

Circuit diagram of D flip-flop

EVICES AND COMPONENTS USED IN THIS EXPERIMENT: –

DEVICES: - 1) Digital Bread board system 2) IC testing kit 3) Multimeter

COMPONENTS: - 1) 7410 (3 I/P NAND gate) 2) 7400 (2 I/P NAND gate)

RESULTS/EXPERIMENTAL OBSERVATIONS: -
Observation table for SR, JK and D flip-flop
Observation table for SR flip-flop:

Page 34 of 57 
 
 
 

CLK(POSITIVE Qn(PRESENT Qn+1(NEXT

Sn Rn
LEVEL) STATE STATE)

Observation table for D flip-flop:

CLK(POSITIVE Qn(PRESENT Qn+1(NEXT

Dn
LEVEL) STATE STATE)

Observation table for JK flip-flop:

(PR) (CR) CLK(POSITIVE Jn Kn Qn Qn+1 (NEXT

PRESET CLEAR LEVEL) (PRESENT STATE)
STATE)
1 1 1 0 0 0 0
1 1 1 0 0 1 1
1 1 1 0 1 0 0
1 1 1 0 1 1 0
1 1 1 1 0 0 1
1 1 1 1 0 1 1
1 1 1 1 1 0 1
1 1 1 1 1 1 0
0 0 1 X X 1 1 ( Qn 1=1)
Forbidden
0 1 1 X X 1 1
1 0 1
CONCLUSION: -

EXPERIMENT NO: - 4

Page 35 of 57 
 
 
 

Date: __/__/____

TITLE: - Realization of Universal shift Register using D flip-flop and logic gates.

OBJECTIVES: - To design a Universal shift Register using D flip-flop and basic gates and verify its
operation.

THEORETICAL APPROACH: An array of n-flip-flops is called a register which can store n-bit
binary words. The binary data can entered or retrieved in to the register either in serial form or parallel
form. Depending on the data is entered and/or retrieved, register are classified as-

1. Serial-in Serial-out (SISO).

2. Serial-in Parallel-out (SIPO)
3. Parallel-in Serial-out (PISO)
4. Parallel-in Parallel-out (PIPO)

SISO: In this register data is entered and retrieved in serial fashion with the clock. It has one input
data line and one output data line. n-clock pulses are required to write n-bit data. Once the data is
read, it is lost from the register.

SIPO: In this register data is entered in parallel fashion and once the data is entered, for an n-bit data
n-output lines can be taken out from the output of n-flip-flops in the register to read the entered data
simultaneously in parallel fashion. In this case no clock pulses are required to read the data.
Obviously n-clock pulses are required to enter the data serially.

PISO: In this register either data can be entered simultaneously asynchronously using ‘Preset’ and
‘Clear’ inputs of the flip-flops or synchronously with the help of clock pulse. n-bits data are entered
simultaneously in parallel form into the register through n-input lines and once the data is entered, it
can be read in serial fashion.

PIPO: in this register, data is entered is entered in parallel form through n-input lines and again read
in the parallel form through n-output lines. Since all the bits of the data are entered and read
simultaneously, it is the fastest shift register.

Page 36 of 57 
 
 
 

CIRCUIT DIAGRAM: -

DEVICES AND COMPONENTS USED IN THIS EXPERIMENT: –

DEVICES: - 1) Digital Bread board system 2) IC testing kit 3) Multimeter

Page 37 of 57 
 
 
 

COMPONENTS: - 1) 7400 (2 I/P NAND gate) 2) 7474 (D-flip-flop)

RESULTS/EXPERIMENTAL OBSERVATIONS: -

Observation table for SISO

Serial Data (Xi)= 1010, Preset Enable= 0, Clear Line= +Vcc

SHIFT SERIL DATA QA (SERIAL DATA

PULSE IN (Xi) OUT)
0 0 0
1 1 0
2 0 0
3 1 0
4 0 0
5 0 1
6 0 0
7 0 1
8 0 0
Observation table for PIPO

Parallel Data Di3 Di2 Di1 Di0= 1010, Preset Enable= 1, Clear Line= +Vcc

PARALLEL DATA INPUT PARALLEL DATA OUTPUT

Di3 Di2 Di1 Di0 QD QC QB QA
1 0 1 0 1 0 1 0
Observation table for PISO

Parallel Data Di3 Di2 Di1 Di0= 1010, Clear Line= +Vcc

PARALLEL DATA INPUT SERIAL DATA OUTPUT

Di3 Di2 Di1 Di0 QA
PRESET ENABLE=1
0
1 0 1 0
PRESET ENABLE=0
0 0 (LSB)
1 1
2 0
3 1 (MSB)
4 0

Observation table for SIPO

Serial Data (Xi) = 1010, Preset Enable= 0, Clear Line= +Vcc

Page 38 of 57 
 
 
 

SHIFT SERIAL INPUT PARALLEL DATA OUTPUT

PULSE (Xi) QD QC QB QA
0 0 0 0 0 0
1 1 0 0 0 0
2 0 1 0 0 0
3 1 0 1 0 0
4 0 1 0 1 0

CONCLUSION: -

1) The operation of the Universal register in all the four modes SISO, SIPO, PIPO & PISO has
been verified with a test data 1010.
2) The shift register designed can shift data in the right direction only hence it is called right
shift register.
3) Data is entered in serial mode starting from LSB.
4) During shift operation of the register, preset enable input should be kept in logic 0 and clear
input at logic 1. Preset enable input should be made 1 only when entering the data
asynchronously.

Page 39 of 57 
 
 
 

EXPERIMENT NO: - 5

Date: __/__/____

TITLE: -DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN COUNTER

AIM: To design and implement 3 bit synchronous up/down counter.
APPARATUS REQUIRED:

THEORY: A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. An up/down counter is one that is
capable of progressing in increasing order or decreasing order through a certain sequence. An
up/down counter is also called bidirectional counter. Usually up/down operation of the counter is
controlled by up/down signal. When this signal is high counter goes through up sequence and when
up/down signal is low counter follows reverse sequence.
K’- MAP:-

Page 40 of 57 
 
 
 

STATE DIAGRAM:

CHARACTERISTICS TABLE:

Page 41 of 57 
 
 
 

LOGIC DIAGRAM:

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
RESULT: Thus the 3 bit synchronous up/down counter was designed implemented.

CONCLUSION: -

Page 42 of 57 
 
 
 

Analog part

EXPERIMENT NO: - 6

Date: __/__/____

Objective:
Design a single stage, Class A, RC Coupled, self-biased amplifier.
(Given: Vcc=12V)
Theory:
By a single stage we mean a single transistor with its bias and auxiliary components used for
amplification. When a single transistor with associated circuitry is used for amplification then it is
known as single stage transistor amplification. A Class A amplifier is the most linear amplifier and the
output signal is true replica of the applied input. The transistor conducts for the entire cycle of the
input signal. As the transistor is always ON, it is very inefficient; there is wastage of power.
The Common Emitter (CE) RC Coupled amplifier is one of the simplest and elementary transistor
amplifiers. The main purpose of this circuit is pre-amplification i.e. to make a weak signal to strong
signal for further processing. Self bias/ Voltage Divider bias is used in all linear and general purpose
amplifiers. It has a steady Q point but use of four resistors is a must. It needs only one supply voltage.

Figure :- A single stage, Class A, RC Coupled, self biased amplifier circuit.

Page 43 of 57 
 
 
 

DC Load Line:-
 The straight line is know as the DC load line
 Its significance is that regardless of the behavior of the transistor, the collector current IC and the
collector-emitter voltage VCE must always lie on the load line, depends ONLY on the VCC, RC and
RE
 (i.e. The dc load line is a graph that represents all the possible combinations of IC and VCE for a
given amplifier. For every possible value of IC, and amplifier will have a corresponding value of
VCE.)
 It must be true at the same time as the transistor characteristic. Solve two condition using
simultaneous equation
  graphically  Q-point !!

Q-Point (Static Operation Point):-

• When a transistor does not have an ac input, it will have specific dc values of IC and VCE.
• These values correspond to a specific point on the dc load line. This point is called the Q-point.
• The letter Q corresponds to the word (Latent) quiescent, meaning at rest.
• A quiescent amplifier is one that has no ac signal applied and therefore has constant dc values of IC
and VCE.
Q-Point (Static Operation Point):-
• When an ac signal is applied to the base of the transistor, IC and VCE will both vary around their Q-
point values.
• When the Q-point is centered, IC and VCE can both make the maximum possible transitions above
and below their initial dc values.
• When the Q-point is above the center on the load line, the input signal may cause the transistor to
saturate. When this happens, a part of the output signal will be clipped off.
• When the Q-point is below midpoint on the load line, the input signal may cause the transistor to
cutoff. This can also cause a portion of the output signal to be clipped.

Page 44 of 57 
 
  
 

IC(sat) = VCC/(RC+RE)
IC(sat) = ICQ + (V CEQ /rC )

DC Load Line ac load line

IC
IC
(mA)
VCE(off) = VCC V CE(off) = V CEQ + ICQ rC

V CE
VCE

a c lo a d lin e

I Q - p o in t
C

d c lo a d lin e

V C E

Page 45 of 57 
 
  
 

AC Load Line
 The ac load line of a given amplifier will not follow the plot of the dc load line.
 This is due to the dc load of an amplifier is different from the ac load.
What does the ac load line tell you?
 The ac load line is used to tell you the maximum possible output voltage swing for a given
common-emitter amplifier.
 In other words, the ac load line will tell you the maximum possible peak-to-peak output
voltage (Vpp ) from a given amplifier.
 This maximum Vpp is referred to as the compliance of the amplifier.
(AC Saturation Current Ic(sat) , AC Cutoff Voltage VCE(off) )
AC Saturation Current and AC Cutoff Voltage
IC(sat) = ICQ + (VCEQ/rC)

r
ac load line
v v c e
C IC
in

R 1
//R 2

VCE(off) = VCEQ + ICQrC

VCE
r C
= R C
//R L

Page 46 of 57 
 
 
 

Graph: Plot Voltage Gain (AV)( on Y-Axis) vs Frequency(on X-Axis) in semi log paper as the
Frequency response.

Page 47 of 57 
 
 
 

Conclusion: Left for who is performing the experiment.

Page 48 of 57 
 
 
 

…REVIEW QUESTIONS……………………………………
1. Discuss the advantages and disadvantages of different types of coupling.
2. What do you mean by dc amplifier?
3. What are the function of CC, CE and CB?

Page 49 of 57 
 
 
 

EXPERIMENT NO: - 7

Date: __/__/____

Oscillator
Feedback plays an important role in almost all electronic circuits. It is almost invariably used
in the amplifier to improve its performance and to make it more ideal. In the process of feedback, a
part of output is sampled and fed back to the input of the amplifier. Therefore, at input we have two
signals: Input signal, and part of the output which is fed back to the input. Both these signals may be
in phase or out of phase. When input signal and part of output signal are in phase, the feedback is
called positive feedback. On the other hand, when they are out of phase, the feedback is called
negative feedback.
The positive feedback results into oscillations and hence used in electronic circuits to generate
the oscillations of desired frequency. Such circuits are called oscillators.
Concept of Positive Feedback
The feedback is a property which allows to feedback the part of the output, to the same circuit
as its input. Such a feedback is said to be positive whenever the part of the output that is fed back to
the amplifier as its input, is in phase with the original input signal applied to the amplifier. Consider a
non-inverting amplifier with the voltage gain (A)

Fig.1 Concept of positive feedback

Assume that a sinusoidal input signal (voltage) (Vs) is applied to the circuit. As amplifier is non-
inverting, the output voltage (Vo) is in phase with the input signal (Vs). The part of the output is fed
back to the input with the help of a feedback network. How much part of the output is to be fed back,
gets decided by the feedback network gain (β). No phase change is introduced by the feedback
network. Hence the feedback voltage (Vf) is in phase with the input signal (Vs).
As the phase of the feedback signal is same as that of the input applied, the feedback is called
positive feedback.
Expression for Gain with Feedback
The amplifier gain is A i.e. it amplifies its input Vi , A times to produce output Vo. A= Vo /
Vi
This is called Open Loop Gain of the amplifier. For the overall circuit, the input is supply voltage Vs
and net output is Vo. The ratio of output Vo to input Vs considering effect of feedback is called
closed loop gain of the circuit or gain with feedback denoted as Af. Af = V0 / Vf
The feedback is positive and voltage Vf is added to Vs to generate input of amplifier Vi.
So we can write,
Vi =Vs + Vf
The feedback voltage depends on the feedback element gain β . So we can write,
Vf = βVo
Vi =Vs + βVo
Vs = Vi- βVo

Page 50 of 57 
 
 
 

Substituting in expression for Af

Dividing both numerator and denominator by Vi

As A= V0 / Vi
Barkhausen Criterion
Consider a basic inverting amplifier with an open loop gain A. The feedback network attenuation
factor β is less than unity. As basic amplifier is inverting, it produces a phase shift of 180° between
input and output as shown in the Fig.2

Fig.2 Inverting amplifier

Now the input Vi applied to the amplifier is to be derived from its output V0 using feedback network.
But the feedback must be positive i.e. the voltage derived from output using feedback network must
be in phase with
Vi. Thus the feedback network must introduce a phase shift of 180° while feeding back the voltage
from output to input. This ensures positive feedback.
The arrangement is shown in the Fig.3 below

Fig.3 Basic block diagram of oscillator circuit

Consider a fictitious (or noise or error) voltage Vi applied at the input of the amplifier. Hence we get,
Vo = AVi
The feedback factor (β) decides the feedback to be given to input Vf = βVo
Substituting Vo
Vf =AβVi
For the oscillator, we want that feedback should drive the amplifier and hence Vf must act as Vi.
From equation (3)
we can write that, Vf is sufficient to act as Vi when,

and the phase of Vf is same as Vi i.e. feedback network should introduce 180° phase shift in addition
to 180° phase shift
introduced by inverting amplifier. This ensures positive feedback. So total phase shift around a loop is
360°.
In this condition, Vf drives the circuit and without external input circuit works as an oscillator. The
two conditions
discussed above, required to work the circuit as an oscillator arc called Barkhausen Criterion for
oscillation.
The Barkhausen Criterion states that:

Page 51 of 57 
 
 
 

1. The total phase shift around a loop, as the signal proceeds from input through amplifier, feedback
network back to input again, completing a loop, is precisely 0o or 360o.
2. The magnitude of the product of the open loop gain of the amplifier (A) and the magnitude of the
feedback factor β is
unity i.e. | Aβ | = 1.
Satisfying these conditions, the circuit works as an oscillator producing sustained oscillations of
constant frequency and amplitude.

R-C Phase Shift Oscillator

RC phase shift oscillator basically consists of an amplifier and a feedback network consisting
of resistors and capacitors arranged in ladder fashion. Hcnoc such an oscillator is also called ladder
type RC phase shift oscillator. To understand the operation of this oscillator let us study RC circuit
first, which is used in the feedback network of this oscillator. The Fig. 7 shows the basic RC circuit.

The capacitor C and resistance R are in series. Now is the capacitive reactance in ohms given by,
Xc=1/2πfC Ω
The total impedance of the circuit is, Z = R-jXc =R-j(1/2πfC) Ω =
The r.m.s. value of the input voltage applied is say Vi volts. Hence the current is given by.

From expression of current it can be seen that current I leads input voltage Vi by angle +.
The output voltage Vo is the drop across resistance R given by,
Vo=VR=IR,
Voltage across the capacitor
Vc =IXc
The drop VR is in phase with current 1 while the drop Vc lags current I by 90° i.e. I leads Vc by 90°.
The phasor diagram is shown in the Fig. 7 (b).
By using proper values of R and C, the angle d adjusted in practice equal to 60°, as required for RC
phase shift oscillator.

RC Feedback Network
As stated earlier, RC network is used in feedback path. In oscillator, feedback network must introduce
a phase shift of 180° to obtain total phase shift around a loop as 360°. Thus if one RC network
produces phase shift of
= 60° then to produce phase shift of 180° such three RC networks must be connected in cascade.
Hence in RC phase shift oscillator, the feedback network consists of three RC sections cadi producing
a phase shift of 60°, thus total phase shift due to feedback is 180° (3x60°). Such a feedback network is
shown in the Fig. 8.

Page 52 of 57 
 
 
 

Fig.8 Feedback network in RC phase shift oscillator

The network is also called the ladder network. All the resistance values and all the capacitance values
are same, so that for a particular frequency, each section of R and C produces a phase shift of 60o

Phase Shift Oscillator using Transistor

In a practical RC phase shift oscillator, a common emitter (CE) single stage amplifier is used
as a basic amplifier. This produces 180° phase shift. The feedback network consists of 3 (RC) sections
each producing 60° phase shift. Such a RC phase shift oscillator using BJT amplifier is shown in the
Fig. 9.
The output of amplifier is given to feedback network. The output of feedback network drives
the amplifier. The total phase shift

Fig. 9 Transistorised RC phase shift oscillator

The frequency of sustained oscillations generated depends on the values of R and C and is given by.

R=39KΩ, C=203=20x103X10-12 F. CE=10uF, RE=3.3KΩ, RC=3.9KΩ, R1=82KΩ, R2=39KΩ,

Actually to satisfy the Barkhausen condition, the expression for the frequency of oscillations is given
by.

Advantages
1. The advantages of R - C phase shift oscillator are,
2. The circuit is simple to design.
3. Can produce output over audio frequency range.

Page 53 of 57 
 
 
 

4. Produces sinusoidal output waveform.

5. It is a fixed frequency oscillator.

Disadvantages
By changing the values of R and C, the frequency of the oscillator can be changed. But the
values of R and C of all three (3) sections must be changed simultaneously to satisfy the oscillating
conditions. But this is practically impossible.
Hence the phase shift oscillator is considered as a fixed frequency oscillator, for all practical
purposes.And the frequency stability is poor due to the changes in the values of various components,
due to effect of temperature, aging etc.

EXPERIMENT NO: - 8

Date: __/__/____

SCHMITT TRIGGER CIRCUIT - USING IC555

Page 54 of 57 
 
 
 

AIM: To study the Schmitt trigger characteristics by using IC555

(and compare theoretical and practical values of the Upper Threshold voltage, VUT
and the Lower Threshold voltage, VLT.)
APPARATUS:
Bread Board
Function Generator
CRO Probes Connecting wires 555 Timer,
Resistors,
Capacitors
THEORY:
555 timer can be used as Schmitt trigger. Here two internal comparators are tied
together and externally biased at VCC/2 through R1 & R2. Since the upper
comparator will trip at (2/3) VCC and the lower comparator at (1/3) VCC the bias
provided by R1 & R2 is centered within these two thresholds. Thus a sine wave of
sufficient amplitude (> VCC /6 = 2/3 VCC – VCC/2) to exceed the reference levels
causes the internal flip–flop to alternately set and reset providing a square wave
output.
CIRCUIT DIAGRAM

Page 55 of 57 
 
 
 

PROCEDURE:
Connect the components/equipment as shown in the circuit diagram.
Switch ON the power supply.
Apply the input sine wave using function generator.
Connect the channel–1 of CRO at the input terminals and Channel-2 at the output
terminals.
Observe the output square waveform corresponding to input sinusoidal signal.
Overlap both the input and output waves and note down positions on sine wave where
output changes its state. These positions denote the Upper threshold voltage and the
Lower threshold voltage (see EXPECTED WAVEFORMS below).
Verify that these practical threshold voltages are almost same as the theoretical
threshold voltages calculated using formulas given in the THEORY section above.
Sketch the waveforms by noting down the amplitude and the time period of the input
Vin and the output Vo.
Explanation:-
The Fig. 1 shows the use of 555 timer as a schmitt trigger. The input is given to the pins 2
and 6 which are tied together. Pins 4 and 8 are connected to supply voltage +Vcc. The
common point of two pins 2 and 6 is externally biased at Vcc/2 through the resistance
network R1 and R2. Generally R1 = R2 to get the biasing of (Vcc/2). The upper comparator
will trip at 2/3 Vex: while lower comparator at (1/3)Vcc. The bias provided by R1 and R2 is
centred within these two thresholds. Thus when sine wave of sufficient amplitude, greater
than Vcc/6 is applied to the circuit as input, it causes the internal flip-flop to alternately set
and reset. Due to this, the circuit produces the square wave at the output, as shown in the
Fig.2

The frequency of square wave remains same as that of input. The Schmitt trigger can
operate with the input frequencies upto 50 kHz.

EXPECTED WAVEFORMS:

Page 56 of 57 
 
 
 

RESULT: QUESTIONS:
What is the output wave of Schmitt trigger if the input is sine wave?
What type of waveform is obtained when triangular waveforms are applied to Schmitt trigger
circuit?
Explain how a square wave is obtained at the output of timer when sine wave input is given?
What is the Threshold voltage?
How do you calculate the theoretical values of VUT and VLT in the case of IC555?
What is the Hysteresis width?
What is the minimum amplitude of the input sine wave in the case of Schmitt trigger using
IC555?
Why do we short pin 2 and pin 6 of IC555 timer for Schmitt trigger operation?
Why do we connect pin 4 of IC555 timer to Vcc?

Page 57 of 57