ECE1371 Advanced Analog Circuits

Noise in Switched-Capacitor Circuits

17 March 2014

Trevor Caldwell
trevor.caldwell@analog.com

What you will learn#

• How to analyze noise in switched-capacitor
circuits

• Significance of switch noise vs. OTA noise

Power efficient solution
Impact of OTA architecture

• Design example for ∆Σ modulator

2
 Review
• Previous analysis of kT/C noise
(ignoring OTA/opamp noise)
Phase 1: kT/C1 noise (on each side)
Phase 2: kT/C1 added to previous noise (on each side)
Total Noise (input referred): 2kT/C1
Differentially: 4kT/C1

Review
• SNR (differential)
Total noise power: 4kT/C1
Signal power: (2V)2/2
SNR: V2C1/2kT

• SNR (single-ended)
Total noise power: 2kT/C1 (sampling capacitor C1)
Signal power: V2/2 (signal from -V to V)
SNR: V2C1/4kT

4
 Noise in an Integrator
• Two noise sources VC1 and VOUT
VC1: Represents input-referred sampled noise on input
switching transistors + OTA
VOUT: Represents output-referred (non-sampled) noise
from OTA

Thermal Noise in OTAs

• Single-Ended Example
Noise current from each transistor is I n2 = 4 kTγ gm
Assume γ = 2 / 3

In3 M3 M4 In4
VOUT

VIN+ M1 In1 In2 M2 VIN-

In5 M5 VB1

6
 Thermal Noise in OTAs
• Single-Ended Example
Thermal noise in single-ended OTA
Assuming paths match, tail current source M5 does not
contribute noise to output
8 kT
PSD of noise voltage in M1 (and M2):
3 gm1

PSD of noise voltage in M3 (and M4):

8 kTgm 3
3 gm2 1

Total input referred noise from M1 - M4

16 kT  gm 3  16 kT
Sn,eq =  1+ = nf
3 gm1  gm1  3 gm1
Noise factor nf depends on architecture

OTA with capacitive feedback

• Analyze output noise in single-stage OTA
Use capacitive feedback in the amplification /
integration phase of a switched-capacitor circuit

8
 OTA with capacitive feedback
• Transfer function of closed loop OTA

VOUT G
H ( s) = =
Vn,eq 1 + s / ω o

where the DC Gain and 1st-pole frequency are

1 β gm1
G≈ = 1 + C1 / C2 ωo =
β CO
Load capacitance CO depends on the type of OTA – for
a single-stage, it is CL+C1C2/(C1+C2), while for a two-
stage, it is the compensation capacitor CC

OTA with capacitive feedback

• Integrate total noise at output
∞

= ∫ Sn,eq (f ) H ( j 2π f ) df
2 2
VOUT
0

16 kT ω o 2
= nf G
3 gm1 4
4 kT
= nf
3 β CO
4 kT
Minimum output noise for β=1 is nf
3CO

Not a function of gm1 since bandwidth is proportional to

gm1 while PSD is inversely proportional to gm1

10
 OTA with capacitive feedback
• Graphically#

Noise is effectively filtered by equivalent brick wall

response with cut-off frequency πfo/2 (or ωo/4 or 1/4ττ)
Total noise at VOUT is the integral of the noise within the
brick wall filter (area is simply πfo/2 x 1/β
β2)

11

Sampled Thermal Noise

• What happens to noise once it gets sampled?
Total noise power is the same
Noise is aliased – folded back from higher frequencies
to lower frequencies
PSD of the noise increases significantly

12
 Sampled Thermal Noise

• Same total area, but PSD is larger from 0 to fS/2

G2 Sn,eq
2
VOUT 4 kT 1
SVout (f ) = = = nf
4τ fS / 2 fS / 2 3 β CO fS / 2
1 πf
Low frequency PSD G2 Sn,eq is increased by = 3 dB
2τ fS fS

13

Sampled Thermal Noise

• 1/f3dB is the settling time of the system, while
1/2fS is the settling period for a two-phase clock
1/ 2 fS
−
e τ < 2 − ( N + 1)
π f3 dB
> ( N + 1)ln2
fS
PSD is increased by at least ( N + 1)ln2
If N = 10 bits, PSD is increased by 7.6, or 8.8dB

• This is an inherent disadvantage of sampled-

data compared to continuous-time systems
But noise is reduced by oversampling ratio after digital
filtering

14
 Noise in a SC Integrator
• Using the parasitic-insensitive SC integrator

• Two phases to consider

1) Sampling Phase
Includes noise from both φ1 switches
2) Integrating Phase
Includes noise from both φ2 switches and OTA

15

Noise in a SC Integrator
• Phase 1: Sampling

Noise PSD from two switches: SRon (f ) = 8kTRON

Time constant of R-C filter: τ = 2RON C1
PSD of noise voltage across C1

8kTRON
SC 1 (f ) =
1 + (2π fτ )2

16
 Noise in a SC Integrator
• Phase 1: Sampling
Integrated across entire spectrum, total noise power in
C1 is
8kTRON kT
VC21,sw 1 = =
4τ C1
Independent of RON (PSD is proportional to RON,
bandwidth is inversely proportional to RON)
After sampling, charge is trapped in C1

17

Noise in a SC Integrator
• Phase 2: Integrating

• Two noise sources: switches and OTA

Noise PSD from two switches: SRon (f ) = 8kTRON
16 kT
Noise PSD from OTA: Svn,eq (f ) = nf
3 gm1
2
Noise power across C1 charges to 2VRon + Vn2,eq

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 Noise in a SC Integrator
• What is the time-constant?

1/ sC2 + RL
Analysis shows that ZIN =
1 + gm1RL
1
For large RL, assume that ZIN ≈
gm1
Resulting time constant τ = (2RON + 1/ gm1 )C1

19

Noise in a SC Integrator
• Total noise power with both switches and OTA
on integrating phase

Svn,eq (f ) SRon (f )
VC21,op = VC21,sw 2 =
4τ 4τ
16kT nf 8kTRON
= =
3 gm1 4(2RON + 1/ gm1 )C1 4(2RON + 1/ gm1 )C1
4 kT nf kT x
= =
3C1 (1 + x) C1 (1 + x)

Introduced extra parameter x = 2RON gm1

20
 Noise in a SC Integrator
• Total noise power on C1 from both phases

VC21 = VC21,op + VC21,sw 1 + VC21,sw 2

4 kT nf kT x kT
= + +
3C1 (1 + x) C1 (1 + x) C1
kT  4 nf / 3 + 1 + 2 x 
=  
C1  1+ x 

Lowest possible noise achieved if x → ∞

2kT
In this case, VC 1 =
2

C1

What was assumed to be the total noise was actually

the least possible noise!

21

Noise Contributions
• Percentage noise contribution from switches
and OTA (assume nf=1.5)
100
Switch
OTA
80
Noise Fraction (%)

60

40

20

0
0 2 4 6 8 10
x=2RONgm1

22
 Noise Contributions
• When gm1 >> 1/RON (x >> 1)#
Switch dominates both bandwidth and noise
Total noise power is minimized

• When gm1 << 1/RON (x << 1)#

OTA dominates both bandwidth and noise
Power-efficient solution
Minimize gm1 (and power) for a given settling
time and noise
kT  4 
gm1 = n + 1+ 2x 
2  3 f
τ VC1  
Minimized for x=0

23

Maximum Noise
• How much larger can the noise get?
Depends on nf# (table excludes cascode noise)

Maximum
Architecture Relative VEFF’s nf +dB
Noise (x=0)
Telescopic/
VEFF,1=VEFF,n/2 1.5 3.kT/C1 1.76
Diff.Pair
Telescopic/
VEFF,1=VEFF,n 2 3.67.kT/C1 2.63
Diff.Pair
Folded
VEFF,1=VEFF,n/2 2.5 4.33.kT/C1 3.36
Cascode
Folded
VEFF,1=VEFF,n 4 6.33.kT/C1 5.01
Cascode

24
 Separate Input Capacitors
• Using separate input caps increases noise
Each additional input capacitor adds to the total noise
Separate caps help reduce signal dependent
disturbances in the DAC reference voltages
C2
1 2
C1
VI
VO
2 1

2
C1a
VDAC kT  4 nf / 3 + 1 + 2 x   C1a 
VC21 =    1 + + ... 
1
C1  1+ x  C1 

25

Differential vs. Single-Ended

• All previous calculations assumed single-ended
operation
For same settling time, gm1,2 is the same, resulting in
the same total power [0dB]
Differential input signal is twice as large [gain 6dB]
Differential operation has twice as many caps and
therefore twice as much capacitor noise (assume same
size per side – C1 and C2) [lose ~1.2dB for nf=1.5, x=0#
less for larger nf]

• Net Improvement: ~4.8dB

26
 Differential vs. Single-Ended
• Single-Ended Noise
kT  4 nf / 3 + 1 + 2 x 
VC21,se =  
C1  1+ x 
• Differential Noise
VC21,diff = VC21,op + VC21,sw 1 + VC21,sw 2
4 kT nf 2kT x 2kT
= + +
3C1 (1 + x) C1 (1 + x) C1
kT  4 nf / 3 + 2 + 4 x 
=  
C1  1+ x 
• Relative Noise (for nf=1.5, x=0)
VC21,diff 4 nf / 3 + 2 + 4 x 4
= =
VC21,se 4 nf / 3 + 1 + 2 x 3

27

Noise in an Integrator
• What is the total output-referred noise in an
integrator?
Assume an integrator transfer function
࢑ࢠି૚ ࢑ࢠି૚
ࡴ(ࢠ) = ≈
૚ + ࣆ ૚ + ࢑ − ૚ + ࣆ ࢠି૚ ૚ − ࢠି૚
C1 1
where k = and µ =
C2 A

28
 Noise in an Integrator
• Total output-referred noise PSD
2
SINT (f ) = SC1(f ) H ( z) + SOUT (f )
4 kT
2
where VOUT = nf
3 β CO
kT  4 nf / 3 + 1 + 2 x 
and VC21 =  
C1  1+ x 
Since all noise sources are sampled, white PSDs
Vx2
Sx =
fS / 2
To find output-referred noise for a given OSR in a ∆Σ
modulator: fS /(2⋅OSR )

VINT = ∫ SINT (f )df

2

29

Noise in a ∆Σ Modulator
• How do we find the total input-referred noise in a
∆Σ modulator?
1) Find all thermal noise sources
2) Find PSDs of the thermal noise sources
3) Find transfer functions from each noise source to
the output
4) Using the transfer functions, integrate all PSDs from
DC to the signal band edge fS/2—OSR
5) Sum the noise powers to determine the total output
thermal noise
6) Input noise = output noise (assuming STF is ~1 in
the signal band)

30
 Noise in a ∆Σ Modulator
• Example
fS = 100MHz, T = 10ns, OSR = 32
SNR = 80dB (13-bit resolution)
Input Signal Power = 0.25V2 (-6dB from 1V2)
Noise Budget: 75% thermal noise
Total input referred thermal noise:
This image cannot currently be display ed.

This image cannot currently be display ed.

31

Noise in a ∆Σ Modulator
1) Find all thermal noise sources

kT  4 nfA / 3 + 1 + 2 xA  kT  4 nfB / 3 + 1 + 2 xB 
Vni2 1 =   Vni2 2 =  
C1A  1 + xA  C1B  1 + xB 
4 kT 4 kT
1 =
2
2 =
Vno nfA 2
Vno nfB
3 β ACOA 3 β BCOB
2kT  Cf 2 Cf 3  2kT
Vn23 =  1+ + = (1 + 2 + 1)
Cf 1  Cf 1 Cf 1  Cf 1
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 Noise in a ∆Σ Modulator
2) Find PSDs of the thermal noise sources
For each of the mean square voltage sources,
Vx2
Sx =
fS / 2

3) Find transfer functions from each noise source

to the output
Assume ideal integrators
z −1
H A ( z ) = HB ( z ) =
1 − z −1
STF( z ) = 1
1
NTF( z ) = (1 − z −1 )2 =
1 + 2H ( z ) + H ( z )2
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Noise in a ∆Σ Modulator
3) Find transfer functions from each noise source
to the output
From input of HA(z) to output#
NTFi 1 ( z ) = ( 2H ( z) + H ( z )2 ) NTF( z )
2H ( z ) + H ( z) 2
= = 2 z −1 − z −2
1 + 2H ( z) + H ( z ) 2

From output of HA(z) to output#

NTFo1 ( z ) = ( 2 + H ( z ) ) NTF( z)
2 + H ( z)
= = (1 − z −1 )(2 − z −1 )
1 + 2H ( z) + H ( z ) 2

34
 Noise in a ∆Σ Modulator
3) Find transfer functions from each noise source
to the output
From input of HB(z) to output#

NTFi 2 ( z ) = H ( z )NTF( z )
H ( z)
= = z −1 (1 − z −1 )
1 + 2H ( z ) + H ( z ) 2

From output of HB(z) to output (equal to transfer

function at input of summer to output)#
NTFo 2 ( z ) = NTF( z ) = (1 − z −1 )2

35

Noise in a ∆Σ Modulator
3) Find transfer functions from each noise source
to the output
Most significant is NTFi1
20
Signal Band

0
Magnitude (dB)

-20

|NTFi1|
|NTFo1|
-40
|NTFi2|
|NTFo2|
-60 -3 -2 -1
10 10 10
Normalized Frequency

36
 Noise in a ∆Σ Modulator
4) Using the transfer functions, integrate all PSDs
from DC to the signal band edge fS/2—OSR
Use MATLAB/Maple to solve the integrals#
fS /(2⋅OSR )
Vni2 1
∫
2
N =
2
i1 NTFi 1 (f ) df
fS / 2 0

Vni2 1  5fS 2fS  π 

=  − sin  
fS / 2  2 ⋅ OSR π  OSR  

2 fS /(2⋅OSR )
Vno
∫
2
N =
2
o1
1
NTFo1 (f ) df
fS / 2 0

1  7 fS  π   π  9fS  π 
2
Vno 2f
=  + S sin   cos  − sin  
fS / 2  OSR π  OSR   OSR  π  OSR  

37

Noise in a ∆Σ Modulator
4) Using the transfer functions, integrate all PSDs
from DC to the signal band edge fS/2—OSR

Vni2 2  fS fS  π 
Ni22 = − sin  
fS / 2  OSR π  OSR  

2 + Vn 3  3fS  π   π 
2 2
Vno f
N 2
=  + S sin   cos  
fS / 2  OSR π
o2
 OSR   OSR 
4f  π 
− S sin  
π  OSR  

(Some simplifications can be made for large OSR)

38
 Noise in a ∆Σ Modulator
5) Sum the noise powers to determine the total
output thermal noise
Assume xA = xB = 0.1 and nfA = nfB = 1.5

2.9kT 1 2kT π2 2.9kT π 2

V ≈
2
+ +
C1A OSR β ACOA 3OSR3
TH
C1B 3OSR3

2kT π4 8kT π 4
+ +
β BCOB 5OSR5 Cf 1 5OSR5

With an OSR of 32, first term is most significant

(assume βA = βB = 1/3)

kT kT kT
2
VTH ≈ 9.1× 10 −2 + 6.0 × 10 −4 + 2.9 × 10−4 +K
C1A COA C1B

39

Noise in a ∆Σ Modulator
6) Input noise = output noise (assuming STF is ~1
in the signal band)
kT
2
VTH ≈ 9.1× 10 −2 = (43.4 µV )2
C1A
=> C1A = 200fF

Assuming other capacitors are smaller than C1A, then

subsequent terms are insignificant and the
approximation is valid

If lower oversampling ratios are used, other terms may

become more significant in the calculation

40
 Noise in a Pipeline ADC
• Similar procedure to ∆Σ modulator, except
transfer functions are much easier to compute

• Differences#
Input refer all noise sources
Gain from each stage to the input is a scalar
Noise from later stages will be more significant since
typical stage gains are as low as 2
Sample-and-Hold adds extra noise which is input
referred with a gain of 1
Entire noise power is added since the signal band is
from 0 to fS/2 (OSR=1)

41

Noise in a Pipeline ADC

• Example
If each stage has a gain G1, G2, # GN

1 + Vni 2 2 + Vni 3
2 2 2 2 2
Vno Vno VnoN
Ni2 = Vni2 1 + + + L +
G12 G12G22 G12G22 L GN2

S/H stage noise will add directly to Vni1

42
 Further Reading
• Appendix C of Understanding Delta-Sigma Data
Converters, Schreier and Temes
• Schreier et al., Design-Oriented Estimation of Thermal
Noise in Switched-Capacitor Circuits, TCAS-I, Nov. 2005

43