Imperial Journal of Interdisciplinary Research (IJIR)
Vol-3, Issue-1, 2017
ISSN: 2454-1362, http://www.onlinejournal.in
A New SMPS with Enhanced Power
Quality for Processor Based Boards
Mr. Mariya Babu1, Mr. Kamal Kiran Tata2 &
Mr. Rushi Santhosh Sing3
1
M.Tech Student Scholar, 2Associate Professor, 3Associate Professor
1,2,3
Department of EEE, MVRCET, Paritala, A.P, India-521 180
Abstract: Designing of high power quality switching
mode power supplies(SMPS) are going to be very
challenging for power supply design engineers. This
project introducing a new methodology of power
factor correction SMPS for processor based boards
made by back to back connected buck-boost
converter in discontinuous conduction mode. The
operation of the bridgeless buck–boost converter in
intermittent conduction mode guarantees
characteristic PFC operation and lessens intricacy
in control. The execution of the proposed different
yield SMPS is assessed under fluctuating input
voltages and loads by Simulating this Circuit in
MATLAB/Simulink environment, and the outcomes
acquired through Simulation are approved
tentatively on a created model. Simulation results
exhibit the enhanced execution of the proposed
SMPS.
1. Introduction
Switched mode power supplies (SMPS) are
utilized for driving up various parts in a personal
computer(PC) by building up different dc voltages
from a single-phase AC voltage from the power grid.
Typically, a diode bridge rectifier (DBR) trailed by a
filter capacitor is utilized at the front end of these
SMPSs. DBR causes critical disintegration in the
power quality [1], [2], prompting to low power factor
(PF) and high harmonic distortion at the AC mains
with a high crest factor of the input current [3]. The
current waveform is extremely peaky, non-
sinusoidal, and profoundly bended; the PF is around
0.48. At full load, the total harmonic distortion
(THD) of input ac mains current is 83.5%. The
performance of the power supply is violating the
various international standards set by different
universal models, for example, the International
Electro Technical Commission (IEC) 61000-3-2 [4].
Because of these issues, enhanced power-quality
SMPSs are widely being researched, which are relied
upon to draw a sinusoidal input current at a high PF.
Improvement in power quality additionally brings
about better reliability and improved productivity. To
accomplish a detectable change in power quality, PF
correction (PFC) circuits are utilized in these SMPSs
Imperial Journal of Interdisciplinary Research (IJIR)
at the utility interface point [5]– [7]. PFC circuits can
accomplish high PF and low THD in the input
current even at fluctuating information voltages and
differing loads. Apart from this, they are likewise fit
for yielding solidly controlled output dc voltages.
The utilization of non-isolated PFC
converters at the front end of these power supplies is
a usually acknowledged answer for accomplish a
decent power quality at different input voltages and
loads [8]. Discontinuous conduction mode (DCM)
operation of these converters brings about inherent
PFC and reduction in sensor prerequisites. Besides,
DCM can likewise be executed with simple control
technique. Recent advancements in the field of
power electronics have empowered the elimination
of DBR at the front end of the power supplies, in this
manner enhancing the power quality at the ac mains.
Different bridgeless single ended primary inductance
converter and Cuk converters are proposed in the
literature, which result in low voltage stress,
enhanced thermal management, and low conduction
losses [9]– [11]. However, the component count is
increased in these converters, which is not
appropriate for low-power SMPS applications, in
spite of the fact that the output voltage range is
genuinely extensive. A bridgeless buck PFC
converter is proposed in [12], which acts as a voltage
double. A bridgeless boost converter is reported in
[13], which eliminates one diode drop in the current
path. However, in both converter topologies, the
output voltage range is restricted. A buck–boost
converter design is most appropriate for PC SMPSs
among different bridgeless converter topologies
especially because it can deal with a larger voltage
range and yet convey solidly regulated output
voltages. Such a bridgeless buck–boost converter is
proposed in [14] for universal input PFC
applications, which offers low switch stress, reduced
magnetic size, and low inductor conduction losses.
However, one of the switching devices is dependably
on in the conduction path. Wei et al. [15] have
proposed a bridgeless buck–boost converter that
utilizes three switches in the conduction path, which
increases the conduction losses. Typically, a half-
bridge voltage source inverter (VSI) is utilized at the
output for high-frequency isolation and different dc
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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-3, Issue-1, 2017
ISSN: 2454-1362, http://www.onlinejournal.in

output voltages in PC power supplies since it
provides better core usage over whatever other
unipolar converter and it is cost effective contrasted
with push–pull and full-bridge converters [16]– [19].
It is seen from the available literature that
the bridgeless converter-based various output SMPS
has not been attempted in this way, especially
capacitors C11 and C12, two high-frequency
switches S1 and S2, and one multiple output high-
frequency transformer (HFT). The HFT is having
one primary winding and four secondary
windings which are connected in center-tapped
configuration to reduce the losses.
Inductor-Capacitor Bridgeless buck-boost
Half Bridge VSI

filter Converter

focusing on SMPSs for PCs. In this manner, an iL1 I01

iin
.
attempt is made here to reduce the current harmonics Dp2
ns1 D1
D2
L1
C01
+
ns2 R1
and to accomplish high PF at the utility interface in a Lin Sp S1
-

Vin Dn1 C11 iL2 I02

various output SMPS by utilizing a bridgeless buck– Cin Lp
Dn2 . . D3 L2
boost converter at the front end. The diode bridge at Sn Vdc
+ ns3
ns4 D4 C01
+
R1 V02
the front end is eliminated, and two buck–boost -
-

Dp1 C12 iL3 I03

converters are associated consecutive so that each
deal with one half cycle of the ac supply. The
bridgeless buck–boost converter is designed in DCM
for single control loop and for inherent PFC. This
regulated dc voltage is given to half-bridge VSI for
acquiring various output dc voltages. The half-
connect VSI is designed in continuous conduction
mode to decrease the component stress. Moreover,
just a single control loop is required to regulate
various dc voltages. The proposed system is
designed, analyzed, and simulated in
MATLAB/Simulink programming [20], and the
execution is studied during various input voltages
and loads to show the enhanced execution as far as
low THD and high PF.
2. Configuration of A new SMPS With
Enhanced Power Quality for Processor
Based Boards
The system configuration of the proposed A
new SMPS with enhanced power quality for
processor based boards is shown in Fig. 1. Single-
phase ac supply is fed to two buck–boost converters
through an inductor–capacitor (Lin–Cin) filter to
eliminate the high-frequency ripples. The upper
buck–boost converter that conducts during the
positive half cycle of the ac supply consists of one
high-frequency switch Sp, inductor Lp, and two
diodes Dp1 and Dp2. Similarly, the lower buck–
boost converter that operates during the negative half
cycle consists of one high-frequency switch Sn,
inductor Ln, and two diodes Dn1 and Dn2. Both
inductors Lp and Ln of buck–boost converters are
designed in DCM to obtain inherent PFC at the input
ac mains. The input capacitor of the half bridge VSI
acts as the filter at the output of the buck–boost
Converter. The voltage and current stresses on the
switches of the buck–boost converters are evaluated
to estimate the switch rating and heat sink design.
The output dc voltage of the buck–boost converter is
regulated by using closed-loop control. The regulated
dc output voltage of the buck–boost converter is fed
to the half-bridge VSI for obtaining multiple dc
voltages. The half-bridge VSI consists of two input
Ln
. L3
ns5 D5
S2
ns6
D6 C01
+
R1 V03
-
iL4 I04
.
ns7 D7 L4 +
ns8 D8 C01 R1 V04
-
Figure 1. Configuration of the proposed SMPS for
processor based boards
At the secondary side of the HFT, filter
inductors L1, L2, L3 and L4 and capacitors Co1,
Co2, Co3, and Co4 are connected to each winding to
reduce the current and voltage ripples, respectively.
The output voltages are regulated by using closed
loop control of one of the output voltages. The
highest rated dc voltage is sensed for this purpose.
The other three outputs are controlled through duty
ratio control of the half-bridge VSI because a
common core is used for all other secondary
windings of the HFT with proper winding
arrangements. The effect of varying input voltages
and loads is studied to reveal the improved
performance of A new SMPS with enhanced power
quality for processor based boards. The hardware of
the SMPS is implemented in a laboratory prototype
to verify the simulated results.
3. Operating Principle of a new SMPS
With Enhanced Power Quality for
Processor Based Boards
The proposed, A new SMPS with enhanced
power quality for processor based boards consists of
a single-phase ac supply feeding two back to- back-
connected buck–boost converters with a half-bridge
VSI and multiple-output High Frequency
Transformer at the load end. The buck–boost
converters are controlled suitably to obtain a high PF
and low input current THD. The half-bridge VSI at
the output takes care of high-frequency isolation with
multiple dc output voltages being regulated. The
operation of both converters in Positive and Negative
switching cycles are described in the following
subsections.

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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-3, Issue-1, 2017
ISSN: 2454-1362, http://www.onlinejournal.in

3.1. Operation of Buck–Boost Converter State 2

During Positive Switching Cycles
Inductor Discharging
Lin Dp2
The switches in the upper and lower buck– Ph
+ - Sp
boost converter is switched on and off alternately in - -
the positive and negative half cycles of the ac Cin
+
Dn1 Lp
Vin C11 +
voltage, respectively. The operation of the upper -
+ Dn2
buck–boost converter in DCM during the positive N
Sn
Isolated
converter
half cycle of the ac input voltage is shown in fig.2. -
C12
The lower one operates in the same way but during Dp1 Ln

the negative half cycle. Three states are observed in +

DCM operation in each switching cycle.

Lin Dp2
Figure 4. Upper switch Sp is off
Sp
State 3
Cin Dn1 Lp Inductor Discharged
Vin C11 Lin Dp2
Dn2
Isolated Ph
+ - Sp
Sn converter -
+
C12 Cin Dn1 Lp
Vin C11 +
Dp1 Ln - Dn2

N Isolated
Sn converter

C12 -
Dp1 Ln
Figure 2: Circuit diagram of back to back connected buck- +
boost converters

In the first state, when the upper switch Sp Figure 5. Both switch and diode are off
is on, inductor Lp starts storing energy from the
input, and the inductor current increases to the
Sp Sp turn off
maximum value, as shown in Fig.3. Diode Dp1 Sp turn on
completes the current flow path in the input side. In
the second state, Sp is turned off, and the energy in Zero inductor
inductor Lp is transferred to the output, thus reducing current

its current from maximum value to zero, as shown in

iLp
Fig.4. In the last state of one switching cycle, neither DT
the switch and nor the diode conducts, and the
inductor current remains zero, ensuring DCM
Vdc
operation as shown in Fig.5. The Fig 6 shows the
waveforms for one complete pulse width modulation
Vdc
(PWM) switching cycle. In the next switching cycle, Sp on Sp off
the same sequence of operation repeats itself.
Similarly, for negative half cycle of the input Figure 6. Buck-Boost converter waveforms in
voltage, the lower buck-boost converter operates, and positive switching cycle
the same sequence of operation continues.
3. Operation of Half-Bridge VSI
State 1
Inductor Charging The controlled output dc voltage of the dual
Lin Dp2 buck–boost converter is fed to the half-bridge VSI
for high-frequency isolation, for voltage scaling, and
Ph + - Sp
for obtaining multiple dc output voltages. The
+
Cin
+
Dn1 Lp operation of the half-bridge VSI in one switching
Vin C11
-
- Dn2 cycle is described in four states. The second and
N Isolated fourth states are similar and occur twice in each
Sn converter
switching cycle, as shown in Fig. 8. In the first state,
C12
Dp1 Ln the upper switch S1 is turned on, the input current
circulates through the primary winding of the HFT to
the lower input capacitor C12. Diodes D1, D3, D5,
and D7 start conducting, and the inductors associated
Figure 3. Upper switch Sp is on

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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-3, Issue-1, 2017
ISSN: 2454-1362, http://www.onlinejournal.in

with the windings start storing energy, as shown in iL1

N
Fig. 7. ns1 D1 L1 +
D2 C01 R1
.Phns2 -
V01
-
State 1 C11 S1 iL2 I02
N N
iL1 I01 +
. D1 L1 + ns3 D3 L2 +
ns1
Vdc D4 C02 R2 - V02
ns2 D2 C01 R1 .Phns4
-V01 iL3 I03
S1 . Ph
C11 iL2 I02 . N
C12 S2 L3
. ns5 D5
+
ns3 D3 L2 + D6 C03
Vdc D4 C02
.Phn.s6 R3
- V03
ns4 R2 V02
- I04
iL4
I03 N
iL3
C12
S2
. ns7 D7 L4 +
ns5 D5 L3 +
ns8 D8 C04 R4 V04
ns6 D6 C03 R3 V03 .Ph -
-
iL4 I04
. +
ns7 D7 L4 Figure 9. When the switch S2 is on
ns8 D8 C04 R4 V04
-

4. Design of The Proposed new SMPS

Figure 7. When the switch S1 is on With Enhanced Power Quality for
Processor Based Boards
Therefore, inductor currents iL1, iL2, iL3, and iL4
increase, and output filter capacitors Co1, Co2, Co3, To simulate the proposed bridgeless-
and Co4 discharge through the loads. In the second converter-based multiple output SMPS, it is essential
state fig.8, both switches are turned off, and all to estimate the component values. To derive the
secondary diodes D1–D8 freewheel the stored energy necessary design equations, the switches and diodes
until the voltage across the HFT becomes zero. are considered to be ideal, and the switching
Therefore, inductor currents iL1, iL2, iL3, and iL4 frequency is considered very high compared to the
start decreasing. line frequency (50 Hz). This enables considering the
average quantity in one switching cycle for analysis
State 2 purposes. The specifications of the proposed
iL1 I01 bridgeless-converter-based multiple-output SMPS
. D1 L1
ns1 + are given in the Appendix.
ns2 D2 C01 R1
-
Vdc/2
iL2
C11 S1
. D3 L2 +
4.1. Design of Buck–Boost Converter
ns3

ns4 D4 C02 R2
Vdc
- The design of the inductors in the buck–
Vdc/2
.
iL3 I03 boost converters is very important to ensure DCM
C12 S2 D5 L3 +
ns5
ns6
operation. The values of upper and lower inductors
D6 C03 R3
- are the same, and they are chosen based on the
.
iL4 I04 change in input current in one switching cycle during
ns7 D7 L4 + on condition of the switch. The inductor value for a
ns8 C04
D8 R4
-
specified current ripple is expressed as
Figure 8. When both switches are off ……………………..…. (1)

In the third state of the switching cycle, the
second switch S2 is turned on, and the input current
flows through upper capacitor C11 and the primary
winding, as shown in Fig. fig.3.12. Associated diodes
D2, D4, D6, and D8 in the secondary windings
conduct, and inductors L1, L2, L3, and L4 start
storing energy as shown in fig.5.12. When the energy
stored in the inductors reaches maximum values, the
switch is turned off. In the last state, all secondary
diodes start conducting, which is similar to the
second state. The same operating states repeat in
each switching cycle.
State 3
Where D is the duty cycle, i.e., ton/T, where ton is
the “on” time of the switch and T is the total period
in one switching cycle, and Vavg is the average of
single-phase ac input voltage across the input of the
buck–boost converter.
In DCM condition, the inductor current ripple is
considered maximum, and it must be equal to twice
the input current
…………………..…..… (2)
Substituting (2) in (1) yields the value of Lp min as
……….……..………..… (3)

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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-3, Issue-1, 2017
ISSN: 2454-1362, http://www.onlinejournal.in
For a deep DCM condition, the inductor value should
be less than one-tenth of the minimum inductor value
[21]. Thus, it is selected as
…………………….…...... (4)
The inductor value is calculated as 60 μH for a D
value of 0.2, with switching time T being 50 μs and
Vavg being 198 V. A 60-μH inductance value is
selected here for ensuring DCM under all operating
conditions.
4.2. Input Filter Design
To filter the higher order harmonics in the
proposed SMPS, it is essential to use an L−C filter.
This filter also reduces the harmonic distortion at the
ac supply. The maximum capacitance value is
expressed as
…….……. (5)
Where Im and Vm are the peak input ac current and
ac voltage, respectively. The maximum capacitance
is estimated as 409 nF for a θ value of 1◦ (for
ensuring high PF). The capacitance value Cin for the
prototype is selected to be 330 nF. The filter inductor
for obtaining low harmonic distortion at input ac
mains is calculated as
= 3.07 mH…………...…………………. (6)
where fc is the cutoff frequency. The filter
inductor Lin is calculated as 3.07 mH. A 2.5-mH
filter inductor is selected for the hardware
development.
4.3. Design of Half-Bridge VSI
The input capacitors of the half-bridge VSI act as a
low-pass filter to eliminate the harmonics, which is
reflected due to the single-phase ac mains.
4.3.1. Design of Input Capacitor
The input capacitor is designed to eliminate
the harmonics introduced due to the single-phase ac
mains. Thus, it is governed by the amount of the 100-
Hz (lowest harmonic) current flowing in the
capacitor. For maintaining PFC operation, the input
current and voltage should be in phase. Therefore,
the input power Pin is
Imperial Journal of Interdisciplinary Research (IJIR)
. ……. (7)
Where the latter term corresponds to the 100-Hz
ripple which is reflected on the input capacitors of
the half-bridge VSI. It is expressed as
……………..… (8)
Where ic(t) is the total current flowing in the
capacitors C11 and C12.
The output voltage ripple corresponding to these
capacitors’ current is given by
………………..… (9)
Sin(ωt) is taken as one for the maximum value of
voltage ripple at the capacitor. Hence, (9) is rewritten
as
……….…………..…… (10)
Therefore, the capacitors C11 and C12 are estimated
as
………….. (11)
Two equal valued input capacitors C11 and C12 are
calculated as 0.63 mF for an ω of 314 rad/s, with
ΔVo being 6 V (2% of Vo) and output current of the
buck–boost converter being 1.2 A. The permissible
current ripple is assumed to be 2%.
4.3.2. Design of Turns Ratio
In steady-state condition, the change in
output inductor current iL1 during switch on and off
conditions is equal to zero, and it is expressed as
…… (12)
Where Vo1 is the sensed dc output voltage, Dh is the
duty cycle of half-bridge VSI, and Th is one
switching time.
Solving (8) for calculating turns ratio
…….. (13)
The turn’s ratio from (13) is calculated as 0.1 for an
output dc voltage of +12 V and for a duty cycle Dh
of 0.4.
5. Control of Proposed New SMPS With
Enhanced Power Quality for Processor
Based Boards
The control of the SMPS is carried out
using two independent controllers. The front-end
bridgeless buck–boost converter utilizes the voltage
follower approach, while the half-bridge VSI utilizes
the average current control.
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ISSN: 2454-1362, http://www.onlinejournal.in

The component values are used in the to maintain the output voltage constant. Thus, the
modeling of the proposed multiple-output computer control is able to take care of the impact of any
SMPS. These values and the ones used in the individual output on the overall variation in the duty
experimental prototype are tabulated in Table 1. ratio and also the contribution of the present load
condition of any of the outputs to the variations in
Table 1. Parameters of a new SMPS with enhanced power Vo1, Vo2, Vo3, and Vo4. If the load on any of the
quality for processor based boards other windings is varied, the duty cycle undergoes a
change according to the impact felt on the highest
Component Calculated Selected Experiment rated output, and hence, voltage regulation is taken
Input care of. However, the response of the other windings
inductors Lp 60µH 60µH 60µH is slightly slower as compared to the winding whose
and Ln output is sensed. Switches S1 and S2 are switched on
Filter and off alternately in each half cycle of one PWM
Capacitor 390nF 330nF 330nF period with sufficient dead time to avoid shoot-
Cin through.
Filter 3.07mH 2.5mH 2.5mH
inductor 7. Simulated performance of the
Capacitor 630µF 660µF 660µF proposed new smps with enhanced power
C11 and C12 quality for processor based boards
5.1. Control of Front-End Converter Performance of the proposed new SMPS
with enhanced power quality for processor based
The control of the PFC bridgeless converter boards is simulated in MATLAB/Simulink
generates the PWM pulses for both switches (Sp and environment using Sim-Power- System toolbox and
Sn) according to the polarity of input ac mains Continuous time sampling. A sampling time of 0.1
voltage. In this technique, voltage error Ve, i.e., the μs is considered during simulation. The waveforms,
difference between the reference voltage Vdcref and such as switching pulses, buck–boost converter
the sensed dc output voltage Vo1, is fed to a output voltage Vdc, multiple-output voltages Vo1,
proportional– integral (PI) voltage controller.The Vo2, Vo3, and Vo4.
voltage error signal (Ve) is expressed as
Ve(n) = Vdcref (n) − Vdc(n)……………… (14)
where n represents the nth sampling instant.
This error voltage signal (Ve) is fed to the
voltage PI controller 1 to generate a controlled output
voltage (Vcc). It is expressed as
Vcc(n)=Vcc(n−1) +kp {Ve(n)−Ve(n−1)} +kiVe(n)
……... (15)
where kp and ki are the proportional and integral
gains of the voltage PI controller 1.
Finally, the output of the voltage controller 1 is
Figure 10. Waveforms of switch pulses and output voltage
compared with a high-frequency saw tooth signal of buck-boost converter
(St) to generate the PWM pulses
For vin >0; if st < Vcc, then Sp = on
If st ≥ Vcc, then Sp = off
For vin <0; if st < Vcc, then Sn = on
if st ≥ Vcc, then Sn = off…… (16)
where Sp and Sn represent the switching signals of
PFC bridgeless buck–boost converter.

5.2. Control of Half-Bridge VSI

For controlling the output voltage of the

half-bridge VSI, an average current control scheme is
used. The highest rated winding output voltage Vo1
is sensed and compared with a constant reference
value Vo1ref. The voltage error signal (Ve1) is fed to
PI controller 2, and its output is compared with the
saw tooth signal to generate PWM switching signals
Figure 11. output voltages of half bridge VSI
8. Conclusion
A new SMPS with enhanced power quality
for processor based boards has been designed,
modeled, simulated. The output dc voltage of the

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Imperial Journal of Interdisciplinary Research (IJIR)
Vol-3, Issue-1, 2017
ISSN: 2454-1362, http://www.onlinejournal.in
first stage buck–boost converter has been maintained
constant, independent of changes in the input voltage
and the load, and it is operated in DCM to
accomplish inherent PFC at the single-phase ac
mains. An agreeable execution has been
accomplished during varying input voltages and
loads with power quality indices staying inside as far
as possible set by IEC 61000-3-2. The proposed
SMPS has shown satisfactory execution, and thus, it
can be suggested as an unmistakable answer for PCs
and other similar appliances.
9. Acknowledgements
I have a number of people to thank for the
help on this paper. I will start by thanking my HOD,
RUSHI SANTHOSH SINGH THAKUR for
encouraging and helping me during the project
period.
I would like to thank my advisor and guide,
Mr. KAMAL KIRAN TATA for providing
sufficient guidance to get me through this project and
to keep me pointed in the right direction and
enlightening ideas.
I would like to thank My Parents for their
continued support and encouragement.
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