Journal of the Korean Physical Society, Vol. 62, No. 8, April 2013, pp.

1188∼1193

Analytical Models for the Electric Potential, Threshold Voltage and Drain
Current of Long-channel Junctionless Double-gate Transistors

Zhihao Ding, Guangxi Hu,∗ Ran Liu and Lingli Wang

ASIC & System State Key Lab, School of Information Science and Technology,
Fudan University, Shanghai, P. R. China 200433

Shuyan Hu
School of Electronics and Information, Tongji University, Shanghai, P. R. China 200092

Xing Zhou
School of Electrical & Electronic Engineering, Nanyang Technological University, Singapore 639798

(Received 15 February 2013, in final form 11 March 2013)

Analytical models for the electric potential, threshold voltage and drain current of long-channel
junctionless (JL) double-gate (DG) field-effect transistors (FET) are presented. A regional method
is used to solve the Poisson equation under different gate biases, and the electric potential is
obtained. With the potential model, an analytical expression for the threshold voltage is achieved.
An expression for the drain current is derived from the potential model. The analytical results are
compared with simulations, and excellent agreements are observed. The models accurately describe
the characteristics of JLDG FETs, and they are very helpful for the design and optimization of
devices.

PACS numbers: 85.30.Tv

Keywords: Analytical, Junctionless, Double-gate, MOSFET, Modeling
DOI: 10.3938/jkps.62.1188

I. INTRODUCTION are reported in the literature [9–14].

The performance of traditional single-gate metal-
oxide-semiconductor field-effect transistors (MOSFETs)
degrades seriously with the scaling of the gate length
and the gate oxide thickness [1]. A decrease in the car-
rier effective mobility and short-channel effects (SCEs)
will largely degrade the device. To improve the device
performance, a new type of transistor, called the junc-
tionless (JL) multigate MOSFET, has been proposed and
studied to some extent [2–6].
Distinct from the traditional double-gate (DG) MOS-
FET that has different doping concentrations in the
channel region and the source/drain regions, the JL
transistor has a uniformly high doping concentration
throughout the source/drain and the channel regions,
which greatly simplifies the fabrication process [3] and
improves the device’s electric properties, such that sub-
threshold slope is small and the on-state current is large
[3–8]. The drain current characteristics, the quantum
electron density in the subthreshold region, and thresh-
old voltage models have been researched, and the results
∗ E-mail: gxhu@fudan.edu.cn
-1188-
Unlike the traditional inversion MOSFET, in a JL
MOSFET, most of the on-state drain current comes from
the channel center [7,8]; therefore, the traditional model
is not applicable for this new device. We present and de-
velop an analytical model to describe the potential pro-
file of a JLDG MOSFET by solving the Poisson equation
(PE). Based on the potential model, we obtain analytic
expressions for the threshold voltage and the drain cur-
rent. We compare our model results with Medici simu-
lations [15], both of which match very well. The models
provide a simple method to calculate the channel poten-
tial, the threshold voltage, and the drain current, and to
understand the behavior of the device.
II. CHANNEL-POTENTIAL MODEL
The structure of a JLDG MOSFET is shown in Fig.
1. The gate length, gate oxide thickness, and channel
thickness are L, tsi , and tox , respectively. The Fermi
level at the source is chosen to be the reference potential.
Analytical Models for the Electric Potential, Threshold Voltage and · · · – Zhihao Ding et al. -1189-

Fig. 2. Schematic view of the three conditions, with the

shaded region indicating the depletion region: (a) fully de-
pleted condition, (b) partly depleted condition, and (c) near
flat-band condition.

The solution of Eq. (2) can be obtained with the bound-

ary conditions
Fig. 1. (Color online) Diagram of a junctionless double- dφ
gate MOSFET. |x=0 = 0 , (3)
dx
εsi dφ
VG − VF B − φs = |x=tsi /2 (4)
Cox dx
The PE can be expressed as
where VG is the voltage applied to the gate, VF B is the

  flat-band voltage, φs is the surface potential, and Cox =
d2 φ qND φ−V εox /tox , with εox being the permittivity of the oxide. The
=− 1 − exp , (1)
dx2 εsi Vt solution is
 
qND t2si qND
where φ is the electric potential, εsi is the silicon permit- φ= − x2 + tsi + VG − VF B . (5)
tivity, ND is the doping concentration, Vt = kB T /q is the 2εsi 4 2Cox
thermal voltage and V is the quasi Fermi potential. It is The maximum of φ occurs at x = 0, which means that
difficult to obtain an analytical solution to Eq. (1). For the whole region will now be depleted if (φc − V )/Vt ≤
simplicity, but without loss of physical insight, we solve −1, with φc being the potential at x = 0. When (φc −
Eq. (1) under different gate biases with different approx- V )/Vt = −1, we obtain
imations. The gate bias will put the channel into one of
four conditions: (i) for the fully-depleted (FD) condition, qND 2 qND
the inequality (φ − V )/Vt < −1 is valid throughout the VG = V + VF B − Vt − t − tsi . (6)
8εsi si 2Cox
whole channel region; (ii) for the partially-depleted (PD)
condition, the inequality (φ−V )/Vt < −1 is satisfied only
in part of the channel region; (iii) for the near-flat-band 2. PD Condition
(NFB) condition, the inequality −1 < (φ − V )/Vt < 1
holds true for the whole channel region, and φ − V = 0
corresponds to the flat-band condition; (iv) for the accu- If VG is larger than the value given in Eq. (6), the
mulation condition, (φ − V )/Vt > 1 is guaranteed. A JL electrons near the channel center cannot be neglected,
transistor seldom works in the accumulation condition, but part of the channel region (near the silicon-oxide
so we only discuss the situations (i) ∼ (iii). Figures. 2(a) interface) is still depleted. We solve different PEs in
∼ (c) respectively demonstrate these three situations. different regions as [16].
We define a location, x0 , at which the equation φ(x0 )−
V = −Vt holds true. The depletion approximation is still
valid for the region x0 < |x| < tsi /2. Because the value
of φ − V is between −Vt and 0 in the region |x| < x0 ,
1. FD Condition the exponential term in Eq. (1) can be approximated as
exp[(φ − V )/Vt ] ≈ 1 + (φ − V )/Vt [17], and PE can be
expressed as
In the FD condition, the exponential term in Eq. (1) 
can be neglected in the whole region |x| < tsi /2, and Eq. d2 φ qND φ−V
εsi Vt for |x| > x0
(1) is simplified to = (7)
dx2 − qN D
εsi for x0 ≤ |x| ≤ tsi /2

d2 φ qND One point that should be noted is that, as we take into

=− . (2) account the dopant concentration only and ignore other
dx2 εsi
-1190- Journal of the Korean Physical Society, Vol. 62, No. 8, April 2013

charges, the model addressed here applies only to a de- With the boundary conditions that φ(0) = φc , φ(x0 ) =
vice with a heavily-doped channel. V − Vt and Eq. (3), the solution to Eq. (7) is

⎧
 
⎪
⎨ V + (φc − V ) cosh x qND /εsi Vt , |x| < x0 (8a)
φ=
⎪ qN
⎩ − D (|x| − x0 )2 − E0 (|x| − x0 ) + V − Vt , x0 ≤ |x| ≤ tsi /2 , (8b)
2εsi

where E0 = −(dφ/dx)|x=x0 . Substituting Eq. (8b) into 3. NFB Condition

Eq. (4), we obtain
 
qND qND In the NFB condition, −1 < (φ − V )/Vt < 1 holds in
(∆x)2 + + E0 (∆x) the whole region, and Eq. (1) can be approximated as
2εsi Cox
εsi E0
+ + VG − VF B − V + Vt = 0 , (9) d2 φ qND φ − V
Cox = . (14)
dx 2 εsi Vt
where
The electric potential can be expressed as
∆x = tsi /2 − x0 (10)
 
φ = V + (φc − V ) cosh x qND /εsi Vt . (15)
Because the electric potential has an almost parabolic
form with respect to x, the electric field’s x component,
With the boundary condition in Eq. (4), we obtain
E, can be approximated as E ≈ gx in the region |x| <
x0 , with g being a constant. Then, the electric field’s
2(VG − VF B − V )
x component at x = 0, E0 , can be obtained, by using φc = V +

 . (16)
the finite difference method, E0 = 2[φc − (V − Vt )]/x0 . 1+ εsi
Cox
qND
εsi Vt exp tsi
2
qND
εsi Vt
Expanding E0 at x0 = tsi /2 and then neglecting φc − V ,
we obtain a concise expression for E0 :
If (φ − V )/Vt is larger than unity, the device will be in
4Vt 8Vt accumulation, which is beyond the scope of this study.
E0 ≈ + 2 ∆x . (11)
tsi tsi

Substituting Eq. (11) into Eq. (9), we obtain

III. THRESHOLD VOLTAGE AND DRAIN
√ CURRENT
−B + B 2 − 4AC
∆x = , (12)
2A
1. Threshold Voltage
where A = qND /2εsi +8Vt /t2si , B = qND /Cox +4Vt /tsi +
8εsi Vt /Cox t2si and C = VG −VF B −V +Vt +4εsi Vt /Cox tsi .
φc can be obtained from Eq. (8a) by using φ(x0 ) = The threshold voltage Vth is the gate voltage that
V − Vt : causes the whole channel to be fully depleted. With Eq.
(6) and V = 0, we can obtain its expression as
Vt
φc = V −

  . (13) qND 2 qND

cosh x0 qND /εsi Vt Vth = VF B − Vt − tsi − tsi . (17)
8εsi 2Cox
With the use of Eqs. (11), (12), and (13), the electric The saturation drain voltage Vsat that depletes the drain
potential in the whole region can be obtained with Eq. end can also be obtained by setting V = Vsat in Eq. (6):
(8).
When C = 0, from Eqs. (12) and (10), we find that
qND 2 qND
∆x = 0 and x0 = tsi /2; thus, φ(x0 ) = φs = V −Vt , which Vsat = VG −Vth = VG −VF B +Vt + t + tsi .
is the beginning of a transition from the PD condition to 8εsi si 2Cox
the NFB condition. (18)
Analytical Models for the Electric Potential, Threshold Voltage and · · · – Zhihao Ding et al. -1191-

2. Drain Current
We will obtain the drain current in the linear region
and the subthreshold region separately.
(i) In the linear region, when VG > Vth and Vds < Vsat ,
the drain current can be expressed as
 Vds
W where γ = (1/Cox )(qεsi ND /Vt )1/2 . The first term on
Ids = µef f [−Qn (V )] dV , (19)
L 0
Qn (V ) = −qND tsi + 2Cox (VF B + φs − VG ) . (20)
Qn (V ) is the charge density per unit area. The first term
on the right-hand side (RHS) of Eq. (20) is the negative
charge from the ionized donor atoms. The second term
describes the charge induced in the silicon by the gate
voltage, which may be positive or negative, depending
on the gate bias. W is the channel width, and µef f is
the effective electron mobility. The surface potential can
be obtained by substituting x = tsi /2 into Eqs. (8) and
(16); then, Qn (V ) can be obtained with Eq. (20). There
are two conditions:
(A) For V < C, which corresponds to the NFB condi-
tion, φs can be obtained with Eq. (15), and the expres-
sion for Qn (V ) can be obtained as
γ−1
Qn (V ) = 2Cox (VG − VF B − V ) − qND tsi , (21)
γ+1
the RHS in Eq. (21) is much smaller than qND tsi in the
NFB condition, so we have Qn (V ) ≈ −qND tsi .
(B) For V ≥ C, which corresponds to the PD condi-
tion, we obtain φs from Eq. (8). With Eq. (20), Qn (V )
can be expressed as
Qn (V ) = 2εsi E0 − 2qND x0 . (22)
Substituting Eqs. (21) and (22) into Eq. (19) and finish-
ing the integral, we obtain an analytical expression for
the drain current in the linear region:

  
V =Vds 
W 8εsi Vt 16εsi Vt −BV (B 2 − 4AC)3/2
Ids = µef f qND tsi Vds + H (Vds − V0 ) + H + 2qND + , (23)
L tsi t2si 2A 12A2 V =V0

where V0 = C for C > 0; otherwise, V0 = 0. H = 0 if where xa = (2/k)1/2 . When x > xa , the second term
Vds < V0 ; otherwise, H = 1. on the RHS of Eq. (26) is small enough to be neglected.
For x < xa , we use 1 − (x/xa )(1 − exp(−2)) to approx-
(ii) Now we will obtain the drain current in the sub- imate exp(−kx2 ); the approximation can be justified by
threshold region. In the subthreshold region (VG < Vth ), numerical computations. Therefore, the integral can be
the electron charge density can be expressed as finished:
 tsi /2  tsi /2  xa √
2 2
e−kx dx ≈ e−kx dx ≈ (1+e−2 )/ 2k . (27)
φ−V
Qn (V ) = −2 qND e Vt dx . (24)
0 0 0

Because now the device is fully depleted, φ can be The analytical expression for subthreshold current is
  1 + e−2 
obtained with Eq. (5). Substituting Eq. (24) into Eq.
(19), the subthreshold current is W
−Vds /Vt
Isub = 2qVt ND µef f 1−e √
W
 L 2k
1 − e−Vds /Vt
 
Isub = 2qVt ND µef f
L 1 qND t2si qND tsi
 × exp + VG − VF B + (28)
tsi /2 Vt 8εsi 2Cox
2
× e−kx dx
0

 
1 qND t2si qND tsi
× exp + V G − VF B + , IV. VERIFICATION
Vt 8εsi 2Cox
(25)
In order to verify the models, we compare the analytic
where k = qND /(2εsi Vt ). To obtain an analytical ex- results with the Medici simulations. The doping concen-
pression, we approximate the integral in Eq. (25) as tration ND is 1019 cm−3 , which is a typical value for a
 tsi /2  xa  tsi /2 JL device. The effective electron mobility is set to be
2 2 2 µef f = 85 cm2 /V·s. We use a p+ polysilicon gate, and
e−kx dx = e−kx dx+ e−kx dx . (26)
0 0 xa the corresponding flat-band voltage is VF B = 1.09 V.
-1192-
Fig. 3. (Color online) Surface and center electric potentials
versus gate voltage. W = L = 1 µm.
Fig. 4. Drain current versus drain voltage. Solid lines are
simulation results [7, Fig. 2] while symbols are results of our
analytical model. W = L = 1 µm, tsi = 10 nm, tox = 7 nm,
and ND = 1019 cm−3 .
Figure 3 shows the electric potentials under different
gate biases. An excellent match between the model and
the Medici simulation results is observed. It is noted that
the potential in the channel center, φc , is larger than the
surface potential, φs , which means the electron density
in the channel center is larger than that near the inter-
face; therefore, most of the drain current is contributed
from the transport of electrons located near the center
of the channel. This is an advantage of the device, be-
cause the electrons will now be less scattered by the in-
terface. Figure (4) shows the drain current versus drain
bias. Squares are our analytical model results while solid
lines are the simulation results obtained by Duarte, et al.
[7]. It’s noted that model results fit the simulations.
Figure 5(a) and (b) show drain current versus gate
bias. The model results agree with the Medici simula-
tions well. The drain currents increase with increasing
tsi and/or tox . For a device with a larger tsi , the num-
ber of carriers in the channel is larger, as is the drain
current. As we know, when VG − VF B < 0, the gate bias
will induce positive charges in the channel. For a device
Journal of the Korean Physical Society, Vol. 62, No. 8, April 2013
Fig. 5. (Color online) Drain current versus gate voltage
for (a) different channel thicknesses and (b) different oxide
thicknesses. W = L = 1 µm.
with a larger tox , the oxide capacitance per unit area will
be smaller, and fewer positive charges will be induced in
the channel, which results in an increase in the drain cur-
rent. Figure 5(a) and (b) show that each of the curves
for the drain current has a turning point (TP), to the
left of which the drain current is almost the same, and
to the right of which the current increases very rapidly
with increasing gate bias. The gate voltage correspond-
ing to the TP is none other than the threshold voltage
Vth . Generally speaking, the extrapolated intercept of
the linear portion of the Ids − VG curve with the VG -axis
will give the value of Vth [18]. With this definition, ac-
cording to Fig. 5(a), VGT P = −0.2 V for a device with tsi
= 10 nm and tox = 5 nm, we obtain Vth = −0.28 V from
Eq. (17). Figure 5(b) shows that VGT P = 0.0 V for a
device with tsi = 12 nm and tox = 3 nm, Vth = −0.04 V
is obtained from Eq. (17). Therefore, the analytical re-
sults for Vth match very well with the simulation results
VGT P .
V. CONCLUSIONS
Analytical Models for the Electric Potential, Threshold Voltage and · · · – Zhihao Ding et al.
Analytical models for the channel potential, thresh-
old voltage and drain current of JLDG MOSFETs are
obtained by solving the PE. With the analytical mod-
els, key parameters, such as the threshold voltage and
drain current, can be extracted easily, and one discov-
ers how to choose the gate oxide thickness, silicon body
thickness, and doping concentration to obtain the de-
sired parameters. The device models can be embedded
in computer-aided design tools, to improve the integrated
circuit design.
ACKNOWLEDGMENTS
The precious support from National Natural Sci-
ence Foundation of China (Grant Nos. 61171010 and
61171011) and the support from the State Key Labora-
tory of Application Specific Integrated Circuit and Sys-
tem are appreciated (Grant No. 11MS015).
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