Device Modeling Engineer

About the Company:

Microsemi SOC Product Group is the leading supplier of nonvolatile, low-power programmable
technologies. Our mission is to manage power consumption at both the chip and the system level,
leveraging the industry's lowest power FPGAs and unique mixed-signal FPGAs to offer system designers
a competitive edge. Our Design Center in Hyderabad, India is a growing and vital member of the group.

About this Position:

You will join the pre-silicon characterization and modeling team. You will work closely with silicon design
engineers, software engineers and technology development engineers to develop timing & power
models for use in Microsemi Libero software suite, simulation and synthesis. This can include the
modeling of complex IPs integrated inside the fabric such as CPUs and various analog blocks. Good
communication and presentation skills are required.

Required Skills and Experience:

• Bachelor or Master’s degree in Electrical or Computer Engineering

• 4-6 years of experience in developing timing & power models (NLDM, CCS, etc.) for standard cell
and custom circuits
• In depth knowledge of electrical engineering fundamentals including CMOS device operation
and characteristics, including understanding of advancing modeling techniques
• Hands on experience with simulation using HSPICE, Hsim or Finesim
• Hands on experience to Static Timing analysis at gate level or transistor level with tools such as
PrimeTime or NanoTime
• Experience with scripting tools such as Perl/Shell/Python etc.
• Initiative (self-motivated, self-confident, self-driven, self-learning, always striving for excellence)
• Commitment (responsible, responsive, commit to winning)
• Work quality ("do it right the first time," attention to detail, good documentation)
• Strong analytical and problem-solving skills
• Excellent communication skills

Preferred Skills:

• Exposure to Physical verification using LVS and LPE tools (Synopsys Hercules or Mentor Graphics
Calibre and StarRC-XT)
• Exposure to Standard cell characterization tools such as SiliconSmart
• Working knowledge of SOC and/or FPGA Architectures
• Knowledge of FPGA design synthesis and routing associated with Microsemi (Libero), Xilinx (ISE),
or Altera (Quartus) tools
• Working knowledge of ASIC/FPGA design flows with a focus on timing and power analysis tools