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DESIGN PROCEDURE
✓ Any combinational circuit can be designed by the following steps of design
procedure.
1. The problem is stated.
2. Identify the input variables and output functions.
3. The input and output variables are assigned letter symbols.
4. The truth table is prepared that completely defines the relationship between the
input variables and output functions.
5. The simplified Boolean expression is obtained by any method of minimization—
algebraic method, Karnaugh map method, or tabulation method.
6. A logic diagram is realized from the simplified expression using logic gates.
✓ The output Boolean functions from the truth table are simplified by any available method,
such as algebraic manipulation, the map method, or the tabulation procedure.
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✓ Usually, there will be a variety of simplified expressions from which to choose.
✓ However, in any particular application, certain restrictions, limitations, and criteria will
serve as a guide in the process of choosing a particular algebraic expression.
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Example 9:The main stairway in a block of flats has three switches for controlling
the lights. Switch A is located at the top of the stairs, switch B is located
halfway up the stairs and switch C is positioned at the bottom of the stairs.
Design a logic network to control the lights on the staircase.
Example 10: Design a circuit to enable a chemical additive to be introduced into the fluid
through another inlet only when the temperature is not too cold or too hot and the fluid
is above the high- level sensor.
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Digital logic design
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COMBINATIONAL LOGIC USING NAND AND NOR GATES
NAND Implementation
➢ The NAND gate is said to be a universal gate because any digital system can
be implemented with it.
➢ To facilitate the conversion to NAND logic, it is convenient to use the two
alternate graphic symbols shown in Figure below.
➢ The AND-invert graphic symbol consists of an AND graphic symbol followed by a small
circle.
➢ The invert-OR graphic symbol consists of an OR graphic symbol that is preceded by small
circles in all the inputs.
➢ Either symbol can be used to represent a NAND gate.
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To obtain a multilevel NAND diagram from a Boolean expression, proceed as follows:
a. From the given Boolean expression, draw the logic diagram with AND, OR, and
inverter gates. Assume that both the normal and complement inputs are
available.
b. Convert all AND gates to NAND gates with AND-invert graphic symbols.
c. Convert all OR gates to NAND gates with invert-OR graphic symbols.
d. Check all small circles in the diagram. For every small circle that is not
compensated by another small circle along the same line, insert an inverter
(one-input NAND gate) or complement the input variable.
➢ In general, the number of NAND gates required to implement a Boolean expression
is equal to the number of AND-OR gates except for an occasional inverter.
➢ Example: implement using only NAND gates.
NOR implementation
The two graphic symbols for the NOR gate are shown in Fig. below.
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d. Any small circle that is not compensated by another small circle along the same line
needs an inverter or the complementation of the input variable.
Example: implement the following Boolean function using only NAND gates.
a. F = (AB + E)(C + D)
b. F = A + (B’ + C)(D’ + BE’)
c. F = (CD + E)(A + B’)
d. F = [(C + D)B' + A](B + C')
e. F = (AB' + CD')E + BC(A + B)
f. F = w(x + y + z) + xy;
• Convert the logic diagram the following to a multiple-level NAND and NOR circuit
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Chapter Six
Design of combinational logic circuits
Half-Adder
➢ The half-adder accepts two binary digits on its inputs and produces two binary digits on
its outputs, a sum bit and a carry bit.
➢ The Sout represents the least significant bit of the sum.
➢ The Cout represents the most significant bit of the sum.
➢ The Boolean functions for the two output from the truth table:
𝑆 =𝑥∙𝑦+𝑥∙𝑦 =𝑥⊕𝑦
𝐶 =𝑥∙𝑦
Full-Adder
➢ The full-adder accepts two input bits and an input carry and generates a sum output and
an output carry.
➢ The basic difference between a full-adder and a half-adder is that the full-adder accepts
an input carry.
➢ The Boolean functions for the two outputs from the truth table:
𝑆 =𝑥∙𝑦∙𝑧+𝑥∙𝑦∙𝑧+𝑥⋅𝑦∙𝑧+𝑥∙𝑦∙𝑧 =𝑥⊕𝑦⊕𝑧
𝐶 = 𝑥 ∙ 𝑦 ∙ 𝑧 + 𝑥 ∙ 𝑦 ∙ 𝑧 + 𝑥 ⋅ 𝑦 ∙ 𝑧 + 𝑥 ∙ 𝑦 ∙ 𝑧 = 𝑥 ∙ 𝑦 + (𝑥 ⊕ 𝑦) ∙ 𝑧
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Implementation of Full Adder with Two Half Adders and an OR Gate
2HALFADDER
1-HALF ADDER
Half-Subtractor
➢ A half-subtractor is a combinational circuit that subtracts two bits and produces their
difference. It also has an output to specify if a 1 has been borrowed.
➢ The Boolean functions for the two outputs of the half-subtractor are derived directly from
the truth table:
𝑫=𝑥∙𝑦+𝑥∙𝑦 =𝑥⊕𝑦
𝐵 =𝑥∙𝑦
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Full-Subtractor
➢ A full-subtractor is a combinational circuit that performs a subtraction between
two bits, taking into account that a 1 may have been borrowed by a lower
significant stage.
➢ This circuit has three inputs and two outputs.
➢ Exercise: - design the full-subtractor combinational logic ckt.??
Binary Parallel Adder
➢ A binary parallel adder is a digital circuit that produces the arithmetic sum of two binary
numbers in parallel.
➢ It consists of full-adders connected in a chain, with the output carry from each full
adder connected to the input carry of the next full-adder in the chain.
➢ Figure below shows the interconnection of four full-adder (FA) circuits to provide a 4-bit
binary parallel adder.
➢ An n-bit parallel adder requires n full-adders.
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➢ Example:
a. What are the sum outputs when 111 and 101 are added by the 3-bit parallel
adder?
b. What are the sum outputs when 1110 and 1011 are added by the 4-bit parallel
adder?
c. What are the sum outputs when 011110 and111011 are added by the 5-bit
parallel adder?
Binary Adder-Subtractor
➢ The subtraction of binary numbers can be done most conveniently by means of
complements, as discussed before.
➢ Remember that the subtraction A - B can be done by taking the 2's complement of
B and adding it to A.
➢ The 2's complement can be obtained by taking the 1’s complement and adding
one to the least significant pair of bits.
➢ The addition and subtraction operations can be combined into one circuit
with one common binary adder.
➢ This is done by including an exclusive-OR gate with each full adder.
➢ A 4-bit adder-subtractor circuit is shown in Figure below.
➢ The mode input M controls the operation.
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➢ When M = 0, the circuit is an adder, and when M = 1, the circuit becomes a subtractor.
➢ Each exclusive-OR gate receives input M and one of the inputs of B.
➢ When M = 0, we have 𝐵 ⊕ 0 = 𝐵
➢ When M = 1, we have 𝐵 ⊕ 1 = 𝐵 (to find 2’s complement)
Magnitude Comparator
The comparison of two numbers is an operation that determines if one number is greater than,
less than, or equal to the other number. A magnitude comparator is a combinational circuit that
compares two numbers, A and B, and determines their relative magnitudes.
➢ The outcome of the comparison is specified by three binary variables that
indicate whether A > B, A = B, or A < B.
➢ Algorithm
• 𝐴 = 𝐴3 𝐴2 𝐴1 𝐴0 ; 𝐵 = 𝐵3 𝐵2 𝐵1 𝐵0
• A = B if 𝐴3 = 𝐵3 , 𝐴2 = 𝐵2 , 𝐴1 = 𝐵1 , 𝑎𝑛𝑑 𝐴0 = 𝐵0
• Equality: 𝑥𝑖 = 𝐴𝑖 ⋅ 𝐵𝑖 + 𝐴𝑖 ⋅ 𝐵𝑖
• (𝐴 = 𝐵) = 𝑥3 ⋅ 𝑥2 ∙ 𝑥1 ∙ 𝑥0
• If the corresponding digit of A is 1 and that of B is 0, we conclude that A > B.
• If the corresponding digit of A is 0 and that of B is 1, we have that A < B.
• (𝐴 > 𝐵) = A3 ∙ B3 + 𝑥3 ∙ A2 ∙ B2 + 𝑥3 ⋅ 𝑥2 ∙ A1 ∙ B1 + 𝑥3 ⋅ 𝑥2 ∙ 𝑥1 ∙ A0 ∙ B0
• (𝐴 < 𝐵) = A3 ∙ B3 + 𝑥3 ∙ A2 ∙ B2 + 𝑥3 ⋅ 𝑥2 ∙ A1 ∙ B1 + 𝑥3 ⋅ 𝑥2 ∙ 𝑥1 ∙ A0 ∙ B0
➢ Implementation
➢ 𝑥𝑖 = (𝐴𝑖 ⋅ 𝐵𝑖 + 𝐴𝑖 ⋅ 𝐵𝑖 )
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Decoders
➢ A decoder is a combinational circuit that converts binary information from n input lines
to a maximum of 2n unique output lines.
➢ If the n-bit decoded information has unused or don't-care combinations, the decoder
output will have fewer than 2n output.
➢ The decoders presented here are called n-to-m-line decoders, where m <= 2n.
➢ Their purpose is to generate the 2n (or fewer) minterms of n input variables.
➢ The name decoder is also used in conjunction with some code converters such as a BCD-
to seven segment decoder.
➢ Only one output can be active (high) at any times.
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Combinational Logic Implementation using decoder
➢ A decoder provides the 2n minterms of n input variables. Since any Boolean function can
be expressed in sum of minterms canonical form, one can use a decoder to generate the
minterms and an external OR gate to form the sum.
➢ In this way, any combinational circuit with n inputs and m outputs can be implemented
with an n-to-2n- line decoder and m OR gates.
➢ The procedure for implementing a combinational circuit by means of a decoder and OR
gates requires that the Boolean functions for the circuit be expressed in sum of minterms.
➢ Example:-Implement a full-adder circuit with a decoder and two OR gates.
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S(x, y, z) = ∑ (1, 2, 4, 7)
C(x, y, z) = ∑ (3, 5, 6, 7)
From the truth table of the full-adder, we obtain the functions for this combinational
circuit in sum of minterms:
Example: A combinational circuit is defined by the following three Boolean functions. Design
the circuit with a decoder and external gates.
𝐹1 = 𝑥 ∙ 𝑦 ∙ 𝑧 + 𝑥 ∙ 𝑧
𝐹2 = 𝑥 ∙ 𝑦 ∙ 𝑧 + 𝑥 ∙ 𝑦
𝐹3 = 𝑥 ∙ 𝑦 ∙ 𝑧 + 𝑥 ∙ 𝑦
E A B
D0 D1 D2 D3
0 X X 0 0 0 0
1 0 0 0 0 0
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Example:- Construct a 3-to-8 line decoder with the use of a 2-to-4 line decoder.
Example:- Construct a 4-to-16 line decoder with the use of a 2-to-4 line decoder.
Example:- Construct a 5-to-32 line decoder with the use of a 3-to-8 line decoder.
Encoders
➢ An encoder is a digital circuit that performs the inverse operation of a decoder.
➢ An encoder has 2n (or fewer) input lines and n output lines.
➢ The output lines generate the binary code corresponding to the input value.
➢ It is assumed that only one input has a value of 1 at any given time; otherwise the
circuit has no meaning.
➢ The encoder can be implemented with OR gates whose inputs are determined directly
from the truth table.
➢ These conditions can be expressed by the following output Boolean function
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Multiplexers Or Data Selectors
➢ A digital multiplexer is a combinational circuit that selects binary information from one
of the 2n input channels and transmits to a single output line.
➢ That is why the multiplexers are also called data selectors.
➢ The selection of the particular input channel is controlled by a set of select inputs.
➢ Select binary information from one of many input lines and direct it to a single output
line
➢ 2n input lines, n selection lines and one output line
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➢ As in decoders, multiplexer ICs may have an enable input to control the operation of the
unit.
➢ When the enable input is in a given binary state, the outputs are disabled, and when it
is in the other state (the enable state), the circuit functions as a normal multiplexer.
➢ The enable input (sometimes called strobe) can be used to expand two or more
multiplexer ICs to a digital multiplexer with a larger number of inputs
Example:- Construct a 8-to-1 multiplexer with the use of a 4-to-1 line multiplexer and external
gate.
Example: - Construct a 16-to-1 multiplexer with the use of only a 4-to-1 line multiplexer.
Demultiplexer
➢ A demultiplexer is a circuit that receives information from a single line and directs it to
one of 2n possible output lines.
➢ The selection of a specific output is controlled by the bit combination of n elected lines.
➢ The term “demultiplexer” means one into many.
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Parity Generator And Checker
➢ In the odd-parity method, the value of the parity bit is chosen so that the total
number of 1s in the code group (including the parity bit) is an odd number.
➢ A parity generator is a combination logic system to generate the parity bit at the
transmitting side.
➢ Parity Checker:- The message bits with the parity bit are transmitted to their
destination, where they are applied to a parity checker circuit.
➢ The circuit that checks the parity at the receiver side is called the parity checker.
➢ The parity checker circuit produces a check bit and is very similar to the parity
generator circuit.
➢ If the check bit is 1, then it is assumed that the received data is incorrect. The check
bit will be 0 if the received data is correct.
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Chapter 7
Latches and flip flops
➢ The logic circuits whose outputs at any instant of time depend on the present inputs as
well as on the past outputs are called sequential circuits.
➢ In sequential circuits, the output signals are fed back to the input side. A block diagram
of a sequential circuit is shown in Figure below.
➢ Sequential circuits are broadly classified into two main categories, known as synchronous
or clocked and asynchronous or unclocked sequential circuits, depending on the timing
of their signals.
➢ A synchronous sequential circuit is a system whose behavior can be defined from the
knowledge of its signals at discrete instants of time.
➢ The behavior of an asynchronous sequential circuit depends upon the order in which its
input signals change and can be affected at any instant of time.
Latches
➢ The latch is a type of temporary storage device that has two stable states (bistable) and
is normally placed in a category separate from that of flip-flops.
➢ Latches are similar to flip-flops because they are bistable devices that can reside in either
of two states using a feedback arrangement, in which the outputs are connected back to
the opposite inputs.
➢ The main difference between latches and flip-flops is in the method used for changing
their state.
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The S-R (SET-RESET) Latch
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4. SET = CLEAR = 0. This condition tries to set and clear the latch at the same time
and can produce ambiguous results. It should not be used.
➢ The arrangement, shown in Figure below, is similar to the NAND latch except that the Q
and Q’ output save reversed positions.
➢ The analysis of the operation of the NOR latch can he performed in exactly the same
manner as for the NAND latch.
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latch inputs of Figure below.
Example: - The waveforms of Figure below are applied to the inputs of the NAND latch.
Assume that initially Q = 0, and determine the Q waveform.
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Example:-Determine the Q output waveform if the inputs shown in Figure below
are applied to a gated S-R latch that is initially RESET.
➢ Example:-Determine the Q output waveform if the inputs shown in Figure below are
applied to a gated D latch, which is initially RESET.
EDGE-TRIGGERED FLIP-FLOPS
➢ Flip-flops are synchronous bistable devices.
➢ In this case, the term synchronous means that the output changes state only at a
specified point on the triggering input called the clock (CLK).
➢ An edge-triggered flip-flop changes state either at the positive edge (rising edge) or
at the negative edge (falling edge) of the clock pulse and is sensitive to its inputs
only at this transition of the clock.
➢ Three types of edge-triggered flip-flops are covered in this section: S-R, D, and J-K.
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➢ Although the S-R flip-flop is not available in IC form, it is the basis for the D and J-K flip-
flops.
➢ The logic symbols for all of these flip-flops are shown in Figure 7-13.
➢ Notice that each type can be either positive edge-triggered (no bubble at C input)
or negative edge triggered (bubble at C input).
➢ The key to identifying an edge triggered flip-flOp by its logic symbol is the small
triangle inside the block.
➢ The S and R inputs of the S-R flip-flop are called synchronous inputs because data on these
inputs are transferred to the flip-flop's output only on the triggering edge of the clock
pulse.
➢ When S is HIGH and R is LOW, the Q output goes HIGH on the triggering edge of the clock
pulse, and the flip-flop is SET.
➢ When S is LOW and R is HIGH, the Q output goes LOW on the triggering edge of the clock
pulse, and the flip-flop is RESET
➢ When both S and R are LOW, the output does not change from its Prior state. An invalid
condition exists when both S and R are HIGH.
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➢ This basic operation of a positive edge-triggered flip-flop is illustrated in Figure below,
and Table is the truth table for this type of flip-flop.
➢ Remember, the flip-flop cannot change state except on the triggering edge of a clock
pulse
➢ The operation and truth table for a negative edge-triggered S-R flip-flop are the same as
those for a positive edge-triggered device except that the falling edge of the clock pulse
is the triggering edge.
Example:- Determine the Q and Q’ output waveforms of the flip-flop in Figure below for the S,
R, and CLK inputs in Figure (a). Assume that the positive edge-triggered flip-flop is initially
RESET.
Example:-Determine Q and Q’ for the S and R inputs in Figure above (a) if the flip-
flop is a negative edge-triggered device.
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Internal Circuitry of the Edge-Triggered S-R Flip-Flop
➢ As shown in Figure (a) above, the edge detector produces a narrow positive-going spike
(CLK*) that occurs coincident with the active transition of the CLK input pulse.
➢ The pulse-steering circuit “steers” the spike through to the SET or the CLEAR input of the
latch in accordance with the levels present at S and R.
➢ The internal circuitry of edge detector is look as follow.
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➢ Actually, the D flip-flop and the J-K flip-flop are available in IC form and more widely
used than the S-R type.
➢ However, understanding the S-R is important because both the D and the J-K flip-
flops are derived from the S-R flip-flop.
➢ Notice that the S-R flip-flop differs from the gated S-R latch only in that it has a
pulse transition detector.
➢ As with the gated latch, an invalid condition exists if a clock pulse occurs when both S
and R are HIGH at the same time.
➢ This is the major drawback of the S-R flip-flop.
➢ The operation of a negative edge-triggered device is, of course, the same, except that
triggering occurs on the falling edge of the clock pulse.
➢ Remember, Q follows D at the active or triggering clock edge.
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The Edge-Triggered J-K Flip-Flop
➢ The J-K flip-flop is versatile and is a widely used type of flip-flop.
➢ The functioning of the J-K flip-flop is identical to that of the S-R flip-flop in the SET,
RESET, and no- change conditions of operation.
➢ The difference is that the J-K flip-flop has no invalid state as does the S-R flip-flop.
➢ Figure below shows the basic internal logic for a positive edge-triggered J-K flip-flop.
➢ It differs from the S-R edge-triggered flip-flop in that the Q output is connected back
to the input of gate G2 and the Q’ output is connected back to the input of gate G1.
➢ The two control inputs are labeled J and K in honor of Jack Kilby, who invented the
integrated circuit.
➢ A J-K flip-flop can also be of the negative edge-triggered type, in which case the clock
input is inverted.
Table below summarizes the logical operation of the edge-triggered j-K flip-flop in truth table
form.
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➢ Notice that there is no invalid state as there is with an S-R flip-flop.
➢ The truth table for a negative edge-triggered device is identical except that it is triggered
on the falling edge of the clock pulse.
Example:-The waveforms in Figure below (a) are applied to the J, K, and clock inputs as indicated
(NET).Determine the Q output, assuming that the flip-flop is initially RESET. (Do it for PET J-K FF
also.)
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Example:-The waveforms in Figure below (a) are applied to the flip-flop as shown (PET).
Determine the Q output, starting in the RESET state.
Example:- Interchange the J and K inputs of the above J-K FF and determine the resulting Q
output.
Example:- The waveforms in Figure above(a) are applied to the flip-flop that is NET. Determine
the Q output, starting in the RESET state.
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EXAMPLE: - For the positive edge-triggered J-K flip-flop with preset and clear inputs in Figure
below.
Determine the Q output for the inputs shown in the timing diagram in part (a) if Q is initially
RESET
EXAMPLE:-For the negative edge-triggered J-K flip-flop with preset and clear inputs in Figure
below. Determine the Q output for the inputs shown in the timing diagram below if Q is
initially LOW.
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