2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies

Conventional versus Vedic mathematical method for

Hardware implementation of a multiplier

Parth Mehta, Dhanashri Gawali

Department of Electronic and Telecommunication,
Maharashtra Academy of Engineering, Alandi(D),
Pune, India
smilingparth@ymail.com, Dhanashree.gawali@gmail.com

Suppose we have to multiply 12 by 13

Abstract- Aim of this paper is to compare and prove (i) We multiply the most significant digit 1 of
implementation of normal multiplication and Vedic
multiplicand vertically by most significant digit 1 of the
multiplication (using Urdhva Tiryakbhyam Sutra) on
digital hardware requires same number of multiplication multiplier, get their product 1 and set it down as the most
and addition operations.It makes difference only for mental significant part of the answer
calculations. Few VHDL codes has been developed for this. (ii) We then multiply 1 and 3, and 1 and 2 crosswise, add
All multipliers has been tested for 16X16 multiplications for the two, get 5 as the sum and set it down as the middle
comparison. Test vectors has been given through a text file. part of the answer and
Implementation has been done for the Xilinx FPGA device, (iii) We multiply 2 and 3 vertically, get 6 as their product
Virtex XCV 300 -6PQ240. Various multiplier and put it down as the last the right hand most part of the
implementations such as Array multiplier, Multiplier answer.
Macro, Vedic multiplier with full partitioning, Vedic
Thus 12 x 13 = 156. It bears a simple extendible form in
multiplier using 4 bit macro, multiplier using 4 bit macro,
fully Recursive Vedic multiplier, Vedic multiplier using 8 a similar way for multi-digit multiplication [10].
bit macro have been tested and compared for optimum area
and speed.

Keywords- Vedic mathematics, hardware multiplier.

I. INTRODUCTION

We appreciate the efforts put by Jagadguru Swami Sri

Bharati Krishna Tirthaji Maharaja to introduce Vedic
Mathematics and acknowledge the work of various
people regarding Vedic Mathematics. However
conventional mathematics is an integral part of
engineering education as most engineering system
designs are based on various mathematical approaches.
A multiplier is one of the key hardware blocks in most
digital signal processing systems. With advances in
technology, many researchers have tried to design
multipliers which offer either of the following- high
speed, low power consumption, regularity of layout and
hence less area or even combination of them in
multiplier. The Vedic mathematics approach is totally
different and considered very close to the way a human
mind works.
The multiplication of numbers utilizing
conventional mathematical methods (successive
additions) needs no explanation. The Urdhva –
Tiryagbhyam sutra under vedic mathematics is the
general formula applicable to all cases of multiplication.
The formula being very short and terse, consists of only
one compound word and means “vertically and
crosswise”. The application of this sutra will ensure
simpler means to solve typical multiplication problems
encountered in the engineering environment. A simple
example will suffice to clarify the operation
The process is ascent and a descent, going forward with
the digits on the upper row and coming crossway with
the digits on the lower row.
II. CONVENTIONAL VS. VEDIC MULTIPLICATION
SCHEME
Looking at figure 1(A) below, one can easily realize that
Vedic method probably makes difference for mental
calculations only. For mental calculations it can be
proved more convenient; as we can easily visualize
Vedic multiplication line diagram. If one tries to do
multiplication mentally, in a conventional method, one
would have to remember first row, then second row and
like wise; and then add all of them. In this case it might
be difficult to remember these many numbers at a time.
But in Vedic method, to visualize line diagram and keep
adding two consecutive product terms is easier for
mental calculations. When it is done one need to
memorize only few numbers. So, one may find Vedic
multiplication faster or more convenient for mental
calculations.
However, on digital hardware, it will not result in a new
circuit or strategy. Irrespective of whether you are
thinking it in a Vedic way or conventional way,

978-0-7695-3915-7/09 $26.00 © 2009 IEEE 640

DOI 10.1109/ACT.2009.162

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 performance of the multiplier circuit will ultimately
depend upon how effectively you utilize hardware
resources on which you are implementing multiplier.
From the perspective of digital hardware, there is no
difference in conventional multiplication and Vedic
multiplication.
Fig.1 (A) Multiplication scheme using conventional
method (B) Multiplication scheme using Urdhva –
Tiryagbhyam sutra with line diagram
Both are combinational multipliers requiring
same number of addition and multiplication operations
and hence the same amount of hardware. In both cases
sub-multiplications can be performed in parallel. In fact
it is the same thing, which few people view differently.
No. of Additions in fig. 1(A) := 0 9
No. of Multiplications in fig. 1(A) := 16
No. of Additions in fig. 1(B) := 09
No. of Multiplications in fig. 1(B) : = 16
In [7] author has put good efforts to show, how Vedic
Multiplication gains benefits against conventional
multiplication. But from implementation point of view,
there is no need of added zeros in shifted rows in
conventional multiplication method. This way it shows
conventional multiplication requires more number of
additions. However it is not true.In [6] author has put
good efforts to show, how Vedic Multiplication can be
used for building faster multipliers. Figure 1(A) is
obtained from [6] itself. Author has generated whole
hardware keeping this figure in mind. There is no
difference in both from a circuit designer’s view.
Essentially both are same. Whatever difference one gets
on hardware is just because of the implementation
strategy or coding style. Both will require same number
of sub-operations for performing multiplication
operation.
II. MULTIPLIER IMPLEMENTATION ON DIGITAL
HARDWARE
Few multipliers have been designed using VHDL,
simulated, synthesized and implemented on Xilinx
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FPGA device, Virtex XCV 300 -6PQ240 to prove above
theory is true with practical results. Tool used is Xilinx
ISE 8.1i, for simulations Modelsim and for synthesis
Xilinx Synthesis Tool has been used. Multipliers have
been demonstrated for seven different implementation
styles and compared. All are 16X16 multipliers.
Implementations shown in a, b, c, d are based on Vedic
mathematical method while e, f, g are based on
conventional mathematical method.
[a] Fully partitioned Vedic multiplier: Here, 16*16
multiplication is done as proposed in [1, 4 and 9]; Here
each 4*4 bit sub-multiplication is also done using Vedic
multiplication. For 1 bit sub-multiplication, AND gate
has been used.
[b] Fully partitioned Recursive Vedic multiplier: It is
implemented based on [6]. In [6], author has tried to
show that using Vedic multiplication how 4*4 multiplier
can be used for building 8*8 Multiplier and 8*8
multiplier for 16*16 multiplier and so on. We have
extended author’s work and made recursive VHDL code,
which is generalized code for this kind of multiplication.
Same code can be used for multiplication of 4*4, 8*8,
16*16, 32*32 bits and so on. For 2*2 bit multiplication
separate VHDL code has been written.
[c] Vedic multiplier using 4 bit macro: It is same as that
of [a]; except the fact that here 4*4 bit sub-
multiplication is done using VHDL multiplication
operator “*”.
[d] Vedic Multiplier using 8 bit macro: Here 8*8 bit sub-
multiplication has been done using VHDL operator “*”.
Then it is used for building 16*16 multiplier using Vedic
scheme as shown in [6].
[e] Array multiplier: It is an array multiplier with each
cell operating as one bit multiplier and full adder.
[f] Simple Multiplier: It is 16*16 multiplication done
using VHDL operator “*”.
[g] Multiplier using 4 bit macro: This has been made to
demonstrate and compare the multiplier demonstrated in
[c] for Vedic and conventional multiplication method.
III. TESTING AND RESULTS:
Xilinx ISE 8.1i Tool has been used for design and testing
various multiplier implementations. Design entered in
the form of VHDL .Various simulations are done for
early testing. Input has been given through a text file.
Synthesis reports and simulations (Post-route simulation)
have been done for device Virtex XCV 300 -6PQ240.
For simulation, random test vectors are applied and for
those test vectors, each method’s waveforms are
compared for speed.
A. SIMULATION RESULT
The results shown here are post place & route
simulations for all the above implementations (a to g).
 hardware implementation point of view. Both require
same number of addition and multiplication operations.
Among above all; [D], [E] and [F] implementations are
(a) found to be the most efficient in terms of area and speed.
Hence for FPGA, with latest EDA tools, one may prefer
macros generated by compiler for hardware multiplier.
Among these; area wise [D] is more efficient but speed
(b)
wise it is slower than the other two, since it uses more
granular macros. [B] Utilizes less granular addition
macros than [A]. Hence, [B] is more optimized for area
and speed compare to [A]. The difference in hardware is
(c) due to the implementation strategy or coding style. It is
not due to Vedic mathematical method; fundamentally it
is not a different method from conventional method.
Both require same number of sub-operations for
(d)
performing multiplication operation.

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