SERIAL NON-VOLATILE RAM S-24 Series eee ‘The $-24 Series is a non-volatile CMOS RAM, composed of a CMOS static RAM and a non-volatile electrically erasable and programmable memory (EPROM) to backup the SRAM. The organization is 16-wordx 16-bit (total 256 bits) for the $-24H45 and the S-24S45, and 8-wordx6-bit (lotal 64 bits) for the $-24H30 and the S-24830. ™ Features + 256 bits ‘$-24H45: TTL input. compatible with the X2444 of Xicor, '$-24545: Schmitt input for STORE and RECALL pins +4 bits S-24H30: TTL input $-24830: Schmit input for STORE and RECALL pins + Non-volatile functions ean be controled by software and hardware Etvonvous store protection :=3.5 V All inputs and outputs are compatible with TTL * Except STORE and RECALL pins for the S-24S Series +5:V single power supply (+5 V+ 10%) Low current consumption Operating: 5 mA typ. Standby 1 .A max EPROM store cycles : 105 times EPROM data rotontion: 10 yoare &:pin DIP/SOP package MI Pin Acsignmont Spin DP B-pinsOP Top view Top view =x Er C___ [Chip enabe cds 2D vec STORE of} >RECATT $a sk C2 7 [STORE Veem]?“ 7/Gno ‘i | Seriai cava input ceqjs 6 jn00 DO [Serial data output o Os 6 [Ree sere sini RECALL _| Recoll STORE [store vof4 5 1] eno GND Ground Vcc | Power supply voltage (+5¥) Figure 1SERIAL NON-VOLATILE RAM $:24 Series Block Diagram Non volatile £?PROM mony are Remy Array = store ew, eae | EAT Decoder cares ‘STORE Le Vee tT pw fF et instruction Column } x ge, ee ce Testwcton 1 coumer Decoder Counter CH Figure 2 ™@ Absolute Maximum Ratings Tobie + Parameter symbol | _Ratinas Unit Romer aapphywckege Ve_[ 31660 [ Vv Input voltage Va 3ievere03 |v Output voltage Vour | 0.010, v Storage temperature underbis | Tyg, | S010 #95] —*C ‘Storage temperature Teg 65 to + 150, *c I Recommended Operating Conditions Table 2 Parameter symbol Conditions min. | we. | max. [unit Bower upplyvatage Vee aE ses aR Series An Mighiewtinpuvetage? | Yu [ESERIES [20 | - | ve | HighTevel nputvaioge | Vas | 24SSeries: STORE nd RAUL | 34_[ =| Vee | V Tah Series “AT Inpats Lowlevelinputvoltege1 | va [saiuseres:Alip oo | — | os |v Tow evel apatvanoge® | Vag [2s eres STORE 3 wav Operating temperature [Tow ofS ee @ Pin Capacitance Table 2 (13425, f= LoMtHe, Voce SV) arameter | symbol | __condiions | win. | typ. | max. | unit TapiReapaatance | — Gy [Varo == Output capacitance | equr [vou =0V SS toe ter‘SERIAL NON-VOLATILE RAM S-24 Series DC Electrical Characteristics Table 6 ran acto 08 Voce 1 SV2 10%) Faramecer symbol onatont wan | ye. | Max [unt parang erent consumption | cc [DO UHORERS a Steep crrent ia. fallinpas re Vee SoC andy rent ipa ]ee— GND, Other input Vee [==] 1 oa Sore curert iso =i Tr input eakage cere ig ae eNOTaVeE ae a cS tout leakage current Tio Wau = ND Vez =a a [MOS oy 100A == ary Low level output voltae Vou [pee ee SSH [MOE igu= = 100 wear = = wighlovcutputvokage | Von [OOS Howe = 100m eaif = = tv Sore ADTTOAVOTaGE Von = av Sct width Vivo [S2a5 Sener STORFns RET | 0a f= — Pv Ml Data Hold Characteristics Tables Parameter symbol condone win [tye Max | une Data haTdwotage Vow [eon RAE Veco | 1s | — | 58] v Date holdewp ane Teo so[ = [= Recovery time ‘s 300 [Ss Date hold mode Vee « no Figure $ Data hold timing chartSERIAL NON-VOLATILE RAM S-24 Series AC Electrical Chracteristics Parameter Conditions ERa Series: Alliaputs Input pulse voltage 5-245 Series: CE, Sk and DI 0010 3.0N 5-265 Series: STORE and RECALL | 00t040V [input pulse riseMalltime TOs TO reference voRoge 13V) [outputioad Ti oop 1. Data input/output timing Table 7 Parameter symbol| Min. | typ. | Max | unit Sk frequency a SK high level pulse width foe [04 | — | — fs SK low level pulse width twa [04 | — [| — | Input data setup time tos | 04 | — | — |e input data hold time tou [0.08 [= [= [Skoatavanatme | tw] = 1 = 103s] fSutput disable ume re a fetsetup ime a [eEhold time teen [04 [= — [a Hid data Huz + CE mustbe kept high during instructions. + When SK rises after selecting CE, the first 1 iz taken into DI input and the fetch of an instruction starts, All previous isignored. Figure 4 Control data timing 2. Recall Cycle Table & Parameter symbol| min. | Typ. Unit Recall eycle time tace_| 2500 | — 7s Recall pulse width tae | 300_[ = =] Recall disable time tar | | = 300 Recall eoble Tine tore [0] = Recall data aceezs time ae [800s * Recoll times ore net limited ace aL T° Undefined data — | Valid date 20 Figure 5 Hardware recall‘SERIAL NON-VOLATILE RAM 8-24 Seri 2. Store Cyole Table 9 Parameter symbol[ win. | tye. [ max | uni sore ume = Store pulse wih ‘se [oe = — tore disable time = =e Store times 10° ines Data retention : 10 years ‘ ia. STORE oS} ae Figure 6 Hardware store Instruction Set Table 10 Format Inetruction symboi| Forma Function rte arabe atch revet_| WROS | —THOXxOUD [Reset wate erate atch (DTabTe wile and Hore] [White enebieTaichset— | WREN | 11000100 [Set write enable lath Enable write and store) Read READ_|-TAAAATIX_ [Read data from RAM address AAAA wte Waite | 1AaAa01t [Write data nto RAM addrecs AAAA Store STO | 1}00XK00T |store RAM datain EPROM Recall ACL | “100X103 [Recall EZPROM data into RAM Sleep SLEEP | DOOXDION Enter sleep mode X: Dovtere AA: Adgressbit + The format is composed ota start bi), adéress(Ay AzA Aa) and an instruction) + AdGrest Ag °K" forthe 2H and the 24530 1SSERIAL NON-VOLATILE RAM $:24 Series Operation 1. Internal latches: ‘The S-24 Series has two latches, one of which controls write operation of the SRAM, and both of which control permission/inhibition of store operation of the EPROM, 4.1 Previous recall latch ‘The previous recall latch controls permission/inhibtion of store operation of EPROM. It is reset when the ower is turned on, and it inhibits store operation of the EPROM. It is set by executing the software recall instruction or hardware recall, and it permits store operation of the E2PROM. 1.2. Write enabie latch The write enable latch controls permission/inhibition of both store operation of the E2PROM and write operation of the SRAM. It Is reset when thé power is turned on or by executing WADS instruction, and it inhibits both store operation of the E2PROM and write operation of the SRAM. It ie set by executing WREN instruction, and it permits hath store oparation of the F2PROM and write operation of the SRAM. When store operation of the E2PROM is completed, the wile enable latch is automatically reset. ‘Theretore, in order to execute store operation again, it is necessary to execute WHEN instructon and to set the write enable latch, 1.3. Both the provioue recall latch and the write enable latch must be set for permission of store operation. ee provion [Rese ation] 280M recall a Power-on >—feset_| ba) control Tea tt es sua Cees a = eee feet onion Figure 7 Internal latch 2.SRAM mode 21 Read The data Is read from te SRAM through READ Insvwction. inputting a start bit, address and Instruction code causes data output on DO. In the S24 Series, a bidirectional serial interface can be made by connecting Dl and DO. See Figures 8 and 9 for the timing. 2.2 Write The dala is willen into Uie SRAM through WRITE instruction. Input dal on DI after a start bit, address and instruction code, See Figures 10 and 11 for the timing. The write enable latch must be set betore WRITE instruction,SERIAL NON-VOLATILE RAM $-24 Series 3. F2PROM mada Data is input to and output from the E2PROM through the SRAM. 3.41 Store ‘The SMAM data is copied into the E2PROM when STO instruction io excouted or ETORE goce low. The ‘SRAM data does not change after STO instruction. Since the data slored in the E2PROM is non-volatile, i is retained even If power is turned of. In the case that store operation is performed wnile data is output on DO and during read operation of the SRAM, DO becomes high-impedance. During store operation, all ‘ther operations are inhibited Both the previous recall latch and the write enable latch must be set before store operation. 32 Recall ‘The E7PROM data ie recopied into the SRAM when RECALL goes low or RCL instruction is executed. In the case that recall operation is performed while data is output on DO and during read operation of SRAM, D0 becomes high-impedance. During recall operation, all otner operations are inhibited, |. Sleep mode Executing SLEEP instruction disables operation of the SRAM. The F2PROM data is retained. The sleep mode ‘ean be roleaced by recall oporation. Since the 8-24 Series is in standby status and the current consumption is low when CE is at GND level, itis not necessary to execute SLEEP instruction in order to reduce the current consumption while not operating. 5, Operation ting After CE rose, when SK clock rises and DI goes high, a start bit is recognized and the fetch of an instruction starts, Daal otha to I terminal a th ise of SK clock 51 Read DO's output a the fal of ho Btn cock, and others are output at th ise of th clock a OB TOIT OT TS D0; 4 BOT XEN XE XENI Xo XK Donteare Figure 8 Read mode timing(S-24H45, $-24845) Do. at {20 X VGN YE NENG YE} X : Don'teare Figure 9 Read mode timing(S-24H30, $-24830)SERIAL NON-VOLATILE RAM $-24 Series 5.2 Write Data is written to the SRAM at the rise of SK clock. 0 AE TM RADDA GG Figure 10 Write mode timing(S-24H45, S-24845) Figure 11 Write mode timing(S-24H190, $-24S30) 8.8 Other operation modes CE must be low between instructions, Figure 12, Other operation modes timingSERIAL NON-VOLATILE RAM $-24 Series MH Interface with CPU with Serial Port + When SK and DI are high at the rise of CE, high of DI io regarded a9 a start bit and the clock 1 generates and the high of Dl ie fetched. When DI ic low, DI ie not rogarded ac a etart bit until DI becomes high at the rise of Sk. + Affler power on of after an instruction is pertormed, LI must be set 1 for preparing the fetch of the start bit of the next instruction, Figures 13 t0 17 show the timings of write/read, and other operation modes, and interfacing examples are shown in Figures 18 to 20. adnate tec Figure 14 Read mode timing(S-241190, $-24530) ote XXX A/T XD XXX XO OX XXX DEE Figure 15 Write mode timing(S-24H45, S.24845) Figure 18 Write mode timing(S-24H30, $-24830) Execute instruction ce sk o Dummy bit: Recommended tobe st to 1 for fetching the YON Hon biof nent instruction * Figure 17. Other operation mode timingSERIAL NON-VOLATILE RAM $:24 Series Interfacing example 1 : With Intel 8051. 8052 raf Veo =H “TEL Figure 18 Th Interfacing example ? : With other CPU When the S-24 Series is connected 10 GPU otner than intel 8091 and 8052, delay circult should be set by a capacitor and a resistor at DO terminal (Figure 19), delaying the signal more than 200 ns as in Figure 20 10 assure the data hold time (Igxy) and the data setup time (Ipsy) of GPU. | lee vee | San foe pe 1 Figure 18 I< ts« sk wo DO validdote XX OOX_ validate (without delay) 0 “Valid data (withdelay) Figure 20 The maximum speed of the SK clock (Isxmax) is expressed by the following formula: 1 1 Syquax> > > TGR Tox” Tosu Tony roma For example, when interfacing wilh NEC .PD7SXX series, Igxwax Is as follows: pPOTSXX corioe tosu + 200 ne min tony + 450 ns min. 5-26 Senes —tpp_: UNS min. , 300 ns max, 1 1x 108 1 fees ee «osaune Ts" HOSS SOO * heyy 7 SPH 10IM Dimensions (Unit:mm) SERIAL NON-VOLATILE RAM $-24 Serles 1. Spin DIP 93(96max.) dood 6s i @ 10 is po i ET thos Tesmex [Vet fanin asf | [loszor Figure 21 2. Bpin SOP. | Ordering Information 3.05.15 max), % 3 BAA A [| al 59 gaso4 [fom 0:35 705 Figure 22 S-24XXK XX XK Package Temperature Memory size Input level toss FU 8s = 105 times. DIP soP 40°C w 85°C. 64-bit 256-bit All pins TTL compatible ‘Schmitt input for STORE and RECALL "SERIAL NON-VOLATILE RAM 5:24 Series mM Characteristics 1. DC Characteristics 1.1 Operating current consumption loc — ‘Ambient temperatureTa ° Vece55V 4 lee (ma) 2 o -40 a5 racy 1.8 Operating current consumption log — ‘SK frequency fsk T Ta=25'c ® Vece55V 4 1‘ hee (ma) 2 To T00k 1M fox (Ha) 41.5 Store current consumption Isto — ‘Ambient temperature Ta ma) | L | ecessv Tare) 1.7 Store inhibition voltage Vw — ‘Ambient temperature Ta i “ ;— racy 12 1.2 Operating current consumption loc — Power supply voltage Voc Tex-a0re (wt) Vee 4.4Sieopletandby curront consumption Igi/iga — Ambient temperature Ta 10 ug WA) og ° —=! 40 85 Tare) 1.8 Store current consumption Isto — Power supply vollage Voc, Ta=-40°C Iso 4 (ma) 4 aaa) ats 6 Veetw)‘SERIAL NON-VOLATILE RAM $-24 Serles 1.8 nput voltage Vin — Ambient temperature Ta 1.8 Input voltage Viy — Power supply voltage Veo ‘S-24H Series : All inputs 'S-26H Series All nputs 8.248 Sori: 8-245 Sories : CE, SK and Ol T Vec=45V Taxes 20 20 Yi Vw “ wo 1s 18 + 40 35 os 6 Taco Veet) "-10lnpit votage Vv — Ambient temperature Te 1.11 Input voltage Vin — Power supply voltage Voc 'S:24S Series : STORE and RECALL 'S-245 Serles : STORE ang RECALL 3 3 J Vis vi Vy ? vw “ Yas wo 1 — 1 Vec=45V O00 35 Se Tec vee) 1.12 High level output current lo — 1.13Low lovel output current lo. — "Ambient temperature Ta “Ambient temperature Ta Veenasv o Vou= 2.6, wh low - ~~] fou, (mA) 5 (mA) 5 0 es ° 3s Tare) = Tare) 1.14 High level oulput voltage Vou — 1.15 Low level output voltage Vo, — ‘Ambient temperature Ta “Ambient temperature Ta 4s 06 Vee= Vou You 3, M40 ae | o2 35 20 rc <4 0 5 Tac) race) 13SERIAL NON-VOLATILE RAM 4 Series 2. AC Charactoristios 2.1 SK pulse width tsx — Ambiant temperature Ta 10 Vec#45V %« w os oan 85 2.3 Input data setup time tos — ‘Ambient temperature Ta 100 vec#45V os (08) 59 ora 0 cc Taco) 2.5 SK data valid time teo — Ambient temperature Ta 5 200 two ae el 100 ° 400 35 recta 2.7 Recall cycle time taco — ‘Ambient temperature Ta Veen 45V 10 ace || _ os a 14 2.2SK pulse width tsx — Power supply valtage Veo 10 154 ws os ° * 5 6 Vee 2.4 Input data hold time tow — “Ambient temperature Ta 20 ———}} Vec=45V oH (3) 49 ° 05 aro 2.6 Recall pulse width tacp — ‘Ambient temperature Ta 100 Vec=45V ‘ace Oy 28Siore time ten — ‘Ambient temperature Ta Vees45V 10 ter (os)SERIAL NON-VOLATILE RAM §-24 Series 3. Rewiling Characteristics TT Tan2ee ‘ minimum voltage 4 “ + 2 10 402 103 108 108 108 store cycle (times) ‘¢ Th information herein is subject to change without notice. '© Sciko Inevuments Ine. is not responsible for any problems caused hy circuits or other diagrams described herein whose Industial properivs, patents oF other rights belong to third parte. Tho application circuit examples explain typical applications ofthe products, and do not guarantee any mass-production design. © When the products described herein include Strategic Products (or sorvice) subject to COCOM regulations, they should not be exported without authrization from the appropiate governmental authites. 1¢ The products desorbed herein cannot be used as part of any device or equipment which influences the human body, such as physical exercise equipment or medical equipment, without prior writen permission of Seiko Instruments Inc. 15