MANIPAL INSTITUTE OF TECHNOLOGY

Manipal University, Manipal

Karnataka -576104

COURSE PLAN

Department : Dept. of E&C Engg.

Course Name & code : Digital System Design using Verilog
Semester & branch : IV,ECE 2204
Name of the faculty : SK,SKT,RS,SD
No of contact hours/week: 3 hours/ week

ASSESSMENT PLAN:

1. In Semester Assessments - 50 %
2 Tests each of 15 marks
 Written tests :

 Assignment/Quiz/ : 3 Quizes. 2 quizes of 6 marks each and last quiz is of 8 marks.

Seminar

2. End Semester Examination - 50 %

 Written examination of 3 hours duration (Max. Marks: 50 )

Portions for Assignment/Quiz/Seminar etc.…

Sl. no. Topics/Lessons
1 L0-L14

2 Open Book Test

3 Group activity/Mini-Project

4
5
Portions for Sessional Test
Test no. Topics/Lessons
1 L0-L14

2 L15-L28

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 Course Outcomes (COs)

At the end of this course, the student should be able to:

No. of Program
Contact Outcomes (POs)
Hours addressed
CO1: Describe the digital implementation styles and design flow. 1,2,5,6,7,8,9,10
05

CO2: Discuss the architectural features and digital circuit implementation using FPGAs and 1,2,5,6,7,8,9,10
CPLDs. 22

CO3: Discuss various testing methods and DFT methodologies employed in digital design. 1,2,5,6,7,8,9,10
04

CO4: Write and analyze the Verilog code for given design using behavioral, switch level, 1,2,5,6,7,8,9,10
04
data flow and structural modeling styles.
CO5: Write the Verilog code for system level building blocks. 1,2,3,4,5,6,7,8,9,10
09

CO6: 1,2,5,6,7,8,9,10
05

Course Plan
Course
L. No. Topics Outcome
Addressed
L0 Introduction to COs

L1 Introduction, Design styles: Full-custom, Semi-custom

L2 Programmable ASICs : CPLDs

L3 MPGAs, FPGAs, Y- chart

L4 Design flow, Logic synthesis

L5 Architecture of ACTEL FPGA logic families

L6 Architecture of ACTEL FPGA logic families

L7 Architecture of XILINX FPGA logic families

L8 Architecture of XILINX FPGA logic families

L9 Architecture of ALTERA logic families

L 10 Architecture of ALTERA logic families

L11 Logic module

L12 Switching technology

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 Course
L. No. Topics Outcome
Addressed
L 13 Implementation of combinational and sequential circuits using FPGAs: Shannon’s decomposition.

L 14 Implementation of combinational and sequential circuits using FPGAs: Shannon’s decomposition.

L 15 Fault models, path sensitization

L16 D algorithm

L 17 Boolean difference

L18 PODEM

L19 ITG

L 20 Testability: Observability and Controllability

L 21 DFT methods: Ad-hoc and scan path

L 22 DFT methods: Ad-hoc and scan path

L23 Introduction to HDL, VHDL versus Verilog, Verilog description of combinational circuits

L 24 Verilog modules

L25 Verilog assignments, Procedural assignments

L 26 Modeling flip-flops using always block

L27 Always blocks using event control statements

L 28 Delays in Verilog

L29 Compilation, simulation, and synthesis of Verilog code

L 30 Verilog data types

L31 Verilog operators

L32 Simple synthesis examples

L33 Verilog models for multiplexers

L 34 Modeling registers and counters using Verilog always statements

L 35 Behavioral, switch level, data flow and structural models.

L 36 Constants. Arrays. Loops in Verilog

L 37 Testing Verilog model. Verilog functions

L38 Verilog tasks, Named association. Generate statements

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 Course
L. No. Topics Outcome
Addressed
L 39 System level design of real-world examples using Verilog : LED displays, ALU

L40 System level design of real-world examples using Verilog : UART, GPIO

L41

L42

L43

L44

L45

L46

L47

L48

References:
1. M. J. S. Smith, Application Specific ICs, Pearson 1997.

2. Charles Roth, Lizy Kurian John, Byeong Kil Lee, Digital System Design Using Verilog, 1st Edition, 2016.

3. Michael D. Ciletti, Advanced Digital Design with the Verilog HDL, Prentice Hall Publishing, Second edition,
2010.
4. Stephen. Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, TMH, 2013.

5. Parag K. Lala, Fault tolerant and Fault testable hardware design, BS Publication, 1990.

6.

7.

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 Submitted by:

(Signature of the faculty)

Date:

Approved by:

(Signature of HOD)

Date:

FACULTY MEMBERS TEACHING THE COURSE (IF MULTIPLE SECTIONS EXIST):

FACULTY SECTION FACULTY SECTION

Shounak De A
Vinod Kumar Joshi B
S.K. Tiwari C
D.V.Kamath D

*********

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