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AIM:
To design and implement the following sequential circuits using Verilog HDL
and verify using the testbench
1. Counters
2. Finite State Machine
APPARATUS REQUIRED:
THEORY:
Counters
stored by the state memory. The next state of the machine is a function of the state
vector in Moore; function of state vector and the inputs in Mealy.
PROCEDURE:
1. Start Xilinx ISE 14.3, click on “CREATE A NEW PROJECT” and then click on
Next.
2. Select your working directory, give the name of the project, then click on
“NEXT”.
3. Select the device family (Spartan 3E), Device (XC3S250E), package (PQ208),
Speed grade (4), Synthesis tool (XST [VHDL/VERILOG]), simulator (ISim) and
preferred language (Verilog) from the available device list, and then click
“NEXT” and click FINISH.
4. Write the HDL code and be careful to give the entity name the same as project
name.
5. In the design window change into simulation and double click behavioral
check syntax.
6. If the HDL code is error free a green check mark will be shown on the
behavioral check syntax.
7. Select simulation then double click on “Simulate Behavioral Model” (here we
can change the level of abstraction. i.e. structural/behavioral/dataflow/switch
level)
8. If there is zero error a new window will be shown. Apply the desired input as
1’s and 0’s and check whether the outputs are correct or not in the output
waveform.
9. Create a new verilog test fixture and give the various input constraints and
save the file and check if any errors are present.
10. Simulate the testbench and analyze the output waveform.
COUNTER
Logic Diagram:
outp <= 0;
end
3'b100: begin
state <= 2'b00;
outp <= 0;
end
3'b101: begin
state <= 2'b11;
outp <= 0;
end
3'b110: begin
state <= 2'b10;
outp <= 0;
end
3'b111: begin
state <= 2'b01;
outp <= 1;
end
endcase
end
end
endmodule
RESULT:
The Sequential circuits were designed and, HDL codes were written and verified
using Testbench circuits