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Course Curriculum
Verilog
HDL
LABS
Contents
• Verilog HDL Labs
Lab 1 - Gate Level Models
2-input “and” gate
1-bit half-adder
1-bit full-adder using half-adder as module instance
1-bit full-adder using gates alone
1-bit half-subtractor
1-bit full-subtractor
2 x 1 mux
4 x 1 mux
Lab 2 - Data Flow Models
1-bit half-adder with vcd test-bench
1-bit full-adder using half-adder as module instance
2 to 4 decoder
2 x 1 mux using conditional operator
Verilog HDL Labs 2
www.dkoplabs.com
Contents
• Verilog HDL Labs
Lab 2 - Data Flow Modeling contd.
4 x 1 mux using conditional operator
wand/triand net verification
wor/trior net verification
wire/tri net verification
Lab 3 – Timing Delays Modeling
rise, fall, min, typ, max delays verification using gate delays
in a 1-bit full-adder model
for the given circuit with wire and gate delays and with
model schematic, verilog description and input waveform
hand draw the waveform for the outputs
for the circuit in previous lab model the h/w and write the
test-bench and verify hand drawn waveform with waveform
generated by this model
Verilog HDL Labs 3
www.dkoplabs.com
Contents
• Verilog HDL Labs
Lab 4 - Behavioral Level Models
writing a clock generator for a given behavior
3 more different clock generators
sequential vs. parallel execution – begin-end, fork-join
2 x 1 mux using if-else, 4 x 1 using case statements
blocking, non-blocking model creation for a given schematic
D-Latch, D-Flip-Flop
4-bit up-counter
4-bit right shift circular register
BCD to 7 segment code converter
convert 4-bit up-counter to generic up-counter using
parameter, defparam usage to create an 8-bit up-counter
Contents
• Verilog HDL Labs
Lab 4 - Behavioral Level Models
write a function to multiply two numbers and create a
model to call it and verify the results
write a task that calculates number of 1’s in an input bit
stream and create a model to call this task and verify the
results
create an FSM for 1101 sequence detector
create an FSM for 10 GB Ethernet module state machine
create the given ALU using various modeling styles
Lab 1
Gate Level Modeling
LAB 1
Gate Level Modeling
• Design 1 – AND GATE – use force command for validation
A B O
0 0 0
1 0 0
0 1 0
1 1 1
LAB 1
Gate Level Modeling
• Design 2 – HALF ADDER – Write a test-bench also
A B S C
0 0 0 0
1 0 1 0
0 1 1 0
1 1 0 1
LAB 1
Gate Level Modeling
• Design 3 – FULL ADDER – Use concept of Instantiation (use half-
adder from previous lab) – Write a test-bench also
LAB 1
Gate Level Modeling
• Design 4 – FULL ADDER – Write a test-bench also
A B Cin Cout S
0 0 0 0 0
1 0 0 0 1
0 1 0 0 1
1 1 0 1 0
0 0 1 0 1
1 0 1 1 0
0 1 1 1 0
1 1 1 1 1
LAB 1
Gate Level Modeling
• Design 5 - HALF SUBTRACTOR – Write a test-bench also
A B DIFF BORROW
0 0 0 0
1 0 1 0
0 1 1 1
1 1 0 0
LAB 1
Gate Level Modeling
• Design 6 - FULL SUBTRACTOR – Write a test-bench also
A B BOR D BOR
(IN) (OUT)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 0
0 1 1 0 0
1 0 0 1 1
1 0 1 0 1
1 1 0 0 0
1 1 1 1 1
LAB 1
Gate Level Modeling
• Design 7 - MULTIPLEXOR 2x1 – Write a test-bench also
A B S C
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
LAB 1
Gate Level Modeling
• Design 8 - MULTIPLEXOR 4x1 – Write a test-bench also
S0 S1 X3 X2 X1 X0 y
0 0 x x x 0 0
0 0 x x x 1 1
0 1 x x 0 x 0
0 1 x x 1 x 1
1 0 x 0 x x 0
1 0 x 1 x x 1
1 1 0 x x x 0
1 1 1 x x x 1
Lab 2
Data Flow Modeling
LAB 2
Data Flow Modeling
• Design 1 – HALF ADDER – Write a VCD test-bench
a b s c
0 0 0 0
1 0 1 0
0 1 1 0
1 1 0 1
LAB 2
Data Flow Modeling
• Design 2 – FULL ADDER – use half-adder from previous lab and
use its instantiation - Write a test-bench also
LAB 2
Data Flow Modeling
• Design 3 – Vectors - 2 to 4 decoder – Write a test-bench also
LAB 2
Data Flow Modeling
• Design 4 - MULTIPLEXOR 2x1 – use ? : operator – Write a test-
bench also
A B S C
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
LAB 2
Data Flow Modeling
• Design 5 - MULTIPLEXOR 4x1 – use ? : operator – Write a test-
bench also
S0 S1 X3 X2 X1 X0 y
0 0 x x x 0 0
0 0 x x x 1 1
0 1 x x 0 x 0
0 1 x x 1 x 1
1 0 x 0 x x 0
1 0 x 1 x x 1
1 1 0 x x x 0
1 1 1 x x x 1
LAB 2
Data Flow Modeling
• Design 6 – wor/trior net
• use wor net declaration and write a test bench to verify the
following table
• use multiple drivers
wor/ 0 1 x z
trior
0 0 1 x 0
1 1 1 1 1
x x 1 x x
z 0 1 x z
LAB 2
Data Flow Modeling
• Design 7 – wand/triand net
• use wand net declaration and write a test bench to verify the
following table
• use multiple drivers
wand/ 0 1 x z
triand
0 0 0 0 0
1 0 1 x 1
x 0 x x x
z 0 1 x z
LAB 2
Data Flow Modeling
• Design 8 – wire/tri net
• use tri net declaration and write a test bench to verify the
following table
• use multiple drivers
wire/tri 0 1 x z
0 0 x x 0
1 x 1 x 1
x x x x x
z 0 1 x z
Lab 3
Timing Delays
LAB 3
Timing Delays
• Design 1 - Run and understand the following design with gate delays
(rise, fall, turn-off, min:typ:max). Try selecting min, max delays also.
LAB 3
Timing Delays
• Design 2 – Given the following circuit with its gate level description
along with Net + Gate delays and the waveform for inputs x1 and x2,
hand draw the waveform for the outputs buf_out, y_inertial, y_tran
including all the delays mentioned (gate, wire/net)
wire #2 y_tran;
and #3 and1(y_tran, x1, x2);
buf #1 buf1(buf_out, y_tran);
and #3 and2(y_inertial, x1, x2);
LAB 3
Timing Delays
• Design 3 - Write the model and the test-bench for the previous Lab
and verify your hand written waveform with the waveform generated
by the tool. Do they match?
wire #2 y_tran;
and #3 and1(y_tran, x1, x2);
buf #1 buf1(buf_out, y_tran);
and #3 and2(y_inertial, x1, x2);
Lab 4
Behavioral Modeling
LAB 4
Behavioral Modeling
• Design 1 - Given the following table write a clock generator using
initial and always blocks in a test-bench
Time Statement
(in ns) Executed
0 clk = 1’b0
25 clk = ~clk
50 clk = ~clk
75 clk = ~clk
100 $finish
LAB 4
Behavioral Modeling
• Design 2 - Try following different models of clock generator
• Can you create more clock generators on your own?
module clkgen(output reg clock);
initial begin
#5 clock = 1;
forever #50 clock = ~clock; module clkgen_25_75_dc;
end reg clk;
endmodule initial begin
clk = 0;
module clkgen_forever;
end
reg clk;
always begin
initial begin
#25 clk = 0;
clk = 0;
#75 clk = 1;
end
always begin end
endmodule
#10 clk = ~clk;
end
endmodule
Verilog HDL Labs 30
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LAB 4
Behavioral Modeling
• Design 3 - Sequential vs. parallel execution
• Use following verilog HDL code snippets to write a test-bench
and understand the execution of sequential vs. parallel
statements with absolute delays
reg x, y;
reg x, y; initial
initial fork
begin x = 1’b0;
x = 1’b0; //execute at t = 0 y = 1’b0;
y = 1’b1; #10 x = 1’b1;
#10 x = 1’b1; //executes at t = 10 #20 y = 1’b0;
#15 y = 1’b0;//executes at t = 25 #20 x = 1’b0;
end #40 y = 1’b1;
join
LAB 4
Behavioral Modeling
• Design 4 - Use if else construct to model 2x1 and case construct to
model 4x1 multiplexor
LAB 4
Behavioral Modeling
• Design 5 – Blocking vs. Non-Blocking
• Part A - Study the behavior of blocking vs. non blocking
assignment by creating two different TB for the given initial blocks
• Part B - Write two different behavioral models for the circuit
shown – one using blocking style, other using non blocking style –
use a synthesis tool to see the logic interpretation
LAB 4
Behavioral Modeling
• Design 6 - Model a D-latch and a D-flip flop in behavioral style. Study
and understand the usage of clock in both the cases?
rst en rst
d q d q
clk clk
LAB 4
Behavioral Modeling
• Design 7 - write a 4 bit up counter model in behavioral style
• remember to write the clock generator in TB not in DUT
• remember to initialize the value of output count
LAB 4
Behavioral Modeling
• Design 8 - Given the following diagram write a behavioral model
which uses shift operator. Suggest a suitable name for this h/w?
reset
D Q D Q D Q D Q
clk
Verilog HDL Labs 36
www.dkoplabs.com
LAB 4
Behavioral Modeling
• Design 9 - Write behavioral model for BCD to 7 segment code
converter using case statement
w3 w2 w1 w0 a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
LAB 4
Behavioral Modeling
• Design 10 – Change the 4 bit up counter developed in lab 7 to a
generic counter by use of parameter definition.
• Make use of defparam keyword to create an 8 bit up counter from
this counter.
LAB 4
Behavioral Modeling
• Design 11 - Write a function for the multiplier shown in the diagram
and develop behavioral model for the full diagram making use of this
function in this model. Check if the correctness of multiplied output.
LAB 4
Behavioral Modeling
• Design 12 - Write a task to count the number of 1’s in an 8 bit input
number e.g. if the data input is 1100110 then the output will be count
4. Call it to check the correctness of the output.
LAB 4
Behavioral Modeling
• Design 13 – The following FSM Mealy machine detects 1101
sequence. Write a behavioral model for it along with a test-bench.
Try to count the number of 1101 sequences detected in a given set of
input bits stream.
LAB 4
Behavioral Modeling
• Design 14 - Write a behavioral model for the following FSM