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5 4 3 2 1

fpga2 proto5
serial SW8
proto5_sel# cardsel# 1 SW DPDT
proto5_[39..0] TDI 2
CTS CTS proto5_[39..0] Apcard[39..0] Apex_TDI
TXD TXD proto5_Vee Vee 3
RXD RXD CLK_Apex4 Apex JTAG bypass switch
RTS RTS clk1 4
pll clk_in_proto5 clk2 5
CLK_OSC1 6 Apex_TDO
serial port DATA[31..0] OSC
CLK_Apex CLK_Apex0 reset#
D CLK_Apex_in CLK_Apex0 CLK_Apex1 sram A[19..1] reset# SW9 D
CLK_Apex1 1 SW DPDT
CLK_Apex2 protocard - 5V 2
CLK_Apex2 CLK_Apex3 A1/A17 A[16..2] A1/A17 protocard CPLD_TDI
CLK_Apex3 A[16..2] 3
CLK_Apex4 D[31..0]
+3.3V Y1 CLK_Apex4 D[31..0] proto_sel# proto[39..0] cardsel# CPLD JTAG bypass switch
proto[39..0] protoIO[39..0] 4
4 3 CLK_OSC0 5
VCC OUT CLK_OSC_in CLK_OSC0 CLK_OSC1 WE# BE[3..0]# sram_WE_n CLK_Apex3 CPLD_TDO
CLK_OSC1 BE[3..0]# sram_BE[3..0]_n clk1 6
CLK_OSC2
CLK_OSC2 CLK_OSC3 OE# OE_n clk_in_proto CLK_OSC2 clk2 SW10
1 NC GND 2 CLK_OSC3 OSC 1 SW DPDT
reset# 2
CLK_OSC4 sram0_CS# sram0_CS_n reset# PMC_TDI
33MHz sram1_CS# sram1_CS_n 3
pll protocard
sram sdram2 4 CPLD JTAG bypass switch
flash sdram_a[13..0] TDO 5
sdram_a[13..0] sdram_dq[63..0] sdram_a[13..0] PMC_TDO
flash_RDY/BSY# sdram_dq[63..0] sdram_dq[63..0] 6
flash_byte# sdram_ba[1..0]
SW1 flash_BYTE# flash_BYTE_n sdram_ba[1..0] sdram_dqm[7..0] sdram_ba[1..0]
user_sw0 flash_OE# sdram_dqm[7..0] sdram_dqm[7..0]
9 8 flash_R/W# flash_WE_n sdram_cas_n sdram_CAS_n
10 7 user_sw1
user_sw2 flash_CS# flash_CS_n sdram_ras_n sdram_RAS_n
11 6 sdram_we_n sdram_WE_n
12 5 user_sw3 A[19..1]
user_sw4 A[19..1] sdram_s0_n sdram_S0_n
13 4 sdram_s1_n sdram_S1_n
14 3 user_sw5 D[15..0]
user_sw6 D[15..0] sdram_DNU sdram_DNU
C 15 2 sdram_SDA sdram_SDA C
16 1 user_sw7
spare sdram_SCL sdram_SCL
CLK_OSC3 spare Apex_boot_sel spare sdram_cke0 sdram_CKE0
SW DIP-8 clk_CPLD Apex_boot_sel Apex_CONF_DONE sdram_cke1 CLK_Apex2 sdram_CKE1
Apex_CONF_DONE Apex_CONF_DONE sdram_CK0
5
6
7
8

5
6
7
8

Apex_nSTATUS CLK_Apex0
RP4 RP5 Apex_nSTATUS Apex_nCONFIG Apex_nSTATUS sdram_CK1
1k RPACK R R R R R R R R 1k RPACK Apex_nCONFIG Apex_DCLK Apex_nCONFIG sdram
Apex_DCLK Apex_DCLK PMC
CLK_OSC0 PMC[74..0] TCK
CLK_Apex clk_OSC PMC[74..0] CLK_Apex1 PMC[74..0]
PMC_TCK TMS
4
3
2
1

4
3
2
1

+3.3V +3.3V clk_Apex_out clk_PMC PMC_TMS PMC_TDO R2


+3.3V Apex_clear# reset# PMC_TDO PMC_TDI
Apex_DEV_CLRn reset# PMC_TDI +3.3V
1k D1A
R36 TCK PMC 18

F
1k TCK TMS user_LED0 RP1
SW2 power TMS CPLD_TDO user_LED0 user_LED1 hex_0F 4 5 17

R R R R

G
TDO user_LED1 user_pb[3..0]
1 3 pb_reset# pb_reset# reset#
reset#
RESET# TDI
CPLD_TDI
user_pb[3..0]
hex_0G 3 6
SPST user_sw[7..0] hex_0A 2 7 16

A
SW3 R3 user_sw[7..0] hex_0A hex_0B
hex_0A 1 8
1 3 Apex_clear# flash 1k hex_0B 15

DP B
SPST hex_0B hex_0C
R37 male header JTAG hex_0C hex_0D 220 RPACK
power +3.3V hex_0D 4 14 +3.3V
hex_0E RP2

CC
B 1k connections: B
+3.3V hex_0E hex_0F hex_0DP 4 5 3

R R R R
pin# jtag

C
hex_0F hex_0G hex_0C
+3.3V 1 TCK hex_0G 3 6
1
2
3
4

hex_0DP hex_0D 2 7 2

D
RP7 2 GND hex_0DP hex_1A hex_0E
hex_1A 1 8
R R R R 3 TDO hex_1B 1

E
1k RPACK +3.3V hex_1B
1
2
3
4

4 Vcc hex_1C
SW4 RP8 hex_1C hex_1D 220 RPACK hex display

Apex_TCK

Apex_TDO
5 TMS

Apex_TMS
hex_1D

Apex_TDI
user_pb0
R R R R hex_1E D1B
8
7
6
5

1 3 1k RPACK 6 Vccio hex_1E


SPST hex_1F 12

F
SW5 7 (NC) hex_1F hex_1G RP3
user_pb1 8 (NC) hex_1G hex_1DP hex_1F
8
7
6
5

1 3 4 5 11

R R R R

A
SPST hex_1DP hex_1A
9 TDI 3 6
hex_1B

TMS
SW6 apex 2 7 10

TCK
10 GND

Apex_TDO

DP B
Apex_TDI
1 3 user_pb2 hex_1DP 1 8
SPST LED1 9
SW7 user_LED0 R4
1 3 user_pb3 JP3 220 RPACK 8 13

C
TCK RP6 +3.3V

CC
SPST yellow LED 330
TDO 1 2 R27 LED2 hex_1C 4 5 7

R R R R

G
TMS 3 4 +3.3V
TRST user_LED1 hex_1G
R5 3 6
+3.3V 5 6 1k hex_1D 2 7 6

D
TDI 7 8 yellow LED 330 hex_1E
9 10 1 8
5

E
A R12 HEADER 5x2 +3.3V A
LED3 220 RPACK hex display
1k flash_byte# R6
JP2
Apex_boot_sel
1 green LED 330
2 Title
HEADER 2 LED7 Nios Development Board- top
R10
Apex_boot_sel determines whether to force +3.3V
Size Document Number Rev
a boot from the default boot sector, or the green LED 330 B Nios Development Board pilot
user-programmed boot sector. power indication
Date: Tuesday, February 06, 2001 Sheet 1 of 11
5 4 3 2 1
5 4 3 2 1
U1A
U1B U1C U1D
OE_n A1 GNDINT VCCINT B1
A2 B2 A13 C1 D1 A1/A17 E1 F1 PMC46 PMC60 G1 H1 PMC47
A10 IO-A2 GNDINT A18 A16 IO-C1 IO-D1 A15 flash_CS_n IO-E1 IO-F1 sram_nBE1 IO-G1 IO-H1 PMC69
A3 B3 C2 D2 E2 F2 PMC49 G2 H2
A11 IO-A3 IO-B3 A9 A12 IO-C2 IO-D2 A14 sram1_CS_n A19 IO-E2 IO-F2 A17 PMC38 IO-G2 IO-H2
A4 B4 C3 D3 E3 F3 G3 H3 PMC50
A7 IO-A4 IO-B4 A8 DATA0 IO-C3 IO-D3 DATA5 IO-E3 IO-F3 sram_nBE2 PMC56 IO-G3 IO-H3 PMC68
A5 IO-A5 IO-B5 B5 C4 IO-C4 DATA5 D4 sram0_CS_n E4 IO-E4 IO-F4 F4 G4 IO-G4 IO-H4 H4
A6 A6 B6 A5 DATA10 C5 D5 DATA6 PMC31 E5 F5 sram_nBE0 PMC59 G5 H5 sram_nBE3
A3 IO-A6 IO-B6 A4 DATA12 IO-C5 IO-D5 DATA11 IO-E5 IO-F5 PMC40 IO-G5 IO-H5 PMC67
A7 IO-A7 IO-B7 B7 C6 IO-C6 IO-D6 D6 sram_WE_n DATA4 E6 IO-E6 GNDINT F6 G6 IO-G6 IO-H6 H6
A1 A8 B8 A2 DATA16 C7 D7 DATA15 E7 F7 PMC39 G7 H7
IO-A8 IO-B8 PMC64 DATA20 IO-C7 IO-D7 DATA3 DATA9 DATA4 IO-F7 DATA8 GNDINT VCCIO-bank8
A9 (NC) IO-B9 B9 C8 IO-C8 DATA3 D8 E8 IO-E8 IO-F8 F8 G8 VCCIO-bank1 GNDINT H8
A10 B10 DATA31 DATA23 C9 D9 DATA19 DATA17 E9 F9 DATA13 DATA7 G9 H9
(NC) IO-B10 DATA30 DATA24 IO-C9 IO-D9 DATA26 DATA18 IO-E9 IO-F9 DATA21 DATA2 IO-G9 VCCINT DATA14
A11 GNDINT IO-B11 B11 C10 IO-C10 IO-D10 D10 E10 IO-E10 IO-F10 F10 G10 DATA2 IO-H10 H10
D PMC0 DATA29 DATA22 DATA1 D
A12 (NC) IO-B12 B12 C11 IO-C11 FAST2 D11 Apex_TDO E11 TDO IO-F11 F11 G11 IO-G11 DATA1 H11
A13 B13 PMC1 PMC19 C12 D12 Apex_TRST E12 F12 Apex_DEV_CLRn DATA27 G12 H12 DATA25
(NC) IO-B13 PMC2 PMC25 IO-C12 TRST +3.3V nCEO FAST1 DATA28 RDYnBSY CLKUSR
A14 (NC) IO-B14 B14 C13 IO-C13 IO-D13 D13 E13 IO-E13 IO-F13 F13 CTS G13 INIT_DONE IO-H13 H13 flash_WE_n
PMC3 A15 B15 PMC4 C14 D14 E14 F14 G14 H14
PMC5 IO-A15 IO-B15 PMC6 IO-C14 IO-D14 IO-E14 IO-F14 RTS IO-G14 VCCIO-bank2
A16 IO-A16 IO-B16 B16 sdram_we_n C15 IO-C15 IO-D15 D15 TXD E15 IO-E15 IO-F15 F15 G15 IO-G15 GNDINT H15
PMC7 A17 B17 PMC8 C16 D16 E16 F16 sdram_dqm7 G16 H16 sdram_dqm6
PMC9 IO-A17 IO-B17 PMC10 sdram_s0_nsdram_dqm5 IO-C16 IO-D16 sdram_s1_n sdram_ras_n
sdram_dqm4 sdram_dqm3 IO-E16 IO-F16 G17 I/O used for A0 -> G17 GNDINT IO-H16 PMC42
A18 IO-A18 IO-B18 B18 C17 IO-C17 IO-D17 D17 E17 IO-E17 GNDINT F17 IO-G17 IO-H17 H17
PMC11 A19 B19 PMC12 hex1_dp C18 D18 hex0_dp PMC26 E18 F18 PMC36 PMC41 G18 H18 PMC51
PMC13 IO-A19 IO-B19 PMC21 hex_1DP IO-C18 IO-D18 hex_0DP PMC29 IO-E18 IO-F18 PMC30 PMC28 IO-G18 IO-H18
A20 B20 C19 D19 PMC24 E19 F19 G19 H19 PMC53
PMC16 IO-A20 IO-B20 spare PMC23 IO-C19 IO-D19 PMC27 PMC37 IO-E19 IO-F19 PMC35 PMC34 IO-G19 IO-H19 PMC45
A21 IO-A21 GNDINT B21 C20 IO-C20 IO-D20 D20 E20 IO-E20 IO-F20 F20 G20 IO-G20 IO-H20 H20
A22 B22 PMC22 C21 D21 PMC14 PMC15 E21 F21 PMC17 PMC62 G21 H21 PMC52
GNDINT VCCINT PMC18 IO-C21 IO-D21 PMC20 PMC33 IO-E21 IO-F21 PMC43 PMC54 IO-G21 IO-H21 PMC44
C22 IO-C22 IO-D22 D22 E22 IO-E22 IO-F22 F22 G22 IO-G22 IO-H22 H22
Apex 20K200E 484 FBGA
Apex 20K200E 484 FBGA Apex 20K200E 484 FBGA Apex 20K200E 484 FBGA

U1E
proto36 proto5_8 U1F U1G U1H
J1 IO-J1 IO-K1 K1
proto37 J2 K2 proto5_18 L1 M1 proto5_5 N1 P1 proto5_15 proto5_26 R1 T1 proto5_25
proto24 IO-J2 IO-K2 proto34 VCCIO-bank8 GNDINT proto5_7 proto35 IO-N1 IO-P1 proto5_28 proto5_27 IO-R1 IO-T1 proto5_36
J3 IO-J3 IO-K3 K3 L2 GNDINT IO-M2 M2 N2 IO-N2 IO-P2 P2 R2 IO-R2 IO-T2 T2
PMC57 J4 K4 proto3 PMC70 L3 M3 proto5_4 proto5_17 N3 P3 proto5_16 proto5_14 R3 T3 proto5_37
proto28 IO-J4 IO-K4 proto25 DATA0 IO-L3 IO-M3 IO-N3 IO-P3 IO-R3 IO-T3
J5 IO-J5 IO-K5 K5 L4 DATA0 nCE M4 Apex_nCE clk_Apex_out proto11 N4 CLK4p CS P4 proto2 proto26 R4 LOCK2 GNDPLL T4
DATA6 J6 K6 PMC71 L5 M5 N5 P5 proto18 R5 T5
proto27 DATA6 IO-K6 Apex_DCLK DCLK TDI proto38 Apex_TDI proto19 IO-N5 CLKLK_OUT2p clk_Apex_out CLKLK_OUT2n VCCPLL sdram_dq62
J7 K7 PMC58 L6 M6 N6 P6 R6 T6
C IO-J7 nCS DATA7 clk_OSC
proto12 CLK2p IO-M6 PMC32 DEV_OE CLKLK_FB2n sdram_dq63 CLKLK_FB2p IO-T6 C
J8 VCCINT DATA7 K8 L7 IO-L7 nWS M7 Apex_DEV_CLRn N7 DEV_CLRn IO-P7 P7 R7 VCCINT GNDINT T7
J9 K9 PMC48 L8 M8 N8 P8 R8 T8
GNDINT VCCIO-bank8 nRS VCCPLL GNDPLL VCCIO-bank7 GNDINT VCCIO-bank6 user_pb1
J10 VCCIO-bank1 GNDINT K10 L9 VCCPLL GNDPLL M9 N9 VCCINT GNDINT P9 R9 VCCIO-bank6 IO-T9 T9
J11 K11 L10 M10 N10 P10 R10 T10 user_sw2
GNDINT VCCINT VCCINT VCCIO-bank7 GNDINT VCCINT user_sw5 hex_1A IO-R10 IO-T10
J12 IO-J12 VCCIO-bank2 K12 L11 GNDINT GNDINT M11 N11 VCCIO-bank6 IO-P11 P11 hex_0A R11 IO-R11 IO-T11 T11 hex_1B
J13 K13 L12 M12 N12 P12 sdram_a13 R12 T12 sdram_dqm1
VCCINT GNDINT GNDINT GNDINT VCCINT IO-P12 sdram_cas_n
sdram_a9 IO-R12 IO-T12
J14 GNDINT VCCINT K14 L13 VCCIO-bank3 VCCINT M13 N13 GNDINT VCCIO-bank5 P13 R13 IO-R13 IO-T13 T13 sdram_cke0
J15 K15 proto17 proto5_10 L14 M14 N14 P14 R14 T14 sdram_a7
PMC55 VCCIO-bank3 IO-K15 proto15 proto5_0 IO-L14 CLKLK_ENA proto5_20 proto5_31 VCCIO-bank4 GNDINT VCCINT IO-T14
J16 IO-J16 IO-K16 K16 L15 IO-L15 IO-M15 M15 N15 IO-N15 VCCINT P15 R15 GNDINT VCCIO-bank5 T15
PMC61 J17 K17 proto31 L16 M16 proto39 proto5_21 N16 P16 sdram_dq11 R16 T16
proto21 IO-J17 CLK3p proto22 clk_in_proto proto33 IO-L16 IO-M16 proto23 proto5_12 IO-N16 IO-P16 proto5_33 sdram_dq8 VCCIO-bank4 GNDINT sdram_dq10
J18 IO-J18 IO-K18 K18 L17 IO-L17 IO-M17 M17 N17 IO-N17 IO-P17 P17 R17 IO-R17 IO-T17 T17
PMC72 J19 K19 proto6 R13 1k L18 M18 proto29 N18 P18 proto5_23 proto5_30 R18 T18
PMC73 IO-J19 IO-K19 proto1 +3.3V MSEL1 CLK1p clk_in_proto5 IO-N18 IO-P18 proto5_1 proto5_19 IO-R18 IO-T18 user_LED0
J20 K20 R14 1k L19 M19 proto5_2 N19 P19 R19 T19
PMC65 IO-J20 IO-K20 PMC74 proto20 MSEL0 NCONFIG proto30 Apex_nCONFIG proto0 IO-N19 IO-P19 proto16 IO-R19 IO-T19 user_LED1
proto5_11
J21 K21 L20 M20 N20 P20 proto5_3 R20 T20
PMC66 IO-J21 IO-K21 proto5 PMC63 IO-L20 IO-M20 proto13 IO-N20 IO-P20 proto14 proto32 IO-R20 IO-T20 proto5_13
J22 IO-J22 IO-K22 K22 L21 IO-L21 GNDINT M21 N21 IO-N21 IO-P21 P21 R21 IO-R21 IO-T21 T21
L22 M22 proto8 N22 P22 proto7 proto9 R22 T22 proto5_9
VCCIO-bank4 VCCINT IO-N22 IO-P22 IO-R22 IO-T22
Apex 20K200E 484 FBGA
Apex 20K200E 484 FBGA Apex 20K200E 484 FBGA Apex 20K200E 484 FBGA
U1I U1J U1K
proto5_34 U1 V1 sdram_dq24 sdram_dq22 W1 Y1 sdram_dq25 AA1 AB1
proto5_35 IO-U1 IO-V1 sdram_dq26 sdram_dq13 IO-W1 IO-Y1 sdram_dq14 VCCINT GNDINT sdram_dq23
U2 IO-U2 IO-V2 V2 W2 IO-W2 IO-Y2 Y2 AA2 GNDINT IO-AB2 AB2
proto5_24 U3 V3 sdram_dq6 sdram_dq4 W3 Y3 sdram_dq5 sdram_dq12 AA3 AB3 sdram_dq36
proto5_38 IO-U3 IO-V3 sdram_dq3 sdram_dq2 IO-W3 IO-Y3 sdram_dq15 sdram_dq34 IO-AA3 IO-AB3 sdram_dq35
B U4 IO-U4 IO-V4 V4 W4 IO-W4 IO-Y4 Y4 AA4 IO-AA4 IO-AB4 AB4 B
proto5_6 U5 V5 sdram_dq16 W5 Y5 sdram_dq60 sdram_dq33 AA5 AB5 sdram_dq32 U2 LP3962
LOCK4 IO-V5 flash_BYTE_n IO-W5 IO-Y5 IO-AA5 IO-AB5

6
U6 V6 W6 Y6 sdram_dq61 sdram_dq46 AA6 AB6 sdram_dq45
GNDINT IO-V6 proto_sel# sdram_SDA IO-W6 IO-Y6 hex0_c sdram_dq44 IO-AA6 IO-AB6 sdram_dq43
U7 V7 W7 Y7 AA7 AB7

ERROR/Sense
GND
proto5_Vee IO-U7 IO-V7 proto5_sel# sdram_SCL IO-W7 IO-Y7 user_pb2 hex_0C sdram_dq42 IO-AA7 IO-AB7 sdram_dq53
hex_1C U8 IO-U8 IO-V8 V8 hex_0D RXD user_pb3 W8 IO-W8 IO-Y8 Y8 AA8 IO-AA8 IO-AB8 AB8
user_sw1 U9 V9 user_sw0 W9 Y9 user_pb0 sdram_dq52 AA9 AB9
user_sw3 IO-U9 IO-V9 user_sw4 IO-W9 IO-Y9 user_sw7 sdram_dq54 IO-AA9 (NC)
U10 IO-U10 IO-V10 V10 Apex_CONF_DONE W10 CONF_DONE IO-Y10 Y10 AA10 IO-AA10 (NC) AB10
U11 V11 proto4 W11 Y11 sdram_dqm2 sdram_dq55 AA11 AB11

GND

Vout
hex_0B user_sw6 IO-U11 FAST4 proto10 Apex_nSTATUS NSTATUS IO-Y11 sdram_dqm0 sdram_dq56 IO-AA11 GNDINT

Vin
SD
U12 IO-U12 FAST3 V12 Apex_TCK W12 TCK IO-Y12 Y12 AA12 IO-AA12 (NC) AB12
sdram_ba1 U13 V13 W13 Y13 sdram_dq59 AA13 AB13
sdram_a10 IO-U13 IO-V13 sdram_a11 sdram_DNU Apex_TMS
sdram_a12 TMS IO-Y13 sdram_ba0 sdram_cke1 sdram_dq48 IO-AA13 (NC)
U14 IO-U14 IO-V14 V14 W14 IO-W14 IO-Y14 Y14 AA14 IO-AA14 (NC) AB14
sdram_a2 sdram_a4 sdram_a6 sdram_a8 sdram_dq49 sdram_dq57 R31

5
U15 IO-U15 IO-V15 V15 W15 IO-W15 IO-Y15 Y15 AA15 IO-AA15 IO-AB15 AB15
sdram_a0 U16 V16 sdram_a1 sdram_a3 W16 Y16 sdram_a5 sdram_dq51 AA16 AB16 sdram_dq58
IO-U16 IO-V16 IO-W16 IO-Y16 hex0_e sdram_dq39 IO-AA16 IO-AB16 sdram_dq47 0
U17 GNDINT IO-V17 V17 hex_0G hex_1G W17 IO-W17 IO-Y17 Y17 hex_0E AA17 IO-AA17 IO-AB17 AB17
U18 V18 W18 Y18 hex1_e sdram_dq40 AA18 AB18 sdram_dq50
hex_1F proto5_39 IO-U18 IO-V18 sdram_dq0 hex_0F hex_1D sdram_dq20 IO-W18 IO-Y18 sdram_dq7 hex_1E sdram_dq29 IO-AA18 IO-AB18 sdram_dq37
U19 V19 W19 Y19 AA19 AB19 +1.8V
sdram_dq1 IO-U19 IO-V19 sdram_dq21 proto5_29 IO-W19 IO-Y19 sdram_dq9 sdram_dq28 IO-AA19 IO-AB19 sdram_dq38 R32 L2 L3
U20 IO-U20 IO-V20 V20 W20 IO-W20 IO-Y20 Y20 AA20 IO-AA20 IO-AB20 AB20
proto5_32 U21 V21 sdram_dq30 sdram_dq17 W21 Y21 sdram_dq19 AA21 AB21 sdram_dq41 10k ferrite ferrite
proto5_22 IO-U21 IO-V21 sdram_dq31 sdram_dq18 IO-W21 IO-Y21 sdram_dq27 GNDINT IO-AB21
U22 IO-U22 IO-V22 V22 W22 IO-W22 IO-Y22 Y22 AA22 VCCINT GNDINT AB22
C3 C4
Apex 20K200E 484 FBGA Apex 20K200E 484 FBGA Apex 20K200E 484 FBGA 10nF 10uF
+3.3V
A[19..1] PMC[74..0] sdram_dq[63..0] VCCPLL
A user_pb[3..0] A1/A17 A[19..1] PMC[74..0] sdram_dq[63..0] +1.8V VCCIO-bank1 +3.3V A
user_pb[3..0] A1/A17 proto[39..0] sdram_a[13..0] VCCIO-bank2
user_sw[7..0] DATA[31..0] proto[39..0] sdram_a[13..0] VCCIO-bank3
user_sw[7..0] DATA[31..0] proto5_[39..0] sdram_ba[1..0] VCCINT +1.8V VCCIO-bank4
proto5_[39..0] sdram_ba[1..0]
sdram_dqm[7..0] GNDPLL VCCIO-bank5 +3.3V
Title
sdram_dqm[7..0] VCCIO-bank6
sram_nBE[3..0] APEX and 1.8V regulator
sram_BE[3..0]_n GNDINT VCCIO-bank7
VCCIO-bank8
Size Document Number Rev
B Nios Development Board pilot

Date: Friday, March 09, 2001 Sheet 2 of 11


5 4 3 2 1
5 4 3 2 1

+3.3V

5
6
7
8
RP9
R R R R
10k RPACK Vcc +3.3V
A19 is pulled high.
GND

4
3
2
1
The top 1/2 of the
D D
flash is dedicated to
Apex images.

A19
flash_CS#
flash_R/W#
flash_BYTE#
A[19..1]
A[19..1]
D[15..0]
D[15..0]
D15/A-1 pin is described as D15.
Note that it is a virtual "A0" when the CPLD loads the Apex (BYTE mode),
but becomes "D15" when the CPU is running in the Apex (WORD mode).

U3 U4

17
29
41
9
A16 1 48 A17
A15 A15 A16 flash_BYTE# D15 A15
2 47 2 23

VCC
VCC
VCC
VCC
A14 A14 BYTE# flash_BYTE# A1 I/O I/O A16
3 A13 GND 46 3 I/O I/O 25
A13 4 45 D15 A2 5 27 A17
A12 A12 D15/A-1 D7 A3 I/O I/O A18 GND for 3k
5 A11 D7 44 6 I/O I/O 28
A11 6 43 D14 A4 8 30 R29
C A10 D14 I/O I/O C
A10 7 42 D6 GND for 3k A5 10 31 0
A9 A9 D6 D13 I/O I/O Apex_DCLK
8 41 R30 11 33
A8 D13 D5 A6 I/O I/O Apex_nCONFIG
9 40 0 12 34
NC D5 D12 I/O I/O Apex_boot_sel
10 NC D12 39
11 38 D4 A7 13 35
flash_R/W# WE# D4 A8 I/O I/O flash_BYTE# spare
RESET# 12 RESET# VCC 37 +3.3V 14 I/O I/O 42
13 36 D11 A9 15 43 flash_OE#
NC D11 D3 A10 I/O I/O flash_CS#
14 NC D3 35 18 I/O I/O 44
15 34 D10 A11 19
flash_RDY/BSY# A19 RDY/BSY# D10 D2 A12 I/O
16 A18 D2 33 20 I/O TCK(I/O) 26 TCK
A18 17 32 D9 A13 21 1
A8 A17 D9 D1 A14 I/O TDI(I/O) TDI
18 A7 D1 31 22 I/O TDO(I/O) 32 TDO
A7 19 30 D8 7
A6 A6 D8 D0 TMS(I/O) TMS
20 29 RESET# 39
A5 A5 D0 INPUT/GCLRN
21 A4 OE# 28 flash_OE# Apex_CONF_DONE 38 INPUT/OE1
A4 22 27 40

GND
GND
GND
GND
A3 A3 GND Apex_nSTATUS INPUT/OE2
23 A2 CE# 26 flash_CS# clk_CPLD 37 INPUT/GCLK
A2 24 25 A1
A1 A0

16
24
36
EPM7064

4
AM29LV800
R28 R33
1k
1k
B +3.3V B

A A

Title
flash and Configuration Controller

Size Document Number Rev


B Nios Development Board pilot

Date: Tuesday, February 06, 2001 Sheet 3 of 11


5 4 3 2 1
5 4 3 2 1

D D

C C

U5
+3.3V 1 Vcca Vccb 20 +3.3V
CLK_OSC0 2 OA0 OB0 19 CLK_Apex0
CLK_OSC1 3 OA1 OB1 18 CLK_Apex1
CLK_OSC2 4 OA2 OB2 17 CLK_Apex2
5 GNDA GNDB 16
CLK_OSC3 6 OA3 OB3 15 CLK_Apex3
CLK_OSC4 7 OA4 OB4 14 CLK_Apex4
8 GNDQ MON 13
9 OEA OEB 12
CLK_OSC_in 10 INA INB 11 CLK_Apex_in
PI49FCT3805 clock driver

B B

A A

Title
Clock Distribution PLL

Size Document Number Rev


A Nios Development Board pilot

Date: Tuesday, February 06, 2001 Sheet 4 of 11


5 4 3 2 1
5 4 3 2 1

D D

PMCJN1
1 2 PMCJN2
PMC_TCK 1 2 PMC0 (PMC_TRST#)
3 4 1 2 R16
PMC1 3 4 PMC2 1 2 +3.3V
5 6 3 4 1k
PMC3 5 6 PMC_TMS 3 4 PMC_TDO
7 7 8 8 PMC_TDI 5 5 6 6
PMC4 9 10 PMC5 7 8 PMC39
9 10 PMC6 PMC40 7 8 PMC41
11 11 12 12 9 9 10 10
13 14 PMC42 11 12
clk_PMC 13 14 PMC7 11 12 +3.3V
PMC43
15 15 16 16 reset# 13 13 14 14
PMC8 17 18 15 16 PMC44
17 18 PMC9 +3.3V
PMC45 15 16
19 19 20 20 17 17 18 18
PMC10 21 22 PMC11 PMC46 19 20 PMC47
PMC12 21 22 19 20 PMC48
23 23 24 24 21 21 22 22
25 26 PMC13 PMC49 23 24
PMC14 25 26 PMC15 PMC50 23 24 +3.3V
PMC51
C 27 27 28 28 25 25 26 26 C
PMC16 29 30 27 28 PMC52
29 30 PMC17 +3.3V
PMC53 27 28
31 31 32 32 29 29 30 30
PMC18 33 34 PMC54 31 32 PMC55
33 34 PMC19 31 32 PMC56
35 35 36 36 33 33 34 34
PMC20 37 38 PMC21 PMC57 35 36
37 38 PMC22 35 36 +3.3V
PMC58
39 39 40 40 37 37 38 38
PMC23 41 42 PMC24 PMC59 39 40
PMC25 41 42 39 40 PMC60
43 43 44 44 +3.3V 41 41 42 42
45 46 PMC26 PMC61 43 44
PMC27 45 46 PMC28 PMC62 43 44 PMC63
47 47 48 48 45 45 46 46
PMC29 49 50 47 48 PMC64
49 50 PMC30 PMC65 47 48
51 51 52 52 49 49 50 50 +3.3V
PMC31 53 54 PMC32 PMC66 51 52 PMC67
PMC33 53 54 51 52 PMC68
55 55 56 56 +3.3V 53 53 54 54
57 58 PMC34 PMC69 55 56
PMC35 57 58 PMC36 PMC70 55 56 PMC71
59 59 60 60 57 57 58 58
PMC37 61 62 59 60 PMC72
B 61 62 PMC38 PMC73 59 60 B
63 63 64 64 61 61 62 62 +3.3V
63 64 PMC74
PMC connector 63 64
PMC connector

PMC[74..0]
PMC[74..0]

A A

Title
PMC connectors

Size Document Number Rev


A Nios Development Board pilot

Date: Tuesday, February 06, 2001 Sheet 5 of 11


5 4 3 2 1
5 4 3 2 1

U6
LM2676

8 tab
LM2676 is a
3A part
J1

feedback
D D
3

Cboost
output

on/off
2

GND
input

NC
1

ADC-002-2 D2

1
2
3
4
5
6
7
DIODE SCHOTTKY
+3.3V

1
Vunreg TP1 TP2 TP3 TP4
C5 C6
10uF 10uF GND point GND point GND point GND point
35V 35V C7 C8 C9
100uF 100uF 100uF
C10

+3.3V
10nF
C 35V C
L1 C50 C51 C52 C53 C54
bypass caps: 1uF 1uF 1uF 1uF 1uF
Coilcraft 22uH
DO3316-223
D3
DIODE SCHOTTKY +3.3V +3.3V +3.3V

C65 C55
10uF 10uF C60 C61 C62 C63 C64
1nF 1nF 1nF 1nF 1nF

+1.8V
B B
+1.8V
+3.3V
C75 C70 C71 C72 C73 C74
R17 10uF 1uF 1uF 1uF 1uF 1uF
1k U7

R18 8 5
pb_reset# PBR RST
10k 6
RST
+3.3V 1 VCC3 SRST 7 reset#
+5V 2 VCC5
3 VCCA
R19
LTC1326-5
+1.8V
39k 1% R20
62k 1%
A A

Title
Power

Size Document Number Rev


A Nios Development Board pilot

Date: Tuesday, February 06, 2001 Sheet 6 of 11


5 4 3 2 1
5 4 3 2 1

protoIO[39..0]
protoIO[39..0]

D D

JP8
reset# protoIO0 1 2 protoIO1
JP9
protoIO2 3 4 protoIO3
1 2 protoIO29 protoIO4 5 6 protoIO5
protoIO30 3 4 protoIO31 protoIO6 7 8 protoIO7
protoIO32 5 6 protoIO33 protoIO8 9 10 protoIO9
protoIO34 7 8 protoIO35 protoIO10 11 12 protoIO11
protoIO36 9 10 protoIO37 protoIO12 13 14 protoIO13
protoIO38 11 12 protoIO39 protoIO14 15 16 protoIO15
13 14 17 18
protoIO16 19 20
HEADER 7X2
protoIO17 21 22
protoIO18 23 24 +3.3V
protoIO19 25 26 protoIO20
C JP10 C
protoIO21 27 28
Vunreg 1 2 protoIO22 29 30 protoIO23 R34
3 4 protoIO24 31 32 10k
+3.3V 5 6 protoIO25 33 34 protoIO26
7 8 protoIO27 35 36 cardsel#
OSC 9 10 protoIO28 37 38 cardsel#
clk1 11 12 39 40
clk2 13 14
HEADER 20X2
15 16
17 18
19 20
HEADER 10X2

B B

A A

Title
3.3V Prototype Card

Size Document Number Rev


A Nios Development Board pilot

Date: Tuesday, February 06, 2001 Sheet 7 of 11


5 4 3 2 1
5 4 3 2 1

Apcard[39..0]
Apcard[39..0]

JP11
JP12 reset# pcard0
R21 1 2 pcard1
1 2 +5V
pcard29 pcard2 3 4 pcard3
D Vee pcard30 3 4 pcard31 pcard4 5 6 pcard5 D
C11
10nF pcard32 5 6 pcard33 pcard6 7 8 pcard7
10k pcard34 7 8 pcard35 pcard8 9 10 pcard9
pcard36 9 10 pcard37 pcard10 11 12 pcard11
pcard38 11 12 pcard39 pcard12 13 14 pcard13
13 14 pcard14 15 16 pcard15
17 18
HEADER 7X2
pcard16 19 20
pcard17 21 22
pcard18 23 24 +3.3V
JP13
pcard19 25 26 pcard20
Vunreg
Vref 1 2 pcard21 27 28
3 4 pcard22 29 30 pcard23 R22
+3.3V 5 6 pcard24 31 32 10k
7 8 pcard25 33 34 pcard26
OSC 9 10 pcard27 35 36 cardsel#
clk1 11 12 pcard28 37 38 cardsel#
clk2 13 14 39 40
C C
15 16
HEADER 20X2
17 18 D5
19 20
1 2 +3.3V
HEADER 10X2
diode 1N4001

+3.3V really any large-value


R38 pull-up will do.
U8, U9, U11, U12 are voltage-limiting switches. 62k 1% I'm just using largest
nets pcard* represent the connector side of the switch R23 D4
Vref value of R
nets Apcard* represent the APEX side of the switch +5V 1 2
already on the board.
U8 U9 100 diode 1N4001
cardsel# 1 24 Vcybus cardsel# 1 24 Vcybus
pcard0 BE1 Vcc pcard1 pcard10 BE1 Vcc pcard11
2 B0 B9 23 2 B0 B9 23
Apcard0 3 22 Apcard1 Apcard10 3 22 Apcard11 Vcybus
B Apcard2 A0 A9 Apcard3 Apcard12 A0 A9 Apcard13 C12 C13 C14 C15 B
4 A1 A8 21 4 A1 A8 21
pcard2 5 20 pcard3 pcard12 5 20 pcard13 1uF 1uF 1uF 1uF
pcard4 B1 B8 pcard5 pcard14 B1 B8 pcard15
6 B2 B7 19 6 B2 B7 19
Apcard4 7 18 Apcard5 Apcard14 7 18 Apcard15
Apcard6 A2 A7 Apcard7 Apcard16 A2 A7 Apcard17
8 A3 A6 17 8 A3 A6 17
pcard6 9 16 pcard7 pcard16 9 16 pcard17 5V LDO for optional use by
pcard8 B3 B6 pcard9 pcard18 B3 B6 pcard19
10 B4 B5 15 10 B4 B5 15 5V Altera daughter card
Apcard8 Apcard9 Apcard18 Apcard19 U10
11 A4 A5 14 11 A4 A5 14
12 13 cardsel# 12 13 cardsel# 5 4
GND BE2 GND BE2 NC NC +5V
6 GND GND 3
CYBUS CYBUS 7 2
U11 U12 GND GND
Vunreg 8 Vin Vout 1
cardsel# 1 24 Vcybus cardsel# 1 24 Vcybus C16 C17
pcard20 BE1 Vcc pcard21 pcard30 BE1 Vcc pcard31 C18 10nF 10uF
2 B0 B9 23 2 B0 B9 23
Apcard20 3 22 Apcard21 Apcard30 3 22 Apcard31 10nF LM78L05
Apcard22 A0 A9 Apcard23 Apcard32 A0 A9 Apcard33 35V
4 A1 A8 21 4 A1 A8 21
pcard22 5 20 pcard23 pcard32 5 20 pcard33
pcard24 B1 B8 pcard25 pcard34 B1 B8 pcard35
A 6 B2 B7 19 6 B2 B7 19 A
Apcard24 7 18 Apcard25 Apcard34 7 18 Apcard35
Apcard26 A2 A7 Apcard27 Apcard36 A2 A7 Apcard37 Title
8 A3 A6 17 8 A3 A6 17
pcard26 9 16 pcard27 pcard36 9 16 pcard37 5V Prototype Card
pcard28 B3 B6 pcard29 pcard38 B3 B6 pcard39
10 B4 B5 15 10 B4 B5 15
Apcard28 11 14 Apcard29 Apcard38 11 14 Apcard39 Size Document Number Rev
A4 A5 cardsel# A4 A5 cardsel# A Nios Development Board pilot
12 GND BE2 13 12 GND BE2 13

CYBUS CYBUS Date: Tuesday, February 06, 2001 Sheet 8 of 11


5 4 3 2 1
5 4 3 2 1

D D

J2A J2B

1 2 sdram_DNU 73 73 74 74 sdram_CK1
sdram_dq0 sdram_dq32 75 76
sdram_dq1 3 4 sdram_dq33 75 76
5 6 77 77 78 78
sdram_dq2 sdram_dq34 79 80
sdram_dq3 7 8 sdram_dq35 79 80
9 10 +3.3V 81 81 82 82 +3.3V sdram_dq48
sdram_dq16 83 84
sdram_dq4+3.3V 11 12 +3.3V sdram_dq36 sdram_dq17 85
83 84
86 sdram_dq49
sdram_dq5 13 14 sdram_dq37 sdram_dq18 85 86 sdram_dq50
15 16 87 87 88 88
sdram_dq6 sdram_dq38 sdram_dq19 89 90 sdram_dq51
sdram_dq7 17 18 sdram_dq39 89 90
19 20 91 91 92 92
sdram_dq20 93 94 sdram_dq52
sdram_dqm0 21 22 sdram_dqm4 sdram_dq21 93 94 sdram_dq53
23 24 95 95 96 96
C sdram_dqm1 sdram_dqm5 sdram_dq22 97 98 sdram_dq54 C
25 26 sdram_dq23 97 98 sdram_dq55
99 100
sdram_a0 +3.3V 27 28 +3.3V sdram_a3
101
99 100
102
sdram_a1 29 30 sdram_a4 sdram_a6 +3.3V 103
101 102
104
+3.3V
sdram_a7
sdram_a2 31 32 sdram_a5 sdram_a8 103 104 sdram_ba0
33 34 105 105 106 106
35 36 107 107 108 108
sdram_dq8 sdram_dq40 sdram_a9 109 110 sdram_ba1
sdram_dq9 37 38 sdram_dq41 sdram_a10 109 110 sdram_a11
39 40 111 111 112 112
sdram_dq10 sdram_dq42 113 114
sdram_dq11 41 42 sdram_dq43 +3.3V
sdram_dqm2 113 114 +3.3V sdram_dqm6
43 44 115 115 116 116
sdram_dqm3 117 118 sdram_dqm7
+3.3V
sdram_dq12 45 46 +3.3V sdram_dq44 117 118
47 48 119 119 120 120
sdram_dq13 sdram_dq45 sdram_dq24 121 122 sdram_dq56
sdram_dq14 49 50 sdram_dq46 sdram_dq25 121 122 sdram_dq57
51 52 123 123 124 124
sdram_dq15 sdram_dq47 sdram_dq26 125 126 sdram_dq58
53 54 sdram_dq27 125 126 sdram_dq59
55 56 127 127 128 128
57 58 +3.3V 129 129 130 130 +3.3V sdram_dq60
sdram_dq28 131 132
B 59 60 sdram_dq29 131 132 sdram_dq61 B
sdram_CK0 61 62 sdram_CKE0 133 133 134 134
sdram_dq30 135 136 sdram_dq62
+3.3V 63 64 +3.3V sdram_dq31 135 136 sdram_dq63
sdram_RAS_n 65 66 sdram_CAS_n 137 137 138 138
sdram_WE_n 67 68 sdram_CKE1 139 139 140 140
sdram_a12 141 142
sdram_S0_n 69 70 sdram_a13 sdram_SDA 141 142 sdram_SCL
sdram_S1_n 71 72 +3.3V 143 143 144 144 +3.3V

sdram connector 144 sdram connector 144

sdram_dq[63..0]
sdram_dq[63..0]
sdram_a[13..0]
sdram_a[13..0]
A A
sdram_ba[1..0]
sdram_ba[1..0]
Title
sdram_dqm[7..0] SODIMM SDRAM connector
sdram_dqm[7..0]
Size Document Number Rev
A Nios Development Board pilot

Date: Tuesday, February 06, 2001 Sheet 9 of 11


5 4 3 2 1
5 4 3 2 1

J3
DB9 female

D D

1
6
2
7
3
8
4
9
5
+3.3V

16
U13
11 14

VCC
TXD TR1IN TR1OUT
CTS 10 TR2IN TR2OUT 7

R24 13 12
RX1IN RX1OUT RXD
1k 8 9
RX2IN RX2OUT RTS
C C19 1 R35 C
+3.3V C1+
1uF 3 1k
C1-
4 C2+
5 C2- +3.3V
C20 2

GND
1uF V+
6 V-
C21 C22 LTC1386

15
1uF 1uF

+3.3V

B B

JP14
TXD RXD
CTS 1 2 RTS
3 4
5 6
HEADER 3X2

A A

Title
Serial Port

Size Document Number Rev


A Nios Development Board pilot

Date: Tuesday, February 06, 2001 Sheet 10 of 11


5 4 3 2 1
5 4 3 2 1

U14 U15
A1/A17 5 7 D0 A1/A17 5 7 D16
A2 A0 I/O0 D1 A2 A0 I/O0 D17
D
4 A1 I/O1 8 4 A1 I/O1 8 D
A3 3 9 D2 A3 3 9 D18
A4 A2 I/O2 D3 A4 A2 I/O2 D19
2 A3 I/O3 10 2 A3 I/O3 10
A5 1 13 D4 A5 1 13 D20
A6 A4 I/O4 D5 A6 A4 I/O4 D21
44 A5 I/O5 14 44 A5 I/O5 14
A7 43 15 D6 A7 43 15 D22
A8 A6 I/O6 D7 A8 A6 I/O6 D23
42 A7 I/O7 16 42 A7 I/O7 16
A9 27 A9 27
A10 A8 D8 A10 A8 D24
26 A9 I/O8 29 26 A9 I/O8 29
A11 25 30 D9 A11 25 30 D25
A12 A10 I/O9 D10 A12 A10 I/O9 D26
24 A11 I/O10 31 24 A11 I/O10 31
A13 21 32 D11 A13 21 32 D27
A14 A12 I/O11 D12 A14 A12 I/O11 D28
20 A13 I/O12 35 20 A13 I/O12 35
A15 19 36 D13 A15 19 36 D29
A16 A14 I/O13 D14 A16 A14 I/O13 D30
18 A15 I/O14 37 18 A15 I/O14 37
38 D15 38 D31
WE# I/O15 WE# I/O15
17 WE 17 WE
C BE#0 39 BE#2 39 C
BE#1 BLE BE#3 BLE
40 BHE VCC 11 +3.3V 40 BHE VCC 11 +3.3V
VCC 33 +3.3V VCC 33 +3.3V
OE# 41 34 OE# 41 34
OE GND OE GND
sram0_CS# 6 CS GND 12 sram1_CS# 6 CS GND 12

IDT71V016S IDT71V016S
R25 R26
10k 10k
+3.3V +3.3V

A1/A17
A1/A17
A[16..2]
A[16..2]
D[31..0]
B D[31..0] B

BE#[3..0]
BE[3..0]#
OE#
OE#
WE#
WE#

A A

Title
SRAM

Size Document Number Rev


A Nios Development Board pilot

Date: Tuesday, February 06, 2001 Sheet 11 of 11


5 4 3 2 1