City University of New York

City College

Department of Electrical Engineering

EE 22100. 3HJ
Professor Hasan Erkan
Laboratory Report #6
Final Project: Digital Clock

Group members: Mohammad Zilon, Mohammad Hijazi

Due date: 11/30/2016

Semester: Fall 2016
Outline:

I. Introduction
II. Components
A. BCD to Seven – Segment Display
B. Experiment with Seven Segment Display
C. Using BCD – to – Seven Segment Display and BCD Counters
D. The Seconds and Minutes Display
E. Building the Clock
F. Time Base Generator for the Digital Clock
III. Conclusion

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 I. Introduction

During this class and previous classes, we have learned how to design simple
circuits, and performed several labs. However, we haven’t had the opportunity to
design big projects yet. Our goal in this lab was to design a digital clock from the
beginning to the end. Digital clocks can be built in many ways; one of those ways
is to create it with counters. The logic behind the circuit of the clock is made of
four modules that are connected:
1. The first module creates a frequency of 32,768 Hz, and this frequency will be
divided with counters till we get 1 Hz for the seconds.
2. The second module counts that up to 60 seconds, and triggers the minutes.
3. The third module is the minutes (same concept like the seconds). It counts up
to 60 minutes, and then triggers the hours.
4. The forth module is the hours. Like the minutes and the seconds, it counts up
to 12 hours and then resets itself.

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 II. Components

A. BCD to Seven – Segment Display

There are a variety of seven segment displays; in this lab, we will be using a two –
digit Light Emitting Diode (LED) display that share a common anode (HDSP 5721).
Each segment on the display is comprised of a single diode, which has a 2V drop
when a current is applied. The diodes are connected to pins 13 and 14 (hence the
common anode). For the segments to display a current range of 5 through 20 mA
must pass through the diodes; if the current exceeds 25 mA, the display will blow out.
The brightness of the display is dependent on the strength of the current.

Figure 1: Two – Digit Seven Segment Display

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Figure 1.a: Two – Digit Seven Segment Display Diagram Schematic

Figure 2: Seven Segment Circuit Connected to a Power Supply: Displaying the Voltage
Drop and Current

B. Experiment with Seven Segment Display

Before beginning to build the digital clock, we needed to experiment with the
seven – segment display to understand how it works. Our goal of the experiment was
to make the number 4 on the right digit light up on the display. To complete our task,

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 we wired the display to the segments needed to display the number 4 (segments
F,G,B,C). After we wired to correct segments, we needed to calculate the necessary
resistance so that the current (ID) wouldn’t exceed 25 mA and remain within the range
of 5-20mA

To calculate the resistance, we used the following values and calculations:

𝑉"" = 9𝑉, 𝑉" = 2𝑉, 𝐼" = 13𝑚𝐴

𝑉"" − 𝑉" = 𝐼" ∗ 𝑅

𝑉"" − 𝑉"
=𝑅
𝐼"
9𝑉 − 2𝑉
= 538.46Ω
13𝑚𝐴
Once we connected the appropriate resistor.

C. Using BCD – to – Seven Segment Display and BCD Counters

There are several commonly used binary codes. In the clock, the binary code that
will be used is Binary Coded Decimal (BCD). BCD is used when binary numbers are
being used to implement decimal digits. In this binary code, 4 bits are used to
represent one digit. As seen in the chart below, numbers above 9 (1001) do not exist
in BCD and will not be generated on the Protoboard.

Decimal BDC
Equivalent
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
10 X
11 X
12 X
13 X
14 X
15 X

Figure 3: Decimal Equivalent to BDC Chart

When building the clock, we will be using a Digital Integrated Circuit (IC)
to assist us in creating the output desired. An IC allows designers of electrical

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 circuits to implement a wide variety of logical, combinational and sequential
functions. To build the digital clock, we will be using a CD 4543 chip; this chip is
designed to input a BCD input and output suitable for a seven – segment display.

Figure 4: Suggested Layout for the Protoboard.

Figure 5: CD 4543 Schematic

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Figure 6: CD 4510 Schematic

In Figure 4, there are two different types of BCD chips; CD 4510 and 4518. The
4510 chips are to be used for the hour’s segments due to the fact they can be preset to
count from a number other than 0. This will be necessary because in a 12 – hour
clock, the count begins at 1.
To get the hours to count to 1 through 12, we needed to understand how the chip
itself worked. The preset and parallel pins on the 4510 chips force the counters to
count from 1 through 12. When the preset signal is set to logical 0, the counters will
begin to count; when the preset signal is set to logical 1, the clock counters will be set
to the logical binary number set by the parallel pins (P1 P2 P3 P4). We want to be able
to see 1 on the 13th count, so we set P1 to power and the other pins to ground (P2 P3
P4). To ensure that we receive the desired results, we will be using a CD 4081 chip,
which consists of AND – gates.

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Figure 7: CD 4081 Schematic

The 4081 chip consists of 4 output pins. When achieving the count to 12 on the
hour display, we want the 4081 chip to count to 13th so that the number 12 will
display, but will reset at 13. To get this output, we will use the pins 3 and 4. Pin 3
will be the output of Q1 & Q2; this output will be the decimal 3. This output will
serve as an input the second AND – gate. Pin 4 will be the output of the 10’s counter,
our output will be 1 which implies 10. From these outputs, we have achieved the
number 13.

D. The Seconds and Minutes Display

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Figure 8: CD 4518

The BCD chips we will be using to count the seconds and minutes are CD 4518
chips. Unlike the 4510 chips, these do can be preset and they will start counting at 0
default. Since they cannot be preset, there are no parallel pins; however, this will
helpful when counting from 0 to 59. We will only be required to use two chips; one
of the minute’s display and a separate one for the seconds’ display.
To successfully get the counters to count from 0 to 59, we need set the Clock
ENABLE and RESETS inputs properly. The counters inside the chip count on the
rising edge of the Internal Clock. When the Enable is set to logical 1, the EXT Clock
is used as an input for the next chip; when the Enable is set to 0, the Enable input is
used for clocking and will count on the falling edge. The RESET is asynchronous
and will reset when the reset line reaches logical 1 independent of the clock signal.
To count minutes, seconds, and hours, we will need to cascade the chips properly.
The second BCD counter is clocked by the EXT Clock input; the minute BCD
counter is clocked by the last stage of the seconds, and the hours the same with
respect to minute. The counters must be clocked on the falling edge of the clock. To
count from 0 to 59, we will be implementing another CD 4081 chip.
On the 4081 chip, we want to logically achieve the number 60 so that we count to
59 and reset at 60. In the first AND – gate, the 1’s display, we will install logical 9
by using the Q2 and Q3 as input. This input will also serve as an input to the second
AND – gate so that the counters count simultaneously. We want the Q2 of the 10’s
display to input into the second AND – gate; the output of this gate will serve as a
reset to the 10’s display. At this point we power the ENABLE of the 10’s display;
and to power the 1’s display, we use Q4 of the 10’s display as the ENABLE and
power accordingly. Considering we will be receiving the clock signal (square wave
at 1Hz) from the 1’s display, it is necessary to ground the 10’s display.

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 E. Building the Clock

Once we had a full understanding as how the components of the digital clock
worked, it was time to build the clock itself. We had used the suggested layout on
our Protoboard in Figure 4 with some modifications. As discussed earlier, to achieve
a successfully counting digital clock, we will need to cascade the counters from the
seconds to minutes and from minutes to hours.

F. Time Base Generator for the Digital Clock

At the stage of building the digital clock, the pulse signal is dependent on a forced
pulse produced by the function generator. The final goal to completing the digital
clock is to implement a crystal liquid oscillator. This component will have its own
internal time base generator that will provide the clock signal for the counters. It will
be connected to one logic gate (CD 4069) and act as an amplifier that will emit
32,768 Hz. The CD 4069 chip contains a NOT - gate, therefore it will act as an
inverting amplifier.

Figure 9: Time Based Generator Circuit

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Figure 10: CD 4069 Schematic

After we have wired the CD 4069 and produce 32,768 Hz, we need to acquire
1Hz for the clock to count properly. To do this, we will be using two CD 4520 BCD
chips. These binary counters are designed to divide the frequency. Figure 8 shows
the schematic for the CD 4520 chip; which is the same schematic for the CD 4518
chip. Pins 3 through 6 and pins 11 through 14 divide the frequency by a power of 2.
For Instance, since pin 3 is denoted Q1A, which translates that the frequency will be
divided by 21. Pin Q1A. We will be using two of these chips so that we can divide
32,768 by 215 (which is equal to 32,768).
To complete this, we will enable Clock A on the first 4520 chip and wire it the
Q4A pin, which will be the input of the Clock B. We will repeat this so that we have
the following process completed:
32768
= 2048
27
2048
= 128
27
128
=8
27
8
=1
29

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 III. Conclusion

Building the digital clock was one of the first experiences designing a circuit for a
practical use. Prior to this lab, we had only constructed circuits so that we would test
several theories. To complete this lab successfully, we needed to take the proper
steps in the procedure.
We commenced the procedure with understanding what components were needed
and how they worked individually. This included understanding how they should be
wired to display a desired a result.
The display chip used for our design was the HDSP 5721 Seven – Segment
Display. This chip used a common anode to supply power to the diodes that were
wired to the CD 4543 chip; the chip was used to decode the binary number that was
to show up on the display.
Once we could wire the display chip to the decoder, we were required to wire the
CD 4510. The 4510 chip was used to count the hours display specifically; this was
because the counter had the ability to be preset to 1 not 0, which was needed to count
the hours in a 12-hour clock. We wire the 4510 to logical 1 so that when it was to
reset to 1 on the 13th count. When getting the hours’ clock to reset at 12, we needed
to use a CD 4081 chip, which contained AND – gates. To count to 12, this chip
needed to be wired at logical 3 at the 1’s pin and logical 1 at the 10’s pin.
After getting the hour’s chip to count from 1 through 12, we needed to implement
the minutes and seconds chips. The processes to install these components were
similar; except the minutes relied on the count of the count on the seconds. We used
the CD 4018 binary counter chips to install the minutes and seconds because there
was no need for a preset, we wanted to start our initial count at 0. Our goal was to get
the minutes and seconds display to count from 0 to 59 and reset at the 60th count.
Like the hours’ counter, we used another CD4081 chip to accomplish this goal.
Once we had completed the clock, we needed to install the time generating circuit
using the liquid crystal oscillator, the CD 4069 chip, two CD 4520 chips, 1 33nF
capacitor and two 330kW resistors. This part of the digital clock allowed the clock to
run off a direct power source without a forced pulse fro the function generator.
After the clock could run on its own, with the use of the liquid crystal generator
and the direct power source, we needed to test how the clock worked when we
applied 9V to the circuit. We could successfully power the digital clock. This lab
provided us with a fundamental application of circuits; and made constructing circuits
more practical as opposed to theoretical.

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