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Edition 31.10.2002
Published by Infineon Technologies AG,
Balanstraße 73,
81541 München
© Infineon Technologies AG 2002.
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TDK 5100
Product Info
Product Info
Features ■ fully integrated frequency synthe- ■ temperature range −40 ... +125°C
sizer
■ power down mode
■ VCO without external components
■ low voltage sensor
■ ASK and FSK modulation
■ selectable crystal oscillator
■ switchable frequency range 6.78 MHz / 13.56 MHz
433-435 MHz / 868-870 MHz
■ programmable divided clock output
■ high efficiency power amplifier for µC
(typically 5 dBm / 2 dBm)
■ low external component count
■ low supply current (typically 7mA)
■ voltage supply range 2.1 - 4 V
Product Description
1.1 Overview
The TDK 5100 is a single chip ASK/FSK transmitter for the frequency bands
433-435 MHz and 868-870 MHz. The IC offers a high level of integration and
needs only a few external components. The device contains a fully integrated
PLL synthesizer and a high efficiency power amplifier to drive a loop antenna.
A special circuit design and an unique power amplifier design are used to save
current consumption and therefore to save battery life. Additional features like
a power down mode, a low power detect, a selectable crystal oscillator fre-
quency and a divided clock output are implemented. The IC can be used for
both ASK and FSK modulation.
1.2 Applications
1.3 Features
Product Description
Functional Description
PDWN 1 16 CSEL
LPD 2 15 FSEL
VS 3 14 PAOUT
LF 4 13 PAGND
TDK 5100
GND 5 12 FSKGND
ASKDTA 6 11 FSKOUT
FSKDTA 7 10 COSC
CLKOUT 8 9 CLKDIV
Pin_config.wmf
Table 2-1
Pin No. Symbol Function
1 PDWN Power Down Mode Control
2 LPD Low Power Detect Output
3 VS Voltage Supply
4 LF Loop Filter
5 GND Ground
6 ASKDTA Amplitude Shift Keying Data Input
7 FSKDTA Frequency Shift Keying Data Input
8 CLKOUT Clock Driver Output
9 CLKDIV Clock Divider Control (847.5 kHz or 3.34 MHz)
10 COSC Crystal Oscillator Input
11 FSKOUT Frequency Shift Keying Switch Output
12 FSKGND Frequency Shift Keying Ground
13 PAGND Power Amplifier Ground
14 PAOUT Power Amplifier Output
15 FSEL Frequency Range Selection (433 or 868 MHz)
16 CSEL Crystal Frequency Selection (6.78 or 13.56 MHz)
Functional Description
Table 2-2
Pin Symbol Interface Schematic1) Function
No.
1 PDWN Disable pin for the complete transmitter cir-
VS cuit.
250 kΩ
Functional Description
35 kΩ
10 kΩ
VS
4
Functional Description
100 µA
Functional Description
13
Detect Output
Input Input Control VS
7 6 1 3 2
FSK 12
Power Low Voltage
Functional Block diagram
Ground
OR
Supply Sensor 2.2V
FSK 11
Switch
On
2-7
14 Power
Crystal XTAL Power
PFD :128/64 VCO :1/2 Amplifier
6.78/13.56 MHz
10 Osc AMP Output
13 Power
Amplifier
Clock Output
Frequency :2/8 LF Ground
Select :4/16
0.85/3.39 MHz 9
8 16 4 15 5
Specification, October 2002
Frequency
Functional Description
Clock Crystal Loop
Select Select Ground
Output Filter
6.78/13.56 MHz 434/868 MHz
TDK 5100
Block_diagram.wmf
TDK 5100
Functional Description
Table 2-3
CSEL (pin 16) Crystal Frequency
1)
Low 6.78 MHz
Open2) 13.56 MHz
1) Low: Voltage at pin < 0.2 V
2) Open: Pin open
For both quartz frequency options, 847.5 kHz or 3.39 MHz are available as out-
put frequencies of the clock output CLKOUT (pin 8) to drive the clock input of a
micro controller.
The frequency at CLKOUT (pin 8) is controlled by the signal at CLKDIV (pin 9)
Table 2-4
CLKDIV (pin 9) CLKOUT Frequency
1)
Low 3.39 MHz
Open2) 847.5 kHz
1) Low: Voltage at pin < 0.2 V
2) Open: Pin open
Functional Description
Table 2-5
FSKDTA (pin7) FSK Switch
1)
Low CLOSED
Open2), High3) OPEN
1) Low: Voltage at pin < 0.5 V
2) Open: Pin open
3) High: Voltage at pin > 1.5 V
In case of operation in the 868-870 MHz band, the power amplifier is fed directly
from the voltage controlled oscillator. In case of operation in the 433-435 MHz
band, the VCO frequency is divided by 2. This is controlled by FSEL (pin 15) as
described in the table below.
Table 2-6
FSEL (pin 15) Radiated Frequency Band
1)
Low 433 MHz
Open2) 868 MHz
1) Low: Voltage at pin < 0.5 V
2) Open: Pin open
Table 2-7
ASKDTA (pin 6) Power Amplifier
1)
Low OFF
Open2), High3) ON
1) Low: Voltage at pin < 0.5 V
2) Open: Pin open
3) High: Voltage at pin > 1.5 V
The Power Amplifier has an Open Collector output at PAOUT (pin 14) and
requires an external pull-up coil to provide bias. The coil is part of the tuning and
matching LC circuitry to get best performance with the external loop antenna.
To achieve the best power amplifier efficiency, the high frequency voltage swing
at PAOUT (pin 14) should be twice the supply voltage.
The power amplifier has its own ground pin PAGND (pin 13) in order to reduce
the amount of coupling to the other circuits.
Functional Description
The supply voltage is sensed by a low power detector. When the supply voltage
drops below 2.15 V, the output LPD (pin 2) switches to the low-state. To mini-
mize the external component count, an internal pull-up current of 40 µA gives
the output a high-state at supply voltages above 2.15 V.
The output LPD (pin 2) can either be connected to ASKDTA (pin 6) to switch off
the PA as soon as the supply voltage drops below 2.15 V or it can be used to
inform a micro-controller to stop the transmission after the current data packet.
The IC provides three power modes, the POWER DOWN MODE, the PLL
ENABLE MODE and the TRANSMIT MODE.
Functional Description
PDWN
ASKDTA
OR
FSKDTA
On
Bias
Source
120 kΩ
Bias Voltage
120 kΩ FSKOUT
FSK
On
868 PA
PLL PAOUT
MHz
IC
Power_Mode.wmf
Table 3-8 provides a listing of how to get into the different power modes
Table 2-8
PDWN FSKDTA ASKDTA MODE
Low1) Low, Open Low, Open
POWER DOWN
Open2) Low Low
Other combinations of the control pins PDWN, FSKDTA and ASKDTA are not
recommended.
Functional Description
High
FSKDTA
Low
to t
DATA
Open, High
ASKDTA
Low
to t
min. 1 msec.
ASK_mod.wmf
DATA
High
FSKDTA
Low
to t
High
ASKDTA
Low
to t
min. 1 msec.
FSK_mod.wmf
Functional Description
High
PDWN
Low
to t
DATA
Open, High
ASKDTA
Low
to t
min. 1 msec.
Alt_ASK_mod.wmf
High
PDWN
Low
to t
Open, High
ASKDTA
Low
to t
DATA
Open, High
FSKDTA
Low
to t
min. 1 msec.
Alt_FSK_mod.wmf
Applications
X2SMA
C8
C2
C4
L2
L1
VCC
C7
433 (868)
MHz C3 C6
Q1
0.85 (3.4)
MHz
16
15
14
13
12
11
10
9
6.78 (13.56)
MHz
TDK 5100
1
2
3
4
5
6
7
8
C1
VCC
T1 R3A
VCC
R3F
R4
R2
ASK FSK
C5
R1
X1SMA
50ohm_test_v5.wmf
Applications
Applications
R1 4.7 kΩ 0805, ± 5%
R2 12 kΩ 0805, ± 5%
R3A 15 kΩ 0805, ± 5%
R3F 15 kΩ 0805, ± 5%
R4 open 0805, ± 5%
C1 47 nF 0805, X7R, ± 10%
C2 39 pF 47 pF 0805, COG, ± 5%
C3 3.9 pF 1.8 pF 0805, COG, ± 0.1 pF
C4 330 pF 100 pF 0805, COG, ± 5%
C5 1 nF 0805, X7R, ± 10%
C6 8.2 pF 0805, COG, ± 0.1 pF
C7 0Ω 434MHz: 22 pF 0805, COG, ± 5%
Jumper 868MHz: 47pF 0805, 0Ω Jumper
C8 15 pF 8.2 pF 0805, COG, ± 5%
L1 100 nH 33 nH TOKO LL2012-J
L2 39 nH 15 nH 39 nH: TOKO LL2012-J
15 nH: TOKO LL1608-J
Q1 13.56875 MHz, Tokyo Denpa TSS-3B
CL=20pF 13568.75 kHz
Spec.No. 10-50205
IC1 TDK5100
T1 Push-button replaced by a short
X1 SMA-S SMA standing
X2 SMA-S SMA standing
Applications
Note the specified operating range: 2.1 V to 4.0 V and −40°C to +125°C.
8,00
7,00
6,00
5,00
4,0V
Pout [dBm]
4,00 3,0V
3,00 2,1V
2,0V
2,00
1,9V
1,00
0,00
-1,00
-2,00
-50 0 50 100 150
T [°C]
pout_over_temp_434.wmf
8,00
7,50
7,00 4,0V
3,0V
Is [mA]
6,50 2,1V
2,0V
6,00 1,9V
5,50
5,00
-50 0 50 100 150
T [°C]
Is_over_temp_434.wmf
Applications
Note the specified operating range: 2.1 V to 4.0 V and −40°C to +125°C.
6,00
5,00
4,00
3,00
4,0V
Pout [dBm]
2,00
3,0V
1,00 2,1V
0,00 2,0V
1,9V
-1,00
-2,00
-3,00
-4,00
-50 0 50 100 150
T [°C]
pout_over_temp_868.wmf
8,00
7,50
7,00 4,0V
3,0V
Is [mA]
6,50 2,1V
2,0V
6,00 1,9V
5,50
5,00
-50 0 50 100 150
T [°C]
is_over_temp_868.wmf
Applications
The crystal oscillator achieves a turn on time less than 1 msec when the
specified crystal is used. To achieve this, a NIC oscillator type is implemented
in the TDK 5100. The input impedance of this oscillator is a negative resistance
in series to an inductance. Therefore the load capacitance of the crystal CL
(specified by the crystal supplier) is transformed to the capacitance Cv.
-R L f, CL Cv
IC
1
Cv = Formula 1)
1
+ω2L
CL
1
Cv = = C6
1
+ω 2L
CL
Applications
FSKDTA
FSKOUT
Csw
-R L f, CL Cv1 Cv2
COSC
IC
The frequency deviation of the crystal oscillator is multiplied with the divider
factor N of the Phase Locked Loop to the output of the power amplifier. In case
of small frequency deviations (up to +/- 1000 ppm), the two desired load
capacitances can be calculated with the formula below.
∆f 2(C 0 + CL )
CL # C 0 (1 + )
N * f1 C1
CL ± =
∆f 2(C 0 + CL )
1± (1 + )
N * f1 C1
Because of the inductive part of the TDK 5100, these values must be corrected
by Formula 1). The value of Cv± can be calculated.
Applications
If the FSK switch is closed, Cv_ is equal to Cv1 (C6 in the application diagram).
If the FSK switch is open, Cv2 (C7 in the application diagram) can be calculated.
The CLKOUT pin is an open collector output. An external pull up resistor (RL)
should be connected between this pin and the positive supply voltage. The
value of RL is depending on the clock frequency and the load capacitance CLD
(PCB board plus input capacitance of the microcontroller). RL can be calculated
to:
1
RL =
fCLKOUT * 8 * CLD
Table 3-2
fCLKOUT= fCLKOUT=
847 kHz 3.39 MHz
Even harmonics of the signal at CLKOUT can interact with the crystal oscillator
input COSC preventing the start-up of oscillation. Care must be taken in layout
by sufficient separation of the signal lines to ensure sufficiently small coupling.
Applications
The power amplifier operates in a high efficient class C mode. This mode is
characterized by a pulsed operation of the power amplifier transistor at a current
flow angle of θ<<π. A frequency selective network at the amplifier output
passes the fundamental frequency component of the pulse spectrum of the
collector current to the load. The load and its resonance transformation to the
collector of the power amplifier can be generalized by the equivalent circuit of
Figure 3-8. The tank circuit L//C//RL in parallel to the output impedance of the
transistor should be in resonance at the operating frequency of the transmitter.
VS
L C RL
Equivalent_power_wmf.
The optimum load at the collector of the power amplifier for “critical” operation
under idealized conditions at resonance is:
V S2
R LC =
2 * PO
The theoretical value of RLC for an RF output power of Po= 5 dBm (3.16 mW) is:
32
R LC = = 1423 Ω
2 * 0 .00316
Applications
PO
E=
VS I C
ROPT ~ VS
and
POUT ~ ROPT
0 *E
o [m W ]
7
6
5
4
3 10*E
2
Po
1
0
0 1000 2000 3000
R L [O h m ]
Power_output.wmf
Figure 3-9 Output power Po (mW) and collector efficiency E vs. load resistor RL.
The DC collector current Ic of the power amplifier and the RF output power Po
vary with the load resistor RL. This is typical for overcritical operation of class C
amplifiers. The collector current will show a characteristic dip at the resonance
frequency for this type of “overcritical” operation. The depth of this dip will
increase with higher values of RL.
Applications
As Figure 3-10 shows, detuning beyond the bandwidth of the matching circuit
results in an increase of the collector current of the power amplifier and in some
loss of output power. This diagram shows the data for the circuit of the test
board at the frequency of 434 MHz. The behaviour at 868 MHz is similar. The
effective load resistance of this circuit is RL = 700 Ω, which is the optimum
impedance for operation at 3 V. This will lead to a dip of the collector current of
approx. 40%.
Ic [mA ]
Po [d B m]
0
420 430 440 450
f [M H z ]
pout_vs_frequ.wmf
C3, L2-C2 and C8 are the main matching components which are used to
transform the 50 Ω load at the SMA-RF-connector to a higher impedance at the
PA-output (700 Ω @ 3 V). L1 can be used for some finetuning of the resonant
frequency but should not become too small in order to keep its losses low.
Applications
LoadImpedance50ohmBoard.wmf
Above you can see the measurement of the evalboard with a span of 100 MHz.
The evalboard has been optimized for 3 V. The load is about 700+j0 Ω at
the transmit frequency.
A tuning-free realization requires a careful design of the components within the
matching network. A simple linear CAE-tool will help to see the influence of
tolerances of matching components.
Suppression of spurious harmonics may require some additional filtering within
the antenna matching circuit. The total spectrum of a typical 50 Ω-Output
testboard can be summarized as:
Table 3-3
Frequency Output Power Output Power
434 MHz Testboard 868 MHz Testboard
Fundamental +5 dBm +2 dBm
Fund − 13.56 MHz -81 dBc -78 dBc
Fund + 13.56 MHz -88 dBc -75 dBc
Reference
Table 4-1
Parameter Symbol Limit Values Unit Remarks
Min Max
Junction Temperature TJ −40 +150 °C
Storage Temperature Ts −40 +125 °C
Thermal Resistance RthJA 230 K/W
Supply voltage VS −0.3 +4.0 V
Voltage at any pin Vpins -0.3 VS + 0.3 V
excluding pin 14
Voltage at pin 14 Vpin14 -0.3 2 * VS V No ESD-Diode to
VS
Current into pin 11 Ipin11 -10 10 mA
ESD integrity, all pins VESD -1 +1 kV JEDEC Standard
JESD22-A114-B
ESD integrity, all pins VESD -2 +2 kV JEDEC Standard
excluding pin 14 JESD22-A114-B
Table 4-2
Parameter Symbol Limit Values Unit Test Conditions
Min Max
Supply voltage VS 2.1 4.0 V
Ambient temperature TA -40 125 °C
Reference
Reference
Reference
Reference
Table 4-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -40°C ... +125°C
Parameter Symbol Limit Values Unit Test Conditions
Min Typ Max
Current consumption
Power Down mode IS PDWN 4 µA V (Pins 1, 6 and 7)
< 0.2 V
PLL Enable mode IS PLL_EN 3.5 4.6 mA
Transmit mode IS TRANSM 7 9.5 mA Load tank see
Figure 4-1 and 4-2
Power Down Mode Control (Pin 1)
Power Down mode V PDWN 0 0.5 V VASKDTA < 0.2 V
VFSKDTA < 0.2 V
PLL Enable mode V PDWN 1.5 VS V VASKDTA < 0.5 V
Transmit mode V PDWN 1.5 VS V VASKDTA > 1.5 V
Input bias current PDWN IPDWN 38 µA VPDWN = VS
Output frequency range 1) fOUT, 868 864 869 874 MHz VFSEL = VS
868 MHz-band fOUT = fVCO
Output frequency range fOUT, 433 432 434.5 437 MHz VFSEL = 0 V
433 MHz-band fOUT = fVCO / 2
ASK Modulation Data Input (Pin 6)
ASK Transmit disabled VASKDTA 0 0.5 V
ASK Transmit enabled VASKDTA 1.5 VS V
Input bias current ASKDTA IASKDTA 33 µA VASKDTA = VS
Reference
Table 4-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -40°C ... +125°C
Parameter Symbol Limit Values Unit Test Conditions
Min Typ Max
FSK Modulation Data Input (Pin 7)
FSK Switch on VFSKDTA 0 0.5 V
FSK Switch off VFSKDTA 1.5 VS V
Input bias current FSKDTA IFSKDTA 35 µA VFSKDTA = VS
Reference
Table 4-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -40°C ... +125°C
Parameter Symbol Limit Values Unit Test Conditions
Min Typ Max
Power Amplifier Output (Pin 14)
Output Power 3) at 434 MHz POUT, 434 -0.5 2.4 dBm VS = 2.1 V
transformed to 50 Ohm.
POUT, 434 0.5 5 7 dBm VS = 3.0 V
VFSEL = 0 V POUT, 434 1.5 6.6 dBm VS = 4.0 V
1) The output-frequency range can be increased by limiting the temperature and supply voltage
range.
Minimum fVCO − 1 MHz => Minimum Tamb + 5°C
Maximum fVCO + 1 MHz => Maximum Tamb − 5°C
Maximum fVCO + 1 MHz => Minimum VS + 25 mV, max. + 40 MHz.
3) Matching circuitry as used in the 50 Ohm-Output Testboard for 434 MHz operation.
Tolerances of the passive elements not taken into account.
Range @ 2.1 V, +25°C: 2.4 dBm +/- 0.7 dBm
Typ. temperature dependency at 2.1 V: +0.4 dBm@-40°C and -1.4 dBm@+125°C, reference +25°C
Range @ 3.0 V, +25°C: 5.0 dBm +/- 1.0 dBm
Typ. temperature dependency at 3.0 V: +0.5 dBm@-40°C and -1.9 dBm@+125°C, reference +25°C
Range @ 4.0 V, +25°C: 6.6 dBm +/- 2.0 dBm
Typ. temperature dependency at 4.0 V: +0.6 dBm@-40°C and -3.1 dBm@+125°C, reference +25°C
4) Matching circuitry as used in the 50 Ohm-Output Testboard for 868 MHz operation.
Tolerances of the passive elements not taken into account.
Range @ 2.1 V, +25°C: 0.0 dBm +/- 1.0 dBm
Typ. temperature dependency at 2.1 V: +0.6 dBm@-40°C and -2.5 dBm@+125°C, reference +25°C
Range @ 3.0 V, +25°C: 2.0 dBm +/- 2.0 dBm
Typ. temperature dependency at 3.0 V: +0.9 dBm@-40°C and -3.6 dBm@+125°C, reference +25°C
Range @ 4.0 V, +25°C: 3.2 dBm +/- 2.7 dBm
Typ. temperature dependency at 4.0 V: +1.3 dBm@-40°C and -4.0 dBm@+125°C, reference +25°C