2010 International Symposium on Electronic System Design
Energy Efficient and Process Tolerant Full Adder Design in Near Threshold Region
using FinFET
Aminul Islam
Department of Electronics and Communication Engg.
Birla Institute of Technology (Deemed University)
Mesra, Ranchi, Jharkhand, India
Email: aminulislam@bitmesra.ac.in
Abstract-- This paper investigates a robust 1-bit static full
adder using FinFET at near-threshold region (NTR), a
design space where the supply voltage is approximately
equal to the threshold voltage of the transistors. This region
provides minimum-energy point for the different frequency
of operation with more favorable performance and
variability characteristics. The proposed design features
higher computing speed (by 4.49  ) and lower energy (by
T
3.90  ) at the expense of 1.13  higher power dissipation.
T
T
T
T
The proposed design also offers 1.38× improvements in
power variability, 2.19× improvements in delay variability
and 2.41× improvement in power delay product (PDP)
variability against process, voltage, and temperature (PVT)
variations. The power, speed and energy evaluation has been
T
carried out using extensive simulation on HSPICE circuit
simulator. The simulation results are based on 32nm
Berkeley Predictive Technology Model (BPTM). T
Keywords- variability; power delay product; (PDP); near-
threshold region (NTR)
I. INTRODUCTION
Addition is a fundamental arithmetic operation and is
the base of many other commonly used arithmetic blocks
in most of the microelectronic systems. Therefore, 1-bit
full adder cell is the most important basic block of an
arithmetic unit of a digital system. It is necessary to
improve the performance of full adder cell for fast and low
energy operations of arithmetic block [1-2]. There is a
pressing need to investigate the performance of multi gate
device with qualitative optimization of device parameters
for low power, high performance and more reliable digital
circuit design in VLSI. In recent technology era increasing
demand of battery operated devices insist for high speed as
well as low energy operation. As a result, designing low-
power and high-performance full adder cells is of great
interest [2]. The aim to increase battery life of handy
electronic devices is to decrease the energy consumed per
arithmetic operation. However lower power consumption
does not necessarily bring about lower energy dissipation
and higher performance. Low power operation using
scaled supply voltage reduces the operating frequency of
the device. Commonly used strategy to reduce the power
consumption is to scale the supply voltage but it increases
the sensitivity of device to process variations and reduces
the yield. Since at very low voltage Si-MOSFETs are more
prone to variation it is necessary to investigate and
compare variation effects in more promising DG FinFET.
In the last five years it has been shown that operating
the device at minimum energy point (MEP) gives large
penalty in delay, where as minimum energy delay point
978-0-7695-4294-2/10 $26.00 © 2010 IEEE
DOI 10.1109/ISED.2010.19
M.W. Akram, Ale Imran, Mohd. Hasan
Department of Electronics Engineering
Zakir Husain College of Engg. and Technology
Aligarh Muslim University, Aligarh, U.P., India
Email: akrammw@gmail.com
(MEDP) gives better circuit performance in terms of delay
as well as energy and turn out to be the center of attraction
for the researchers. However there is a new class of circuit
applications which demands for ultra low energy
consumption with moderate throughput. These circuits
must be operated at MEP to achieve energy at ultra low
level. This represents an important mind-shift: rather than
starting out from a design optimized for maximum
performance. The initial design point is now the minimum-
energy one. It has been shown that for most of the digital
circuits minimum energy point occurs in the subthreshold
operational region of the MOS transistors [3-7]. However,
performance degradation due to minute leakage current as
drive current and more sensitivity for process variation due
to exponential dependency of drive current on threshold
voltage limits its application area. Hence there is pressing
need to overcome these limitations by device technology
parameter optimization or selecting operating point of the
device where both energy and speed are in acceptable
range. Our proposed method is to design energy efficient
and moderate performance 1-bit full adder in moderate
inversion region (MIR) [8], where devices are operated at
or near their threshold voltage. In the moderate inversion
region (MIR), the dependencies of MOSFET drive current
on VDD, Vth and temperature come closer to exponential. As
a result, MIR designs show a striking increase in
performance uncertainty.
In this paper, a static 1-bit full adder cell using FinFET
[9-13] has been proposed. Moreover it also provides the
variability analysis of the full adder cell against process,
voltage, and temperature (PVT) variations. The
implementation of the full adder cell using conventional
MOSFET and FinFET has been performed in the near-
threshold region (NTR). FinFET based full adder cell is
also used to provide more robust circuit compared to the
conventional MOSFET based full adder cell. The analysis
and comparison developed here for full adder cell
operating at a frequency of 100 MHz have been carried out
with simulation runs on HSPICE for 32nm technology
node using Berkeley Predictive Technology Model
(BPTM) [14].
The rest of the paper is organized as follows. Section II,
briefly describes the structure of selected full adder cell.
Multi-gate (MuGFET) devices structure is reported in
Section III. Performance analysis and comparison of
FinFET and Si-MOSFET is carried out in Section IV.
Process, voltage, and temperature (PVT) variation effects
on performance parameters FinFET is explored using
sufficient Monte-Carlo simulation run in Section V.
Conclusions are drawn in Section VI.
56
 II. THE 1-BIT FULL ADDER CELL
The full-adder function can be described as follows:
Given the three inputs A, B, and Cin . It is desired to
calculate the two outputs Sum and C out , where
Sum  A  B  C in
C out  A.B  C in .( A  B)
Several logic styles have been used in the literature to
design full adder cells. Each design style has its own
merits and demerits. Classical designs of full adders
normally use only one logic style for the whole full-adder
design. One example of such design is the standard static
CMOS full adder shown in Fig. 1. This full adder is based
on regular CMOS structure with conventional pull-up and
pull-down transistors providing full-swing output and good
driving capabilities. The main drawback of static CMOS
circuits is the existence of the PMOS block, because of its
low mobility compared to the NMOS devices. Therefore,
the PMOS devices need to be sized up to attain the desired
performance. The input capacitance of a static CMOS gate
is large because each input is connected to the gate of at
least a PMOS and an NMOS device.
III. MULTI-GATE(MUGFET) DEVICE
Technology parameters of the conventional device
scales down aggressively to reduce the power
consumption and also to increase the transistors density
per chip. But beyond submicron region increased static
leakage power dissipation and increased sensitivity for
process variation in performance parameter cause major
bottleneck for further technology scaling. Research has
been shown that the promising multi-gate transistor [10-
13] offers remarkable advantages in terms of different
design metrics. It increases the driving current with the
sub-threshold and gate tunneling leakage currents within
acceptable limit as compared to the standard single-gate
MOSFETs. The multiple electrically coupled gates and
the thin silicon body suppress the short-channel effects
(SCE), hence reducing the subthreshold leakage current in
a multi-gate MOSFET. Reduced SCE improves
subthreshold slope allows to increase the oxide thickness
which results in lower gate leakage current and hence
reducing the total leakage power dissipation.
Figure 1. Standard CMOS 1-bit full adder cell with conventional
MOSFET [2]
(1)
(2)
Figure 2. Symmetric FinFET architecture. L: gate length. tsi: fin
thickness. Hfin: fin height. tox: oxide thickness [12].
It has been also observed from the previous research that
multi-gate devices shows better parameters variation
immunity than conventional single gate device. The most
striking multi-gate device is the FinFET [12] due to the
self alignment of the two gates and the relative
compatibility with the existing standard CMOS
fabrication process. The architecture of a double-gate
FinFET with symmetric gates is shown in Fig. 2.
IV. ANALYSIS OF FULL ADDER CELL
The 1-bit static CMOS full adder cell is analyzed with
different supply voltages above and below the threshold
voltage for the different frequency of applications.
Structure was simulated with load capacitance of 50fF and
temperature at 50°C with minimum size transistors. The
minimum size transistors have been chosen to minimize
the area occupancy. The Berkeley Predictive Technology
Model (BPTM) considered for MOSFET is the 32nm high-
k metal gate, which is the Intel's latest silicon process
technology. Over the last 15 years Intel has led the
industry in transistor gate dielectric scaling using silicon
dioxide (SiO2) for seven logic-process generations.
However as the transistors get smaller, leakage current can
increase. Managing that leakage is very important for high-
speed and reliable operation. Intel has made a noteworthy
breach in solving the chip power problem, identifying a
new high-k (Hi-k) material called hafnium (HfO 2 ) to
B B
replace the transistor's SiO2 gate dielectric, and new
metals to replace the polysilicon gate electrode of NMOS
and PMOS transistors. These novel materials, along with
the right process method, diminish gate leakage more than
100-fold, while delivering record transistor performance.
The proposed design implementation of the full adder cell
using FinFET provides even more energy efficient and
Delay efficient while enabling more robust circuit. The
proposed design of full adder cell is implemented by
replacing all the N-type MOSFET and P-type MOSFET
used in conventional CMOS 1-bit full adder by its N-type
FinFET and P-type FinFET structure shown in Fig. 3. The
threshold voltages for MOSFET technology has been
considered similar to that of FinFET technology, to
provide further improvement in delay, PDP and also to
find out the optimum operating voltage for the same
technology. The threshold voltage of 0.29V has been
considered for 32nm technology.
Power delay product (PDP) of the full adder cell for
different combinations of supply voltage is reported in Fig.
4, Fig. 5, and Fig. 6. It is observed from Fig. 4 and Fig. 5
that the minimum-energy point for the full adder cell using
57
MOSFET technology is at operating supply voltage of
V DD = 0.4V for an input frequency of 1MHz and 10MHz
B B

and for an input frequency of 100MHz the operating PDP at different supply voltage
supply voltage is at V DD = 0.3V. However, the full adder
B B
( Operating frequency at 1MHz )
300

Power Delay Product ( X E-18 J )

cell using FinFET is having the minimum-energy point at
V DD = 0.3V for all the frequency mentioned above. It is
B B

250 MOSFET
clear from Fig. 4 and Fig. 5 that the PDP increases in
above threshold region; this is because dynamic energy 200 FinFET
increases as the supply voltage increases, which are the 150
dominant contributor for total energy consumption. As the
supply voltage becomes lower than the threshold voltage 100
and decreases, the PDP increases, since leakage energy
50
becomes the dominant contributor for the total energy
consumption. In the sub-threshold region as the supply 0
voltage reduces leakage energy increases at a faster rate 0.1 0.2 0.3 0.33 0.4 0.5 0.6 0.7 0.8 0.9
than the dynamic energy, because delay increases Supply Voltage ( V )
tremendously [15]. What reduction in dynamic energy we
get because of reduction in supply voltages it is less than
what penalty we suffer from increase in leakage energy, Figure 4. PDP of the full adder cell for different supply voltages at
because of the increase in delay? It is observed from Fig 4 frequency=1MHz
that the transistors of full adder cell operate in all three
region of operation at frequency of 1MHz. It is clear from
Fig. 5 that the transistors of full adder cell is also operating
PDP at different supply voltage
in all three region of operation at frequency of 10MHz.
( Operating frequency at 10MHz )
Fig. 6 shows that the transistors of full adder cell operates

Power Delay Pro du ct ( X E-18 J )

only in near-threshold and super-threshold region of 525
operation at frequency of 100MHz. At frequency higher 450 MOSFET
than 100MHz the transistors of full adder cell will also FinFET
375
operate in only near-threshold and super-threshold region.
Three different frequency of operation is considered only 300
to find out the minimum energy point, in all three regions 225
like super-threshold, near-threshold and sub-threshold
150
region of operation. However if the transistor operates in
near-threshold region or super-threshold region of 75
operation then the circuits can operate at a much higher 0
frequency than the circuit operates in sub-threshold region. 0.2 0.3 0.33 0.4 0.5 0.6 0.7 0.8 0.9
Therefore after finding out the minimum energy point at Supply Voltage ( V )
all frequency, which is at the supply voltage of VDD =
0.30V, the operating frequency of 100MHz has been
considered for the near-threshold region of operation.
Figure 5. PDP of the full adder cell for different supply voltages at
Extensive simulation on HSPICE was carried out to frequency=10MHz
establish the optimum supply voltage and found that VDD =
0.33V is the optimum operating voltage in the near-
threshold region (NTR). This supply voltage has been PDP at different supply voltage
chosen, to minimize the effect of delay penalty and also to ( Operating frequency at 100MHz )
consider the parameter variation effects by 10%, though
3500
Power Delay Product ( X E-18 J )

VDD = 0.30V is the optimum operating voltage in the near-

MOSFET
threshold region (NTR), which provides minimum-energy 3000
point. Process parameters of FinFET structures optimized FinFET
2500
in [12] are used in the proposed design.
2000
1500
1000
500
0
0.3 0.33 0.4 0.5 0.6 0.7 0.8 0.9
Supply Voltage ( V )

Figure 6. PDP of the full adder cell for different supply voltages at
Figure 3. N-type FinFET and P-type FinFET Structure used in the frequency=100MHz
proposed full adder cell design

58
 TABLE I. DIFFERENT PERFORMANCE PARAMETERS FOR
THE FULL ADDER CELL AT SUPPLY VOLTAGE@0.33V
Delay at different supply voltages
Technology Different Design Metrics
T

( Operating frequency at 100MHz )

used Power Delay T Power Delay
 10 S  Product
T

Dissipation 10 25
 10 08
W  T

10 J 16
20
MOSFET

Delay ( X E-10 S )
MOSFET 64.3(0.9) 19.2(4.5) 12.3(3.9) FinFET
FinFET 73.9(1) 4.27(1) 3.16(1)
15

The values of power dissipation, delay and PDP are 10

normalized with respect to FinFET and are reported in
bracket in Table I. It is observed from Fig. 8 that FinFET 5
based adder consumes higher power dissipation compared
to MOSFET based full adder cell for all combination of 0
supply voltage, since FinFET is having higher driving 0.3 0.33 0.4 0.5 0.6 0.7 0.8 0.9
current [12-13] at the same supply voltage, due to the Supply Voltage ( V )
presences of double gate. Though the leakage power
dissipation for the FinFET structure is less than the single
gate MOSFET structure, however increase in dynamic Figure 7. Delay of the full adder cell for different supply voltages
power dissipation is higher than the reduction in leakage
power dissipation. It is clear from Fig. 7 that full adder
cell with FinFET provides less delay than the full adder Average Power at different supply voltages
cell with conventional MOSFET for all combination of (Operating frequency at 100MHz )
supply voltage, since FinFET is having higher current
700
driving capability for the same supply voltage, moreover
with lower gate capacitances [12-15]. The full adder cell Av erage Po wer ( X E-07 W ) 600 MOSFET
with FinFET offers the lower PDP than full adder cell with FinFET
500
MOSFET, since reduction in delay outweigh the increase
in power dissipation at the same supply voltage. From 400
Table I we observed that the full adder cell with FinFET
300
structure at optimum operating voltage offers 4.49  T

improvements in delay and 3.90  improvements in PDP T

T
200
at the expense of 1.13  higher power dissipation. An
T

100
T

improvement in delay and penalty in power dissipation is

because of higher current driving capability of FinFET 0
structure for the same supply voltage and also 0.3 0.33 0.4 0.5 0.6 0.7 0.8 0.9
improvement in gate capacitances. There is an Supply Voltage ( V )
improvement in PDP also, since reduction in delay
outperforms the increase in power dissipation. Figure 8. Average Power of the full adder cell for different supply
voltages
V. PVT VARIATION INVESTIGATION
As can be seen, all the mentioned parameters
T Due to aggressive scaling, random variations in affecting (t p ) are process, voltage or temperature B B

process, supply voltage and temperature (P, V, T) are dependent. Within-die delay variations among critical
posing a major challenge to high performance circuits and paths causes both mean (µ) and standard deviation (σ) of
system design [16-18].The process variations include die frequency distribution. Therefore; propagation delay
T

variation in oxide thickness, channel length in short (t p ) along with average power dissipation (P) and Power
T B B T

channel devices, channel width in narrow channel devices, Delay Product (PDP) have been taken as an important
substrate doping concentration, channel doping design metrics for the analysis and design of full adder
concentration, polysilicon gate doping concentration, circuit in this paper. PVT variations can be mitigated by
source/drain sheet resistance. All these process parameters various design techniques. Adaptive body biasing is one
affect V th , which in turn modulates the drain to source
B B

such technique [20]. Circuit design techniques such as

current I DS . The ubiquitous portable devices demand for
B B

body biasing will help, but their effect diminishes with

low power causing supply voltage scaling thereby making technology scaling [21]. The adder is one of the most
voltage variations a major problem for system important and critical building block of any Digital
performance. The growth in operating frequency has System. Hence, optimization of the adder in terms of speed
caused high junction temperature and within-die (WID) and power consumption is necessary and beneficial. Its
temperature variation. Within-die temperature fluctuations robustness against PVT variations is even more important
have existed as a major performance and packaging and essential in deep submicron technology. This paper
challenge for many years. The propagation delay (t p ) of a B B

investigates for the first time to the best of our knowledge

circuit [19] is a function of t pHL and t pLH which are in turn
B B B

static CMOS 1-bit full adder against process, voltage, and

function of V th , load capacitance C L , supply voltage V DD
B B B B B B

temperature (PVT) variations at 32nm technology node in

and gain factor (β=µε/tox(W/L)). the near-threshold region.

59
 TABLE II. PERCENTAGE VARIABILITY FOR AVERAGE
POWER, DELAY, AND PDP UNDER PVT VARIATIONS AT
SUPPLY VOLTAGE@0.33V
Different Technology used
%Variability   
T
Design Metrics  
 
Power MOSFET 9.52(1.38)
Dissipation FinFET 6.9(1)
Delay MOSFET 14.4(2.19)
FinFET 6.58(1)
Power Delay MOSFET 9.23(2.41)
Product FinFET 3.83(1)
Moreover, it also provides a static CMOS 1-bit full adder
using FinFET for more robust circuit implementation
against PVT variations. This comparison has been carried
in terms of ±3σ process parameters, supply voltage (V DD ),
and temperature variations (±10%) by applying Gaussian
distribution and Monte Carlo analysis at 32nm technology
node using HSPICE. The spread in power dissipation,
delay and PDP are normalized with respect to that of
FinFET and are reported in bracket. It is observed from
Table II, that the full adder cell with FinFET at optimum
operating voltage offers 1.38× improvement in power
variability, 2.19 × improvements in delay variability and
2.41× improvement in PDP variability against PVT
variations, besides having less Delay, and PDP. FinFET
based full adder cell offers more robust circuit compared to
conventional MOSFET based full adder cell, since it
minimizes the short channel effects and process variation
effects due to the presence of double gate, and intrinsic
characteristics which provides superior controllability over
the channel.
VI. SUMMARY AND C ONCLUSION
This paper presents a FinFET-based full adder cell
operating in the near-threshold region (NTR). It has been
optimized in terms of overall average power, delay, and
energy efficiency through the selection of optimum
operating voltage and the optimized process parameters. It
is found that the full adder cell with FinFET structure
provides higher switching speed and energy efficiency as
compared to full adder cell with conventional MOSFET at
optimum operating voltage. The proposed design also
offers tight spread in power consumption, delay, and PDP
against PVT variations. Therefore, MOSFETs in full adder
cell can be effectively replaced by the FinFET structure to
optimize overall average power, delay, and energy, thereby
making the design more robust against process variations.
REFERENCES
[1] H. T. Bui, Y. Wang, and Y. Jiang, “Design and analysis of low-
power 10-transistor full adders using XOR–XNOR gates,” IEEE
Trans Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no.
1, pp. 25–30, Jan.2002.
[2] A.M. Shams, T.K. Darwish, M.A. Bayoumi, “Performance analysis
of low-power 1-bit CMOS full adder cells,” IEEE Transactions on
VLSI Systems, Vol. 10, pp. 20–29, Jan.2002.
[3] B. Calhoun, A. Wang, and A. Chandrakasan, “Modeling and sizing
for minimum energy operation in subthreshold circuits’’,IEEE J.
Solid-State Circuits, vol. 40, no. 9,pp. 1778–1786, Sep. 2005.
[4] B. Zhai et al., “A 2.60 pJ/inst subthreshold sensor processor for
optimal energy efficiency’’, in IEEE Symp. VLSI Circuits
Dig.Tech. Papers, 2006, pp. 154–155.
[5] R. Swanson and J. Meindl, “Ion-implanted complementary MOS
transistors in low-voltage circuits’’, IEEE J. Solid-State Circuits,
vol. 7, no. 2, pp. 146–153, 1972.
[6] C. Enz, F. Krummenacher, and E. Vittoz, “An analytical MOS
transistor model valid in all regions of operation and dedicated to
low-voltage and low-current applications’’, J. Analog IC Signal
Proc., vol. 8,no. 1, pp. 83–114, Jul. 1995.
[7] E. A. Vittoz, “Weak inversion for ultimate low-power logic’’, in
Low-Power Electronics Design, C. Piguet, Ed. Boca Raton, FL:
CRC,2005.
[8] Dejan Markovic, Cheng C. Wang, Louis P. Alarcon, Tsung-Te Liu,
B B
and Jan M. Rabaey, “Ultralow-power design in near-threshold
region”, Proceedings of the IEEE, Vol. 98, No. 2, February 2010.
[9] H. Shang et al., “Investigation of FinFET devices for 32nm
technologies and beyond,” Proceedings of the IEEE Symposium on
VLSI Technology, pp. 54-55, June 2006.
[10] K. Kim et al., “Leakage power analysis of 25-nm double-gate
CMOS devices and circuits,” IEEE Transactions on Electron
Devices, Vol. 52, No.5, pp. 980-986, May 2005.
[11] E. Nowak et al., “Turning silicon on its edge,” IEEE Circuits &
Devices Magazine, Vol. 20, No. 1, pp. 20-31, January/February
2004.
[12] Sherif A. Tawfik, Volkan Kursun, “FinFET technology
development guidelines for higher performance, lower power, and
stronger resilience to parameter variations,” mwscas, pp.431-434,
2009 52nd IEEE International Midwest Symposium on Circuits
and Systems, 2009.
[13] Ramesh Vaddi, S. Dasgupta, and R. P. Agarwal, “Device and
circuit co-design robustness studies in the subthreshold logic for
ultralow-power applications for 32 nm CMOS’’, IEEE
Transactions on Electron Devices, vol. 57, issue 3, pp. 654-664,
2009.
[14] Berkeley Predictive Technology Model: Device Group, University
of California at Berkeley [online] Available: http://www-
H
device.eecs.berkeley.edu/~ptm .H
[15] Xiaoxia Wu, Feng Wang, and Yuan Xie. “Analysis of subthreshold
Finfet circuit for ultra-low power design.” Proceedings of IEEE
International System-on-Chip Conference (SOCC), pp. 91-93,
Sept. 2006.
[16] Bowman, K., et al., “Impact of die-to-die and within die parameter
fluctuations on the maximum clock frequency distribution for
gigascale integration”, IEEE Journal of Solid-state Circuits,
Volume 37, Feb 2002, pp.183-190.
[17] S. Borkar, et al., “Parameter Variations and Impact on Circuits and
Microarchitecture”, ACWIEEE DAC, pp. 338-342, June 2003.
[18] T. Karnik, et al., “Probabilistic and variation- tolerant design: key
to continued Moore’s law”, ACWSIGDAIIEEE TAU Workshop,
Austin, pp. 66, February 2000
[19] Sung-Mo Kang and Yusuf Leblebici, “CMOS digital integrated
circuits – analysis and design”, 3/e, TMH, 2003.
[20] James W. Tschanz, et al., “Adaptive body bias for reducing
impacts of die-to-die and within-die parameter variations on
microprocessor frequency and leakage”, IEEE Journal of Solid
State Circuits, Vol. 37, No. 11, November 2002.
[21] S. Borkar, “Design challenges of technology scaling”, IEEE Micro,
vol. 19, no. 4, Jul.- Aug. 1999, pp. 23-29.
60