A1425 Datasheet PDF

A1425
High Accuracy Analog Speed Sensor IC with Integrated Filter

Capacitor and Dual Zero-Crossing Output Signal
Features and Benefits Description
▪ Used in sensing motion of ring magnet or ferrous targets The A1425 AC-coupled Hall-effect sensor IC is a monolithic
▪ Integrated filter capacitor integrated circuit that switches in response to changing
▪ Wide operating temperature range differential magnetic fields created by rotating ring magnets
▪ Operation with magnetic input signal frequency from and, when coupled with a magnet, by ferrous targets. The device
20 Hz to 20 kHz is a true zero-crossing detector: the output switches precisely
▪ Resistant to EMI when the difference in magnetic field strength between the
▪ Large effective air gaps two Hall elements is zero. A unique dual-comparator scheme
▪ 4.0 to 26.5 V supply operating range provides for accurate switching at the zero crossing on both the
▪ Output compatible with both TTL and CMOS logic positive and negative-going regions of the differential signal,
families while utilizing hysteresis to prevent false switching. The zero-
▪ Reverse battery protection crossing nature of this device provides excellent repeatability
▪ Resistant to mechanical and thermal stress and accuracy for crankshaft applications.
▪ Accurate true zero-crossing switchpoint
Changes in field strength at the device face, which are
induced by a moving target, are sensed by the two integrated
Package: 4 pin SIP (suffix K) Hall transducers. The transducers generate signals that are
differentially amplified by on-chip electronics. This differential
design provides immunity to radial vibration within the
operating air gap range of the A1425, by rejection of the
common mode signal. Steady-state magnet and system offsets
are eliminated using an on-chip differential band-pass filter.
This filter also provides relative immunity to interference from
electromagnetic sources.
Continued on the next page…
Functional Block Diagram

VS+
VCC
(Pin 1)
TEST
Diagnostic (Pin 3)
Circuitry
Regulator
Bandpass Filter Integrated
Dual Hall Tracking Capacitor VOUT
Transducers
(Pin 2)
Comparator
0.1 uF Hall Gain

Stage VREF
Amp
GND
(Pin 4) (Required)
1425-DSa, Rev.3
High Accuracy Analog Speed Sensor IC with Integrated
A1425
Filter Capacitor and Dual Zero-Crossing Output Signal
Description (continued)
The device utilizes advanced temperature compensation for the and an output driver, which requires a pull-up resistor. The on-
high-pass filter, sensitivity, and Schmitt trigger switchpoints, board regulator permits operation with supply voltages from 4.0
to guarantee optimal operation to low frequencies over a wide to 26.5 V. The output stage can easily switch 20 mA over the full
range of air gaps and temperatures. frequency response range of the device, and is compatible with
both TTL and CMOS logic circuits.
Each Hall effect digital integrated circuit includes a voltage
regulator, two Hall effect elements, temperature compensating The device is packaged in a 4-pin plastic SIP. It is lead (Pb) free,
circuitry, a low-level amplifier, band-pass filter, Schmitt trigger, with 100% matte tin plated leadframe.
Selection Guide
Switchpoints
Part Number Packing* BRP(MIN) BOP(MAX)
(G) (G)
A1425LK-T Bulk, 500 pieces/bag –11 11
*Contact Allegro for additional packing options.
Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units
Supply Voltage VCC Refer to Power Derating section 28 V
Reverse Supply Voltage VRCC –18 V
Continuous Output Current IOUT 25 mA
Continuous Reverse-Output Current IROUT –50 mA
Operating Ambient Temperature TA Range L –40 to 150 ºC
Maximum Junction TJ(max) 165 ºC
Storage Temperature Tstg –65 to 170 ºC
Pin-out Diagram Terminal List Table

Name Number
VCC 1
VOUT 2
TEST 3
GND 4
1 2 3 4
Allegro MicroSystems, LLC 2

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A1425
OPERATING CHARACTERISTICS Valid at TA = – 40ºC to 150ºC, TJ ≤ 165°C; over operational air gap range and VCC within
operating range, unless otherwise noted. Typical operating parameters: VCC = 12 V and TA = 25°C.
Characteristic Symbol Test Conditions Min. Typ. Max. Units
ELECTRICAL CHARACTERISTICS
Supply Voltage VCC Operating; TJ < TJ(max) 4.0 – 26.5 V
Supply Current ICC – 4.2 7.0 mA
Output Saturation Voltage VOUT(SAT) ISINK = 20 mA – 140 400 mV
Output Leakage Current IOFF VOUT = 24 V, Bdiff = 0 – – 5 μA
PROTECTION COMPONENT CHARACTERISTICS
Reverse Supply Current IRCC VCC = –18 V – – –1 mA
Supply Zener Current IZSupply VS = 28 V – – 10 mA
Supply Zener Clamp Voltage1 VZSupply ICC = 10 mA, TA = 25°C 28 33 37 V
Output Zener Current IZOutput VOUT = 28 V – – 3 mA
Output Zener Clamp Voltage VZOutput IOUT = 3 mA, TA = 25°C 28 – – V
Output Short Circuit Current Limit2 IOUTS(lim) – – 50 mA
RESPONSE CHARACTERISTICS
Power-On State POS t < tResponse – High – V
Power-On Time3,7 tPO VCC > VCC(min) – 4.5 9 ms
Settling Time4,7 tSettle fBdiff ≥ 100 Hz 0 – 50 ms
Response Time7 tResponse Equal to tPO + tS; fBdiff ≥ 100 Hz 4.5 – 59 ms
Upper Corner Frequency fcu –3 dB, single pole 20 – – kHz
Lower Corner Frequency fcl –3 dB, single pole – – 20 Hz
OUTPUT CHARACTERISTICS
Output Rise Time5 tr RPU = 1 kΩ, COUT2 = 10 pF – – 200 ns
Output Fall Time tf RPU = 1 kΩ, ISINK = 20 mA, COUT2 = 10 pF – – 200 ns
MAGNETIC CHARACTERISTICS
Bdiff increasing, fBdiff = 200 Hz, Bdiff = 50 Gp-p;
Output Off Switchpoint6,7 BOP –11 0 11 G
digital output signal switches low to high
Bdiff decreasing, fBdiff = 200 Hz, Bdiff = 50 Gp-p;
Output On Switchpoint6,7 BRP –11 0 11 G
digital output signal switches high to low
Applied Magnetic Field7,8 Bdiff Differential p-p magnetic field 50 – 1250 G
1I
CC equivalent to ICC(max) + 3 mA.
2I
OUT does not change state when IOUT > IOUTS(lim) , regardless of changes in the impinging magnetic field.
3Time required to initialize device.
4Time required for the output switchpoints to be within specification.
5Output Rise Time will be dominated by the RC time constant.
6For other sinusoidal signal frequencies and magnetic fields, –B
OP = BRP = sinα(Bdiff ⁄ 2) ± 25%, where α is the phase shift shown in the Characteristic
Data section.
7See Definitions of Terms section.
8Exceeding the maximum magnetic field may result in compromised absolute accuracy.

A1425
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions Rating Units
Package Thermal Resistance RθJA Single-layer PCB, with copper limited to solder pads 177 ºC/W
Power Derating Curve Maximum Power Dissipation, PD(max)
30 900
28 850
26
VCC(max) 800
750
24
Maximum Allowable VCC (V)
700
22 650
20 600 (R
Power Dissipation, PD (m W)
18 550 θJ
A =
500 17
16 (RθJA = 177 ºC/W) 7
450 ºC
14 /W
400 )
12
350
10 300
8 250
6 200
150
4 VCC(min)
100
2
50
0 0
20 40 60 80 100 120 140 160 180 20 40 60 80 100 120 140 160 180
Temperature (ºC) Temperature (°C)
Definitions of Terms
The following provide additional information about some of output switches from high to low. This value may be greater
the parameters cited in the Operating Characteristics table. than or less than 0 G.
For additional information, visit the Allegro Web site at
Power-On Time, tPO – The time needed by the device, after
www.allegromicro.com.
power is applied, to initialize all circuitry necessary for proper
Applied Magnetic Field, Bdiff – The differential magnetic flux operation.
density which is calculated as the arithmetic difference of the
Settling Time, tSettle – The time required by the device, after tPO,
flux densities observed by each of the two Hall elements.
and after a valid magnetic signal has been applied, to provide
Output Off Switchpoint (Operate Point), BOP – The value of proper output transitions. Settling time is a function of magnetic
increasing differential magnetic flux density at which the device offset, offset polarity, signal phase, signal frequency, and signal
output switches from low to high. This value may be greater than amplitude.
or less than 0 G.
Response Time tResponse – The total time required for generat-
Output On Switchpoint (Release Point), BRP – The value of ing zero-crossing output transitions after power-up (the sum of
decreasing differential magnetic flux density at which the device power-on time and settling time).

A1425
Empirical Results
Supply Current by Ambient Temperature Output Voltage by Ambient Temperature

ISINK = 20 mA
7 500
VCC (V) 450 VCC (V)
6 4.5 4.5
400
12.0
VOUT(SAT) (mV)
12
12.0
5 26
20.0 350 20.0
ICC (mA)
4 300
250
3 200
2 150
100
1 50
0 0
–50 0 50 100 150 200 –50 0 50 100 150 200
TA (ºC) TA (ºC)
Supply Current by Supply Voltage Output Voltage by Supply Voltage

ISINK = 20 mA
7 500
TA (ºC) 450 TA (ºC)
6 150 150
400
VOUT(SAT) (mV)
25 25
5 –40 350
–40
ICC (mA)
4 300
250
3 200
2 150
100
1
50
0 0
0 10 20 30 0 5 10 15 20 25
VCC (V) VCC (V)
Continued on next page.

A1425
Empirical Results, continued
116
Repeatability (º of Rotation)
Air Gap (mm)
116
Repeatability (º of Rotation)
Air Gap (mm)

A1425
Simulation Results
A1425 Minimum Switching Fields

Over the Range of Ambient Operating Temperatures, TA
fBdiff(low) = 15 Hz, fBdiff(high) ≈ 30 kHz
40
35
30
25
25
Bdiff(min) (G)
150
20
–40
15
10
0
0.01 0.1 1 10 40
Frequency, fBdiff (kHz)
A1425 Typical Phase Shift

Over the Range of Applied Magnetic Fields, Bdiff
fBdiff(low) = 15 Hz, fBdiff(high) = 30 kHz
40
30
50
20 100
500
10 750
Phase Shift (º)
0 1250
–10 Bdiff in Gp-p
–20
–30
–40
–50
–60
0.01 0.1 1 10 40
Continued on next page.

A1425
Simulation Results, continued
A1425 Typical Delay

20
15
IOUT Leading
10
IOUT Delay (μs)
5 Bdiff in Gp-p
0
50
–5 12
IOUT Lagging
0
75
0
50
50
–10
100
–15
–20
0.1 1 10 40
Positive values of delay indicate a lagging output, while negative values indicate a leading output.
A1425 Typical Delay

1000
IOUT Leading
0
1250
–1000 750
IOUT Delay (μs)
500
–2000
–3000 Bdiff in Gp-p

IOUT Lagging
–4000
0
10
–5000
50
–6000
0 100
Frequency, fBdiff (Hz)
Positive values of delay indicate a lagging output, while negative values indicate a leading output.

A1425
Device Evaluation: EMC Characterization
Please contact Allegro MicroSystems for EMC performance information.
Test Name Reference Specification

ESD – Human Body Model* AEC-Q100-002
ESD – Machine Model* AEC-Q100-003
Conducted Transients ISO 7637-1
Direct RF Injection ISO 11452-7
Bulk Current Injection ISO 11452-4
TEM Cell ISO 11452-3
*ESD testing is performed with no external components.
Vs
R1
RPU
1
C1 VCC
A1425
4 2
GND VOUT
TEST
COUT2
3
(Required)
Recommended EMC test circuit.
Component Value Units

RPUa 1.2 kΩ
R1b 100 Ω
C1 0.1 μF
COUTc 4.7 nF
aPull-up resistor not required for protection but for normal operation.
bFor improved CI performance
cFor improved BCI performance

A1425
Functional Description
The A1425 is a versatile high-precision differential Hall-effect Start-up

device that can be used in a wide range of applications. Proper
During power-on time, tPO, the output signal, VOUT, is high.
choice of the target material and shape, and assembly techniques Beyond this time, if the applied magnetic field, Bdiff, is absent or
enables large working air gaps and high switchpoint accuracy less than 50 G peak-to-peak, the switching state and VOUT polar-
over the device operating temperature range. ity are indeterminate. VOUT will be valid for Bdiff > 50 Gp-p, after
the additional settling time, tSettle, has also elapsed. Also during
Device Operation
tPO, a circuit in the A1425 is briefly enabled that charges the on-
The A1425 sensor IC contains two integrated Hall transducers chip capacitor. This feature reduces tPO, relative to the long RC
that are used to differentially respond to a magnetic field across time constant of a high-pass filter.
the surface of the IC. Referring to figure 1, the trigger switches Delay
the output off (output high) when the differential magnetic field
The on-chip band-pass filter induces delay in the output signal,
crosses zero while increasing in strength (referred to as the posi-
VOUT, relative to the applied magnetic field, Bdiff. Simulation data
tive direction), and switches the output on (output low) when
shown in the Characteristic Data section quantify the effect of the
the differential magnetic field crosses zero while decreasing (the input signal amplitude on the phase shift of the output.
negative direction).
AC-Coupled Operation
The operation is achieved through the use of two separate com-
Steady-state magnet and system offsets are eliminated using an
parators. Both comparators use the same reference point, 0 G, to
on-chip differential band-pass filter. The low and high frequency
provide high accuracy, but one comparator has a positive hyster-
poles of this band-pass filter are set using internal integrated
esis, BHYS1, and the other a negative hysteresis, BHYS2. Therefore, capacitors and resistors. The differential structure of this filter
one comparator switches (BOP) at the zero crossing on an increas- improves the ability of the IC to reject single-ended noise on
ing differential signal and the other switches (BRP) at the zero the ground (GND pin) or supply line (VCC pin) and, as a result,
crossing on a decreasing differential signal. The hysteresis on makes it more resistant to electromagnetic interference typically
each comparator precludes false switching on noise or target jitter. seen in hostile remote-sensing environments.
11.0 BOP(max) / BRP(max)

BHYS1 
Applied Magnetic BOP(typ)
0.0
Field, Bdiff BRP(typ)

BHYS2
–11.0 BOP(min) / BRP(min)
Comparator 1
Comparator 2
Switching State Off On Off
Output Signal, VOUT t+
Figure 1. Typical output characteristics with dual comparator operation. Characteristics shown without delay, see Characteristic
Data section charts for delay and phase shift contributions.

A1425
Applications Information
Target Selection Power Supply Protection
The zero-crossing switchpoints and AC-coupled operation of this The A1425 contains an on-chip voltage regulator and can oper-
device make target selection important. For high-density target ate over a wide supply voltage range. In applications that operate
geometries or small target features that produce a sinusoidal the device from an unregulated power supply, transient protec-
magnetic signal, the high-pass filter is capable of filtering offsets tion must be added externally. For applications using a regulated
that may be induced in the final device output. If such offset is line, EMI/RFI protection may still be required. The circuit
present, and the target has larger features, then the high-pass shown in figure 3 is the most basic configuration required for
filter may not be effective at higher speeds and an accuracy shift proper device operation.
may occur. These relationships are shown in figure 2.
Large Feature (Tooth) Valley

Differential Magnetic
+B
Flux Density, Bdiff
(a)
0 VCC
1
–B 0.1 uF RPU
+V A1425 2 VOUT
4
Device Output
Voltage, VOUT
0 (Required)
t
Figure 3. Basic application circuit. A pull-up resistor, RPU, is required

Output Edge with the output driver.
Differential Magnetic
Shift
+B
Flux Density, Bdiff
(b)
0
–B
+V
Device Output
Voltage, VOUT
0
t
Figure 2. Large Feature Effects. (a) Large target feature but no device offset,
normal edge position. (b) Large target feature with negative device offset, shifted
(advanced) output edge position.

A1425
Power Derating A worst-case estimate, PD(max), represents the maximum allow-

able power level (VCC(max), ICC(max)), without exceeding
The device must be operated below the maximum junction
TJ(max), at a selected RJA and TA.
temperature of the device, TJ(max). Under certain combina-
tions of peak conditions, reliable operation may require derating Example
supplied power or improving the heat dissipation properties of
the application. This section presents a procedure for correlating Reliability for VCC at TA = 150°C, using minimum-K PCB
factors affecting operating TJ. (Thermal data is also available on
Observe the worst-case ratings for the device, specifically:
the Allegro MicroSystems Web site.)
RJA = 177°C/W, TJ(max) = 165°C, VCC(max) = 26.5 V, and
The Package Thermal Resistance, RJA, is a figure of merit sum- ICC(max) = 7.0 mA.
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air. Calculate the maximum allowable power level, PD(max). First,
Its primary component is the Effective Thermal Conductivity, invert equation 3:
K, of the printed circuit board, including adjacent devices and Tmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C
traces. Radiation from the die through the device case, RJC, is
relatively small component of RJA. Ambient air temperature, This provides the allowable increase to TJ resulting from internal
TA, and air motion are significant external factors, damped by power dissipation. Then, invert equation 2:
overmolding.
The effect of varying power levels (Power Dissipation, PD), can PD(max) = Tmax ÷ RJA = 15°C ÷ 177 °C/W = 84 mW
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD. Finally, invert equation 1 with respect to voltage:
PD = VIN × IIN (1) VCC(est) = PD(max) ÷ ICC(max) = 84 mW ÷ 7.0 mA = 12 V

 T = PD × RJA (2) The result indicates that, at TA, the application and device can
TJ = TA + ΔT (3) dissipate adequate amounts of heat at voltages ≤VCC(est).
For example, given common conditions such as: TA= 25°C, Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reli-
VCC = 5.0 V, ICC = 4.2 mA, and RJA = 177 °C/W, then: able operation between VCC(est) and VCC(max) requires enhanced
RJA. If VCC(est) ≥ VCC(max), then operation between VCC(est)
PD = VCC × ICC = 5.0 V × 4.2 mA = 21.0 mW and VCC(max) is reliable under these conditions.
 T = PD × RJA = 21.0 mW × 177 °C/W = 3.7°C For example, when a standard diode with a 0.7 V drop is used:
TJ = TA + T = 25°C + 3.7°C = 28.7°C VS(max) = 12 V + 0.7 V = 12.7 V

A1425
Package K, 4-pin SIP
+0.08
5.21 –0.05
45°
B
E E
1.50 1.55 ±0.05
2.20
D
NNNN
1.29 E Mold Ejector YYWW
+0.08 Pin Indent
3.43 –0.05
E1 E2 1
45°
Branded
D Standard Branding Reference View
Face
2.16 0.84 REF N = Device part number
MAX Y = Last two digits of year of manufacture
W = Week of manufacture
A
For Reference Only; not for tooling use (reference DWG-9010)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
1 2 3 4
A Dambar removal protrusion (8X)

14.73 ±0.51
B Gate and tie bar burr area
C Branding scale and appearance at supplier discretion
+0.07 +0.06
0.41 –0.05 0.38 –0.03
D Active Area Depth, .0.42 mm
E Hall elements (E1 and E2); not to scale
1.27 NOM
Copyright ©2005-2013, Allegro MicroSystems, LLC

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com


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A1425

High Accuracy Analog Speed Sensor IC with Integrated Filter

Continued on the next page…

Functional Block Diagram

0.1 uF Hall Gain

Absolute Maximum Ratings

Pin-out Diagram Terminal List Table

Allegro MicroSystems, LLC 2

Allegro MicroSystems, LLC 3

Power Derating Curve Maximum Power Dissipation, PD(max)

Temperature (ºC) Temperature (°C)

Allegro MicroSystems, LLC 4

Supply Current by Ambient Temperature Output Voltage by Ambient Temperature

Supply Current by Supply Voltage Output Voltage by Supply Voltage

Continued on next page.

Allegro MicroSystems, LLC 5

Empirical Results, continued

Air Gap (mm)

Air Gap (mm)

Allegro MicroSystems, LLC 6

A1425 Minimum Switching Fields

A1425 Typical Phase Shift

Continued on next page.

Allegro MicroSystems, LLC 7

Simulation Results, continued

A1425 Typical Delay

A1425 Typical Delay

–3000 Bdiff in Gp-p

Allegro MicroSystems, LLC 8

Device Evaluation: EMC Characterization

Please contact Allegro MicroSystems for EMC performance information.

Test Name Reference Specification

Recommended EMC test circuit.

Component Value Units

Allegro MicroSystems, LLC 9

The A1425 is a versatile high-precision differential Hall-effect Start-up

11.0 BOP(max) / BRP(max)

Switching State Off On Off

Output Signal, VOUT t+

Allegro MicroSystems, LLC 10

Large Feature (Tooth) Valley

Figure 3. Basic application circuit. A pull-up resistor, RPU, is required

Allegro MicroSystems, LLC 11

Power Derating A worst-case estimate, PD(max), represents the maximum allow-

PD = VIN × IIN (1) VCC(est) = PD(max) ÷ ICC(max) = 84 mW ÷ 7.0 mA = 12 V

Allegro MicroSystems, LLC 12

Package K, 4-pin SIP

A Dambar removal protrusion (8X)

E Hall elements (E1 and E2); not to scale

Copyright ©2005-2013, Allegro MicroSystems, LLC

Allegro MicroSystems, LLC 13

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