M2 Test System

M2 Test System
Programming and Operations Manual
Revision 4.0
For Revision 5.03 or higher Software Library
Copyright © July, 2006 KVD Company, Inc. All rights reserved.
KVD Company, Incorporated
2465 Impala Drive
Carlsbad, CA 92008
Phone 760-931-5085
Fax 760-931-5092
If you have any comments on this manual, please email them to service@kvdco.com
For software bug reports and feature requests, please email bugs@kvdco.com
Please visit our website at: http://www.kvdco.com
M2 Windows Test System Programming and Operations Manual - Revision 4.0

Table of Contents
Chapter 1: Introduction and Overview
Purpose of the Manual ...................................................................................................... 1-1
Recent Major Changes to the Manual ................................................................................. 1-1
Where to Look for Online Help........................................................................................... 1-1
Quick-Start Guide ............................................................................................................. 1-2
Nomenclature ............................................................................................................. 1-3
Warnings and Cautions ..................................................................................................... 1-3
System Overview.............................................................................................................. 1-4
Feature Summary ............................................................................................................. 1-5
Device Families Tested on the KVD M2............................................................................... 1-6
Chapter 2: Safety and Regulatory Summary

Safety Statement.............................................................................................................. 2-1
Warnings and Cautions ................................................................................................ 2-1
Operator Safety .......................................................................................................... 2-1
Maintenance Personnel Safety...................................................................................... 2-2
General Working Safety.......................................................................................... 2-2
Shock Hazards Contained in the Test System ........................................................... 2-2
Lithium Battery Caution.......................................................................................... 2-2
Electrostatic Discharge ...................................................................................................... 2-3
Protective Grounding ........................................................................................................ 2-3
Ergonomic Statement........................................................................................................ 2-4
Chemicals ........................................................................................................................ 2-4
Ionizing Radiation............................................................................................................. 2-4
Chapter 3: Unpacking and Installation Guide

Physical Installation .......................................................................................................... 3-1
Utilities ............................................................................................................................ 3-1
Environmental .................................................................................................................. 3-1
Maintenance Access Space ................................................................................................ 3-1
Handler/Prober/Laser Trimmer Interfacing ......................................................................... 3-3
Chapter 4: System Hardware

AC Power Distribution Unit ................................................................................................ 4-1
DC Power Control and Flow ............................................................................................... 4-5
CPU Overview .................................................................................................................. 4-9
Packaging................................................................................................................... 4-9
Motherboard ............................................................................................................. 4-10
Contents-1
M2 Test System Programming and Reference Manual
PCIDIS ..................................................................................................................... 4-11

HCIF and PHLIC ........................................................................................................ 4-12
Laser ETTL Interface ................................................................................................. 4-13
CPU Features ............................................................................................................ 4-13
Peripherals ............................................................................................................... 4-14
Communication ......................................................................................................... 4-14
Power Supplies............................................................................................................... 4-14
DC Power Supply Assembly........................................................................................ 4-15
Distribution............................................................................................................... 4-17
Nomenclature of DC Power Wiring.............................................................................. 4-17
Fuses ....................................................................................................................... 4-18
Overtemp Resettable Circuit Breaker .......................................................................... 4-20
Power Supply Variations ............................................................................................ 4-21
Standard Linear Used For M2 Mixed Signal Systems ............................................... 4-21
Mixed Linear/Switcher Used For M2m Test Systems ............................................... 4-21
Enhanced Supply Used For Some M2i Imager Test Systems .................................... 4-21
Converted Supply From a Laser Trim System to an M2m ........................................ 4-21
Power Plus Power Supply ................................................................................................ 4-26
Power Plus (Multi-output Switcher Power Supply) and Power GUI ................................. 4-26
Choosing the Proper Power Supply in the TCT ............................................................. 4-26
DC Output Capabilities............................................................................................... 4-27
Digital Supplies.................................................................................................... 4-27
Analog Supplies ................................................................................................... 4-27
Control Features .................................................................................................. 4-27
Maintainability Features........................................................................................ 4-27
Power Supply GUI................................................................................................ 4-28
Block Diagram........................................................................................................... 4-29
PowerPlus Internal Arrangement ................................................................................ 4-33
PowerPlus Control Wiring........................................................................................... 4-36
Dual Cal Bus Switching .............................................................................................. 4-37
Cables & Connectors....................................................................................................... 4-37
X1 - Calibration Bus and Miscellaneous Signals to Test Head ........................................ 4-37
X2 - Analog DC Power ............................................................................................... 4-38
X3 - Digital DC Power ................................................................................................ 4-39
X4 - Keithley Cal Bus ................................................................................................. 4-40
X5 - CPU Power Control ............................................................................................. 4-41
Hypertronics ............................................................................................................. 4-42
Calibrator....................................................................................................................... 4-43
Optional Calibration Meters ........................................................................................ 4-43
Important Father Card Note - Precision Meter Measurements ....................................... 4-43
Keithley Capabilities and Specifications ....................................................................... 4-43
Modifications............................................................................................................. 4-44
Calibration ................................................................................................................ 4-46
Contents-2
Table of Contents
Test Head ...................................................................................................................... 4-46

Mechanical ............................................................................................................... 4-47
Mother Boards .......................................................................................................... 4-48
Motherboard Bus Signal Definitions ............................................................................ 4-52
Motherboard Digital Bus ....................................................................................... 4-52
Motherboard Interconnect (IC) Bus ....................................................................... 4-53
Motherboard Analog Bus ...................................................................................... 4-54
DISCONT.................................................................................................................. 4-55
Connector Pin Assignments ........................................................................................ 4-56
High Speed Link (HSL) .................................................................................................... 4-57
Father Cards .................................................................................................................. 4-58
DC Power Wiring ....................................................................................................... 4-60
Fuses ....................................................................................................................... 4-61
Grounds ................................................................................................................... 4-62
Relays and Relay Drivers ........................................................................................... 4-63
DUT Cards ................................................................................................................ 4-63
Custom Father Cards ................................................................................................. 4-63
Chapter 5: Calibration and Maintenance

Safety Warning................................................................................................................. 5-1
ESD Warnings and Procedures........................................................................................... 5-1
Instrument Replacement Instructions................................................................................. 5-1
Removing Test Head Instruments................................................................................. 5-1
Inserting Test Head Instruments .................................................................................. 5-1
Repairing Surface Mount Fuses .................................................................................... 5-2
Subassembly Replacement ................................................................................................ 5-2
Power Supply.............................................................................................................. 5-2
CPU ........................................................................................................................... 5-3
Keithley or Agilent DMM............................................................................................... 5-3
Preventive Maintenance .................................................................................................... 5-3
Monthly ...................................................................................................................... 5-3
Software Backups........................................................................................................ 5-5
Installing New KVD Library Releases............................................................................. 5-5
Installing Software on a New Hard Disk.............................................................................. 5-6
Motherboard Driver Support......................................................................................... 5-7
Configuring a Windows XP System ............................................................................... 5-7
Installing Borland C++ Builder 5 .................................................................................. 5-7
Configuring Borland..................................................................................................... 5-8
Installing PCI-GPIB Driver ............................................................................................ 5-9
Installing for PCIDIS, PHLIC, and PowerPlus USB ........................................................ 5-10
Installation Swapping Tool ......................................................................................... 5-17
Offline Emulator Mode - Notester Install........................................................................... 5-17
Contents-3
Notester Emulation Mode........................................................................................... 5-17

Test Head Power Control................................................................................................. 5-18
Power-off Reboot Required to Reload PCIDIS Xilinx ..................................................... 5-18
Tester Configuration Tool - TCT....................................................................................... 5-19
Functional Description ............................................................................................... 5-19
Calibration and Diagnostics ............................................................................................. 5-25
Theory of Calibration ................................................................................................. 5-25
The Ideal Instrument ................................................................................................ 5-26
A Real Instrument ..................................................................................................... 5-27
Calibration Files......................................................................................................... 5-28
A Surprisingly Bad Instrument.................................................................................... 5-29
KVD Calibration and Checker Tool.................................................................................... 5-29
Changes Since Release 5.02....................................................................................... 5-29
Fast Launch Tab ....................................................................................................... 5-30
FPGA Booting Process................................................................................................ 5-30
Simulated LED Results ............................................................................................... 5-31
Aborting a Program in Progress .................................................................................. 5-31
Calibration and Checker Options................................................................................. 5-32
Results Summary Display........................................................................................... 5-33
Recent Improvements to MP and HP Cals.................................................................... 5-33
Explanation of Calibration Activities ............................................................................ 5-33
MPDCMOD Calibration ............................................................................................... 5-34
MPDCMOD Checker ................................................................................................... 5-36
MPUVM Calibration .................................................................................................... 5-37
MPUVM Checker........................................................................................................ 5-38
HPDCMOD Calibration................................................................................................ 5-38
HPDCMOD Checker ................................................................................................... 5-38
DSPIO Calibration...................................................................................................... 5-38
DIGMOD................................................................................................................... 5-38
TMU......................................................................................................................... 5-38
Recalibration of Cal Meter ............................................................................................... 5-38
Other KVD Checkers (Diagnostics) ................................................................................... 5-39
Father Card Checkers ................................................................................................ 5-39
PHLIC Checker .......................................................................................................... 5-39
GPIB Checker............................................................................................................ 5-39
Laser Communications Debugging Tools........................................................................... 5-40
GSI-M310 ................................................................................................................. 5-40
Stop Trim Interface ................................................................................................... 5-41
ESI 2050/2100.......................................................................................................... 5-42
Chapter 6: Development Environment

Software Installation - Offline Emulator .............................................................................. 6-1
Contents-4
Table of Contents
Borland C++ Builder ......................................................................................................... 6-1

Setting Up Your Own Test Application ................................................................................ 6-5
Adding New Files to a Project .......................................................................................... 6-10
Copying KVD Projects Using the KVD Copy Project Tool..................................................... 6-12
The Borland Debugger .................................................................................................... 6-13
Sending Datalog Information to the Debugging Environment ............................................. 6-15
Real Time Interface ........................................................................................................ 6-16
MPDCMOD DUT Source Page ..................................................................................... 6-17
User Voltmeter (UVM) Page ....................................................................................... 6-20
HP DUT Source Page ................................................................................................. 6-21
DSPIO Pins ............................................................................................................... 6-22
DSPIO Patterns (Running and Debugging) .................................................................. 6-23
DSPIO Patterns (Readback) ....................................................................................... 6-24
FC Relays Page (Father Card Relays) .......................................................................... 6-25
DIG Relays Page (Digital Drivers and Analog Bus Relays) ............................................. 6-26
TMU (Time Measurement Unit) .................................................................................. 6-27
DIGMOD Pages ......................................................................................................... 6-28
System Functions Page .............................................................................................. 6-28
Shared Connections - DSPIO, Father Card, RMX, App................................................... 6-29
Changing the Resource Names Shown in the RTI ........................................................ 6-29
Debugging Applications Run From the KVD Launcher ........................................................ 6-30
Plot Tool ........................................................................................................................ 6-30
Setting Up the Plot Object.......................................................................................... 6-31
Loading Data into the Plot Object ............................................................................... 6-31
Viewing the Plot Object ............................................................................................. 6-32
Setup, Logging, Testing and Binning ................................................................................ 6-32
Understanding How the Binning Process Works on a KVD System ................................. 6-33
LIMITS File ............................................................................................................... 6-33
Testing Against the Limits.......................................................................................... 6-34
Extended Limits Editor............................................................................................... 6-35
Loading the Limits File............................................................................................... 6-35
Units ........................................................................................................................ 6-35
Table of All Predefined Units ...................................................................................... 6-35
BIN File .................................................................................................................... 6-36
Setting up a BIN File ................................................................................................. 6-36
Binning Field Explanations ......................................................................................... 6-36
Bin Description Editor ................................................................................................ 6-37
Setting Up and Using Disqualify Binning ........................................................................... 6-38
Creating the New Limits File Using the Extended Limits Editor ...................................... 6-38
Creating a BIN File for the Downgrade Process............................................................ 6-38
Loading the New Limits File Using the Command......................................................... 6-38
Contents-5
Sample Disqualify Datalog Display .............................................................................. 6-39

Interrogating the Bin Status ....................................................................................... 6-39
Bin Trend Setup and Alarms ............................................................................................ 6-40
Bin Setup Tool - To Support Yield Alarms and Custom Alert Messaging ......................... 6-40
Changing the Datalogging Mode From Program Control..................................................... 6-41
Status Memo .................................................................................................................. 6-42
Fast Logger.................................................................................................................... 6-42
Generating Data Reports From Test Program Control ........................................................ 6-42
Setting Customer Preferences From Program Code ........................................................... 6-42
Error Class ..................................................................................................................... 6-42
General Exception Handler .............................................................................................. 6-44
Correlation Mode ............................................................................................................ 6-45
Other LOG Object Commands.......................................................................................... 6-45
Test In Progress Splash Screen........................................................................................ 6-46
High-level Classes........................................................................................................... 6-46
Instrument Classes ......................................................................................................... 6-46
KVD Object Commands ................................................................................................... 6-46
SYS Object Commands.................................................................................................... 6-47
Data Bus Command Pipelining Changed For Increased Consistency of Timing .......... 6-47
SITE Object Commands .................................................................................................. 6-47
KVD Trace Tool .............................................................................................................. 6-47
Meter Class .................................................................................................................... 6-48
Plotting Measurement Memory ........................................................................................ 6-49
Instrument Availability .................................................................................................... 6-49
Connections and Relays .................................................................................................. 6-50
RTI Support of Shared Connections ............................................................................ 6-50
Father Cards and DUT Connections.................................................................................. 6-50
FC Relay Setup Tool .................................................................................................. 6-50
DUT Board Relays ..................................................................................................... 6-51
Connections Table Tool ................................................................................................... 6-52
Why is a Connections Table Useful? ...................................................................... 6-52
The Name Column ............................................................................................... 6-53
The Array Column [] ............................................................................................ 6-53
The Addr, Bit Columns ......................................................................................... 6-53
The Import/Export Menu Items............................................................................. 6-54
Options ............................................................................................................... 6-54
Creating Connections ........................................................................................... 6-56
Placement Of Data............................................................................................... 6-57
Loading and Saving Files ...................................................................................... 6-57
Sample Test Program Flow- User Class.cpp ...................................................................... 6-57
Contents-6
Table of Contents
VirtualHandlerClass......................................................................................................... 6-58
Test Program Automation................................................................................................ 6-58
Utilization Log File .......................................................................................................... 6-59
Wafer Mapping............................................................................................................... 6-59
Creating a Wafer Description File................................................................................ 6-59
Text Editor Method .............................................................................................. 6-59
M310Direct Method.............................................................................................. 6-60
Creating a Wafer Map Color File ................................................................................. 6-60
Loading the Wafer Description File ............................................................................. 6-61
Loading the Wafer Color File ...................................................................................... 6-61
Enabling Wafer Testing in the Customer Pref Tool ....................................................... 6-61
Delay Table.................................................................................................................... 6-61
send_value .................................................................................................................... 6-61
Setsites.......................................................................................................................... 6-62
Multisite Development..................................................................................................... 6-62
Multisite Testing........................................................................................................ 6-62
Limitations................................................................................................................ 6-64
Group Objects........................................................................................................... 6-64
Data Output Files ...................................................................................................... 6-64
SITE Object Control................................................................................................... 6-64
SITE >lastresult................................................................................................... 6-64
SITE >disable...................................................................................................... 6-65
SITE >enable ...................................................................................................... 6-65
SITE >IsActive .................................................................................................... 6-65
SITE >resetall ..................................................................................................... 6-65
SITE >set_default_sites ....................................................................................... 6-65
SITE >setsites ..................................................................................................... 6-65
SITE >sitemask ................................................................................................... 6-66
Resource Manager .......................................................................................................... 6-66
RMX Implementation............................................................................................ 6-67
Objects Created by the KVD Library ................................................................................. 6-67
BootTester .......................................................................................................... 6-67
K[0 thru 80] ........................................................................................................ 6-68
DDBUSA_TO_DDCH[NUMDDCHANNELS]; .............................................................. 6-68
DDDRV_TO_DDCH[NUMDDCHANNELS];................................................................ 6-68
TH ...................................................................................................................... 6-68
User-defined Forms for Production Operation ................................................................... 6-69
Chapter 7: Operations Environment

Customer Preferences Tool................................................................................................ 7-1
Preferences Page ........................................................................................................ 7-1
Datalog Control Page................................................................................................... 7-5
Handler Options Page .................................................................................................. 7-6
Contents-7
Parallel Handler Driver Instructions............................................................................... 7-6

TEL .......................................................................................................................... 7-10
Additional TEL-TSK Driver Low-level Commands .......................................................... 7-11
TSK.......................................................................................................................... 7-12
Site-swapping on Multitest 93xx and Aetrium V8 Multisite Handlers............................... 7-12
Multitest ................................................................................................................... 7-12
Parallel Handler/Prober Interfacing ............................................................................. 7-12
HCIF (Handler Control Interface) .......................................................................... 7-13
Parallel Handler Cabling ....................................................................................... 7-13
PHLIC (Prober Handler Laser Interface Card) .............................................................. 7-16
PHLIC to DB25 Adapter Cable ............................................................................... 7-17
Handler Bin Table Tool.................................................................................................... 7-17
Handler Bin Table Example ........................................................................................ 7-19
Custom Data DLLs..................................................................................................... 7-20
CSV Format DLL........................................................................................................ 7-20
DLL Overview ...................................................................................................... 7-20
Output File Data Format ............................................................................................ 7-21
XML Data Output Format Support............................................................................... 7-22
Two-pass Prober Test Support and Wafer Mapping...................................................... 7-22
Multipass Prober Operation With XML Data Output ...................................................... 7-22
Engineering Options on the Preferences Tool .............................................................. 7-30
Updating the Windows Registry.................................................................................. 7-30
Setup File Tool ............................................................................................................... 7-31
Test Program Launcher ................................................................................................... 7-35
Error Checking for Lot Names .................................................................................... 7-36
Preferences Flowchart..................................................................................................... 7-36
Launch Flow Overview .................................................................................................... 7-37
Engineering Launcher ..................................................................................................... 7-38
Datalogs ........................................................................................................................ 7-38
Test Time Profiling .................................................................................................... 7-39
Summaries..................................................................................................................... 7-40
Summary Counts Match Physical Device Counts........................................................... 7-40
Histograms..................................................................................................................... 7-41
Test Data Analysis .......................................................................................................... 7-42
Production Operator's Interface ....................................................................................... 7-42
Production View ........................................................................................................ 7-43
Engineering View ...................................................................................................... 7-44
Test Statistics View ................................................................................................... 7-45
Wafer Map View........................................................................................................ 7-45
Custom Forms........................................................................................................... 7-45
Test Time Calculations, Displays, and Speed-Up Techniques......................................... 7-46
Contents-8
Table of Contents
Speed-up Techniques ................................................................................................ 7-46

Test Time Report Display........................................................................................... 7-47
Running Yield Display ................................................................................................ 7-48
Real-Time Yield Alarms .............................................................................................. 7-49
Yield Alarms and Running Yield Display Tabsheet ........................................................ 7-50
Site-based Yield Delta Alarms..................................................................................... 7-50
Last "N" Yield per Site ............................................................................................... 7-51
Cleared Alarms.......................................................................................................... 7-51
Operator ID .............................................................................................................. 7-52
Alarm Holdoff And Retriggering Algorithms ................................................................. 7-53
Test Statistics Page Enhancements ............................................................................. 7-53
Obtaining Datalogs, Summaries, Histograms, and TDA Files ......................................... 7-54
Running the Test Program ......................................................................................... 7-55
Other Custom Tab Sheets - Quick Tool Pull-down Menu ............................................... 7-55
Voltmeter Memory Plots ....................................................................................... 7-55
Graphical Histograms ........................................................................................... 7-56
Conditional Breakpoints........................................................................................ 7-57
Track Result by Test Number................................................................................ 7-59
Chapter 8: DC Instruments
MPDCMOD (Octal DUT Source) .......................................................................................... 8-1
MPDCMOD Pictorial ..................................................................................................... 8-1
Functional Description ................................................................................................. 8-1
Physical Description..................................................................................................... 8-2
MPDCMOD Objects...................................................................................................... 8-3
Force Voltage.............................................................................................................. 8-3
Force Current.............................................................................................................. 8-3
Voltage Ranges ........................................................................................................... 8-4
Current Ranges ........................................................................................................... 8-4
Driver Improvements for Increased Reliability Since Release 5.02 ................................... 8-5
Voltage and Current Clamps......................................................................................... 8-5
Kelvin Connections ...................................................................................................... 8-5
Administrative Commands............................................................................................ 8-6
Measure ..................................................................................................................... 8-7
ABUS Connection to Digital Pins ................................................................................... 8-8
New MPDCMOD Functions ........................................................................................... 8-8
MPDCMOD and HPDCMOD Ranging Lockout.................................................................. 8-9
Readback Functions .................................................................................................. 8-10
MPDS[i] >actual_sample_rate............................................................................... 8-10
MPDS[i] >Exists................................................................................................... 8-10
MPDS[i] >mpdsirange .......................................................................................... 8-10
MPDS[i] >mpdsloopcomp ..................................................................................... 8-10
MPDS[i] >mpdsmode ........................................................................................... 8-10
MPDS[i] >mpdsval ............................................................................................... 8-10
MPDS[i] >mpdsvrange ......................................................................................... 8-10
Contents-9
MPDS[i] >ResourceSide ....................................................................................... 8-11

MPDS[i] >ResourceSlot ........................................................................................ 8-11
MPDS[i] >result................................................................................................... 8-11
MPDS[i] >vmmode .............................................................................................. 8-11
MPDS[i] >get_board_local_groundsense ............................................................... 8-11
MPDS[i] >getname .............................................................................................. 8-11
MPDS[i] >read_temperature................................................................................. 8-11
User Voltmeter (UVM) ..................................................................................................... 8-12
MPUVM Objects ........................................................................................................ 8-13
MP UVM Measure ...................................................................................................... 8-13
MPUVM[i] >getname............................................................................................ 8-15
Semi-parallel Measurements ...................................................................................... 8-15
Pinouts ..................................................................................................................... 8-16
QUVM (Quad User Voltmeter instrument) ......................................................................... 8-16
QUVM Pictorial .......................................................................................................... 8-16
HPDCMOD (High Power DUT Source) ............................................................................... 8-17
HPDCMOD Pictorial.................................................................................................... 8-17
HPDCMOD Support for Low Voltage Rails .................................................................... 8-17
Physical Description................................................................................................... 8-18
Force Voltage............................................................................................................ 8-19
Force Current............................................................................................................ 8-19
Voltage Ranges ......................................................................................................... 8-19
Current Ranges ......................................................................................................... 8-20
Driver Improvements for Increased Reliability ............................................................. 8-20
Voltage and Current Clamps....................................................................................... 8-21
Kelvin Connections .................................................................................................... 8-21
Administrative Commands.......................................................................................... 8-21
Measure ................................................................................................................... 8-22
HPDS[i] >actual_sample_rate ............................................................................... 8-23
HPDS[i] >Exists ................................................................................................... 8-23
HPDS[i] >hpdsirange ........................................................................................... 8-23
HPDS[i] >hpdsloopcomp ...................................................................................... 8-23
HPDS[i] >hpdsmode ............................................................................................ 8-23
HPDS[i] >hpdsval ................................................................................................ 8-23
HPDS[i] >hpdsvrange .......................................................................................... 8-23
HPDS[i] >getname .............................................................................................. 8-24
Pinouts ..................................................................................................................... 8-24
Keithley and HP Meter..................................................................................................... 8-24
Relays and Reliability ...................................................................................................... 8-25
Relay Matrix Board (RMX) ............................................................................................... 8-28
Features ................................................................................................................... 8-28
Contents-10
Table of Contents
RMX Block Diagram ................................................................................................... 8-29

Using the Relay Matrix Class ...................................................................................... 8-29
RMX Commands........................................................................................................ 8-30
Other Commands and Readback Syntax...................................................................... 8-30
RMX0 >Clear ....................................................................................................... 8-30
RMX0 >CreateNamedConnection .......................................................................... 8-31
RMX0 >GetLineStatus .......................................................................................... 8-32
RMX0 >GetLineToLineStatus................................................................................. 8-32
RMX0 >GetPinStatus............................................................................................ 8-32
RMX0 >NClear..................................................................................................... 8-33
RMX0 >NSet ....................................................................................................... 8-33
RMX0 >resetall.................................................................................................... 8-33
RMX0 >resetline .................................................................................................. 8-33
RMX0 >ResetNamedList ....................................................................................... 8-33
RMX0 >Set.......................................................................................................... 8-33
RMX I/O Pinout ......................................................................................................... 8-35
Chapter 9: Digital Instruments

DSPIO Family ................................................................................................................... 9-2
Support for DSPIOR4 Instruments ................................................................................ 9-2
Support for DDD8 Instruments..................................................................................... 9-3
DSPIO Functional Description ............................................................................................ 9-3
Overview of Digital Test Concepts...................................................................................... 9-4
Pattern Driving............................................................................................................ 9-4
Pattern Comparing ...................................................................................................... 9-6
Send Serial Memory .................................................................................................... 9-7
Capture Serial Memory ................................................................................................ 9-9
Putting It All Together - Pattern and Send/Capture Memory ......................................... 9-10
Memory Address Sequencer ....................................................................................... 9-11
Clocking ................................................................................................................... 9-12
Drive and Compare Voltage Levels ............................................................................. 9-13
Formats and Edge Timing .......................................................................................... 9-13
DSPIO Patterns .............................................................................................................. 9-13
KVD Pattern Editor/Compiler ...................................................................................... 9-14
Input .................................................................................................................. 9-14
Output ................................................................................................................ 9-14
Rules .................................................................................................................. 9-14
Vector Information .................................................................................................... 9-14
Mandatory Input Vector Fields .............................................................................. 9-14
Alternate Drive Format ......................................................................................... 9-15
Optional Input Vector Fields ................................................................................. 9-15
Sequencer OpCodes .................................................................................................. 9-16
Flags ........................................................................................................................ 9-17
Pattern Syntax .......................................................................................................... 9-18
Timeset Info ............................................................................................................. 9-18
Contents-11
Fail Disabling ............................................................................................................ 9-18

Serial/Parallel Send/Receive ....................................................................................... 9-19
Channel Default ........................................................................................................ 9-19
Pattern Example........................................................................................................ 9-20
Compiled Pattern ...................................................................................................... 9-20
.sym (Symbol Table) ................................................................................................. 9-21
Pattern Editor/Compiler Screens ................................................................................. 9-21
Pattern Editor ........................................................................................................... 9-22
DSPIO Program Structure................................................................................................ 9-26
One Time (in SystemInit or LotInit) ............................................................................ 9-26
At Least One Time (Location of Your Choice) .............................................................. 9-27
Every Time (Inside TSeq, the Mainloop Test Sequencer) .............................................. 9-27
Defining PATDATA..................................................................................................... 9-27
DSPIO Pattern Loading into Send Memory .................................................................. 9-28
Loading the pat_list into DSPIO Memory................................................................ 9-28
DSPIO Clocking & Synchronization ................................................................................... 9-29
Instrument-level Software Commands ........................................................................ 9-30
Reset .................................................................................................................. 9-30
Patload ............................................................................................................... 9-31
Patexe ................................................................................................................ 9-31
Dstop.................................................................................................................. 9-32
Dwait.................................................................................................................. 9-32
Failure Results ..................................................................................................... 9-32
Dclr .................................................................................................................... 9-32
Dflags ................................................................................................................. 9-33
Master Clock Selection ......................................................................................... 9-33
dt0t .................................................................................................................... 9-33
Send/Capture Memory Setup ................................................................................ 9-34
DSPIO Channel Commands ............................................................................................. 9-35
Data Formats ............................................................................................................ 9-35
Main Formats............................................................................................................ 9-35
Other Formats .......................................................................................................... 9-36
Pin Electronics .......................................................................................................... 9-36
Channel Software Functions ....................................................................................... 9-37
Multisite Objects ....................................................................................................... 9-37
Enable or Disable the Driver....................................................................................... 9-38
Format and Timing.................................................................................................... 9-38
Comparator Strobe Time............................................................................................ 9-38
Drive and Compare Levels ......................................................................................... 9-38
RTI Support.............................................................................................................. 9-38
Summary of Other Commands ................................................................................... 9-39
DIG0 >dcap_drv_en ............................................................................................ 9-39
DIG0 >dcap_read ................................................................................................ 9-39
DIG0 >dcap_setup .............................................................................................. 9-39
DIG0 >dcap_wait ................................................................................................ 9-39
Contents-12
Table of Contents
DIG0 >dclr .......................................................................................................... 9-39

DIG0 >dconfig..................................................................................................... 9-39
DIG0 >dd_xclkinfreq............................................................................................ 9-39
DIG0 >dd_xclkoutfreq.......................................................................................... 9-39
DIG0 >ddclock .................................................................................................... 9-39
DIG0 >ddpllbits ................................................................................................... 9-40
DIG0 >ddrv_load................................................................................................. 9-40
DIG0 >ddrv_load_side ......................................................................................... 9-40
DIG0 >ddrv_load_side_mask................................................................................ 9-40
DIG0 >ddrv_setup ............................................................................................... 9-40
DIG0 >dfail ......................................................................................................... 9-40
DIG0 >dfailaddr .................................................................................................. 9-40
DIG0 >dflags ...................................................................................................... 9-40
DIG0 >dmclkconfig .............................................................................................. 9-40
DIG0 >dreadfail................................................................................................... 9-41
DIG0 >dstatus..................................................................................................... 9-41
DIG0 >dstop ....................................................................................................... 9-41
DIG0 >dt0t ......................................................................................................... 9-41
DIG0 >dwait ....................................................................................................... 9-41
DIG0 >dwaitfail ................................................................................................... 9-41
DIG0 >dwaitnofail ............................................................................................... 9-41
DIG0 >dxclkena .................................................................................................. 9-41
DIG0 >getsym..................................................................................................... 9-41
DIG0 >patexe ..................................................................................................... 9-42
DIG0 >patexe_sym.............................................................................................. 9-42
DIG0 >patload .................................................................................................... 9-43
DIG0 >patload1................................................................................................... 9-43
DIG0 >reset ........................................................................................................ 9-43
DIG0 >set_DDXTALFREQ ..................................................................................... 9-43
DDCH[i][1] >dcomp............................................................................................. 9-43
DDCH[i][1] >dfmt................................................................................................ 9-44
DDCH[i][1] >dfmt_long........................................................................................ 9-44
DDCH[i][1] >disable ............................................................................................ 9-44
DDCH[i][1] >dka ................................................................................................. 9-44
DDCH[i][1] >dlevel .............................................................................................. 9-45
DDCH[i][1] >dmatch............................................................................................ 9-45
DDCH[i][1] >dstrb ............................................................................................... 9-45
DDCH[i][1] >enable............................................................................................. 9-45
DDCH[i][1] >getcomplev...................................................................................... 9-45
DDCH[i][1] >getformat ........................................................................................ 9-45
DDCH[i][1] >gethighlev ....................................................................................... 9-46
DDCH[i][1] >getkeepalive .................................................................................... 9-46
DDCH[i][1] >getlowlev......................................................................................... 9-46
DDCH[i][1] >getname.......................................................................................... 9-46
DDCH[i][1] >getstarttime..................................................................................... 9-46
DDCH[i][1] >getstate........................................................................................... 9-46
DDCH[i][1] >getstoptime ..................................................................................... 9-46
DDCH[i][1] >getstrobe......................................................................................... 9-46
DDCH[i][1] >setname .......................................................................................... 9-47
Contents-13
Test Program Examples ............................................................................................. 9-47

DSPIO Pinouts................................................................................................................ 9-49
DSPIO Drive and Capture ................................................................................................ 9-50
DSPIO Capture and Drive Shift Registers..................................................................... 9-50
OPCODE Shift Register Control ............................................................................. 9-52
CAPTURE Shift Register........................................................................................ 9-52
Two Channel 8-bit Serial ADC Example.................................................................. 9-53
DRIVE Shift Register ............................................................................................ 9-53
Two Channel 8-bit Serial DAC Example.................................................................. 9-54
DSPIOTI Chip ........................................................................................................... 9-55
DISMODE............................................................................................................ 9-55
TIMODE .............................................................................................................. 9-56
AUTOMODE......................................................................................................... 9-56
Details of the Control Word........................................................................................ 9-56
Patterns .............................................................................................................. 9-58
ADDR 32 bit Control Word .................................................................................... 9-59
FD FAIL DISABLE................................................................................................. 9-59
TSET[2:0] TIME SET ............................................................................................ 9-60
SR[2:0] SHIFT REGISTER CONTROL ..................................................................... 9-60
OPCODE[3:0] VECTOR OPCODE ........................................................................... 9-60
FLAG[3:0] CONDITIONAL FLAG ............................................................................ 9-61
NR NEGATIVE RELATIVE ADDRESSING ................................................................. 9-61
DIGMOD16/32................................................................................................................ 9-62
Description ............................................................................................................... 9-62
Features and Basic Specifications ............................................................................... 9-62
Drive/Compare .................................................................................................... 9-63
PMU.................................................................................................................... 9-63
Pattern Formatting............................................................................................... 9-63
Block Diagram........................................................................................................... 9-64
High Speed Link ............................................................................................................. 9-65
DIGMOD Calibration and Checker .................................................................................... 9-66
DIGMOD Programming.................................................................................................... 9-67
DIGMOD Pin Definition.................................................................................................... 9-67
Basics....................................................................................................................... 9-67
Pin Definition & Grouping........................................................................................... 9-68
Single Pin Naming................................................................................................ 9-68
Grouping Pins ...................................................................................................... 9-68
Grouping of Groups.............................................................................................. 9-68
DIGMOD Pin (DMCH) Programming.................................................................................. 9-69
DMCH Pin Programming Functions.............................................................................. 9-69
DMCH[x]->SetSiteMode ....................................................................................... 9-69
DMCH[x]->enable................................................................................................ 9-69
DMCH[x]->disable ............................................................................................... 9-70
DMCH[x]->forcemode .......................................................................................... 9-70
DMCH[x]->forceenable ........................................................................................ 9-70
Contents-14
Table of Contents
DMCH[x]->force .................................................................................................. 9-70

DMCH[x]->dlevel ................................................................................................. 9-71
DMCH[x]->cmplevel............................................................................................. 9-71
DMCH[x]->vil ...................................................................................................... 9-71
DMCH[x]->vih ..................................................................................................... 9-72
DMCH[x]->vol ..................................................................................................... 9-72
DMCH[x]->voh .................................................................................................... 9-72
DMCH[x]->trm .................................................................................................... 9-72
DMCH[x]->trmenable........................................................................................... 9-73
DMCH[x]->pmuenable ......................................................................................... 9-73
DMCH[x]->setv ................................................................................................... 9-73
DMCH[x]->seti .................................................................................................... 9-73
DMCH[x]->irange ................................................................................................ 9-74
DMCH[x]->vrange ............................................................................................... 9-74
DMCH[x]->imeter ................................................................................................ 9-74
DMCH[x]->vmeter ............................................................................................... 9-74
DMCH[x]->measvm ............................................................................................. 9-75
DMCH[x]->ldenable ............................................................................................. 9-75
DMCH[x]->loaddisable ......................................................................................... 9-75
DMCH[x]->load ................................................................................................... 9-75
DMCH[x]->dig_con .............................................................................................. 9-76
DMCH[x]->dig_discon .......................................................................................... 9-76
DMCH[x]->abus_con ........................................................................................... 9-76
DMCH[x]->abus_discon ....................................................................................... 9-77
DMCH[x]->l1abus_con ......................................................................................... 9-77
DMCH[x]->l1abus_discon ..................................................................................... 9-77
DMCH[x]->dtiming .............................................................................................. 9-77
New Timing Setup Command: dtimingT0 .................................................................... 9-78
DMCH[x]->dtiming_combine ................................................................................ 9-79
DMCH[x]->dfmt................................................................................................... 9-79
DMCH[x]->dcmp ................................................................................................. 9-79
DMCH[x]->dcomp................................................................................................ 9-80
DMCH[x]->tset .................................................................................................... 9-80
DMCH[x]->fmt , DMCH[x]->format ....................................................................... 9-80
DMCH[x]->start................................................................................................... 9-80
DMCH[x]->stop ................................................................................................... 9-81
DMCH[x]->enastart ............................................................................................. 9-81
DMCH[x]->enastop.............................................................................................. 9-81
DMCH[x]->cmpstart............................................................................................. 9-81
DMCH[x]->cmpstop ............................................................................................. 9-81
DMCH[x]->keepalive............................................................................................ 9-82
DMCH[x]->dka .................................................................................................... 9-82
DMCH[x]->tmucon .............................................................................................. 9-82
DMCH[x]->measfreq............................................................................................ 9-82
DMCH[x]->start_measfreq ................................................................................... 9-83
PMU Comparator Enables........................................................................................... 9-83
DIGMOD Sequencer Definition ......................................................................................... 9-84
Basics....................................................................................................................... 9-84
Sequencer Definition & Grouping................................................................................ 9-84
Contents-15
Single Board Sequencer ....................................................................................... 9-84

Grouping Boards.................................................................................................. 9-84
DIGMOD Sequencer Programming ................................................................................... 9-85
Sequencer Programming Functions............................................................................. 9-85
SEQ0->SetSiteMode............................................................................................. 9-85
SEQ0->SetMode .................................................................................................. 9-85
SEQ0->mclk_sel .................................................................................................. 9-86
SEQ0->MasterSlave ............................................................................................. 9-86
SEQ0->SetupMCLK .............................................................................................. 9-87
SEQ0->dt0t......................................................................................................... 9-87
SEQ0->dt0div...................................................................................................... 9-87
SEQ0->keepalive_timeset..................................................................................... 9-87
SEQ0->dflags ...................................................................................................... 9-88
SEQ0->running ................................................................................................... 9-88
SEQ0->dwait....................................................................................................... 9-88
SEQ0->dfail......................................................................................................... 9-88
SEQ0->cycle_count.............................................................................................. 9-89
SEQ0->status ...................................................................................................... 9-89
SEQ0->set_wait_timeout...................................................................................... 9-90
SEQ0->get_wait_timeout ..................................................................................... 9-90
Pattern Management and Execution............................................................................ 9-90
SEQ0->patloadmap.............................................................................................. 9-90
SEQ0->createpatmap........................................................................................... 9-91
SEQ0->patload .................................................................................................... 9-91
SEQ0->patload_parallel........................................................................................ 9-92
SEQ0->patload_pformat....................................................................................... 9-92
SEQ0->patexe ..................................................................................................... 9-92
Alternate 1: using the pattern index ...................................................................... 9-92
Alternate 2: using the pattern index and offset ...................................................... 9-93
SEQ0->patexe_array............................................................................................ 9-93
SEQ0->patexe_parallel......................................................................................... 9-93
SEQ0->getsym .................................................................................................... 9-94
SEQ0->dcap_setup .............................................................................................. 9-94
DIGMOD[x]->dcap_setup ..................................................................................... 9-94
DIGMOD[x]->dcap_read ...................................................................................... 9-95
DIGMOD[x]->ddrv_setup ..................................................................................... 9-95
DIGMOD[x]->ddrv_load ....................................................................................... 9-95
DIGMOD .pformat Pattern File Structure........................................................................... 9-95
PFORMAT Pattern Structure ....................................................................................... 9-95
Loading .pformat Files ............................................................................................... 9-96
Old Pattern Structure ........................................................................................... 9-96
New Pattern Structure.......................................................................................... 9-96
Pattern Loading ........................................................................................................ 9-96
.bp Pattern Loading (multisite): ............................................................................ 9-96
.pformat Loading: ................................................................................................ 9-96
DIGMOD Resource Manager (DMRMan) ...................................................................... 9-97
The DIGMOD Resource File........................................................................................ 9-97
Loading the DMResources ini File ............................................................................... 9-97
Contents-16
Table of Contents
Mapping Names to Pins ............................................................................................. 9-98

DIGMOD Pattern Editor ................................................................................................... 9-98
DIGMOD Pattern Editor.............................................................................................. 9-98
Logic Analyzer Mode for the DIGMOD Pattern Editor .................................................. 9-102
Necessary Steps...................................................................................................... 9-102
Cautions ................................................................................................................. 9-103
Logic Analyzer Class User Functions.......................................................................... 9-103
void TlogicAnalyzer::Run(); ................................................................................ 9-104
DIGMOD SHMOO.......................................................................................................... 9-107
X Axis..................................................................................................................... 9-108
Y Axis..................................................................................................................... 9-108
Main....................................................................................................................... 9-109
General Fields ......................................................................................................... 9-109
How it Works .......................................................................................................... 9-110
A Word About the GUI Interface............................................................................... 9-110
Other Commands .................................................................................................... 9-110
Margin Shmoos ....................................................................................................... 9-111
DIGMOD RTI Support ................................................................................................... 9-112
Time Measurement Unit ................................................................................................ 9-119
Functional Description ............................................................................................. 9-119
Theory of Operation ................................................................................................ 9-119
Pinouts ................................................................................................................... 9-121
TMU Object ............................................................................................................ 9-121
TMU Commands...................................................................................................... 9-121
Data Types Used by the TMU ................................................................................... 9-123
TMU Commands...................................................................................................... 9-123
TMU >ddchan ................................................................................................... 9-123
TMU >enable .................................................................................................... 9-123
TMU >freq ........................................................................................................ 9-124
TMU >input....................................................................................................... 9-124
TMU >interval ................................................................................................... 9-124
TMU >level ....................................................................................................... 9-125
TMU >meas ...................................................................................................... 9-125
TMU >meas_array ............................................................................................. 9-125
TMU >meas_neg ............................................................................................... 9-125
TMU >reset....................................................................................................... 9-125
Chapter 10: AC Instruments

DSP Testing on KVD M2 Test System ............................................................................... 10-1
Clocking ................................................................................................................... 10-1
Example ................................................................................................................... 10-1
Ideal Conditions................................................................................................... 10-1
PWD Clock Setup ................................................................................................. 10-1
DSPIO Clock Setup .............................................................................................. 10-2
Contents-17
PWS Clock Setup ................................................................................................. 10-3

The Test Frequency ............................................................................................. 10-4
Direct Digital Synthesis......................................................................................... 10-5
Conclusion .......................................................................................................... 10-6
Waveform Source ........................................................................................................... 10-6
Control ..................................................................................................................... 10-6
WS Connections ........................................................................................................ 10-7
Pinouts ..................................................................................................................... 10-8
Waveform Source Commands.......................................................................................... 10-9
WS->start (<waveform>,<frequency>,<amplitude>);........................................... 10-9
WS->clock (<source>,<destination>);.................................................................. 10-9
WS->init ( )......................................................................................................... 10-9
WS->reset ( ).................................................................................................... 10-10
WS->pllbits ( <numerator>,<denominator>,<divisor>) ....................................... 10-10
WS -> xclkinfreq (<frequency>);........................................................................ 10-10
WS->xclkoutfreq (<frequency>);........................................................................ 10-11
WS->offset ( <ws>,<offset>) ............................................................................ 10-11
WS->filter (<source>, <filter>).......................................................................... 10-11
WS->atten (<source>,<attenuation>)................................................................ 10-12
WS->store_sine20bit (<address>, <length>,<amplitude>,<offset>);................... 10-12
WS->store_wave20bit (<wave structure>);......................................................... 10-12
WS->store_sine16bit_hs (<address>,<length>,<amp>,<offset>)........................ 10-13
WS->store_ramp20bit (<address>,<length>,<amplitude>,<offset>) ................... 10-13
Precision WS ................................................................................................................ 10-13
PWS Commands ........................................................................................................... 10-15
Connection ............................................................................................................. 10-15
Clocking ................................................................................................................. 10-15
Filter/Level(DC)....................................................................................................... 10-15
General .................................................................................................................. 10-16
PWS Connection Syntax........................................................................................... 10-16
PWSx -> con ..................................................................................................... 10-16
PWSx -> con_to_switch_bus .............................................................................. 10-16
PWSx -> con_to_cal_bus.................................................................................... 10-16
PWSx -> con_to_l1 ............................................................................................ 10-16
PWSx -> con_to_ic ............................................................................................ 10-16
PWSx -> con_to_agnd ....................................................................................... 10-17
PWSx -> discon ................................................................................................. 10-17
PWSx -> discon_from_switch_bus ...................................................................... 10-17
PWSx -> discon_from_cal_bus............................................................................ 10-17
PWSx -> discon_from_l1 .................................................................................... 10-17
PWSx -> discon_from_ic .................................................................................... 10-17
PWSx -> discon_from_agnd ............................................................................... 10-18
PWS Clocking Syntax ............................................................................................... 10-18
PWSx -> dds_setup ........................................................................................... 10-18
PWSx -> dds_reset ............................................................................................ 10-18
Contents-18
Table of Contents
PWSx -> clock_reset .......................................................................................... 10-18

PWSx -> xclockoutfreq....................................................................................... 10-19
PWSx -> xclockinfreq ......................................................................................... 10-19
PWSx -> clock ................................................................................................... 10-19
PWS Filter/DC Syntax .............................................................................................. 10-20
PWSx -> offset .................................................................................................. 10-20
PWSx -> filter.................................................................................................... 10-20
PWSx -> atten................................................................................................... 10-20
PWSx -> setv .................................................................................................... 10-21
PWS General Syntax................................................................................................ 10-21
PWSx -> reset ................................................................................................... 10-21
PWSx -> init...................................................................................................... 10-21
Waveform Digitizer ....................................................................................................... 10-22
Functional Description ............................................................................................. 10-22
Processing and Control ............................................................................................ 10-22
WD Connections...................................................................................................... 10-23
Pinouts ................................................................................................................... 10-24
Waveform Digitizer Commands ...................................................................................... 10-24
WD->start (< source >,<waveform>); ............................................................... 10-24
WD->clock (<source>,<destination>); ............................................................... 10-24
WD->init........................................................................................................... 10-25
WD->reset ........................................................................................................ 10-25
WD -> pllbits (<numerator>,<denominator>,<divisor>)...................................... 10-25
WD->xclkinfreq (<frequency>)........................................................................... 10-26
WD->xclkoutfreq (<frequency>) ........................................................................ 10-26
WD->offset (<source>,<offset>); ...................................................................... 10-26
WD->filter (<source>,<filter>); ......................................................................... 10-27
WD->gain (<source>,<gain1>,<gain2>)............................................................ 10-27
WD->lfadc (<adcclock>,<sample rate>)............................................................. 10-27
WD->hfadc (<sample rate>);............................................................................. 10-28
Precision WD................................................................................................................ 10-28
PWD Commands........................................................................................................... 10-30
Connection ............................................................................................................. 10-30
Clocking ................................................................................................................. 10-30
General .................................................................................................................. 10-30
DSP........................................................................................................................ 10-30
Filter/Level(DC)....................................................................................................... 10-31
PWD Connection Syntax .......................................................................................... 10-31
PWDx -> instr_con ............................................................................................ 10-31
PWDx -> input_con ........................................................................................... 10-31
PWDx -> instr_discon ........................................................................................ 10-31
PWDx -> input_discon ....................................................................................... 10-32
PWD Clocking Syntax .............................................................................................. 10-32
PWDx -> dds_setup........................................................................................... 10-32
PWDx -> dds_reset............................................................................................ 10-32
PWDx -> clock_reset ......................................................................................... 10-33
Contents-19
PWDx -> clock_div ............................................................................................ 10-33

PWDx -> clock .................................................................................................. 10-33
PWDx -> clockselect .......................................................................................... 10-34
PWD General Syntax ............................................................................................... 10-34
PWDx -> reset .................................................................................................. 10-34
PWDx -> start ................................................................................................... 10-34
PWDx -> stop.................................................................................................... 10-35
PWDx -> wait.................................................................................................... 10-35
PWD DSP Processing Syntax .................................................................................... 10-35
PWDx -> setup_fft............................................................................................. 10-35
PWDx -> fft_exec .............................................................................................. 10-36
PWDx -> fft....................................................................................................... 10-36
PWDx -> thd ..................................................................................................... 10-36
PWDx -> snr ..................................................................................................... 10-36
PWDx -> sinad .................................................................................................. 10-37
PWDx -> thd_filter............................................................................................. 10-37
PWDx -> snr_filter ............................................................................................. 10-37
PWDx -> sinad_filter.......................................................................................... 10-38
PWD Filter/DC Syntax .............................................................................................. 10-38
PWDx -> offset.................................................................................................. 10-38
PWDx -> filter ................................................................................................... 10-39
PWDx -> gain.................................................................................................... 10-39
PWDx -> read_wd2000_dc................................................................................. 10-39
DSP (Digital Signal Processing) ...................................................................................... 10-40
Defining Waveforms ................................................................................................ 10-40
TI DSP Programs .......................................................................................................... 10-40
PWS Programs ........................................................................................................ 10-41
PWD Programs........................................................................................................ 10-41
TI Memory Locations ............................................................................................... 10-41
PWS Instrument ................................................................................................ 10-41
PWD Instrument ................................................................................................ 10-42
WS Specific Declarations.......................................................................................... 10-43
WD Specific Declarations ......................................................................................... 10-45
Dspclocksetup......................................................................................................... 10-46
Default Clock Setup ........................................................................................... 10-46
Example for Setting WS0->clock_reset ................................................................ 10-47
Clocking and Synchronization ................................................................................... 10-47
Clocking Example............................................................................................... 10-47
DDS (Direct Digital Synthesis) .................................................................................. 10-51
DDS Example .................................................................................................... 10-54
PLL Setup ............................................................................................................... 10-54
Chapter 11: Non-Instrument Software Command Summary

LOG Object .................................................................................................................... 11-1
TLOG .................................................................................................................. 11-1
LOG >CurTestNum .............................................................................................. 11-1
LOG >DataToEventLog ........................................................................................ 11-1
Contents-20
Table of Contents
LOG >DisableAlarms ............................................................................................ 11-1

LOG >EngineeringMode ....................................................................................... 11-1
LOG >plottestnum ............................................................................................... 11-1
LOG >SystemMsgToEventLog ............................................................................... 11-1
LOG >ActiveWaferTesting .................................................................................... 11-2
LOG >ApplicationName ........................................................................................ 11-2
LOG >BadDieCount.............................................................................................. 11-2
LOG >BinFileName .............................................................................................. 11-2
LOG >Comment .................................................................................................. 11-2
LOG >ComputerName.......................................................................................... 11-2
LOG >DatalogFileName ........................................................................................ 11-3
LOG >DataPath ................................................................................................... 11-3
LOG >Default_LOT_DataFileName ........................................................................ 11-3
LOG >Default_SUBLOT_DataFileName .................................................................. 11-3
LOG >DUTSN ...................................................................................................... 11-3
LOG >EnablePrintDatalogFile ................................................................................ 11-3
LOG >EnablePrintHistogramFile ............................................................................ 11-4
LOG >EnablePrintSummaryFile ............................................................................. 11-4
LOG >EnablePrintTDAFile ..................................................................................... 11-4
LOG >FileDatalogAll............................................................................................. 11-4
LOG >FileDatalogFails .......................................................................................... 11-5
LOG >FileDatalogOff ............................................................................................ 11-5
LOG >FileSampleNum .......................................................................................... 11-5
LOG >FileSampleSize ........................................................................................... 11-5
LOG >FirstTestNum ............................................................................................. 11-5
LOG >FixtureID ................................................................................................... 11-5
LOG >GoodDieCount............................................................................................ 11-6
LOG >HandTestModeActive .................................................................................. 11-6
LOG >Job ........................................................................................................... 11-6
LOG >LastDatalogString....................................................................................... 11-6
LOG >LastTestNum ............................................................................................. 11-6
LOG >LibraryVersion............................................................................................ 11-6
LOG >LotNumber ................................................................................................ 11-7
LOG >LotNumber ................................................................................................ 11-7
LOG >NoDataCollection........................................................................................ 11-7
LOG >OperatorID ................................................................................................ 11-7
LOG >ParameterFileName .................................................................................... 11-7
LOG >RuntimeLevel............................................................................................. 11-7
LOG >SavedDatalogFileName ............................................................................... 11-8
LOG >ScreenDatalogAll ........................................................................................ 11-8
LOG >ScreenDatalogFails ..................................................................................... 11-8
LOG >ScreenDatalogOff ....................................................................................... 11-8
LOG >ScreenSampleNum ..................................................................................... 11-8
LOG >ScreenSampleSize ...................................................................................... 11-8
LOG >StartedByKVDLauncher ............................................................................... 11-9
LOG >StartLotTime.............................................................................................. 11-9
LOG >StopFF ...................................................................................................... 11-9
LOG >TesterID.................................................................................................... 11-9
LOG >UploadDataPath ......................................................................................... 11-9
LOG >UsingCustomDataDLL ................................................................................. 11-9
Contents-21
LOG >UsingDeviceHandler ................................................................................. 11-10

LOG >WaferDescFileName ................................................................................. 11-10
LOG >WafermapColorsFileName ......................................................................... 11-10
LOG >WafermapDescFileName ........................................................................... 11-10
LOG >WaferMapX.............................................................................................. 11-10
LOG >WaferMapY.............................................................................................. 11-10
LOG >WaferNumber .......................................................................................... 11-11
LOG >WaferTestFlow......................................................................................... 11-11
LOG >AddLimitUnit ............................................................................................ 11-11
LOG >AddUserComment .................................................................................... 11-12
LOG >ClearUserComments ................................................................................. 11-12
LOG >CurrentBin ............................................................................................... 11-12
LOG >DatalogComment ..................................................................................... 11-13
LOG >DeleteWaferData...................................................................................... 11-13
LOG >DownGrade ............................................................................................. 11-13
LOG >ExecuteProgram....................................................................................... 11-13
LOG >FindWaferData......................................................................................... 11-14
LOG >GetLimitsEntry ......................................................................................... 11-14
LOG >GetPassBinSite ......................................................................................... 11-14
LOG >IsFailing .................................................................................................. 11-14
LOG >IsPassing................................................................................................. 11-14
LOG->test_fail[tn] ............................................................................................. 11-15
LOG >IsValidBin ................................................................................................ 11-15
LOG >load_bin_data .......................................................................................... 11-15
LOG >load_extlimits_data .................................................................................. 11-15
LOG >load_limits_data....................................................................................... 11-16
LOG >load_waferdesc_file.................................................................................. 11-16
LOG >load_wafermap_colors.............................................................................. 11-16
LOG >LoadCustomerPrefFile............................................................................... 11-17
LOG >TestInProgress......................................................................................... 11-17
LOG >UserGenDatalog ....................................................................................... 11-17
LOG >UserGenHistogram ................................................................................... 11-18
LOG >UserGenSummary .................................................................................... 11-18
LOG >UserGenTDA ............................................................................................ 11-19
KVD Object .................................................................................................................. 11-19
KVD >UserParamFileName ................................................................................. 11-19
KVD >CalibrateAll .............................................................................................. 11-19
KVD >CalibrateMenu.......................................................................................... 11-19
KVD >DaysSinceLastCal ..................................................................................... 11-19
KVD >HoursSinceLastCal.................................................................................... 11-20
KVD >LoadConfig .............................................................................................. 11-20
KVD >ReadLauncherString ................................................................................. 11-20
KVD >ReadParameterString................................................................................ 11-20
KVD >SelectView ............................................................................................... 11-21
KVD >Test ........................................................................................................ 11-21
KVD >TestNoFail ............................................................................................... 11-21
KVD >tnum ....................................................................................................... 11-22
KVD >UserComment .......................................................................................... 11-22
Relay and Connection Commands .................................................................................. 11-22
Contents-22
Table of Contents
TRelay Constructor ............................................................................................ 11-22

TRelay -> close ................................................................................................. 11-23
TRelay -> open ................................................................................................. 11-23
TConnection Constructor .................................................................................... 11-23
TConnection -> con ........................................................................................... 11-24
TConnection -> discon ....................................................................................... 11-25
Appendix A: Detailed Specifications ............................................................A-1
Appendix B: Release Notes and Updates .....................................................B-1
Appendix C: Custom Father Cards ................................................................C-1
Contents-23
Contents-24
List of Figures
Help Menus.................................................................................................................................... 1-2
Help Window.................................................................................................................................. 1-2
M2 System..................................................................................................................................... 1-4
M2m Cabinet and Manipulator ......................................................................................................... 1-5
Dimensions of the M2m .................................................................................................................. 1-5

Power Supply Danger Label............................................................................................................. 2-2
ESD Caution Label .......................................................................................................................... 2-3
Protective Ground Identification Label.............................................................................................. 2-4

Maintenance Access Space - M2 Test System ................................................................................... 3-2
Maintenance Access Space - M2m Test System................................................................................. 3-3

Main Cabinet .................................................................................................................................. 4-1
Power Distribution Unit (Front) ........................................................................................................ 4-1
Power Distribution Unit (Rear) ......................................................................................................... 4-2
Remote/Local PDU Switch ............................................................................................................... 4-2
Main Power Switch ......................................................................................................................... 4-2
AC Power Flow Block Diagram ......................................................................................................... 4-4
Power Distribution Unit Wiring......................................................................................................... 4-5
DC Power Flow Block Diagram......................................................................................................... 4-6
Origination of the Control Signal on the PCIDIS ................................................................................ 4-7
Power Control Schematic ................................................................................................................ 4-8
New CPU Front View....................................................................................................................... 4-9
New CPU Rear View........................................................................................................................ 4-9
CPU Internal View ........................................................................................................................ 4-10
CPU Optional Boards..................................................................................................................... 4-10
CPU Add-in Boards ....................................................................................................................... 4-11
PCIDIS Pictorial ............................................................................................................................ 4-11
PHLIC Card .................................................................................................................................. 4-12
Peripherals Bay ............................................................................................................................ 4-14
Power Supply Enclosure ................................................................................................................ 4-15
Power Supply Fan Door................................................................................................................. 4-15
Power Supply Interior ................................................................................................................... 4-16
Power Supply Rear Panel .............................................................................................................. 4-17
Power Supply Motherboard ........................................................................................................... 4-18
Power Supply Motherboard Locations............................................................................................. 4-19
Fuse Detail................................................................................................................................... 4-19
Thermostat Overall Location.......................................................................................................... 4-20
Thermostat Detail......................................................................................................................... 4-20
List of Figures-1
Thermostat Control Wiring ............................................................................................................ 4-21

M2 Linear Power Supply DC Block Diagram .................................................................................... 4-22
M2m Power Supply DC Block Diagram............................................................................................ 4-23
M2i Enhanced Imager Power Supply DC Block Diagram ................................................................... 4-24
Converted Laser Power Supply DC Block Diagram ........................................................................... 4-25
PowerPlus Front Panel .................................................................................................................. 4-28
Power GUI ................................................................................................................................... 4-28
PowerPlus Status Tab ................................................................................................................... 4-29
PowerPlus Supply Overview........................................................................................................... 4-30
Power Plus Supply Pictorial............................................................................................................ 4-31
PowerPlus Block Diagram .............................................................................................................. 4-32
PowerPlus Internal View ............................................................................................................... 4-33
PowerPlus Digital Supply "A" ......................................................................................................... 4-34
PowerPlus Analog Supply "B"......................................................................................................... 4-35
Cartridge Fuses ............................................................................................................................ 4-35
PowerPlus Supply Wiring - ON/OFF Control .................................................................................... 4-36
Dual Cal Bus & DMM Wiring .......................................................................................................... 4-37
X1 Cable Connector ...................................................................................................................... 4-38
X1 Pinout..................................................................................................................................... 4-38
X2 Pinout..................................................................................................................................... 4-39
X3 Pinout..................................................................................................................................... 4-40
X4 Pinout..................................................................................................................................... 4-40
X5 Pinout..................................................................................................................................... 4-41
Hypertronics Connector (Male) ...................................................................................................... 4-42
Hypertronics Female on Fathercard (Close-up) ............................................................................... 4-42
Keithley 2000 DMM....................................................................................................................... 4-43
Keithley 2000 Spec Summary ........................................................................................................ 4-44
Keithley Input Button.................................................................................................................... 4-44
Keithley DMM Rear Panel .............................................................................................................. 4-45
Rear Panel Connector Modifications ............................................................................................... 4-45
Internal Fuseholder Added for Current Calibration........................................................................... 4-45
Calibration ................................................................................................................................... 4-46
Test Head .................................................................................................................................... 4-47
Test Head Mechanical ................................................................................................................... 4-48
Empty Test Head.......................................................................................................................... 4-49
Test Head Motherboard ................................................................................................................ 4-49
Populated Test Head .................................................................................................................... 4-50
Test Head Cables ......................................................................................................................... 4-50
Analog and Digital Ground Test Points ........................................................................................... 4-51
DIN Connector (Female) ............................................................................................................... 4-51
Motherboard Digital Bus................................................................................................................ 4-52
Motherboard Interconnect (IC) Bus................................................................................................ 4-53
List of Figures-2
List of Figures
Motherboard Analog Bus ............................................................................................................... 4-54

DISCONT Pictorial......................................................................................................................... 4-55
DISCONT to Fathercard Pin Assignments........................................................................................ 4-56
PCIDIS to DISCONT Signals .......................................................................................................... 4-57
Father Card Pictorial ..................................................................................................................... 4-58
Father Card Top View ................................................................................................................... 4-59
Father Card Power Supply Monitor LEDs......................................................................................... 4-60
Chip Fuse Chart............................................................................................................................ 4-62
Coto Relays on the Father Card ..................................................................................................... 4-63

Inspect for Bent Male DIN Connector Pins ........................................................................................ 5-2
Slide Rail Latches ........................................................................................................................... 5-3
DC Power Supply Adjustment Limits................................................................................................. 5-4
Example Power Supply Adjustment Points ........................................................................................ 5-5
Install question screen .................................................................................................................... 5-6
KVD Library Installation Screen........................................................................................................ 5-6
KVD Power Control Icon................................................................................................................ 5-18
Tester Configuration Tool Screen ................................................................................................... 5-19
TCT Screen with Configured Test Head .......................................................................................... 5-20
Selecting an Instrument in the TCT................................................................................................ 5-21
Power Supply Selection ................................................................................................................. 5-22
Father Card Selection.................................................................................................................... 5-22
Xilinx File Location ........................................................................................................................ 5-23
TCT Ports Screen.......................................................................................................................... 5-24
TCT Revision Field ........................................................................................................................ 5-24
An Ideal Instrument ..................................................................................................................... 5-26
A Real Instrument - Offset Error .................................................................................................... 5-27
A Real Instrument - Gain Error ...................................................................................................... 5-28
A Surprisingly Bad Instrument ....................................................................................................... 5-29
Fast Launch Tab........................................................................................................................... 5-30
Simulated LEDs ............................................................................................................................ 5-31
Termination Bar ........................................................................................................................... 5-31
Calibration and Checker Options .................................................................................................... 5-32
Modify Custom Value Screen ......................................................................................................... 5-33
GSI-M310 Screen ......................................................................................................................... 5-40
Stop Trim Interface ...................................................................................................................... 5-41
ESI 2050/2100 Screen .................................................................................................................. 5-42

Launching the Generic Application Shell Installer .............................................................................. 6-1
Generic Test Application Installation ................................................................................................ 6-2
Generic Test Application Installation Directory .................................................................................. 6-2
Generic Test Application Installed Files............................................................................................. 6-3
Launching Borland C++ Builder ....................................................................................................... 6-5
Open Project Command .................................................................................................................. 6-6
Selecting the KVDTestApp.bpr File ................................................................................................... 6-6
List of Figures-3
Main Borland IDE Display ................................................................................................................ 6-7

Environment Options ...................................................................................................................... 6-8
Use Precompiled Headers................................................................................................................ 6-9
RUN Button.................................................................................................................................... 6-9
Compilation in Progress ................................................................................................................ 6-10
Copy Project Tool ......................................................................................................................... 6-12
Project View................................................................................................................................. 6-13
Tuser::DeviceInit Function ............................................................................................................ 6-14
Setting a Breakpoint ..................................................................................................................... 6-14
Execution Halted .......................................................................................................................... 6-14
Debugger Shortcuts...................................................................................................................... 6-15
Real Time Interface Main Screen ................................................................................................... 6-16
MP RTI Screen Display (Tab 1) ...................................................................................................... 6-17
MP RTI Screen Display (Tab 2) ...................................................................................................... 6-19
User Voltmeter RTI Display ........................................................................................................... 6-20
HP RTI Display ............................................................................................................................. 6-21
DSPIO RTI ................................................................................................................................... 6-22
Patterns/Running RTI ................................................................................................................... 6-23
Patterns/Readback RTI ................................................................................................................. 6-24
Fathercard Relays RTI .................................................................................................................. 6-25
Digital Relays RTI ......................................................................................................................... 6-26
TMU RTI ...................................................................................................................................... 6-27
DIGMOD RTI................................................................................................................................ 6-28
System Functions RTI ................................................................................................................... 6-28
Connections RTI........................................................................................................................... 6-29
Limits File Editor Screen................................................................................................................ 6-33
Bin Description Editor Screen ........................................................................................................ 6-37
BIN Setup Tool............................................................................................................................. 6-40
Library Output Messages............................................................................................................... 6-43
Exception Handler ........................................................................................................................ 6-44
Trace Tool ................................................................................................................................... 6-48
Measvm Plot Tool ......................................................................................................................... 6-49
FC Relay Setup Tool ..................................................................................................................... 6-51
CON Table Screen ........................................................................................................................ 6-52
Import/Export Connections Menu .................................................................................................. 6-54
Options Menu............................................................................................................................... 6-55
Connection Table.......................................................................................................................... 6-56
Utilization Log File ........................................................................................................................ 6-59

Launching the Customer Preferences Tool ........................................................................................ 7-1
Main Customer Preferences Screen .................................................................................................. 7-1
Datalog Control Preferences ............................................................................................................ 7-5
Handler Options Screen .................................................................................................................. 7-6
Parallel Handler Timing Chart .......................................................................................................... 7-8
Bin Table Example .......................................................................................................................... 7-9
List of Figures-4
List of Figures
Selecting the GenHCIF.dll................................................................................................................ 7-9

Handler Menu .............................................................................................................................. 7-10
Prober Engineering Form Screen.................................................................................................... 7-10
HCIF Pictorial ............................................................................................................................... 7-13
Amphenol Connector Close-up....................................................................................................... 7-13
Handler Parallel Interface Pinout - Amphenol.................................................................................. 7-14
Alternate DB25 Handler Interface Bracket ...................................................................................... 7-15
Alternate DB25 Handler Interface Signals ....................................................................................... 7-16
Bin Table Tool Screen ................................................................................................................... 7-18
Sample Bin Table ......................................................................................................................... 7-19
Custom Data DLL Screen .............................................................................................................. 7-20
Wafer File Definition Flowchart ...................................................................................................... 7-23
Wafer File Maker Screen ............................................................................................................... 7-24
Setup File Tool - Special Fields ...................................................................................................... 7-27
Multipass Flowchart ...................................................................................................................... 7-29
Preferences Tool - Engineering Options.......................................................................................... 7-30
Updating the Registry ................................................................................................................... 7-30
Launch the Setup File Tool from the Start Menu ............................................................................. 7-31
Initial Setup File Tool Screen ......................................................................................................... 7-31
Setup Files Location...................................................................................................................... 7-32
Job Plan Name and Executable Entered.......................................................................................... 7-32
Limits File Chosen......................................................................................................................... 7-33
Limits File Displayed ..................................................................................................................... 7-33
Saving the Setup File .................................................................................................................... 7-34
Saved Setup File Location ............................................................................................................. 7-34
Launching the Launcher................................................................................................................ 7-35
KVD Test Program Launcher Screen............................................................................................... 7-35
Entering Operator and Lot Data..................................................................................................... 7-36
Double-click a program name to launch it....................................................................................... 7-36
Program Launch Flowchart............................................................................................................ 7-37
Engineering Launcher ................................................................................................................... 7-38
Main Production Screen ................................................................................................................ 7-43
Engineering View.......................................................................................................................... 7-44
Test Statistics View....................................................................................................................... 7-45
Changes to Production View .......................................................................................................... 7-46
Speed-Up Techniques ................................................................................................................... 7-47
Bin Trend Chart............................................................................................................................ 7-48
Password Required ....................................................................................................................... 7-48
Bin Setup Tool.............................................................................................................................. 7-49
Bin Trend Chart With Legend ........................................................................................................ 7-50
Alarm Window.............................................................................................................................. 7-50
Site Data - Bins Per Site ................................................................................................................ 7-51
Site Data - Statistics Per Site ......................................................................................................... 7-51
Clearing an Alarm ......................................................................................................................... 7-52
Clearing an Alarm - No Supervisor Required ................................................................................... 7-52
Changes to Test Statistics ............................................................................................................. 7-53
List of Figures-5
Test Statistics View....................................................................................................................... 7-53

Test Statistics - Hidden Tests Options ............................................................................................ 7-54
Engineering View.......................................................................................................................... 7-54
Select Tests to Plot MEASVM ......................................................................................................... 7-55
MEASVM Results........................................................................................................................... 7-56
Histogram Plot Selection ............................................................................................................... 7-56
Test Results ................................................................................................................................. 7-57
Break on Test Number .................................................................................................................. 7-57
Runtime Breakpoint Event............................................................................................................. 7-58
Break on Failing Test Number........................................................................................................ 7-58
Runtime Breakpoint Event............................................................................................................. 7-59
Track Result by Test Number ........................................................................................................ 7-59
MPDCMOD ..................................................................................................................................... 8-1
MPDCMOD DC Sources ................................................................................................................... 8-1
MPDCMOD Block Diagram With Software Commands ........................................................................ 8-2
Test Head Motherboard .................................................................................................................. 8-8
MPDCMOD User Voltmeter With Software Commands ..................................................................... 8-12
MPDCMOD I/O Pinout ................................................................................................................... 8-16
HPDCMOD Pictorial ....................................................................................................................... 8-17
HPDC Module Block Diagram with Software Commands................................................................... 8-18
HPDCMOD I/O Pinout ................................................................................................................... 8-24
Relay Matrix (RMX) Pictorial .......................................................................................................... 8-28
RMX Block Diagram ...................................................................................................................... 8-29
RMX I/O Pinout ............................................................................................................................ 8-35

DSPIO Pictorial............................................................................................................................... 9-1
DSPIO Board Block Diagram............................................................................................................ 9-1
DSPIO Rev. 4 Photo........................................................................................................................ 9-2
DSPIO Master Block Diagram .......................................................................................................... 9-4
Digital Drive Memory ...................................................................................................................... 9-5
Digital Drive Vector......................................................................................................................... 9-6
Compare Pattern Data .................................................................................................................... 9-7
Serial Send Memory........................................................................................................................ 9-9
Serial Capture Memory.................................................................................................................. 9-10
Memory Banks in the DSPIO.......................................................................................................... 9-11
Pattern Editor Screen.................................................................................................................... 9-21
Pattern Compiler Screen ............................................................................................................... 9-22
Pattern Editor and Compiler Tool - Code View................................................................................. 9-22
Pattern Editor and Compiler Tool - Column Edit Mode ..................................................................... 9-23
Find Text Dialog Box..................................................................................................................... 9-23
Replace Text Dialog Box ............................................................................................................... 9-24
Go To Line Number Dialog Box ...................................................................................................... 9-24
Pattern Editor and Compiler Tool - Graphical View .......................................................................... 9-25
Pattern Editor and Compiler Tool - Digital Pin Format View .............................................................. 9-25
List of Figures-6
List of Figures
Master Clock Setup Tool................................................................................................................ 9-26

Pattern RAM Memory Management ................................................................................................ 9-29
Digital Clocking Block Diagram ...................................................................................................... 9-30
Timing Diagrams of the Various Formats ........................................................................................ 9-35
Pin Electronics Block Diagram........................................................................................................ 9-37
DSPIO Father Card Pin Assignments .............................................................................................. 9-49
Block Diagram of CAPTURE and DRIVE Shift Registers .................................................................... 9-50
Details of CAPTURE and DRIVE Shift Registers ............................................................................... 9-51
OPCODE SHIFT REGISTER CONTROL............................................................................................. 9-52
Two Channel 8-bit ADC CAPTURE .................................................................................................. 9-53
Two Channel 8-bit DAC & DRIVE Shift Register............................................................................... 9-54
Block Diagram of DSPIOTI Chip..................................................................................................... 9-55
Pattern State Controls................................................................................................................... 9-56
Sequencer Opcodes ...................................................................................................................... 9-57
Flag Opcodes ............................................................................................................................... 9-58
DIGMOD 16 ................................................................................................................................. 9-62
DIGMOD 32 ................................................................................................................................. 9-62
DIGMOD Block Diagram ................................................................................................................ 9-64
Pin Electronics.............................................................................................................................. 9-65
Select DIGMOD16R7..................................................................................................................... 9-66
Calibration and Checker Options .................................................................................................... 9-67
Pattern Manager........................................................................................................................... 9-91
Main DM Pattern Editor screen ...................................................................................................... 9-99
DM Pattern Editor Graphical View ................................................................................................ 9-100
DM Pattern Editor Format View.................................................................................................... 9-101
Help Screen ............................................................................................................................... 9-102
Logic Analyzer............................................................................................................................ 9-104
Results for Pins of Interest .......................................................................................................... 9-105
Use the Span and Position Sliders to Adjust Resolution.................................................................. 9-106
Results Shown in the DM Pattern Editor ....................................................................................... 9-107
Schmoo Plot............................................................................................................................... 9-108
SHOW CHANS Screen ................................................................................................................. 9-112
CONFIG Screen .......................................................................................................................... 9-113
LEVELS Screen ........................................................................................................................... 9-114
TIMING Screen .......................................................................................................................... 9-115
PMU Screen ............................................................................................................................... 9-116
FREQ Screen .............................................................................................................................. 9-117
SEQUENCER Screen.................................................................................................................... 9-118
TMU Pictorial.............................................................................................................................. 9-119
TMU Block Diagram .................................................................................................................... 9-120
TMU I/O Pinout .......................................................................................................................... 9-121
Test Head Motherboard .............................................................................................................. 9-122

Simplified PWD, Single Channel, Clock Relationships ....................................................................... 10-2
Simplified PWS, Single Channel, Clock Relationships........................................................................ 10-3
List of Figures-7
Waveform Source Pictorial ............................................................................................................ 10-6

WS Block Diagram ........................................................................................................................ 10-7
WS I/O Pinout .............................................................................................................................. 10-8
Precision Waveform Source Pictorial............................................................................................. 10-13
WS2000 Precision Waveform Synthesizer Block Diagram ............................................................... 10-15
Waveform Digitizer Pictorial......................................................................................................... 10-22
WD Block Diagram...................................................................................................................... 10-23
Waveform Digitizer Hypertronics Pinout ....................................................................................... 10-24
Precision Waveform Digitizer Pictorial........................................................................................... 10-28
WD2000 QUAD Audio Digitizer Block Diagram............................................................................... 10-30
DSP Clocking.............................................................................................................................. 10-49
Waveform Source DSP Block Diagram .......................................................................................... 10-50
WS DSP – DAC Program.............................................................................................................. 10-51
Sampled Sine Wave .................................................................................................................... 10-52
Direct Digital Synthesis ............................................................................................................... 10-53
Chapter 11: Non-Instrument Software Command Summary
List of Figures-8
Purpose of the Manual
The M2 Test System Windows Programming and Operations Manual is intended to be a single reference
for this model of KVD ATE system. It is not designed to be an in-depth reference for the semiconductor
ATE universe, nor should it be used to gain an expert knowledge of mixed-signal DSP principles. Other
resources will be pointed out for obtaining this knowledge.
The target audience is experienced semiconductor test engineers transitioning from the ATE systems of
other vendors, who are already familiar with test concepts such as digital test techniques, precision analog
measurement systems, and grounding issues peculiar to ATE.
On the maintenance side, service personnel must have working knowledge of good ESD practices, careful
mechanical adjustment and replacement techniques, and the willingness to perform thoughtful
troubleshooting flowcharts if necessary to discover the root cause of problems.
Recent Major Changes to the Manual

• Added sections from DIGMOD and DSP training documents.
• Merged in most 5.02 and 5.03 Release Notes and screenshots of new features.
• Better discussion of multisite programming and operation.
• Relocated all instrument software commands from the summary in Chapter 11, which is now reserved
for non-instrument objects such as LOG and SYS.
Where to Look for Online Help

Always look under the Start menu for various "How To Documents" and for KVD "New Feature Notices".
The latest information is distributed on-line in this way with new library software releases, as well as
emailed to registered customer addresses. To join this list, please send an email to service@kvdco.com
with your request.
The master on-line help file is located under the Start menu->KVD Help->KVD Library Help.
1-1
Figure 1.1: Help Menus
Click on Symbol Reference if necessary to open the list. Then click on Classes to open a list of KVD
classes.
Select a class and open it, then click on members to obtain a list of functions in another window. Clicking
on a function will then display an explanation in the main help window.
Figure 1.2: Help Window
This KVD Manual will also be available in PDF format, either on the individual system or on your
company's servers, according to your administrator's preferences.
Quick-Start Guide
There is a generic (blank) test program shell available to quickly begin with a compilable job plan. Read
about it in Chapter 6, and you can soon be exploring the debugging environment and production GUI
displays. Your development group may also have its own custom test program template, with specialized
functions to make your job easier. Consult with administrators or your manager.
1-2
Introduction and Overview
Nomenclature
Here is a short list (by no means exhaustive) of acronyms and terms used in this manual which may be
unfamiliar.
• KVD - Kundrouf / Veitas / deHollan, the last names of the founders of the KVD Company
• ATE - Automatic Test Equipment
• DUT - Device Under Test
• DSP - Digital Signal Processor/Processing
• PDU - Power Distribution Unit
• DIN - Deutsches Institut für Normung (European standards institute referenced for instrument and
motherboard connectors)
• Hypertronics - Manufacturer of the low resistance, two-piece connectors used in various locations,
especially in the test head.
• IDE - Integrated Development Environment
• DLL - Dynamically Linked Library (software program only usable by other programs, and only loaded if
required - thus saving resources such as load time and memory space)
• GUI - Graphical User Interface
• Borland - Vendor of C++ Builder, the KVD software and debugging environment
• PCIDIS - Personal Computer Interface - Digital Interface Standard. The acronym of the KVD serial bus
to PCI interface board, located in the CPU.
• DISCONT - Digital Interface Standard - Controller. The acronym of the KVD serial bus interface to test
head instrument interface board, located in the test head.
Warnings and Cautions
Warning! Maintenance Instructions described in this manual are for use by trained and qualified staff
only. To avoid risk of personal injury or hazard to human life, do not open covers, remove
safety interlocks, or troubleshoot any items with the AC power turned on. These Warnings and
this Manual are not represented to document all possible or foreseeable hazards associated
with test equipment of this class, and there is no substitute for personal common sense for risk
avoidance.
Caution! All electronic equipment, including your KVD Test System, contains items which can be
damaged or latently degraded by Electro-Static Discharge (ESD). You will enjoy a longer and
more satisfying relationship with your equipment if you always practice safe ESD techniques.
This includes personal grounding systems (wrist strap or conductive foot-wear), static-safe
workstations for handling maintenance items, and the constant use of static-proof packaging
and shipping materials for all electronic items.
1-3
System Overview
Figure 1.3: M2 System
There are various packaging and cabinet options. The standard M2 cabinet is pictured above. There is
room for an additional 7" of rack-mounted equipment at the lower front part of this cabinet.
For test floors with space challenges, KVD offers the M2m system, with integrated manipulator and a
cabinet with no additional rack space.
1-4
Figure 1.4: M2m Cabinet and Manipulator
Figure 1.5: Dimensions of the M2m
Feature Summary
The M2 Mixed Signal Test System is designed to test high volume, low to medium pin count consumer
Mixed Signal semiconductor ICs. The system contains analog and digital instrumentation integrated into a
test head, and design features to maximize throughput.
1-5
The system can be configured to address various types of devices: RFID, SmartCard, Automotive,
Standard Linear and Mixed Signal, Image Sensors, Audio Processors and RF devices.
A tightly-integrated laser trim interface is available, with communication over a dedicated Ethernet
connection to enhance robustness and reduce message latency.
Testing multiple devices on one system in parallel dramatically reduces the cost of test for devices with
short test times. The system software handles the multi-site nature of testing, freeing the test engineer
from the complexities of such multi-site testing. The M2 Mixed Signal Test Systems include:
• Multi-Site Architecture
• Inherently Low-Noise Floor Design
• Windows Production Software Interface
• C++ Test Language and Development Environment
• Mixed Signal Digital Pins with Send/Capture Memory
• Range of DC Source/Voltmeters
• Time Measurement Unit
• Waveform Synthesizers/Digitizers
• Optional Instruments designed for specific applications
Device Families Tested on the KVD M2

Imagers (M2i Test System) Industrial
CMOS - CIF to > 16 MPixels Op Amps
CCD Comparators
ADC
RFID DAC
Smart Cards Analog Switches
Garage Door Openers VREG
Remote Keyless Entry VREF
Alarms Power Drivers
Embedded Microcontrollers PWM
Phase Locked Loops Sense Amps
Oscillators
1-6
Telecommunications Interface
Line Cards SCSI Terminators
Codecs Passive Terminators
Modems
DTMF Automotive
SLIC Electronic Ignitions
ISDN Anti-Skid Braking
Cellular Telephones Electronic Fuel Injection
Mobile and Portable Radio Electronic Power Train
Temperature Controlled Oscillators Engine Control
Electronic Motor Controllers
1-7
1-8
Safety Statement
The general safety information in this summary applies to both Operators and Maintenance Personnel.
Warning! Only trained and qualified personnel should work on the equipment documented in this
manual. To avoid risk of personal injury, limit your maintenance or operations activities to
those described in this manual unless you are trained to do additional tasks.
Warnings and Cautions
Caution! Statements indicate that conditions are present that could result in damage to the test
equipment or other property.
Warning! Statements identify conditions or operations that could result in injury or loss of life.
Danger! Statements indicate a personal injury hazard immediately accessible.
only. To avoid risk of personal injury or hazard to human life, do not open covers or
troubleshoot any items with the AC power turned on.
Operator Safety
The general safety information presented in this summary is meant for both operators and service
personnel. Specific warnings and cautions will be found where they apply, but may not appear in this
summary.
2-1
Maintenance Personnel Safety
General Working Safety

The maintenance of KVD equipment can expose the service person to hazardous voltages, particularly
when adjusting the system power supplies. Only authorized and trained personnel should work on KVD
equipment.
Shock Hazards Contained in the Test System

The test system Power Supply Assembly contains various power supplies and control circuit elements
where hazardous AC voltages may be present.
Figure 2.1: Power Supply Danger Label
The CPU contains a certified and sealed power supply assembly, not user-maintainable. No energy of a
hazardous nature comes out of this assembly.
The Keithley 2000 DMM is also a non-maintainable assembly, with no hazardous voltages appearing at its
terminals.
The KVD test system test head assembly, likewise, contains no hazardous voltages according to ANSI
definitions. All voltages present are less than 30V RMS, 42.4V peak, or 60 VDC, so there are no interlocks
or other required cutoff circuits.
Lithium Battery Caution
Warning! There is a risk of an explosion of the battery on the CPU motherboard is replaced with an
incorrect part number.
Replace only with the same, or an equivalent, item as recommended by the CPU motherboard
manufacturer, when the battery life is exceeded and the CPU on-board clock no longer keeps
time properly when the CPU power is shut off. Dispose of used batteries according to the
manufacturer's instructions, or return to KVD for proper disposal.
2-2
Safety and Regulatory Summary
Electrostatic Discharge
Electrostatic Discharge (ESD) can occur whenever proper procedures are not followed. Static voltages as
low as 25V can cause catastrophic or latent failures in semiconductor devices, so proper grounding is
essential to safe handling of these devices. A conductive wrist or heel strap should always be used when
handling boards, and these straps should be checked regularly to insure that they are working properly,
and replaced when defective. System circuit boards should be properly transported in static shielded bags,
and only removed from their packaging at static safe workstations.
The KVD test head includes a standard grounded banana jack, for connecting an operator or maintenance
staff ESD straps.
Figure 2.2: ESD Caution Label
Protective Grounding
The test system is grounded through the protective grounding conductor of the power cord. To avoid
electrical shock the grounding conductor must be connected by the customer to a properly-wired
receptacle.
The test system cabinet is attached to protective (earth) ground by means of a green/yellow wire
connected from the cabinet frame to the grounding terminal of the Power Distribution Unit. The attachment
points for this wire are marked with the following symbol at each end:
2-3
Figure 2.3: Protective Ground Identification Label
Do not operate the test system without this wire being attached securely at each end.
Ergonomic Statement
The KVD M2 test system includes the equipment cabinet, the test head, a CRT monitor, keyboard, and
mouse. Since each customer's test floor environment is unique, KVD does not provide a work surface or
seating for the operations or programming personnel. Thus it is up to the customer to provide ergonomic
accommodation for the user, terminal, keyboard, and mouse, to satisfy SEMI standard S8-0999.
Chemicals
There are no relevant chemicals involved with the operation, manufacture, or maintenance of this
equipment. Various parts of the test head that come into contact with contaminants may need cleaning,
and the choice of method and cleaning materials is left to the discretion of the customer.
Ionizing Radiation
This system has no ionizing radiation hazards.
2-4
Physical Installation
Unpacking and installation will be performed by KVD service engineers or your local representative
distributor. Please do not uncrate or unpack the test system, or discard any packing materials, until the
authorized representative inspects for shipping damage and powers the system up successfully.
The test system weighs less than 500 pounds (225 Kg), so no special arrangements need to be made for
floor strength.
The M2 and M2m systems can pass through doors having 30" openings. Typically no special
arrangements need to be made for door or hallway passages.
The test head weighs approximately 25 pounds (11Kg), depending on configuration.
Utilities
The test system requires a protected circuit rated at 15 Amps of 115VAC single-phase power. (+/- 10%),
50 or 60 Hz. 230VAC is available as an option. The customer must provide overcurrent protection in the
form of a circuit breaker or fuse to satisfy all local regulations.
Environmental
The environment must be maintained at 20-30 Degrees Celsius, and 20%-80% non-condensing humidity.
Maintenance Access Space

Aisles can be combined with adjacent systems for efficiency. Cabinets are on casters for movement and
rotation in case of restricted access. See drawing.
3-1
Figure 3.1: Maintenance Access Space - M2 Test System
3-2
Unpacking and Installation Guide
Figure 3.2: Maintenance Access Space - M2m Test System
Handler/Prober/Laser Trimmer Interfacing

Covered in Chapter 7: Operations Environment.
3-3
3-4
The Test System Cabinet contains the AC PDU, DC Power Supply Assembly, CPU, and the Calibrator
DMM.
The Test Head contains the test instrument boards, the motherboard, and the device-specific Fathercard.
An optional test head manipulator, if present, may be integrated as part of the main Cabinet or as a free-
standing unit.
Figure 4.1: Main Cabinet
AC Power Distribution Unit

This unit is located at the top of the Cabinet, and contains the main AC circuit breaker on the front edge.
Figure 4.2: Power Distribution Unit (Front)
4-1
The rear surface holds a multiple power output strip for the various system elements, and the single power
input connector.
Figure 4.3: Power Distribution Unit (Rear)
The Remote/Local PDU Switch is a feature for possible ganging of multiple PDUs. It is presently not used,
and the switch should always be in the LOCAL position. If it is not, the PDU will not power up and the test
system will not operate.
Figure 4.4: Remote/Local PDU Switch
This unit is sealed and needs no user maintenance. The unit contains a main breaker, line filter, surge
protection, and a remote control relay board for possible master/slave power distribution design.
Danger! The PDU is never to be opened with the AC Power cord attached. Hazardous voltages are
present within.
Figure 4.5: Main Power Switch
4-2
System Hardware
The Main Power Switch also serves as the Emergency OFF control for the system. The circuit breaker
being used has a 5,000 Amps A.I.C. (Amperes Interrupting Capacity) when connected to the customer
supplied external circuit breaker or fuse panel. It is required by all jurisdictions that cord-powered
equipment such as the KVD test system be protected by an external overcurrent protection device.
All AC power connectors are the international IEC standard for 15 Amp current. Internal relays limit the
PDU supply to 10 Amps for each bank of four output AC receptacles. As long as all four standard elements
of the test system are not plugged into the same bank, this limitation will not be exceeded.
Note: Line Voltage AC Power is totally contained within the Test System Cabinet, and is not brought out
to the Test Head. This enhances safety for the operator and maintenance personnel, as well as
lowering the power frequency noise level in the test head.
4-3
Figure 4.6: AC Power Flow Block Diagram
4-4
System Hardware
Figure 4.7: Power Distribution Unit Wiring
DC Power Control and Flow

DC Power Cables connect the Main Power Supply Assembly with the other elements of the system.
The CPU contains a control circuit for a solid-state relay in the Power Supply, so it can be powered on and
off by software command. The Test Head also contains a power switch that can override the software
control to shut the DC power OFF.
The Keithley Calibrator measurement lines are routed through the test head cables for convenience.
4-5
Figure 4.8: DC Power Flow Block Diagram
4-6
System Hardware
The following applies only to the original series of KVD power supplies, not the alternative Power Plus
supplies used in systems with DIGMOD instruments The PowerPlus supply is controlled via a USB
controller board.
Figure 4.9: Origination of the Control Signal on the PCIDIS
Figure 4.10 shows how the DC control signal originates from the PCIDIS board in the CPU, passes
through the Power Monitor board in the Power Supply Assembly, and then goes to the test head. After
passing through the power switch in the test head, it loops through the three test head cables (to ensure
for safety that the test head power goes off if any of the three cables is disconnected) and ends up at the
Solid State Relay in the Power Supply Assembly. This SSR is designed to only turn on when the AC line
voltage is at zero, thus reducing to a minimum the inrush current to and the stress on the supplies.
4-7
Figure 4.10: Power Control Schematic
4-8
System Hardware
CPU Overview
Heavy-duty industrial enclosures are used to house the Pentium CPU, with front-integrated fans and filter
assemblies for maintenance ease.
Packaging
Figure 4.11: New CPU Front View
The CPU is slide-mounted in the main cabinet, and can be pulled forward for servicing, or removed for
heavier maintenance. Safety latches are part of the rails, and must be pushed aside to allow total removal.
Often, one latch must be pushed, and the CPU pulled forward slightly to make sure the latch does not lock
again while the other side is being unlatched. This is sometimes a challenging process - please do not
become frustrated.
Figure 4.12: New CPU Rear View
Inside the CPU chassis are the motherboard, internal storage options, CPU power supply, and KVD add-in
boards.
Details of the CPU may change as newer technology becomes available.
4-9
Figure 4.13: CPU Internal View
Motherboard
Figure 4.14: CPU Optional Boards
Various optional and add-in boards are installed by KVD according to customer configuration needs.
These could include video drivers, GPIB, serial communications, handler interface, and alternative network
boards.
Standard KVD boards include the high-speed data communication port to the Test Head. (PCIDIS)
4-10
System Hardware
Figure 4.15: CPU Add-in Boards
PCIDIS
Figure 4.16: PCIDIS Pictorial
The PCIDIS (Personal Computer Interface - Digital Interface Standard) is used to communicate with the
instruments in the test head. The interface card is connected to the test head via a standard 50 pin SCSI
connector. This connector routes four sets of serial output buses and four sets of serial input buses
between the computer and the test head.
4-11
The PCIDIS converts the address and data information on the CPU's PCI bus into serial data for
transmission to the test head. The PCIDIS contains four 12.5MHz serial buses for communications with the
test head. The first two serial buses are used for side 0 and 1 of the test head. The remaining two buses
are reserved for future development.
Data written from the computer to test head address 0x100 to 0x1FF is converted to serial words and
transmitted up the side 0 serial bus. Data written to address 0x200 to 0x2FF is transmitted serially through
the side 1 serial bus. Data written to address 0x300 to 0x3FF is converted to serial words and transmitted
to side 0 and side 1 simultaneously.
The PCIDIS card employs the use of field programmable gate arrays (FPGA) in implementing the digital
logic functions necessary to convert the PC parallel bus data to the SCSI serial bus format. The FPGA
resident on the PCIDIS must be loaded, or "booted", before the card can be used.
HCIF and PHLIC
Figure 4.17: PHLIC Card
The legacy parallel handler interface board in the PC was called the HCIF.
The PHLIC card is the replacement for the HCIF card. The reason for this is due to the PC industry
discontinuing the ISA bus standard, which was used for the HCIF. The PHLIC card has many advanced I/
O features that will allow it to control a large variety of handler, probers and laser trimmers. Test programs
will not need to change, and peripheral control will be transparent as to whether the HCIF or PHLIC is in
use.
Features overview:
• PCI bus based for compatibility with future PC mother boards.
• 16 Inputs and 16 outputs, all optically isolated.
• 2 Isolated Interrupt sources for use in dual-site start test pulse capture.
• Isolated +5 Volt 100 mA power supply for driving opto isolators.
4-12
System Hardware
• 37 pin female D connector for easy cable connection, or custom adapters according to customer
preference to emulate other tester cable schemes.
• Complete software compatibility with HCIF handler drivers
• Additional features accessed through PhlicClass.cpp driver class
• PhlicChecker program allows full loopback testing of the card
• PhlicTool allows individual control of all I/O lines for diagnostics
Laser ETTL Interface
Pending
CPU Features
Rack mount - metal enclosure
CPU Pentium IV, 2GHz. or better
Memory 512 MB minimum main memory
Disk Capacity 20.0 GB minimum
PCIDIS Timer 1 µ s resolution for timing of setup delays
Operator Console SVGA color terminal
Network 10/100 Base T Ethernet
Prober Interface GPIB
Handler Interface PHLIC Parallel port, GPIB
4-13
Peripherals
• Floppy disk drive

• CD-RW
• Front access USB for flash drive
Figure 4.18: Peripherals Bay
Communication
Typical communication cables may include:

• GPIB or parallel to a handler/prober
• Ethernet to corporate LAN and laser trimmer
• GPIB communication to the Keithley or Agilent Calibrator
Since each customer's configuration may be slightly different, the implementation details are not
documented here.
Power Supplies
There are two series of supplies, depending on the system configuration. Previous to the DIGMOD
instrument availability, all supplies were a combination of linears and switchers mounted to a motherboard.
DIGMOD systems use what's called the PowerPlus supply, with two multiple-output switchers in a cabinet
with a USB controller.
4-14
System Hardware
DC Power Supply Assembly
The main DC Power Supply Assembly is contained in the same industrial housing as used for the CPU.
This allows for the same rack-mounting rails to be used, for ease of maintenance or adjustment.
Figure 4.19: Power Supply Enclosure
Behind the left door on the front of the Assembly is a foam air filter, which should be inspected every
month, and cleaned as needed. When the filter is removed, check for proper operation of the one or two
cooling fans.
Figure 4.20: Power Supply Fan Door
4-15
With the top cover of the Power Supply removed, you can observe the various linear and switcher supplies
installed.
Figure 4.21: Power Supply Interior
4-16
System Hardware
Distribution
The rear panel of the Power Supply contains connectors for AC power input, three circular connectors for
Test Head power cables, one control and communication cable to the CPU, and one to the Keithley
Calibrator.
Note: All five cables are differently-sized, eliminating any possible cabling errors.
X1 To Test Head
X2 To Test Head
X3 To Test Head
X4 Keithley Calibrator
X5 CPU Control
Figure 4.22: Power Supply Rear Panel
Nomenclature of DC Power Wiring
In the KVD tester, positive voltages are preceded with a P, and negative with an N. Examples: P5V (for
+5V), N12V (for -12V)
If the voltage has a decimal point, as in 5.2V, it is written as 5P2 to ensure that the decimal point is not lost
in multi-generational copying. Example: N5P2V (for -5.2V)
A supply used for analog circuits (with lower noise requirements than digital circuits) will have the suffix F,
standing for "filtered". Example: N15VF (for -15V filtered)
The high voltage rails used for various circuits are called PHV and NHV, for positive HV and negative HV
respectively. Voltages on these rails is dependent on the tester configuration, but is usually from -20V to
+40V maximum. Not all power supply versions contain these rails.
4-17
Fuses
There are various glass cartridge fuses contained inside the Power Supply Assembly in case of failures or
shorts.
Figure 4.23: Power Supply Motherboard
4-18
System Hardware
Figure 4.24: Power Supply Motherboard Locations
Figure 4.25: Fuse Detail
4-19
Overtemp Resettable Circuit Breaker
Certain power supplies also contain a resettable overtemperature circuit breaker, to guard against failure
of the cooling fans in the enclosure. If the power supply assembly shuts down, and it is not caused by
missing AC power, or any of the control circuits (test head power switch, front panel power switch, CPU
software control GUI), you should suspect the internal thermal circuit breaker.
Look for it inside the power supply, attached to the 5V supply in location 9 (usually). If tripped, you will
need to manually reset the central button, which will go back in with a click. It is not an automatic resetting
breaker, because it will only trip in case of a fault such as inoperative cooling fans, which you need to take
action inside the power supply to fix.
Figure 4.26: Thermostat Overall Location
Figure 4.27: Thermostat Detail
4-20
System Hardware
Figure 4.28: Thermostat Control Wiring
Power Supply Variations
There are variations of the power supply assemblies for various customer configurations. All supplies
contain a line filter, SSR (solid-state relay) for remote control, input fuses where the line cord connects to
the rear panel, fan(s) for cooling, and a Power Monitor board that has features designed for future
enhancements to voltage monitoring and diagnostics.
Standard Linear Used For M2 Mixed Signal Systems

This supply is built with all linear supplies, for the lowest possible noise floor in this package size.
Mixed Linear/Switcher Used For M2m Test Systems

Many devices tested by the M2m test system require slightly different HV rails, so this supply was
designed with asymmetrical rails, of +40V and -20V.
Enhanced Supply Used For Some M2i Imager Test Systems

Same as standard linear, except that the P5V supply is upgraded to a 20A switcher from the original 12A
linear. Used only in certain configurations of M2i test systems.
Converted Supply From a Laser Trim System to an M2m

Most shipments of laser trim systems were originally +/-30V rails, and due to customer requirements, were
converted to +40, -20V. The jumpers to accomplish this make the block diagram slightly different, which is
shown in Figure 4.32.
4-21
Figure 4.29: M2 Linear Power Supply DC Block Diagram
4-22
System Hardware
Figure 4.30: M2m Power Supply DC Block Diagram
4-23
Figure 4.31: M2i Enhanced Imager Power Supply DC Block Diagram
4-24
System Hardware
Figure 4.32: Converted Laser Power Supply DC Block Diagram
4-25
Power Plus Power Supply

Power Plus (Multi-output Switcher Power Supply) and Power GUI
For support of new instruments, most importantly the DIGMOD high speed digital subsystem, we offer the
Power Plus power supply assembly, and a required upgrade test head assembly with improved cross-flow
air cooling. The test head contains at least eight fans (four on each side), but some configurations have as
many as 12. If you have an installation using a manipulator mount that could cover the test head side that
used to be blank, please contact KVD service for suggestions about mounting alternatives.
Note: TMU Minimum Rev "D" needed: for new PowerPlus power supply and test head systems.
TMU instruments of at least rev level "D" will be required for this configuration system.
• The obsolete P10V power bus, which was unused in earlier M2 test systems, now carries +24V. The
previous TMU circuit had components touching this power bus that were not rated for 24V, which had
to be removed.
• TMU ECL inputs from the motherboard DSPIO channels have better noise immunity with a modified
pull-up resistor value.
Choosing the Proper Power Supply in the TCT
Currently the most used choice is the "PW" emulation mode, although low voltage rail selections such as
the 16V option will be used in the future.
4-26
System Hardware
DC Output Capabilities
Digital Supplies
+5V*: 35A *= Kelvin (F & S) wiring.
+12V*: 50A|
-5.2V: 10A
+48V: 7.5A
Analog Supplies
+/- 20V: 8A
+/- 15V: 8A
+24V: 4A
+/- 12V: 1A
+/- 5V: 10A
PHV + Rail for MP and HP Modules selectable (levels below)
NHV - Rail is fixed to 20V
Control Features
• USB plug and play control from CPU
• X5 cable from CPU to Power Supply no longer needed.
• Status checking of AC-ready signals
• Remote switching (controlled by TCT - Tester Configuration Tool) between HV and LV instrumentation
supply rails. Selectable from three choices:
• 16V
• 24V
• 40V
Maintainability Features
• +5 and +12 cartridge fuses located inside enclosure. All others accessible behind front door by
maintenance staff.
• All supplies monitored by front panel indicators.
• Heartbeat LED in the "HDD" position of the enclosure will blink when the supply is under positive USB
control.
4-27
Figure 4.33: PowerPlus Front Panel
Power Supply GUI

Similar to previous one, but with a status readback tab.
Figure 4.34: Power GUI
4-28
System Hardware
Figure 4.35: PowerPlus Status Tab
Block Diagram
Pending completion.
4-29
Figure 4.36: PowerPlus Supply Overview
4-30
System Hardware
Figure 4.37: Power Plus Supply Pictorial
4-31
Figure 4.38: PowerPlus Block Diagram
4-32
System Hardware
PowerPlus Internal Arrangement
Figure 4.39: PowerPlus Internal View
4-33
Figure 4.40: PowerPlus Digital Supply "A"
4-34
System Hardware
Figure 4.41: PowerPlus Analog Supply "B"
Figure 4.42: Cartridge Fuses
4-35
PowerPlus Control Wiring
Figure 4.43: PowerPlus Supply Wiring - ON/OFF Control
4-36
System Hardware
Dual Cal Bus Switching
Figure 4.44: Dual Cal Bus & DMM Wiring
Cables & Connectors

X1 - Calibration Bus and Miscellaneous Signals to Test Head
This cable connects the Power Supply to the test head, and brings the cal bus and other control signals to
the motherboard.
• VMLO is the voltage cal bus, which various instruments connect to so the Keithley or Agilent DMM can
measure their outputs.
• VMLO4W is the current cal bus, routed to the DMM for measuring current sources.
4-37
• AGND is Analog Ground

• DGND is Digital Ground
• ACON is a control signal sent from the power supply to the power switch in the test head, then looped
through the other cables as a safety measure to the SSR in the power supply
• Other signals are not used, and may be used for future expansion.
Figure 4.45: X1 Cable Connector
Figure 4.46: X1 Pinout
X2 - Analog DC Power
4-38
System Hardware
This connector carries analog DC power to the motherboard in the test head. SPR pins are spare, for
expansion or future custom use. ONOFFB and ONOFFC are used for the DC control signal, and detect if
this cable is unplugged to shut down the power supply.
X3 - Digital DC Power
This connector carries digital DC power to the test head motherboard. ONOFFD is a pin for the SSR
control signal, and ensures the power supply cannot be powered on if this cable is disconnected.
4-39
X4 - Keithley Cal Bus
The cal bus (Calibration Bus) signals are sent from the test head motherboard through the power supply
assembly. A Keithley 2000 or 2002 DMM option uses the X4 cable. If your configuration uses an HP/
Agilent 3458A DMM, a slightly different cable with banana plugs is in use.
4-40
System Hardware
X5 - CPU Power Control
Currently, the only active signal on this connector is the ONOFFA pin, which comes from the CPU PCIDIS
board, routes through many cables and the test head power switch, and ends up at the power supply SSR
to turn it on. If the power supply fails to power up, trace this signal to find the open circuit.
Systems using the PowerPlus supply will not have this cable, since power supply control is entirely USB-
based.
4-41
Hypertronics
Figure 4.55: Hypertronics Connector (Male)
Hypertronics are very low resistance and reliable connectors used on the top edges of the KVD
instruments to connect to the father cards. The male pins are on the instruments, and you must use care in
handling them to avoid bent pins. They are brittle and do not often bend straight without micro-fracturing,
thus reducing their life.
Figure 4.56: Hypertronics Female on Fathercard (Close-up)
The female receptacle is the secret to their low resistance, having a hyperbolic arrangement of tiny wires,
so the male pin is touched in multiply redundant places, instead of the usual 2-4 point contacts by a fork
connector. They can accommodate a few millimeters of engagement depth as well, so the father card
connections have more reliability than the typical pogo pin contacts.
4-42
System Hardware
Calibrator
Figure 4.57: Keithley 2000 DMM
Optional Calibration Meters
For increased accuracy, KVD offers support for Keithley 2000, 2002, and HP/Agilent 3458A DMMs. The
cal meter in use must be selected in the TCT. All other functions for meter operation during calibration and
checkers are automatic.
Important Father Card Note - Precision Meter Measurements
Some father cards are designed with independent cable access to the meter, for use in real time test
programming. Some of these tests are sensitive enough that the presence of the cal cable injects noise
into the measurement. Thus when calibration is finished, the cal cable must be removed from the rear of
the Keithley 2002, or the front panel FRONT/REAR switch must be pushed (to select the FRONT inputs)
on a 3458A configuration. Selecting the wrong configuration will cause cal to fail in one case, or yield to fall
in the other case.
Keithley Capabilities and Specifications
The front of the meter contains a series of mode and range setting buttons which provide manual access to
the various meter settings. The Keithley can be used as a standard voltmeter if the user provides the test
leads and presses the Local button which switches the Keithley out of remote mode.
The Keithley uses three inputs for calibration, a ground, a voltage input and a current input.
These three wires create the calibration bus which is routed from the test head through the mainframe
power supply and then to the Keithley. The instrument which is to be calibrated is connected to the
calibration bus and the meter is manipulated via the RS232 or GPIB port to make the appropriate
measurement.
Which port is used is typically set by the factory, and can be modified if necessary in the program called
the Tester Configuration Tool, or TCT. This is documented in the Production Environment chapter.
4-43
The DMM acts as a NIST traceable calibrator for the instrumentation in the test head. For detailed
accuracy and drift characteristics, please see the Keithley manual, included with all system shipments.
Measure Capabilities DC voltage and current

AC voltage and current
Resistance, Frequency
Resolution 6 digits
Long term accuracy 35ppm (voltage)
Figure 4.58: Keithley 2000 Spec Summary
Modifications
The Keithley voltmeter does not provide a current input port on the rear panel of the meter, which requires
KVD to remove the connections from the rear panel inputs and short the rear inputs to the front inputs. This
modification allows the use of the rear voltage and ground inputs and the front current input.
Note: Because of this change, the front/rear input switch, located on the front panel of the Keithley,
should be left to the "front" setting at all times. If it is changed, then the DUT sources will pass their
voltage cal, but fail all current range calibrations with zero for readings.
Figure 4.59: Keithley Input Button
4-44
System Hardware
Figure 4.60: Keithley DMM Rear Panel
Figure 4.61: Rear Panel Connector Modifications
Figure 4.62: Internal Fuseholder Added for Current Calibration
KVD also installs a separate internal fuseholder for the current cal bus input. In case of a failure to calibrate
all of the DC source's current functions, but the voltage cal is OK, this fuse is a suspect for going open.
Remove the Keithley from the system, then remove its cover, and check the fuse with an ohmmeter. A
proper replacement is 3A fast blow.
4-45
Calibration
Figure 4.63: Calibration
This is the diagram of the cal bus path from the test head motherboard to the Keithley DMM. The return
side of the cal bus is connected to Analog Ground in the Test Head. The signal names of the cal bus are
VMLO for voltage cal, and VMLO4W for current. For the motherboard bus definitions, see “Motherboard
Bus Signal Definitions” on page 4-52.
During operation, the front panel of the Keithley DMM may display the readings as they happen, or they
may be suppressed for speed.
Test Head
The test head is the second of the two major components of the test system. It contains all of the test
instruments that directly drive and measure the device under test. All instruments connect to a common
backplane (called the "Motherboard") which provides the power supply rails and data I/O ports.
The Motherboard is partitioned into two symmetrical sets of slots, called sides. SIDES are designed into
the package for convenience, but have nothing to do with the software concept of testing SITES, of which
the KVD can handle 32.
Opposite the Motherboard, each test instrument has at least one Hypertronics connector that provides I/O
access to the device under test through a board called the Fathercard.
The Fathercard is similar to the DUT interface boards used on other types of ATE equipment except that it
contains serial interface controlled relay driver ICs used to open and close the relays. Instruments that can
populate the test head include a DC source and voltmeter module, a set of digital subsystem modules, a
waveform generator card and a waveform digitizing card.
4-46
System Hardware
Figure 4.64: Test Head
Mechanical
Test Head is approximately 14" x 14" x 7" enclosure, with possible fan plenum extensions on certain
variants. The Test Head mechanics allow overhead probe mounting.
Test head weight is approximately 25 pounds. (11 Kilograms)
4-47
Figure 4.65: Test Head Mechanical
Mother Boards
The Motherboard serves as a passive backplane for the test head modules. Located at the bottom of the
test head card cage, the Motherboard is a printed circuit board with up to 24 slots available to hold test
head instrumentation cards. The DC power cable connects directly to the Motherboard from the power
supply assembly located in the main tester cabinet.
The Motherboard as a test head backplane provides two primary functions. First, it connects the power
supply rails from the power connector(s) to the test head instrumentation modules. Secondly, it provides
interconnection traces between certain Motherboard card slots.
This is a test head without instruments, showing the Motherboard at the bottom.
4-48
System Hardware
Figure 4.66: Empty Test Head
This is the Motherboard without the enclosure, showing the DIN connectors used to connect to the
instrument boards, along with the symmetrical slot arrangement for the two sides. Slots 0 through 6 on
each side are designed for full-width instruments, using three DIN connectors; slots 7-11 are for single-
width instruments. There is normally a card guide surrounding the center hole, which can be used for
microscope access, or to house the LED illuminator for CMOS Imager test heads.
Figure 4.67: Test Head Motherboard
Test heads have two sides. Side 0 (Zero) is always on the end with the power cables. Side 1 (One) is away
from the power cables.
Side 0, Slot 0 (Zero) is dedicated to the exclusive use of the DISCONT Data Communication board.
4-49
Figure 4.68: Populated Test Head
Figure 4.69: Test Head Cables
The other cable at the left of this photo is the communication cable from the CPU. It appears to be a
standard SCSI cable physically, but the signals are not SCSI. Do not ever plug in a SCSI data chain to this
connector or cable. You can also see the DC power switch to the right of the fan.
4-50
System Hardware
Figure 4.70: Analog and Digital Ground Test Points
Analog and digital grounds are usually connected together at this point on the Motherboard, since they
need to be tied together somewhere to prevent them from drifting apart, and the system can be operated
and calibrated without a father card or DUT board.
This is a detailed close-up of the DIN connector. Inside the plastic ramp is a gold-plated metallic fork. In
case of a bent male pin on an instrument board, you may find damaged plastic ramps on the female side.
This is one place to observe closely in case you suspect intermittent connections or erratic instrument
behavior.
Figure 4.71: DIN Connector (Female)
4-51
Motherboard Bus Signal Definitions
Motherboard Digital Bus
Figure 4.72: Motherboard Digital Bus
The digital bus goes to all instrument slots, both large (3 DIN connectors) and small (1 DIN connector). It
carries the data bus from the DISCONT board, the cal bus, and all power rails as well.
4-52
System Hardware
Motherboard Interconnect (IC) Bus
Figure 4.73: Motherboard Interconnect (IC) Bus
The Interconnect Bus is available for future designs, if a board set is required that needs to communicate
among themselves but not on the main KVD data bus. This is also used in our current DSPIO and
DIGMOD implementation, for master/slave clock distribution and vector address communication.
4-53
Motherboard Analog Bus
Figure 4.74: Motherboard Analog Bus
The Analog Bus is available to carry signals from boards such as DUT Sources to resources such as
digital instruments. This is the method used by DS1 to connect to various digital channels for continuity
tests, using DDBUSA, for instance.
4-54
System Hardware
DISCONT
Figure 4.75: DISCONT Pictorial
The Digital Interface Standard Controller (DISCONT) card works in conjunction with the PCIDIS to create
the data communications link between the system computer and the test head.
The DISCONT card acts as the communications liaison between the computer and the test head modules.
The DISCONT accepts the serial data from the PCIDIS via the SCSI cable, decodes it and outputs the
resulting address and data to the appropriate test head module.
In the opposite direction, the DISCONT receives data from the various test head modules, formats the data
for transmission over the SCSI cable, and sends the data to the PCIDIS for processing by the system
computer. The DISCONT board has four distinct serial bus interfaces: two for receiving data from the
PCIDIS and two for sending data back to the PCIDIS.
The DISCONT board allocates one receive and one send bus to each of the two test head sides allowing
for true parallel communications with both test head sides.
The DISCONT also carries small chip fuses, to protect the digital DC power supplies which it passes
through from the motherboard to the father card.
Connections from the DISCONT to the father card are grouped into two 33-pin Hypertronics - one for
power and grounds - the other for bi-directional serial data buses used for controlling relays, loading Xilinx
FPGAs, data converters, and other father card resources.
4-55
Connector Pin Assignments
These are the pin assignments of the DISCONT board to the Fathercard Hypertronics connectors.
Figure 4.76: DISCONT to Fathercard Pin Assignments
4-56
System Hardware
This is the signal definition for the 50-pin connector used from the PCIDIS to the DISCONT board. It is a
SCSI-appearing connector in physical form factor, but note that it is NOT true SCSI.
Figure 4.77: PCIDIS to DISCONT Signals
High Speed Link (HSL)

Pending
4-57
Father Cards
Figure 4.78: Father Card Pictorial
The test head Father Card serves as the device interface board between the device under test and the test
head resources. It mounts on top of the test head modules (opposite the motherboard) and connects to the
instrumentation resources through the Hypertronics connectors located on top of each of the
instrumentation modules.
Each Father Card has unique signal connections for each test device and often contains numerous relays
for complex connection schemes. The DC source outputs from the MPDC Module are often routed through
networks of Father Card relays to create a matrix-like environment allowing for great flexibility in source
and voltmeter connections. Digital I/O connections are typically routed directly to the device but may be
connected to any point on the Father Card. However, for ease of troubleshooting, many designers route
digital channels through isolation relays.
Relay driver ICs are located on-board the Father Card to provide the voltage necessary to the energize the
relay coils. The relay driver ICs are controlled by serial bus lines generated on the DISCONT board.
This is a more efficient use of interconnect pins than the normal ATE architecture of having a separate
relay driver board requiring one interconnect per relay driver.
4-58
System Hardware
When allocating resources the Father Card can be configured with great flexibility. The DC source and
measurement resources within a test program typically require the greatest connection flexibility. This is
achieved on the Father Card by setting up several "resource buses". These connection networks are
created from a number of main bus wires. Generally, one bus wire is allocated for each DC source on each
side.
All resource or device pin connections made to the resource bus are through relays located on the Father
Card. This allows complete isolation of the resource bus from all Father Card locations. On the resource
side, the bus wire is assigned a DC source connection and, in most cases, a voltmeter connection. Device
pin connections are then allocated to each bus after consideration of the DC needs they will require. It is
common to connect device pins to more than one resource bus to allow for various connection schemes.
Within the test program, resources are connected and removed from the resource buses as the need
arises. When source or measurement connection to a device pin is required, all other pins can be
removed. Device supply and reference pins are often the lone device pins on a given resource bus in
cases where the device under test requires a supply rail.
Figure 4.79: Father Card Top View
4-59
DC Power Wiring
Figure 4.80: Father Card Power Supply Monitor LEDs
DC Power is connected to the Fathercard through dedicated Hypertronics pins as follows:
From the DISCONT board (always slot 0), intended for Fathercard Digital resources:
• P5V (+5V)
• N5P2V (-5.2V)
• P12V (+12V)
From the first DUT Source board (typically Side 0, Slot 1), intended for Father Card Analog resources:
• P12VF (+12V Filtered)
• P15V (+15V)
• N5VF (-5V Filtered)
• N15V (-15V)
• P5VF (+5V Filtered)
• N12VF (-12V Filtered)
And from an MPDCMOD or HPDCMOD (if present):

• PHV (Positive High Voltage)
• NHV (Negative High Voltage)
Note: Depending on the Power Supply Configuration in your test system (set at the factory for the device
families you will be testing) there are two possible variations of the PHV/NHV rails: [+/- 30V] and
[+40V/-20V]
KVD Fathercard designs typically include monitoring LEDs and test points for all DC power supplies to aid
in quick troubleshooting.
4-60
System Hardware
Fuses
Besides fuses in the Power Supply Assembly in the main test system cabinet, these DC supplies are also
fused on the DISCONT and DCMOD boards, to reduce the risk of Hypertronics pin and Fathercard PC
damage in case of accidental short circuits.
Note: Recent KVD change orders recommend use of 4Amp fuses on all test head instruments, to reduce
nuisance opening. That way, if the father card fuse is a lower value, it will open preferentially
before the instrument fuse on the same voltage, and it is far easier and faster to replace the father
card fuse.
Most Fathercard designs include fuses on the Fathercard, many of them now socketed instead of surface
mount.
These are opaque fuses, and cannot be visually inspected like glass fuses. If a suspected power supply
failure causes a Fathercard monitor LED to go dark, please also investigate the Fathercard, the DISCONT
or MPDCMOD board as appropriate. Spare fuses are available from KVD to avoid the expense of sending
a DISCONT or MPDCMOD board back to the factory for a simple fuse repair. You must take care when
replacing them to use an energy-controlled soldering station such as ones made by Metcal, to avoid
damaging the pads that the fuses are soldered to.
The commercial part numbers and code markings are as follows:
0.5A Code "FF" Digikey F1232CT-ND Littelfuse 429.500
1.0A Code "FH" Digikey F1234CT-ND Littelfuse 429.001
2.0A Code "FN" Digikey F1238CT-ND Littelfuse 429.002
4.0A Code "FS" Digikey F1274CT-ND Littelfuse 429.004
Socketed (father cards and newer instruments) - Littelfuse 451 series:
0.5A Digikey F1141CT-ND
DC Cable Motherboard Board Board Fuse KVD Fuse Hypertronics

Supply Pin Bus Fuse Value P/N Pin
P5VF X2-F X1/2-A/B/C15 DCMOD F261 2A 13-00002-SM SA2-22
MPDCMOD none SA1/2-22
N5VF X2-K X1/2-A/B/C11 DCMOD F263 2A 13-00002-SM SA2-23
P15VF X2-D X1/2-A/B/C17 DCMOD F1 2A 13-00002-SM SA2-20
4-61
DC Cable Motherboard Board Board Fuse KVD Fuse Hypertronics

Supply Pin Bus Fuse Value P/N Pin
HPDCMOD none SA1-18
MPDCMOD none SA1-18
N15VF X2-H X1/2-A/B/C13 DCMOD F262 2A 13-00002-SM SA2-25
HPDCMOD none SA1-15
MPDCMOD none SA1-15
PHV X2-C X1/2-A/B/C18 DCMOD F265 OPEN SA2-19
HPDCMOD F1,F4 4A 13-00004-FA SA1-19
MPDCMOD F1,F2 4A 13-00004-FA SA1-19
NHV X2-G X1/2-A/B/C14 DCMOD F266 OPEN SA2-26
HPDCMOD F2,3 4A 13-00004-FA SA1-16
MPDCMOD F3,F4 4A 13-00004-FA SA1/2-19
P5V X3-A/F X1/2-A/B/C22 DISCONT F1 2A 13-00002-AX SA2-1,2
P12V X3-G/H X1/2-A/B/C19 DISCONT F2 2A 13-00002-AX SA2-7,8
N5P2V X3-J/K X1/2-A/B/C20 DISCONT F4 2A 13-00002-AX SA2-19,20
P12VF X2-E X1/2-A/B/C16 DCMOD F260 2A 13-00002-SM SA2-21
N12VF X2-J X1/2-A/B/C12 DCMOD F264 2A 13-00002-SM SA2-24
Figure 4.81: Chip Fuse Chart
Grounds
Analog and Digital ground planes are kept separate in the power supply and cables, but are typically
shorted together on the test head motherboard.
The Zero Volt Reference for the DUT Sources and all measurement systems is called GROUND SENSE,
and for best accuracy, must be connected to the DUT at only one point. Connecting it at a ground plane
point distant from the DUT is possible, but may introduce an error proportional to the ground plane
resistance and the current flow in it between the DUT and the GROUND SENSE connection.
In many cases, this will only be a fraction of a millivolt, but the effect needs to be carefully considered if you
are measuring or attempting to correlate to a sub-millivolt accuracy level.
4-62
System Hardware
Relays and Relay Drivers
The KVD architecture is unusual in that there is no separate instrument board for relay drivers, as it was
judged to be a unnecessary dedication of relatively expensive resources such as test head slots and
Hypertronics pins. Rather, a serial bus from the DISCONT board is used to control relay drivers on the
Fathercard itself, and all registers and drive circuits are available for easy troubleshooting.
Figure 4.82: Coto Relays on the Father Card
DUT Cards
Some custom Father Card and DUT board designs are using 68-pin Hypertronics connectors exclusively.
Custom applications documentation will be provided by the responsible applications engineer.
Custom Father Cards
Additional Father Card designs created by KVD include versions to test families of power conditioning
devices, data converters, laser-trimmed devices, and CMOS image sensor devices including multi-site.
Schematics of custom father cards are provided as a troubleshooting aid to the customer. Custom
application items have a warranty, but failures are normally handled on a return-to-factory basis due to the
uniqueness of the items. For this reason, customers with particular needs for production uptime should
stock their own spares.
Please contact the factory to discuss any possible requirements you might have for testing new
configurations or device families.
4-63
4-64
Safety Warning
only. To avoid risk of personal injury or hazard to human life, do not open covers, remove
safety interlocks, or troubleshoot any items with the AC power turned on.
ESD Warnings and Procedures
Instrument Replacement Instructions

Removing Test Head Instruments
1. Turn off Test Head Power by using the test head rocker switch or the software command icon on the
desktop of the monitor.
2. Remove the Father Card cover if present.
3. Remove the Father Card if present by loosening four captive screws, then carefully pulling up around
its edge. Take care to not tilt the Father Card excessively during removal, to avoid bending
Hypertronics pins on the instruments
4. For full-width instruments (with three DIN motherboard connectors) in slots 0 through 6, use the board
edge ejectors to loosen the board for removal. For single-width instruments in slots 7-11, carefully pull
them out by grasping the edges of the Hypertronics connector body.
Inserting Test Head Instruments
1. Inspect the new instrument for bent pins on both the Hypertronics and the DIN connectors to avoid
later damage.
2. Being careful to replace the instrument in the correct slot, insert it without using excessive force.
3. If the instrument is one that has not been present in the test head configuration before (if you are
adding an additional DSPIO, for instance), make sure to use the TCT (Tester Configuration Tool) to
add the instrument to the test head configuration.
4. Install the Father Card, taking care to orient it properly, side 0 and side 1. There are four steel locating
pins on each Father Card to prevent reversal.
5. The four captive screws do not need to be tightened for short-term experiments, just before release of
the tester back to production.
6. Power up the Father Card by reversing your previous method of powering it off.
5-1
7. Check DC voltages at the test points on the Father Card if you suspect power supply issues.
8. If you are adding an instrument permanently to the test head configuration, you may need to adjust
power supplies to compensate for the added load. To ensure that the power supply comes up safely
even with an open wire in the cables, the supplies have their force and sense wires shorted inside the
power supply, not remoted to the test head motherboard. This has the side effect of possibly requiring
adjustments in case of load changes. (adding or removing boards permanently)
Figure 5.1: Inspect for Bent Male DIN Connector Pins
Repairing Surface Mount Fuses
If necessary due to an accidental short, such as during father card or DUT board debugging, you may
need to replace a surface mount (chip) fuse on an instrument board. Please use only the proper energy-
controlled soldering tools for this purpose, such as a Metcal brand soldering station, and water-soluble
flux, followed by a suitable rinse and drying process. Do not under any circumstances use rosin flux on any
KVD instrument, as permanent contamination and leakage may occur.
Subassembly Replacement
Power Supply
1. Power down.
2. Remove cables with circular connectors from rear panel, plus AC power cord(s).
3. Remove screws from front rack mounting flanges and slide assembly out from the front.
4. Release slide latches on each slide rail by using a flat-bladed screwdriver to press the latch spring to
the OUTSIDE direction. Pulling forward on each side of the supply as you release the latch will reduce
frustration as the latches have a tendency to click back into locking position.
5-2
Calibration and Maintenance
Figure 5.2: Slide Rail Latches
CPU
1. Power down.
2. Remove all cables on the rear of the CPU, plus the AC power cable.
3. Make sure you note which is the mouse and keyboard cable. If not marked well on the rear of the CPU,
the LOWER one is the keyboard, and the UPPER one is the mouse. The CPU will not pass the POST
(Power On Self Test) if these are reversed.
4. Also make note of which is the upper and lower Ethernet network cable if there are more than one, and
keep them separate from the CAT5 network cable we use for the High Speed Link.
5. Remove the CPU in the same way as the Power Supply Assembly.
Keithley or Agilent DMM
1. Power down.
2. Remove the X4 round cable from rear of Keithley, as well as the AC power cable, and the RS-232 or
GPIB communications cable, whichever one is present.
3. Remove four mounting screws from the front of the cabinet, and remove the Keithley for repair or
recalibration as required. See Paragraph 5.14 for the recalibration interval requirement.
Note: Some early KVD test systems used a mounting tray to hold the Keithley, which requires the
maintenance engineer to remove an access plate and unscrew the Keithley from below. Contact
KVD if you would like to upgrade to the newer mounting bracket design for ease of future
maintenance.
Preventive Maintenance
Monthly
• Inspect all fans for proper operation: Test Head, Power Supply Assembly, and CPU.
• Clean fan filter pads in Power Supply and CPU
• Check DC Power supplies at the Father Card against the specs given in the following chart. Adjust
voltage only if necessary as trained. Do not adjust current limits.
5-3
• Check free space on hard disk to make sure that files have not been allowed to accumulate to the
point where production could be halted by a full disk. Typically this would be a danger if the disk were
above 80% full. Consult with your responsible software staff if this is a recurring issue.
• Calibration and checker results are stored in folders which are not currently cleared out, and could
grow without bound. Especially wasteful of disk space are histograms, which should be cleared out
regularly if not archived, and are not useful unless you're looping a checker. Go to
C:\_kvdco_CustFiles\Calibration, and in a folder for each instrument type, remove the files you do
not wish to retain.
• Ensure that the responsible staff has been performing software backups if not done automatically by
network connection.
Supply Nominal Minimum Maximum
P5V +5.00 +4.85 +5.15
P12V +12.00 +11.85 +12.15
N5P2V -5.20 -5.05 -5.35
P5VF +5.00 +4.85 +5.15
N5VF -5.00 -4.85 -5.15
P12VF +12.00 +11.85 +12.15
N12VF -12.00 -11.85 -12.15
P15VF +15.00 +14.85 +15.15
N15VF -15.00 -14.85 -15.15
P20VF (on motherboard +20.00 +19.85 +20.15

only)
N20VF (on -20.00 -19.85 -20.15

motherboard only)
PHV Depends on System:

Standard: +35.00 +34.80 +35.20
M2m: +40.00 +39.80 +40.20
NHV Depends on System:

Standard: -35.00 -34.80 -35.20
M2m: -20.00 -19.80 -20.20
Figure 5.3: DC Power Supply Adjustment Limits
5-4
Figure 5.4: Example Power Supply Adjustment Points
Software Backups
If necessary at your site, these should be done according to your local responsible staff's instructions.
Installing New KVD Library Releases
1. Open the KVD installation CD, or obtain the newest library release from our FTP site according to
instructions given to your responsible staff.
2. Move the released library, with a name of the form KVDLib0503Release3.exe, to your system's
desktop or other convenient location. This name will change according to the update level of the
release.
Note: Do not attempt to launch or install it directly from the CD-ROM. Errors may result.
3. Double click on that executable to install the system software.
Note: If you are installing the "No Tester" version, your CPU must have a licensed copy of the Full Install
of Borland C++ Builder Professional, and the Borland Update Patch (available on the KVD
Windows Support Disk or from the Borland web site.) The "No Tester" library is supported on the
Windows 98, 2000, and XP operating systems only at this time.
5-5
Figure 5.5: Install question screen
Figure 5.6: KVD Library Installation Screen
Installing Software on a New Hard Disk

If you need to perform this operation in the field, make sure you have the required auxiliary files on CD-
ROM from the factory before beginning.
You will also need your original Windows installation CD-ROM, and license key, possibly your CPU
Motherboard Installation disk (for motherboard-specific drivers), along with your site copy of the Borland
C++ Builder installation CD-ROM.
5-6
Motherboard Driver Support
Refer to your motherboard manual and CD-ROM for installation instructions and BIOS configuration
settings. Each system shipped from KVD includes the CPU motherboard manufacturer's manual and CD-
ROM, but the exact model and manufacturer may change according to technology improvements and
availability. KVD cannot guarantee consistency of all subassemblies such as this among test systems
shipped at different times. The test systems will perform to published specifications, however, and
interoperability is assured.
Configuring a Windows XP System
Make sure you have all the necessary software and drivers:
• The driver for mother board
• WinXP PCI GPIB driver
• Borland C++ CD
• BCB5ProUpdate1.exe
• Kvd library release
First place to stop is the BIOS.
1. Press DEL to enter setup.

2. Go to the Boot tab.
3. Plug & Play OS: Enabled - Boot Virus Detection: Disabled - Bootup Floppy Seek: Disabled
4. If the OS is going to be Window 2000 please make sure PnP is OFF
5. Save and exit.
When the PC first boots up and starts to finalize the Windows XP Installation, there will be prompts for the
PC's name and whether you want to configure the PC on a domain. Please ask your MIS people to setup
the network now or skip it and have them do it later.
When you are able to log in to the machine, do so as the administrator account to the local machine.
• The machine name will appear in the Log On dialogue
• If there will be a general account for most users, then you might want to spend some time setting up
the environment.
Run Window XP update.
Installing Borland C++ Builder 5
1. Use the Borland C++ Builder 5 CD from your package to start the install.
2. When you chose the version of C++ you want to install, make sure chose FULL INSTALL.
Note: The key you will need to install both Borland and the Update is included on the Borland license
paperwork that was shipped with the system, or on the CD-ROM.
3. Reboot the machine, when it's done.

4. Run BCB5ProUpdate1.exe from your backup CD.
5-7
5. Now, you will need to install the KVD library.

6. There is another Borland user update you will need to run, you can find it from Start button ->
Programming Tools -> Borland C builder user update.
Configuring Borland
Note: Needs also to be done per user.
1. When Borland is opened, go to Tools - Editor Options, then Code Insight. Uncheck Code
Completion, Code Parameters, and Tooltip Symbol Insight, then select OK.
2. Open Tools again => Environment Options. Turn on Autosave Options and uncheck Background
Compilation.
3. Start from Tools again and go to Debugger Options then Event Log. Uncheck all under General.
5-8
4. Last go to Project => Options => Compiler, select Use Pre-compiled Header.
Installing PCI-GPIB Driver
Assuming the board has been installed physically, just need to install the driver. First run setup.exe file
from folder PCI GPIB WinXP. Follow the instruction and select PCI-GPIB for the board #1, and none for
board #2.
5-9
Restart the computer when done.
From the Start menu => Programs => gpib-32 library, run config.
Follow the instruction and selection PCI-GPIB for board 0 and none for board 1.
Then from Start menu => Programs => gpib-32 library, run test.
If everything returned ok, then we are finished with GPIB install.
Installing for PCIDIS, PHLIC, and PowerPlus USB
The driver for PCIDIS, PHLIC board and power supply driver are all in the folder C:\_kvdco\PCIDIS_INF.
When Window XP detects this hardware, just point the driver out from the list.
The PowerPlus USB driver may be more tricky, due to not wanting the Plug and Play FTDI Universal Serial
Bus USB driver. If this driver shows up in the Device Manager (due to an unwanted XP Automatic update),
you will need to remove it. One clue that the PowerPlus USB control is not automatically running on a port
and detecting the USB board in the supply is that the Power Control GUI will look like this non-USB-
enabled one:
5-10
Then you need to go into the System Device Manager, open the line for Universal Serial Bus controllers,
and delete the item that says USB Serial Converter, if you right click on it, and its properties do NOT say
it's an FTDI -KVD Power Supply Controller.
5-11
This is the proper display for the driver.
5-12
If you need to update the driver, use the wizard and proceed as follows:
5-13
5-14
5-15
At the end of the process, the Device Manager will display it as "KVD Power Plus", and when you reboot
and launch the power GUI, the heartbeat LED on the supply will flash steadily, and the power GUI will have
this appearance, with a status tab:
5-16
Installation Swapping Tool
For experimenting with new releases, the new Programming Tool->Installation Swapping Tool can
save a few minutes going back and forth.
Note: From 5.03R2 forward, recalibration will not be necessary just because you swap releases, as long
as both the old and new libraries are at 5.03R2 or later. This could save significant time while
running beta experiments. If the cal file format ever changes in the future, the names will also
change, and this may trigger a need for recalibration. Having a stale calibration may also require a
re-cal. But simple library-swapping will not.
Offline Emulator Mode - Notester Install

Notester Emulation Mode
Tester versus notester emulation mode is now determined at runtime instead of when the KVD Release
software is installed. This has the benefit of allowing the engineer to compile on an offline system, and the
executable can run without recompiling on a tester. Also, all tools are available from any install.
The notester choice selection has been removed from the install screen, which displays the target
Operating System, the KVD Library number being installed, and you only have two choices.
5-17
If you wish to have only the KVD proprietary Image File Viewing Tool installed on an off-line computer,
check the upper box. If you wish to group the KVD shortcuts under one selection under your Start menu,
check the lower box.
Test Head Power Control

There are both hardware and software controls for test head power. The hardware control is a rocker
switch on the cable end of the test head. The original Power Supply Assembly also has a power push
button behind the door on the right side of its front face, but this almost never is turned off except by
maintenance personnel.
The software ON/OFF control is either a Desktop Icon, or a START Menu program, that you need to turn
ON to energize the solid state relay in the Power Supply Assembly.
Figure 5.7: KVD Power Control Icon
Remember that BOTH of these controls must be energized to power up the test head.
Every time the power is cycled to the test head, the XILINX FPGA chips must be booted, in order for them
to contain their programmed personalities. The operator is usually prompted to boot the test head, or it is
forced automatically, a choice which is set in the Customer Preferences Tool.
Power-off Reboot Required to Reload PCIDIS Xilinx
The PCIDIS board in the CPU has a modified Xilinx programming file in 5.03R2 (for DIGMOD HSL
support), and the normal warm reboot will not force a Xilinx reload. You must at least once shut the CPU
power off totally, and perform a cold restart.
5-18
Tester Configuration Tool - TCT
Figure 5.8: Tester Configuration Tool Screen
Functional Description
The TCT allows the user to configure the test head and communication ports on each KVD Test system.
The TCT writes not only user information, but standard KVD setup information into the Windows Registry.
All tools, along with any test program that uses a KVD library, read this setup information at the very
beginning of startup. The benefit of this is that the KVD Testers can be reconfigured for different products,
and the test programs/tools do not have to be recompiled.
The image above shows the main screen of the TCT.
The main page shows all the slots within the test head. By double clicking on a slot, the user is shown a list
of KVD supported hardware that can go into the slot. By selecting a board, the registry will be updated to
include the chosen board for the chosen slot.
5-19
Figure 5.9: TCT Screen with Configured Test Head
5-20
The image below shows the user has opened the instrument selection menu for a slot by double-clicking
on it.
Figure 5.10: Selecting an Instrument in the TCT
5-21
Similarly, the Power Supply Type, Father Card, and Calibration Meter type can be selected from a pull-
down menu after double-clicking their respective boxes. If your site is using any custom configuration
Father Cards, their choices will appear in this menu. Please ensure you know which is your correct choice
before selecting one. (in other words, don't guess)
Figure 5.11: Power Supply Selection
Figure 5.12: Father Card Selection
There are more choices for calibration meters. Keithley 2002 and HP3458A will offer enhanced accuracy
of calibration for MP and HP instruments than the original Keithley 2000.
The user can also select the disk and path to the XILINX files. The XILINX files are files KVD supplies to
'boot' the FPGAs in the test head. Having this selection as an option allows the pre-release testing of new
files, or the use of previous releases if subtle problems are found.
5-22
Shown in the image below, the XILINX files that will be used are on drive C in the folder named
_kvdco\Released Xilinx Files. This is the standard location, and should not be changed without good
reason and instructions from KVD Engineering.
Figure 5.13: Xilinx File Location
TCT configuration information can be saved to a file with the extension .tct_config, and loaded again using
buttons on the GUI. This can save time removing instruments from the TCT for minimum configuration
troubleshooting, for instance, and for quick restoration to the original config. These .tct_config files can
also be enforced by test program control using the KVD >LoadConfig function.
Notice at the top of the TCT application, there is another TAB labeled "Ports". Clicking on this TAB will
bring up another page that allows the user to change the port used for the calibration voltmeter, and also
the type of port being used.
5-23
The image below shows the Ports page.
Figure 5.14: TCT Ports Screen
In this configuration, the interface being used, that is, the interface attached to the Calibration Standard is
the GPIB port. All test systems should use GPIB for this choice, using the primary address of 16 (hex
10), with a secondary address of zero (hex 0).
On testers that are configured to be imager testers using the Tungsten-Halogen illuminator, the lower
portion of this page could be 'enabled' and similar port configurations would be entered. Systems using the
LED illuminators (any version) do not have need for these preferences, and should not be entered. There
is a separate tool for LED illuminator configuration selection, which is documented in the Imager
subsystem manual.
Finally, the very bottom of the TCT tool shows the TCT Revision, Root key, and a Status message area. If
there is ever a problem with TCT information being lost, or corrupted, these two pieces of information along
with any error messages, should be made available to KVD.
Figure 5.15: TCT Revision Field
5-24
Note: Once ANY change has been made to the TCT, on either page, the Update Registry button must be
clicked so that the TCT can save the changes to the Windows Registry.
If the TCT program is exited without an Update Registry being performed, any changes the user made are
lost.
Calibration and Diagnostics

Theory of Calibration
Calibration is the process whereby a real-world instrument, with inaccuracies and other features designed
to make it affordable, is compared to a more accurate standard. This standard can be traceable, which
means its measurements of voltage, current, and so forth, can be ultimately compared to the world's
standards, to make sure that all instruments agree to some degree of certainty. The standards institute for
the United States is the NIST (National Institute of Standards and Technology), which used to be called the
NBS, for National Bureau of Standards.
Calibration makes the instrument more "ideal" by comparing it to a transfer standard, then measuring the
inaccuracies, then compensating in hardware or software before the user ultimately uses the instrument.
The results are confirmed in checks later.
Long experience with real-world devices reveal that most errors are linear, due to built-in component
accuracies. KVD compensations are performed almost exclusively in software, and not using the alternate
technique of hardware adjustment DACs, which would add complexity and cost.
There are two main categories of errors: Offset and Gain, when we discuss the DC source or
measurement sorts of instruments. For digital instruments, there is also the category of errors in the timing
realm, where the difference between ideal and actual is measured by timing circuits instead of voltmeters,
but the theory is very similar.
5-25
The Ideal Instrument
In an ideal instrument, the actual measurements equal the desired ones.
Figure 5.16: An Ideal Instrument
5-26
A Real Instrument
You have offset error when the actual results are not zero when you want them to be zero.
Figure 5.17: A Real Instrument - Offset Error
5-27
You have gain error when the actual results are not full scale when you want them to be.
Figure 5.18: A Real Instrument - Gain Error
Always measure and compensate for offset error first. When you subtract the offset error, component
inaccuracies will still give you gain error. The slope of the ideal/actual line is NOT exactly 45 degrees until
you compensate for gain error.
Calibration Files
Each range of an instrument will have its own offset and gain errors
Each feature of an instrument can be calibrated, both sourcing and measurement functions
Assuming the instrument is linear can save time and complexity in the calibration process.
Calibration may not always be performed at full-scale values, depending on the calibration instrument.
Calibration factors are stored on the hard drive in files, but if you move instruments to new slot locations,
you always need to recalibrate. (Cal files are not currently indexed by instrument serial numbers)
5-28
A Surprisingly Bad Instrument
This is an example of a bad set of measurements which could be made by a diagnostic check, and the
interpretation suggests that the root cause might be a low power supply, that drifted out of spec after an
earlier good calibration. All the dots but one are in spec, where the actual is close to the ideal
measurement, and the single rogue measurement is at the high end of the instrument's range. (A possible
power supply fault, or failing instrument. Troubleshooting would involve measuring the power supply, and
then exchanging the instrument.)
Figure 5.19: A Surprisingly Bad Instrument
KVD Calibration and Checker Tool

Changes Since Release 5.02
Calibration and Checker programs were previously run from one integrated executable program, with a
custom GUI. This presented barriers for ease of updating, segregation of functions, and data
interpretation. For release 5.03, cals and checkers were all rewritten to execute as their own standard test
programs, using the normal production GUI and data storage features, with a wrapper/launcher program
called the Cal & Checker Launcher.
The previous Calibration program is no longer supported, and should be removed from the START Menu
shortcut list and anywhere else you may have a shortcut linked. Use only the Calibration and Checker
Launcher now.
Launch the program via the Start menu, -> Testhead Setup and Calibrate, then KVD Calibration and
Checker Launcher.
5-29
Fast Launch Tab
When the program launches, there are two tab choices at first, the top one showing fast launch buttons.
There is a single-button CalAll function, similar to the previous cal launcher, as well as CheckAll and
Check And Calibrate All buttons and a Boot Test Head button to check gross functionality of the data
bus.
Figure 5.20: Fast Launch Tab
As long as the DUT board is removed, you can press the button of your choice, and it will run unattended.
Each cal and checker program will run from a script, display the standard production GUI for a time, and
finish by showing a results summary display.
FPGA Booting Process
The following is a printout from a log file of BOOTing the test head, with various instruments being
programmed by the Xilinx files. The PCIDIS board is located in the CPU, whose power cannot be
interrupted as the test head can, so it almost always displays the result that it is already loaded.
If you accidentally configure the TCT with an instrument in the wrong slot, or if you remove an instrument
and do not remove it from the TCT, the Xilinx boot process will fail, with an error message about "maximum
retries exceeded." This may also happen in case of a failed instrument.
Running BOOT_ALL
B Boot PCIF with C:\xil370\PCIDIS.XIL Side, Slot = 3,10 subslot=0 base_addr=768
PCIDIS XILINX Already Loaded, Reloading
PCIDIS XILINX Loaded !!
D Boot DISCONT with C:\xil370\DISCONT.XIL Side, Slot = 3,0 subslot=0 base_addr=768
DISCONT Booted !!
M Boot DCMOD0_500MA with C:\xil370\DCMOD.XIL Side, Slot, VSlot = 1,1, 1 subslot=0
base_addr=256
M Boot WS with C:\xil370\WSXIL.XIL Side, Slot, VSlot = 1,3, 3 subslot=0 base_addr=256
M Boot WD with C:\xil370\WDXIL2.XIL Side, Slot, VSlot = 1,4, 4 subslot=0 base_addr=256
M Boot DSPIO0 with C:\xil370\DSPIOCNT.XIL Side, Slot, VSlot = 2,1, 1 subslot=0 base_addr=512
S Boot DSPIO0 with C:\xil370\DSPIOTI.XIL Side, Slot = 2,1 subslot=3 base_addr=512
S Boot DSPIO0 with C:\xil370\DSPIODD.XIL Side, Slot = 2,1 subslot=2 base_addr=512
S Boot DSPIO0 with C:\xil370\DSPIOADR.XIL Side, Slot = 2,1 Massubslot=1 base_addr=512
M Boot DCMOD1_500MA with C:\xil370\DCMOD.XIL Side, Slot, VSlot = 2,3, 3 subslot=0
base_addr=512
M Boot WD with C:\xil370\WDXIL2.XIL Side, Slot, VSlot = 2,5, 5 subslot=0 base_addr=512
M Boot TMU with C:\xil370\TMUXIL.XIL Side, Slot, VSlot = 2,8, 8 subslot=0 base_addr=512
A Boot STD_FC with C:\xil370\STDFC.XIL Side, Slot, VSlot = 3,12, 0 subslot=0 base_addr=768
12.5Mhz DIS Selected
5-30
Simulated LED Results
An overall PASS/FAIL result section shows at the bottom of the GUI. Yellow LEDs are programs in
progress, while black LEDs are programs that have not yet been run.
Figure 5.21: Simulated LEDs
Aborting a Program in Progress
If you wish to terminate any cal or checker program while the production GUI is on display, click on the
yellow termination bar just below the simulated LEDs.
Figure 5.22: Termination Bar
5-31
Calibration and Checker Options
You have the ability to run custom options in most of the cals and checkers, either limiting the number of
sources/channels run, various other selections, or program a repetitive loop. Choose the Options tab, then
click the selected options. Then press the Run Selected Programs button.
Figure 5.23: Calibration and Checker Options
Note: When a custom option field requires you to type in a value, a box will pop up. To clear the value
from the box currently requires you to type "-1" as a value in the box. As displayed, it says (-1 for
default).
5-32
Figure 5.24: Modify Custom Value Screen
Results Summary Display
After a Cal and/or Checker run, a summary of the results is shown, with red for programs that generated at
least one failure, and green for pass. This summary display is a list of hyperlinks to the real datalog files,
located in resource folders underneath C:\_kvdco_CustFiles\Calibration with date stamped filenames
such as the following:
dspiock_KVD-LASER153_060606_1321.log
Recent Improvements to MP and HP Cals
Changes were recently made to cal algorithms, meter ranging, and timing to improve headroom between
instrument performance and spec limits. Added in-house options to characterize amplifier thermal drift and
run at tighter limit percentages. New scatter test to characterize aging current range relays, which can be
run as a predictor of future failures and allow preventive maintenance. Scatter test should be run at some
longer interval than the weekly cal, at least once per quarter currently. Recommendations for longer-term
intervals will follow when we have more field data.
UVM Calibration has been enhanced in two ways:

• To better accommodate a slight discontinuity around zero, the cal algorithm now uses eight points per
range, four points each side of zero. Two best-fit lines are generated, one for positive and one for
negative values, again - per UVM range.
• For increased accuracy, gain and offset cal factors using the new algorithm, are applied to each
sample before averaging. This is especially useful when the sample population has points on both
sides of zero.
Any time KVD changes the calibration file format or algorithms, we now change the name of cal file to
reflect a new revision. Thus old cal files will never be inadvertently read in while running a new release. We
don't anticipate ever needing to clear out old cal files to encourage a new cal to succeed, but some
customers have found it useful. Please contact KVD service if you find yourself in that situation, so we can
consult on the issue.
Explanation of Calibration Activities
Initially, launching the calibration utility will open a connection to the Cal meter, either Keithley or HP/
Agilent. If this fails, then you need to troubleshoot either the meter power or communication. Typically
systems are configured using the GPIB port to communicate to the meter, so you must ensure that no one
has changed the front panel defaults. This often happens when the DMM is returned from an outside
calibration lab.
5-33
The basic flow is that Voltage features are calibrated first, then current. When calibrating a feature, we use
the instrument to force some value, and then measure it with the DMM using the cal bus. This reading is
used to calibrate the gain and offset for the forcing function. Then we use the A/D converter built into the
instrument to measure the SAME feature. This is used to calculate the measurement side gain and offset.
MPDCMOD Calibration
Pending a more complete explanation:
Here is a sample MPDCMOD cal log file. Note that the software library in use is displayed at the beginning
of the file, to act as an audit trail. In the MPDCMOD cal, we also keep track of a temperature sensor on the
instrument. There is only one per board, not one per channel, but we display it on a per-channel basis so
we can spot temperature drift easily, such as that caused by not allowing enough warm-up time before
starting a cal.
• Tests T200-T205 involve the Voltage Force function, Range 0, on MP DUT Source Channel 0
(MPDS0) MP channels begin at zero for ease of programming software.
• The initial tests on any function are the "RAW" measurements, before any calibration compensation is
done. If these measurements are outside limits, the cal will fail. In this case T200 and T201 are the
pre-cal readings.
• Forcing function cals are performed using the Keithley or HP/Agilent, so you will often see "DMM"
(stands for Digital MultiMeter) in the comments.
• T202 and T203 are the calculated gain and offset numbers for this voltage forcing range on MPDS0.
• T204 and T205 are a post-cal confirmation step, or checker, to make sure that the calculated gain and
offset numbers work properly to obtain in-spec performance from the instrument.
• Tests T206-T211 involve the built-in A/D converter, not the DMM. They ensure that the measurement
circuit is working pre-cal (Tests 206-207), then the system calculates gain and offset numbers for the
measurement circuit (T208-209), and finally, a post-cal checker confirms that the gain and offset are
operating in-spec.
Note: Tests T210-211 display the RESIDUAL error, not the actual measurement. We subtract the
measurement from the ideal number, and display only the difference, which is the reason these
numbers are quite small.
• Since there are four voltage ranges on the MPDCMOD, we repeat this process for Ranges R1, R2,
and R3.
• There are five current ranges on the MPDCMOD, and Tests beginning at T2505 perform the same
process for each of them. First, we measure the raw forcing accuracy with the Keithley, then calculate
gain and offset factors, then use those factors to check the forcing function accuracy. Next, we use the
built in ammeter to measure the same cal points, derive gain and offset numbers, then measure and
display the residual error.
• If any limits are exceeded, the word FAIL will be added to the right end of the cal log line, the cal GUI
cell that contains that cal factor will turn red, and the cal GUI will display a red virtual LED as a
reminder.
• Finally, the voltage and current clamps are calibrated, in this example in Tests T5386-5686.
5-34
----------------------------------------------------
---------------BEGIN DATA LOG ----------------------
---------------Start Log Time : 12/30/2005 9:58:58 AM
----------------------------------------------------
----------------------------------------------------
Program ID : C:\_kvdco\Checkers\mp_debug\mp_debug.exe (12/30/05 09:48:52)
Operator ID :
Tester : UC11
Fixture :
Lot ID : NOLOTNUM
Comment :
LimitsFile : C:\_kvdco\Checkers\mp_debug\MP_DEBUG.LIM (12/30/05 09:58:56)
BinFile : C:\_kvdco\Checkers\mp_debug\MP_DEBUG.BIN (12/30/05 09:58:56)
ParametersFile :
LibraryVersion : Version 05_03_Release_1
----------------------------------------------------
DEVICE(s) : 1
S0 T1 0=K2000 1=K2002 2=HP345 1.000000 Code 0.000 2.000
S0 T10 MP0 PreCal Temperature 35.000000 deg 0.000 60.000
S0 T200 MP0 FORCEV0 LO RAW -14.001970 V -16.000 -12.000
S0 T201 MP0 FORCEV0 HI RAW 24.164961 V 22.000 26.000
S0 T202 MP0 FORCEV0 GAIN 1.004393 V 0.500 1.500
S0 T203 MP0 FORCEV0 OFFSET 0.059531 V -2.000 2.000
S0 T204 MP0 FORCEV0 LO CAL -13.995553 V -14.012 -13.988
S0 T205 MP0 FORCEV0 HI CAL 24.001844 V 23.988 24.012
S0 T206 MP0 MEASV0 LO RAW -14.016663 V -16.000 -12.000
S0 T207 MP0 MEASV0 HI RAW 24.041798 V 22.000 26.000
S0 T208 MP0 MEASV0 GAIN 1.001607 V 0.500 1.500
S0 T209 MP0 MEASV0 OFFSET 0.001382 V -2.000 2.000
S0 T210 MP0 MEASV0 LO CAL 0.091788 mV -20.000 20.000
S0 T211 MP0 MEASV0 HI CAL -0.033339 mV -20.000 20.000
S0 T212 MP0 FORCEV1 LO RAW -15.038656 V -16.000 -14.000
S0 T213 MP0 FORCEV1 HI RAW 15.096373 V 14.000 16.000
S0 T214 MP0 FORCEV1 GAIN 1.004501 V 0.500 1.500
S0 T215 MP0 FORCEV1 OFFSET 0.028859 V -1.000 1.000
S0 T216 MP0 FORCEV1 LO CAL -14.999698 V -15.006 -14.994
S0 T217 MP0 FORCEV1 HI CAL 15.000463 V 14.994 15.006
S0 T218 MP0 MEASV1 LO RAW -15.022810 V -16.000 -14.000
S0 T219 MP0 MEASV1 HI RAW 15.025678 V 14.000 16.000
S0 T220 MP0 MEASV1 GAIN 1.001611 V 0.500 1.500
S0 T221 MP0 MEASV1 OFFSET 0.001051 V -1.000 1.000
S0 T222 MP0 MEASV1 LO CAL -0.011940 mV -10.000 10.000
S0 T223 MP0 MEASV1 HI CAL -0.162630 mV -10.000 10.000
S0 T2505 MP0 FORCEI0 LO RAW -148.643262 mA -180.000 -120.000

S0 T2506 MP0 FORCEI0 HI RAW 148.703060 mA 120.000 180.000
S0 T2507 MP0 FORCEI0 GAIN 0.991154 A 0.500 1.500
S0 T2508 MP0 FORCEI0 OFFSET 0.029899 mA -30.000 30.000
S0 T2509 MP0 FORCEI0 LO CAL -150.005966 mA -150.100 -149.900
S0 T2510 MP0 FORCEI0 HI CAL 150.000178 mA 149.900 150.100
S0 T2511 MP0 MEASI0 LO RAW -151.442059 mA -180.000 -120.000
S0 T2512 MP0 MEASI0 HI RAW 151.879252 mA 120.000 180.000
S0 T2513 MP0 MEASI0 GAIN 1.011050 A 0.500 1.500
S0 T2514 MP0 MEASI0 OFFSET 0.221522 mA -30.000 30.000
S0 T2515 MP0 MEASI0 LO CAL -4.694285 uA -160.000 160.000
S0 T2516 MP0 MEASI0 HI CAL 3.606983 uA -160.000 160.000
S0 T2517 MP0 FORCEI1 LO RAW -14.931523 mA -18.000 -12.000
S0 T2518 MP0 FORCEI1 HI RAW 14.941357 mA 12.000 18.000
S0 T2519 MP0 FORCEI1 GAIN 0.995763 A 0.500 1.500
S0 T2520 MP0 FORCEI1 OFFSET 0.004917 mA -3.000 3.000
S0 T2521 MP0 FORCEI1 LO CAL -14.999913 mA -15.010 -14.990
S0 T2522 MP0 FORCEI1 HI CAL 14.999682 mA 14.990 15.010
S0 T2523 MP0 MEASI1 LO RAW -15.074947 mA -18.000 -12.000
S0 T2524 MP0 MEASI1 HI RAW 15.117308 mA 12.000 18.000
S0 T2525 MP0 MEASI1 GAIN 1.006422 A 0.500 1.500
S0 T2526 MP0 MEASI1 OFFSET 0.021297 mA -3.000 3.000
S0 T2527 MP0 MEASI1 LO CAL -0.136713 uA -16.000 16.000
S0 T2528 MP0 MEASI1 HI CAL -0.251601 uA -16.000 16.000
S0 T5386 MP0 VCLAMP RAW -10.286614 V -15.750 -4.250

S0 T5387 MP0 VCLAMP RAW 14.313218 V 8.250 19.750
S0 T5388 MP0 VCLAMP GAIN 1.024993 V 0.800 1.200
S0 T5389 MP0 VCLAMP OFFSET -0.036684 V -1.000 1.000
S0 T5390 MP0 VCLAMP CAL -9.972562 V -10.800 -9.200
S0 T5391 MP0 VCLAMP CAL 13.993687 V 13.200 14.800
S0 T5675 MP0 ICLAMP RAW 25.014997 mA -70.000 90.000
5-35
S0 T5676 MP0 ICLAMP RAW 130.366202 mA 45.000 205.000

S0 T5677 MP0 ICLAMP GAIN 0.916097 A 0.600 1.400
S0 T5678 MP0 ICLAMP OFFSET 15.854023 mA -80.000 80.000
S0 T5679 MP0 ICLAMP CAL 13.374432 mA -14.000 34.000
S0 T5680 MP0 ICLAMP CAL 124.353433 mA 117.000 133.000
S0 T5681 MP0 ICLAMP RAW -33.292747 mA -90.000 70.000
S0 T5682 MP0 ICLAMP RAW -133.645287 mA -205.000 -45.000
S0 T5683 MP0 ICLAMP GAIN 0.872631 A 0.600 1.400
S0 T5684 MP0 ICLAMP OFFSET -24.566439 mA -80.000 80.000
S0 T5685 MP0 ICLAMP CAL -16.317708 mA -34.000 14.000
S0 T5686 MP0 ICLAMP CAL -124.974384 mA -133.000 -117.000
S0 T154 Board0Total Temp Change 0.937500 deg -4.000 4.000

S0 T6252 MP0 LKG/CM_I0 10 V -12.843403 uA -790.000 790.000

S0 T6253 MP0 LKG/CM_I0 5 V 9.203452 uA -475.000 475.000
S0 T6254 MP0 LKG/CM_I0 0 V 6.155364 uA -480.000 480.000
S0 T6255 MP0 LKG/CM_I0 -5 V 2.870530 uA -475.000 475.000
S0 T6256 MP0 LKG/CM_I0 -10 V 12.843403 uA -790.000 790.000
S0 T6257 MP0 OFFSET_I0 0.000000 uA -160.000 160.000
S0 T7693 MP0 FAST Loopcomp IR0 0.866320 ms 0.420 1.420

S0 T7694 MP0 SLOW Loopcomp IR0 7.397040 ms 6.100 11.100
MPDCMOD Checker
The checker performs a spec confirmation without running the cal first, on multiple points on each range to
also confirm linearity.
----------------------------------------------------
---------------BEGIN DATA LOG ----------------------
---------------Start Log Time : 12/29/2005 4:34:09 PM
----------------------------------------------------
----------------------------------------------------
Program ID : C:\_kvdco\Checkers\mpdcck\mpdcck.exe (12/29/05 15:09:28)
Operator ID :
Tester : UC11
Fixture :
Lot ID : NOLOTNUM
Comment :
LimitsFile : c:\_kvdco\Checkers\mpdcck\mpdcck.lim (12/29/05 16:34:10)
BinFile : c:\_kvdco\Checkers\mpdcck\mpdcck.bin (12/29/05 16:34:10)
ParametersFile :
----------------------------------------------------
DEVICE(s) : 1
S0 T0 MP0 DeltaTemp 1.562500 deg -3.000 3.000
S0 T32 MP0 Dummy 0.000000 deg -1.000 1.000
S0 T65 MP0 Force IR0 -160.013976 mA -160.240 -159.760
S0 T66 MP0 Measure IR0 -160.025818 mA -160.240 -159.760
S0 T67 MP0 Force IR0 -120.000484 mA -120.220 -119.780
S0 T69 MP0 Force IR0 0.019074 mA -0.160 0.160
S0 T70 MP0 Measure IR0 0.028518 mA -0.160 0.160
S0 T71 MP0 Force IR0 120.027086 mA 119.780 120.220
S0 T72 MP0 Measure IR0 120.001608 mA 119.780 120.220
S0 T73 MP0 Force IR0 160.019688 mA 159.760 160.240
S0 T75 MP0 Force IR1 -18.005633 mA -18.016 -17.984
S0 T77 MP0 Force IR1 -9.000575 mA -9.016 -8.984
S0 T79 MP0 Force IR1 0.001242 mA -0.016 0.016
S0 T80 MP0 Measure IR1 0.002418 mA -0.016 0.016
S0 T81 MP0 Force IR1 9.003280 mA 8.984 9.016
S0 T83 MP0 Force IR1 18.004787 mA 17.984 18.016
S0 T3300 MP0 Force VR0 -14.999072 V -15.017 -14.983
5-36
S0 T3301 MP0 Measure VR0 -14.997201 V -15.025 -14.975

S0 T3302 MP0 Force VR0 -7.496936 V -7.517 -7.483
S0 T3303 MP0 Measure VR0 -7.494905 V -7.525 -7.475
S0 T3304 MP0 Force VR0 0.004479 V -0.017 0.017
S0 T3305 MP0 Measure VR0 0.001174 V -0.025 0.025
S0 T3306 MP0 Force VR0 7.505355 V 7.483 7.517
S0 T3307 MP0 Measure VR0 7.502884 V 7.475 7.525
S0 T3308 MP0 Force VR0 15.005542 V 14.983 15.017
S0 T3309 MP0 Measure VR0 15.003424 V 14.975 15.025
S0 T3310 MP0 Force VR1 -15.000732 V -15.008 -14.992
S0 T3311 MP0 Measure VR1 -15.001072 V -15.012 -14.988
S0 T3312 MP0 Force VR1 -7.499198 V -7.508 -7.492
S0 T3313 MP0 Measure VR1 -7.497833 V -7.513 -7.487
S0 T3314 MP0 Force VR1 0.001823 V -0.008 0.008
S0 T3315 MP0 Measure VR1 0.001078 V -0.013 0.013
S0 T3316 MP0 Force VR1 7.501921 V 7.492 7.508
S0 T3317 MP0 Measure VR1 7.501538 V 7.487 7.513
S0 T3318 MP0 Force VR1 15.001823 V 14.992 15.008
S0 T3319 MP0 Measure VR1 15.001838 V 14.988 15.012
MPUVM Calibration
The MPDCMOD instrument also contains the floating differential voltmeter also called the UVM. These can
be calibrated separately, but they depend on a valid cal of the MP DUT source being done first, at least
sources 0 and 1 on each board.
In the calibration routine, various offsets are checked for each range, common mode voltage is added to
calibrate the CM effect, and finally, the various ranges are individually calibrated and checked. There are
six UVM ranges, R0-R6, explained in section 8.1.17.
Here is an excerpt from the datalog file:

----------------------------------------------------
---------------BEGIN DATA LOG ----------------------
---------------Start Log Time : 12/30/2005 9:55:44 AM
----------------------------------------------------
----------------------------------------------------
Program ID : C:\_kvdco\Checkers\uvm_debug\uvm_debug.exe (12/30/05 09:41:02)
Operator ID :
Tester : UC11
Fixture :
Lot ID : NOLOTNUM
Comment :
LimitsFile : C:\_kvdco\Checkers\uvm_debug\UVM_DEBUG.LIM (12/30/05 09:55:46)
BinFile : C:\_kvdco\Checkers\uvm_debug\UVM_DEBUG.BIN (12/30/05 09:55:46)
ParametersFile :
----------------------------------------------------
DEVICE(s) : 1
S0 T1 UVM0 VR0 RAW INOFF 0.419935 mV -100.000 100.000
S0 T2 UVM0 VR0 CAL INOFF -21.973327 uV -200.000 200.000
S0 T4 UVM0 VR1 CAL INOFF 19.531846 uV -200.000 200.000
S0 T8 UVM0 VR3 CAL INOFF 13.428144 uV -200.000 200.000
S0 T601 UVM0 VR0 RAW CM@-10.0 -2.794275 mV -100.000 100.000

S0 T602 UVM0 VR0 RAW CM@10.0 3.059175 mV -100.000 100.000
S0 T603 UVM0 VR0 CAL CM@-10.0 138.554033 uV -1000.000 1000.000
S0 T604 UVM0 VR0 CAL CM@10.0 144.657735 uV -1000.000 1000.000
S0 T61 UVM0 VR0 UVMHI -4.000556 V -5.000 -3.000

S0 T62 UVM0 VR0 UVMLO 4.000244 V 3.000 5.000
5-37
S0 T63 UVM0 VR0 DIFF_VIN -8.000800 V -9.000 -7.000

S0 T64 UVM0 VR0 RAW -7.940085 V -9.000 -7.000
S0 T65 UVM0 VR0 UVMHI 4.000102 V 3.000 5.000
S0 T66 UVM0 VR0 UVMLO -4.000361 V -5.000 -3.000
S0 T67 UVM0 VR0 DIFF_VIN 8.000463 V 7.000 9.000
S0 T68 UVM0 VR0 RAW 7.941839 V 7.000 9.000
S0 T69 UVM0 VR0 GAIN 0.992542 V 0.800 1.200
S0 T70 UVM0 VR0 OFFSET 1.044345 mV -200.000 200.000
S0 T71 UVM0 VR0 CAL 0.103246 mV -2.000 2.000
S0 T72 UVM0 VR0 CAL -0.111989 mV -2.000 2.000
S0 T401 UVM0 UVMHI INPUT -15.001329 V -15.700 -14.300

S0 T402 UVM0 VREF NOMINAL -15.000000 V -15.700 -14.300
S0 T403 UVM0 UVMETER RAW -14.906956 V -15.700 -14.300
S0 T404 UVM0 UVMHI INPUT 25.003720 V 24.300 25.700
S0 T405 UVM0 VREF NOMINAL 25.000000 V 24.300 25.700
S0 T406 UVM0 UVMETER RAW 25.169566 V 24.300 25.700
S0 T407 UVM0 VREF GAIN 1.001787 V 0.800 1.200
S0 T408 UVM0 VREF OFFSET 0.121175 V -0.700 0.700
S0 T409 UVM0 UVMETER CAL -0.431844 mV -1.450 1.450
S0 T410 UVM0 UVMETER CAL 0.186696 mV -1.450 1.450
MPUVM Checker
Pending
HPDCMOD Calibration
Pending.
HPDCMOD Checker
Pending.
DSPIO Calibration
Pending.
DIGMOD
Pending.
TMU
Pending.
Recalibration of Cal Meter

The Keithley or HP/Agilent DMM calibration interval, to retain its NIST tracability, is 12 months. The
customer is responsible for obtaining this certification, if needed, and loaner Keithleys are available from
KVD to allow the meter to be sent to a local cal lab.
5-38
Other KVD Checkers (Diagnostics)

As of Release 5.0.0, the Start -> Checkers menu contains diagnostics for other instruments and father
cards. Other instruments will be added in future releases.
The calibration software includes a verification process to ensure that the calibration was successful and
accurate. The basic difference in checkers is that:
1. Features of the instruments that are not calibrated can be verified (slew rate, noise, additional source
or measurement values).
2. A calibration is not performed just before the diagnostic is run, so drift between cals can be determined
to verify the calibration interval is suitable.
Father Card Checkers
Diagnostics for custom Father Cards with significant installed base are included under the Checkers menu.
These require the use of matching load boards for full functionality. Future checkers will be linked here as
they are developed.
PHLIC Checker
GPIB Checker
Discussed in “Installing PCI-GPIB Driver” on page 5-9.
5-39
Laser Communications Debugging Tools

These are documented more fully in the respective manuals for the laser trim options.
GSI-M310
Figure 5.25: GSI-M310 Screen
5-40
Stop Trim Interface
Figure 5.26: Stop Trim Interface
5-41
ESI 2050/2100
Figure 5.27: ESI 2050/2100 Screen
5-42
Software Installation - Offline Emulator
If you have a full Borland C++ Builder license for your portable or office system, you can install the KVD
library on it as well for editing and test compiling. Discussed in the software section, page 5-6.
Borland C++ Builder

KVD uses the Borland C++ Builder compiler (currently version 5.0 but soon to be Borland 2006) for library
development, tool development, and test program development. The C Builder compiler (BCB5) is a C++
windows compiler with an outstanding IDE and debugger.
The book Teach Yourself Borland C++Builder in 21 Days, by Kent Reisdorph and Ken Henderson, Borland
Press/Sams Publishing, ISBN 0-672-31020-1, which can be purchased at many technical book stores and
on-line retailers, contains valuable information on using the debugger, and understanding the IDE and
Borland supplied tools.
The Borland web site at http://www.borland.com/us/products/cbuilder/index.html is also a good beginning.
KVD installs on each test system one or more KVD libraries, and a standard C++ header file. The libraries
support test program development (kvdwin.lib) and other instruments under development if present. The
libraries are typically located in the folder C:\_kvdco\Libraries. The header file (kvdwin.h) is located in
the folder C:\_kvdco\Include.
KVD also supplies a generic test program shell, which is wrapped in an installation program. Under the
Windows Start menu, Programming Tools, you will find a link to the KVD Generic Application Shell.
Figure 6.1: Launching the Generic Application Shell Installer
6-1
When launched, it will display the following:
Figure 6.2: Generic Test Application Installation
By running the installation program, the user can select the location to copy the files needed for a generic
test program. The program shell contains a representative set of all files necessary to build a test program
on the KVD M2 test system.
Figure 6.3: Generic Test Application Installation Directory
6-2
Development Environment
The following screen capture shows the files copied by the installation program.
Figure 6.4: Generic Test Application Installed Files
The purpose of each file is discussed below.
Filename Purpose
ACTests.cpp/h This file is empty, and can be used for ac tests that the engineer writes.
DCTests.cpp/h This file is empty, and can be used for dc tests that the engineer writes.
Connections.cpp/h This file is empty, and can be used to declare and instantiate TConnection
objects.
KVDTestApp.bin This file will contain any bin numbers, comments, and pass/fail information.
This file defines the bin descriptions that appear on the Production View
Screen while testing devices, and the counters for excessive failures.
6-3
Filename Purpose
KVDTestApp.cpp/dsk/bpr This is the main project file. The engineer should never edit this file. If the
engineer saves the project under another name, then these three files will
be created with that newly saved name. The .dsk file is the Borland
"desktop" save file, which will preserve your desired pattern of open window
locations and sizes, plus environment options.
RevisionNotes.txt A file for use by the engineer to keep revision history of the test program.
This is only a text file, and does not get compiled.
KVDTestApp.lim Used to declare the limits, units, and the "Bin if Fail" for each test.
KVDTestApp.inf Used in legacy applications to declare the start up conditions for

datalogging, file locations, and other optional selections. No longer used,
due to superior flexibility provided in the Customer Preferences Tool and
the Setup File Tool. (documented elsewhere)
UserClass.cpp/h The main starting file for the engineer. This class file has all the entry points
declared that the main system software will access. The test sequence is
located here, as are initialization procedures run at the start of every test
program load time, lot, sublot, and device, plus the cleanup procedures run
at the end of each device, sublot, lot, and test program run. See this
comment from the generic UserClass.cpp file:
//////////////////////////// IMPORTANT /////////////////////////
// This section is the only section available to the user. The
// routines in this section are called from WinMain with the following
// flow
//-------------------------------------------------------
//----SystemInit
//--------LotInit
//------------SubLotInit
// ---------------DeviceInit <--|
//----------------TSeq <--| loops on this until EOT
//----------------DeviceFinish <--|
//------------SubLotFinish
//--------LotFinish
//----SystemFinish
//////////////////////////// IMPORTANT //////////////////////////
The functions listed here have empty templates when you generate a generic test program shell, but the
names are fixed. The KVD Library code depends on these exact function names to operate the mainloop
device testing process. As you can see, various initialization functions are available for you to set up your
own GUIs, data handlers, variables, pattern loads, and so forth, which should not be done once per device.
The trio of functions (DeviceInit, Tseq, DeviceFinish) are performed once per device, and you should keep
any slow processes out of this loop, such as operations that access the network or hard drive.
DeviceFinish is designed to be executed without fail on all devices tested, even ones that abort (skip) out
of the main test sequence Tseq due to a failure, PLUS the Stop on First Fail flag being set.
6-4
Setting Up Your Own Test Application

To begin, use the KVD Generic Application Shell Installation program. If the system has been normally set
up and installed, this should be located on the Start menu as explained previously.
This installation program will ask you for a location to put the generic test application code. Select a folder,
and then let the installation run automatically and complete. The test application program file will be named
KVDTestApp, but you can rename this later.
Then run it so you can see that it compiles with no errors and/or warnings, and so you can take a look at
the main KVD screen.
Start up the C++Builder 5.0 compiler. (This should be in the Start, then Programs menu, or else a desktop
shortcut.)
Figure 6.5: Launching Borland C++ Builder
6-5
Once it is running, go to File, and then Open Project.
Figure 6.6: Open Project Command
Browse to the location that you selected for the KVD Generic App, and select the KVDTestApp.bpr file.
Figure 6.7: Selecting the KVDTestApp.bpr File
6-6
Once it is open, you should have the main compiler screen, with the code windows, project windows, and
debug windows, in front of you.
Figure 6.8: Main Borland IDE Display
You should take some time to become familiar with the IDE, the integrated development environment. For
now, set a couple of BCB5 (Borland C Builder 5.0) options, and then compile the KVDTestApp. You can
skip the setting of options and go right to the compile section if you choose to. The only options you should
set now are the automatic saving of the editor files, and the desktop files.
To set the auto save of the files, click on the Tools menu item at the top of the BCB5 IDE, and select the
Environment Options. On the dialog box that appears make sure that the two AutoSave options <Editor
Files> and <Project Desktop> are checked. You can also uncheck the box for <Background
Compilation>, since compiling goes so quickly, there is no benefit to running it in the background.
6-7
Figure 6.9: Environment Options
Click on OK to save these options.
6-8
You should also make sure, to save time during compile & debug sessions, that the use of precompiled
headers is activated. Bring up the Options screen from the Project pulldown menu:
Figure 6.10: Use Precompiled Headers
Click the Compiler tab, then the button for Use Precompiled Headers, then type the name
KVDTestApp.csm in the File Name window. (Or your project name if you have renamed it from
KVDTestApp).
Figure 6.11: RUN Button
Now click on the RUN icon (green right pointing icon) on the IDE (designed to look like the RUN button on
a VCR), or select Run and then Run again on the menu or press Function Key F9. (Many actions have
defined Function Key shortcuts.)
6-9
The project should compile with no warnings and no errors if everything has been set up properly. Should
you encounter any errors or warnings at this point, please make note of them and let KVD know of these
so that they can be corrected on future installation setups.
Figure 6.12: Compilation in Progress
Assuming everything goes according to plan, the main KVD production screen should show up once the
application has been compiled, and executed. You can start the job plan execution, observe datalogs, and
pause its execution if desired.
The Production screens and functions are documented in the Windows Operations Chapter, and are not
repeated here.
Adding New Files to a Project

To add a new file to an existing KVD Test program, follow these steps:
1. Click on FILE, NEW.

2. A dialog box appears with tabs for different types of setups.
3. Make sure the NEW tab is the active tab
4. Scroll down to the bottom of the NEW tab.
5. Click on UNIT, then click OK.
6-10
This will add a new unit (CPP and H file) to your project. It has a name of UNIT1. Click on FILE, then SAVE
AS to save it under a more realistic name. The corresponding header file will also be given this name.
Make sure you save it in the same folder as the project.
Now, if you used the KVD Generic Application Shell installation program to create this project, it should
have a header file named KVDTestAppMainHeader that gets included in all the CPP files. Open up this
KVDTestAppMainHeader.h file and add an include for your new units H file. Save this file. In your new
units CPP file, replace the code at the top, which usually looks like this:
//-----------------------------------------------------------------------
#include <vcl.h>
#pragma hdrstop
#include "MyNewUnit.h"
To this
//------THESE NEXT TWO LINES MUST REMAIN THE SAME. ADD ANY CODE AFTER THE #include
"KVDTestAppMainHeader.h"
#pragma hdrstop
The include (in this example) for MyNewUnit.h is now in the KVDTestAppMainHeader.h file.
6-11
Copying KVD Projects Using the KVD Copy Project Tool

The KVD Copy Project Tool (located from the Start menu under the Customer Support folder) was
developed to make copying a KVD Test program, and all support files, easier. The tool has a very simple
interface, and is shown below.
Figure 6.13: Copy Project Tool
You'll notice that there are numbered sections (1 through 4). These are the four steps you will follow to
copy the project to another folder, whether that folder is on the same hard drive, or located on the network.
1. Select the folder where the project files to be copied are located. This is known as the "source" folder.
This location can be a folder on a local or network drive.
2. Select the folder where all the selected files will be copied into. This is known as the destination folder.
This location can be a folder on a local or network drive.
3. Step three allows the necessary files extension masks to be selected so that only the appropriate files
are copied. The check boxes on the left side of the file list box select the source code files. The check
boxes on the right side on the file list box are used to select the compiled (or runtime) files. If you are
moving a project from development into production, you would normally select ALL runtime files. If you
also want to include ALL the source code files, click on the ALL button in the Source Code Files group.
At this point you should see all the files in the list. These files are the files to be copied from the source
location to the destination location.
6-12
4. This is the final step. All the files in the files list box will be copied from the source location to the
destination local. You can then use the files that are in the destination location.
Note: The files are copied. If you want to remove the files from the source location, first copy them using
this tool, and then manually delete the source location files.
The Borland Debugger

Now we will see how the debugger works while interacting with the test program.
(In the image below, the Project Manager view for the BCB5 IDE is shown on the left. If this view is not
being displayed on your screen, click on the VIEW, and then PROJECT MANAGER menu items.) This
window should be dockable so it sticks where you wish it to stay. Drag it around by its top bar.
Figure 6.14: Project View
Open the file UserClass.cpp by double clicking on the filename in the PROJECT MANAGER view. The file
should open up to the right of the PROJECT MANAGER view. Scroll down until you get to the function
named TUser::Tseq.
6-13
Figure 6.15: Tuser::DeviceInit Function
By clicking in the GRAY vertical bar to the left of the editor screen you can set a breakpoint. A breakpoint
will cause the program to suspend running at that point, and allows the test engineer to debug beginning at
that point. When a break point is set, it will change the line the break point is set on to a red highlighted
line.
Figure 6.16: Setting a Breakpoint
Now, rerun the program, and once the main Production screen appears, click on the START button, once
the execution has reached this breakpoint, the editor window will appear, and the main screen will be
hidden. At this point in a normal test program, all the other debugging tools could be used.
You could single step through the code, step into a routine, look at data, variables, or use the evaluate/
modify function of the debugger. The image below (except that it will probably be printed in B&W if on
paper) shows a green arrow in the gray vertical column. This is indicating that the program is stopped at
that line in the code. It stops immediately BEFORE executing the instruction. The little blue dots that you
see indicate valid lines of code that break points can be set on.
Figure 6.17: Execution Halted
6-14
Here is a list of useful debugger commands and their shortcut keys:
Command Shortcut Key
RUN - also RUN TO NEXT BREAKPOINT F9
Toggle Breakpoint F5
Step Over (Single Step - stay at same "level") F8
Trace Into (Go into a function - "down a level") F7
Run to Cursor F4
Evaluate/Modify (examine variables and change them) Ctrl-F7
Program Reset Ctrl-F2
Figure 6.18: Debugger Shortcuts
Sending Datalog Information to the Debugging Environment

When debugging a test program, it is nearly impossible to get back to the MAIN KVD screen and see
datalogged information because of the window being hidden by the debugger. But there is a way to
redirect the KVD datalog info to a viewable screen in the debugger.
1. Set the variable KVD->DataToEventLog equal to true using either the Evaluate/Modify window
(CTRL+F7) or by putting it in your code.
2. Enable the Event Log. While in the Borland Cbuilder Environment, click on VIEW, then DEBUG
WINDOWS, and finally EVENT LOG. You should see the Event Log window on the Desktop. You
might want to "dock" it to something that is always visible on the desktop, so that you can view it. Now,
right click in the Event Log window and click on CLEAR EVENTS. This will clear any previously logged
events. Now, right click again in the Event Log window and select PROPERTIES. A Dialog Box
appears, with two "sections". In the MESSAGES sections, you want to make sure that Output
Messages are the ONLY type checked. You might also want the Clear Log on Run also checked so
each time you run the application, any previous messages will be deleted. Now click on OK.
When you run your application, you will see datalog information in this window if the
KVD->DataToEventLog variable is true. If the KVD->DataToEventLog variable is false, no data is sent
to this window.
Another variable, KVD->SystemMsgToEventLog, can also be toggled on (true) or off (false) to redirect
System type messages to the event log.
Note: Ensure that all debug flags such as this are turned OFF before releasing the test program back to
production. Test time is always fastest when features like this are not being used.
6-15
Real Time Interface

KVD has developed a tool that assists the engineer in debugging and writing tests. This tool is the Real
Time Interface (RTI). The RTI is composed of various 'pages' (TABS) that perform specific functions
directly on the instruments in the test head.
The RTI is also a read back tool. That is, it is capable of displaying the status of all boards and resources
in the test head, when the debugger is halted at a breakpoint.
You can change the modes (forceV, forceI) of sources, click on relay state boxes, affect connections,
modify the levels, and take measurements.
Note: The REFRESH button may be used at any time to obtain a fresh readback image of the state of
the hardware instruments. It is not automatically updated when you halt at subsequent breakpoints
unless you press the REFRESH button or the AUTO REFRESH ON box is checked. We
recommend that you do not leave the AUTO REFRESH ON feature permanently on, since the
constant communication to and from the instruments tends to slow down execution speed, and
interfere with expected debugging results. Only turn it on sparingly, and knowing that the updates
are happening constantly. (every 100mS).
Figure 6.19: Real Time Interface Main Screen
6-16
The RTI has many pages specific to either related functions, or boards in the test head.
• DUT Sources and their UVMs
• Digital Resources and Patterns
• Father Card Relays
• DIG Relays
• TMU
• RMX
• System Functions
MPDCMOD DUT Source Page
The MPDCMOD RTI has been split into two tabs to show more sources on one page and also has a button
which starts a continuous measurement loop. Number of measurements averaged for a manual measure
or this continuous loop is also selectable. The second tab contains displays and controls for Ground
Sense, and Acquire Sample Rate. (Enable/Disable control is available, but discouraged because the
control loop goes open when a source is disabled, and offset drift may result in instantaneous spikes when
the source is later enabled.)
Figure 6.20: MP RTI Screen Display (Tab 1)
6-17
You can type in new values, change the state of relays or connections, and make immediate
measurements.
Column Description
FORCE A 'V' indicates that the DS is forcing voltage. An 'I' indicates the DS is forcing
current. This can be changed by simply typing in an 'I' or a 'V', and pressing
return.
Warning! Be extremely cautious when changing the mode of a running

source, as the value may be set to something that may damage
your DUT, or you may be hot-switching relays on the instrument or
your applications circuits, with unintended or damaging results.
VALUE A real value (double) is shown in this column indicating the forcing value. The
user can enter a new value, and press return to set the DS to that value.
IRANGE The active current range is displayed in this column. Press return to set the
range. Other kinds of sources will have alternate choices of ranges.
DOMEAS This column allows the user to make an immediate measurement on the DS.
Place the cursor in the box. Typing in V will measure the voltage on the DS.
Typing in I will measure the current. (Averaged 10 measure strobes on the A/D)
STATE The STATE column shows whether the DS is ON or OFF. Typing in ON or OFF
will change the DS to that state, after return is pressed.
RESULT Any measurement will produce a result, and that result will be displayed in this
column. This column is read only. No inputs are allowed.
ALARM If a measurement has resulted in the DS alarming, then this column will show
that alarm. If the column is empty, the DS is not alarming.
6-18
Figure 6.21: MP RTI Screen Display (Tab 2)
6-19
User Voltmeter (UVM) Page
The MPDCMOD instrument contains a separate differential floating voltmeter, called the UVM. This is its
real time interface page:
Figure 6.22: User Voltmeter RTI Display
You can change the connection points, measurement range, and make immediate measurements.
6-20
HP DUT Source Page
Figure 6.23: HP RTI Display
In the same way that you can interrogate the state of or change attributes of the MP, you can do the same
for the HP DUT Source.
6-21
DSPIO Pins
Figure 6.24: DSPIO RTI
The Digital Resources page displays the configuration and state of each available Digital pin. This grid will
show between 16 and 32 digital channels. If DSPIO boards are present on both sides of the test head, a
SIDES button group will be displayed which allows the user to toggle between side 0 and side 1 digital.
There is also a Time Set radio group that is available to toggle between the two available time sets.
The grid displays nine columns which contain data for each available digital pin.
The nine columns are labeled:
Column Description
FORMAT The formats available to the engineer, for each digital pin, are RZ, NRZ, CS,
RO, RZC, CSC, ROC, CLK2, CLK4, CLK8, LOW, and HIGH. A value of
NOFORM indicates that the digital pin has not been programmed with a dfmt
statement. To change the format value, type in a valid format, and press return.
START The start column indicates the start time for edge placement. To change this,
enter a new (double) value, and press return.
STOP The stop column indicates the stop time for edge placement. To change this,
enter a new (double) value, and press return.
STROBE The strobe column indicates the data out strobe time. To change this, enter a
new (double) value, and press return.
6-22
Column Description
VIL The vil column is a DC value that is the level the digital pin uses for a logical 0.
To change this, enter a valid value in the range for digital pin low values, and
press return.
VIH The vih column is a DC value that is the level the digital pin uses for a logical 1.
To change this, enter a valid value in the range for digital pin high values, and
press return.
CMPLEV The cmplev column is a DC value that is the level the digital pin uses for the
comparator value. To change this, enter a valid value in the range for digital
comparator values, and press return.
KA This is the keep alive column. It indicates a 1 or a zero, which are the only two
logical states a pin can be at when a pattern is NOT running. To change this,
enter a 1 or a 0, and press return.
STATE Digital pins can be either enabled (ENA) or disabled (DIS). Enter either ENA or
DIS, and press return to change this value.
DSPIO Patterns (Running and Debugging)
The Patterns page actually contains two sub pages beneath it. One page offers the user the patterns that
are loaded so that they can be run and/or edited. The Readback page allows the user to confirm or change
the pattern setup, as well as general pattern timing.
Figure 6.25: Patterns/Running RTI
6-23
The Patterns/Running page lists all the patterns that are loaded. To select a pattern as the current pattern,
double click on the pattern name in this list. Click on the Execute button to run the current pattern. Click on
the Stop button to halt a pattern (if a pattern is running). The dflag1 and dflag2 buttons implement the
DSPIO dflags command. Clicking on the Update Results button will perform a DSPIO dstatus, and show
whether the pattern is passing, failing, and possible fail address. There is also a Green LED that indicates
the pattern running status. If the LED is on, the pattern is running. If the LED is off, the pattern has halted.
DSPIO Patterns (Readback)
Figure 6.26: Patterns/Readback RTI
The Readback page shows the user the current setting for DDXTALFREQ (the master clock frequency),
and the T0 rate, which is the pattern burst rate per vector. Also shown is the DSPIO configuration of
Master and Slave, if there are two DSPIO boards on the same side. The Disassemble button shows the
current pattern being pointed to. If the Disassemble button is clicked, the pattern will be read from pattern
memory, and disassembled into source code format.
The Examine button, which has an address entry box next to it, will read back the raw pattern data for the
address in pattern memory. Clicking on the Next button will read the next X addresses, where X is the
number in the entry box next to the Next button.
Finally, clicking Clear will clear the listing of any previous Readback functions.
6-24
FC Relays Page (Father Card Relays)
Figure 6.27: Fathercard Relays RTI
On many generic Father Cards built by KVD, there are 80 relay drive registers available to the engineer,
but some may have more. A register may be connected to more than one relay in hardware. They are
typically distributed with 40 relays per side. These relays can be opened or closed through the RTI by
simply clicking on the check box next to the named relay. A check mark in the box indicates that the relay
is closed. An un-checked box indicates that the relay is open.
Note: This page does not apply to custom Father Cards such as those designed for Laser Trim
applications. Future KVD software releases will add RTI support for these custom items.
6-25
DIG Relays Page (Digital Drivers and Analog Bus Relays)
Figure 6.28: Digital Relays RTI
The digital relays shown on this page actually reside on the DSPIO board. These relays connect the digital
pin to either the analog bus (for DC testing) or to the Digital Driver (for digital functions and patterns).
The above image shows the side 1 Digital relays. If there are DSPIO board(s) on side 0, then there would
also be a side 0 box showing the same relays for the same digital pins. To connect a digital pin to the
driver, or the analog bus, simply click on the check box next to the digital pin. A check mark indicates the
relay is closed (connected). An empty box indicates that the relay is opened (disconnected).
You can also connect the DUT Source DS1 to the analog bus. This is useful, in combination with a digital
pin being connected to the analog bus, to perform DC tests on the digital pin.
6-26
TMU (Time Measurement Unit)
Figure 6.29: TMU RTI
The TMU page, although it looks complicated, it actually fairly straightforward. Each of the boxes (Level,
Enable, DDCHAN, Input, frequency, Interval, and Measure) correspond directly to the TMU command set.
For example, the Level box contains the same fields that the TMU->level command expects. Clicking on a
Set button in any of the boxes issues the corresponding command. Clicking on the Refresh Data button
will read back from the TMU its current state, and those values will be shown in the appropriate boxes. The
TMU Side button group allows the user to toggle between reading/writing a TMU on side 0, or side 1.
6-27
DIGMOD Pages
The DIGMOD RTI is more complex and interactive with the pattern editor, and is more fully documented in
Chapter 9: Digital Instruments. Here is a sample screen shot:
Figure 6.30: DIGMOD RTI
System Functions Page
Figure 6.31: System Functions RTI
6-28
The System Functions page contains buttons that perform more system-wide functions. All the reset
buttons do exactly as they are labeled. They will reset the Resource, and return it to its initial or
unprogrammed state. The system status window shows any messages returned from the system library.
These can include setup messages, boot messages, and possible warnings and/or errors.
Shared Connections - DSPIO, Father Card, RMX, App
Figure 6.32: Connections RTI
Pending a fuller explanation.
Changing the Resource Names Shown in the RTI
The RTI (Real Time Interface) has pages that show various resources:
• MP DUT Sources
• HP DUT Sources
• Digital Pins
If you want to show a different, customized, name of your choice on the RTI than the default resource
name/number, you can. It is very simple. The command is the same for each of the four types, so we will
show the syntax first, then some examples. The command to change the name should be put somewhere
in your code where it only happens once, such as LotInit, SubLotInit, or some routine called at that level.
Syntax:
Resource->setname(new_name);
Where new_name is a string enclosed in double quotes.
6-29
Examples:
If you are using MPDS[0] as VDD in your test program, you might want the name VDD to appear on the
MPDCMOD page of the RTI instead of MPDS[0]. To do this, add the following statement to your code
MPDS[0]->setname("VDD");
In the case where you create a resource variable named VDD, and want it to also show up as VDD in the
RTI, you would have something like this,
TMPDS* VDD; //just the declaration
…
… some code
VDD = MPDS[0]; //this is where you are making the VDD object equal to MPDS[0]
VDD->setname("VDD"); //before this command, the name was taken from the MPDS[0], which was MPDS[0]
Note: The name change will show up the next time RTI is run. If it is running when the setname
command is executed, the new name won't appear until RTI is shut down and then restarted.
Debugging Applications Run From the KVD Launcher

It is typical for the Test Engineer to debug the test program using the Borland CBuilder IDE. This is fine for
debugging the actual test program code and functionality. However, once the test program is released to
production, and is launched using the KVD Launcher, other problems could appear due to the different
flow of the process itself. If you find that this is the case, you can set up your applications and KVD
Launcher to help debug this process flow.
If you do not know how to create setup files that the KVD Launcher uses, please read “Setup File Tool” on
page 7-31, or the Help file in the KVD Setup File Tool after you launch it.
One new entry in the Setup File Tool allows the engineer to specify the location and file for the Borland
Cbuilder Project File (.bpr). With an entry in the setup file for the BPR location, and by selecting
Engineering mode from the Customer Preferences Tool, the KVD Launcher will run Borland CBuilder
and then your test program instead of launching the executable file. This then puts your application in
debug mode, and all break points, watches, etc. can be used just like the normal test application debug
process.
Plot Tool
The KVD Library has built in functions available to allow the Test Engineer to plot data and view the plotted
data using the KVD Plot Tool. The steps necessary to plot your data are outlined below. There are three
main steps that have to be performed:
• Setup the Plot object
• Load data into the Plot object
• View the Plot object
Note that for simple viewing of measurement sample data from a source meter or the UVM, the production
GUI has a quick tool called MeasVM Plot. Please see also the documentation in Chapter 7: Operations
Environment.
6-30
Setting Up the Plot Object
Setting up the plot object involves mainly just allocating the memory for the plot. The number of points
needed must be known before the allocation. Allocating the memory for the plot should happen only once
during a program run, so it is suggested that the allocation occur in the TUser::SystemInit function. The
KVD Library creates eight plot objects, which allows the user to create and use eight different plots. To
allocate memory for one of the eight plots, use the global function:
PlotAllocate (plotnum, plotsize)
where the plotnum is one of the eight plots (0 through 7) and the plotsize is the maximum number of points
that the plot will contain. For example, to allocate plot 0 to display 6000 data points, the plot allocate
function would be
PlotAllocate (0, 6000);
The next step in the plot setup involves setting the title, and the x and y axis labels. Each of the eight plot
objects ( plot[0] through plot[7] ) have fields that can be set that will show up in the Plot Tool display. These
fields are:
• title
• xlabel
• ylabel
• comments
All four fields are character arrays (title, xlabel and ylabel are 50 characters, and the comment is 120
characters). In our example for plot[0], the fields could be set as follows
strcpy( plot[0]->title, "Plot Demo Title");
strcpy( plot[0]->xlabel," index number");
strcpy( plot[0]->ylabel,"data points");
strcpy( plot[0]->comments," This is the comment for Plot Demo");
These fields could be set or changed whenever the user needs to, since, unlike the PlotAllocate command,
they do not involve memory allocation.
Loading Data into the Plot Object
Loading the data into one of the eight plot objects is done by calling the setdata function, which is a method
of each of the plot objects. The format of the setdata function is:
setdata ( dataindex, datavalue);
where the dataindex is from 0 to the number of points allocated (minus 1) and the datavalue is a valid
"double" value. So, in our example, to create a one cycle sine wave, you would have a function like this:
const double PI = 3.1415269;
for (int index=0; index<6000; index++)
plot[0]->setdata(index, sin(2*PI*((double)index/6000)));
Here, we are loading plot[0] with 6000 data points. In your own code, you would have whatever data
generation functions you would want to plot.
There is a corresponding function for reading back data from a plot object. Its format is
getdata (index);
which returns the double value for the indexed data point. So, to read back the seventh number stored in
plot[0]'s data array, you would use:
6-31
double value = plot[0]->getdata(6); //remember, it is zero based
The full description of the TPLOT class follows

class TPLOT {
public:
int size;
char title[50];
char ylabel[50];
char xlabel[50];
char comments[120];
double minx;
double maxx;
double miny;
double maxy;
unsigned gridlineforevery;
unsigned show_vertical;
unsigned show_horizontal;
unsigned allocated;
bool dirty;
short plotindex;
short setdata(unsigned index, double value);

double getdata(unsigned index);
};
Viewing the Plot Object
On the Windows Start menu, click on Debugging Tools, and then select the KVD Plot Tool. The tool will
open up and display all available plots. The lowest numbered plot (plot[0]) will be the default plot, and it will
be shown automatically. To see any other plots generated, you'll click on the Plot name in the lower right
portion of the Plot Tool. On the far right of the plot tool are all the data points used in the plot. If you place
the mouse cross bars over a particular portion of the plot, you'll see (down at the bottom) the data point
number and the value that corresponds to that point. The plot tool also allows saving and loading of plots,
as well as printing of plots.
Setup, Logging, Testing and Binning

The commands listed in this section assist the user in setting up the test program, data logging results, and
performing the testing of results against limits.
The LOG object is a global object created from the TLOG class. The LOG object is used to load in limits
files, bin descriptions files, and wafermap description files.
The KVD object descends from the main production form. Its functions allow the user to test against limits,
setting the current test number, and to send comments to the datalog screen.
The SYS object is related to the PCI data bus interface functions, and allows the user to send low-level
register commands, read timer counters, and set execution delays.
6-32
The SITE object descends from the TSite class. It allows the user to read the results of a measurement, or
other functions that produce results. It also supplies the functions necessary to set up resource site masks
for dc sources, digital, tmu, wd, and ws, useful for multisite programs.
Understanding How the Binning Process Works on a KVD System
Test programs will categorize devices based on tests that have failed, or not failed. This is called Binning.
The KVD Library supports software bins from 1 to 63. Typically, a Bin 1 is considered a "good" devices, but
this is by convention, and is not a permanent rule. The "bin" a device falls into is based on two things
1. The Bin associated with a test in the LIMITS file.

2. The pass or fail category for a bin, which is determined in the BIN file.
The two file types (as they pertain to binning) are described below.
LIMITS File
Each test in a test program can have an upper and lower limit for that test, as well as a comment and a fail
bin. Actually, there can be multiple fail bins for the case where a test is being used for downgrading and
categorization. This is documented in the section concerning Disqualify Binning.
Using the Limits file editor, a typical limit file will look like this:
Figure 6.33: Limits File Editor Screen
If a test fails in the test program, it will be sent to the Fail Bin for this test. The first column, Tnum, is the
Test Number, and the file does not have to contain these in any particular sorted order. There is no
practical limit on test numbers - increased from 6199 in 5.02.
6-33
Testing Against the Limits
Tests are measured against the upper (UL) and lower (LL) limits with the command
KVD->Test();
If the KVD->Test() command returns true, it means that the test has failed. If the command returns false, it
means the test has passed. To establish the test number that the command will use to get its limits, you
use the KVD->tnum(number) command, where number is the test number. Looking at the limit table
above, to test against the limits for test number 101, you would do this :
1. KVD->tnum(101);
2. …
3. …
4. …assume some code puts a value in SITE->lastresult.value
5. …
6. …
7. if (KVD->Test()) return(FAIL);
8. …
9. …
10. …more code and tests
11. …
12. …
13. return(PASS);
The above code contains line numbers only for the discussion of them here. In "real" code, the line
numbers do not exist. Line 1 sets the current test number to 101. This means that the limits for test number
101 (-4.2V and -3.8V) will be used for the KVD >Test() command on line 7. What happens when the
KVD->Test() command is executed? The result that is sitting in the variable SITE->lastresult.value will be
compared to the limit's upper and lower values. If the SITE >lastresult.value is less than or equal to the
upper limit AND greater than or equal to the lower limit, the command returns false (meaning it did not fail).
Otherwise, it returns true (meaning it DID fail).
If you do not explicitly set the test number, the KVD->Test() command will automatically increment it by
one from the previous, and the first test is implicitly set to 1 if you do not set another number.
The driver code for the KVD DUT sources (MPDCMOD, and HPDCMOD) automatically places the
average of your measurements in this SITE >lastresult.value variable. Other drivers, such as the current
TMU driver, require you to assign the measurement there deliberately. If you are doing any scaling, math,
or other manipulation on a measurement before testing it against the limits, make sure you assign it to
SITE->lastresult.value before you execute KVD >Test();.
Before returning, if the result does fail, the KVD library code checks to see if the device under test (DUT)
has already failed a previous test. If it has, the library just logs this fail, and returns. If it hasn't previously
failed, the library will set the current BIN equal to the FAIL BIN for this test, and then return. This is how the
fail bin gets set. The setting of the fail bin is locked in, that is, it cannot be changed for this device.
On the next DUT, the current bin is set to the default passing bin until a fail occurs. If no fail ever occurs on
a DUT, then the current bin remains the default passing bin, and after Tuser::Tseq has finished, the device
bins out. So now we know that a FAIL BIN gets assigned based on a TEST NUMBER and a TEST FAIL.
But there is one more place where we have to tell the KVD library where that the FAIL BIN from the limits
file is a FAIL BIN, as opposed to a PASSING BIN. Remember, we only enter the FAIL BIN number in the
limits file. The BIN file tells the library code which bins are passing bins, and which bins are failing bins.
SITE->lastresult.alarm is set true if an instrument sets an alarm, for instance in case of a clamp being
activated or a measurement being overranged. If you wish to have an alarm noticed, you need to change
the default which is to have them ignored.
Example:
LOG->DisableAlarms = false;
6-34
Extended Limits Editor
Pending
Loading the Limits File
Pending
Units
The list below contains all the pre-defined unit names and values that are available on the KVD system.
You can define your own custom units as many as you wish) using the LOG >AddLimitUnit function.
Example:
Currently, these need to be defined before you load in your limits file from the hard drive, but this restriction
may be lifted in a subsequent release. You can also define them in a file:
An even better way to add your own units is to place them in a file that the library will add automatically. To
do this, create a text file with the same name as your application and with the extension ".units". So, for
example, if you application is named XXX_YYY.exe, create a text file named XXX_YYY.units. Then, in this
file, make the first line [UNITS] and after that initial line, added a line for each new unit where you specify
the unit name = unit value. So, again in our example using GHz, our ".units" file would look like this:
[UNITS]
GHz = 1e9
This .units text file should then be saved into the same folder as the application. The KVD Library will read
this file when it first creates its own units.
Table of All Predefined Units

V = 1.0
mV = 1.0E-3
uV = 1.0E-6
A = 1.0
mA = 1.0E-3
uA = 1.0E-6
nA = 1.0E-9
pA = 1.0E-12
W = 1.0
mW = 1.0E-3
uW = 1.0E-6
Ohm = 1.0
KOhm = 1.0E3
MOhm = 1.0E6
s = 1.0
ms = 1.0E-3
us = 1.0E-6
ns = 1.0E-9
ps = 1.0E-12
H = 1.0
Hz = 1.0
KHz = 1.0E3
MHz = 1.0E6
GHz = 1.0E9
dB = 1.0
pct = 1.0E2
deg = 1.0
Code = 1.0
Vect = 1.0
Rat = 1.0
ratio = 1.0
uF = 1.0E-6
pF = 1.0E-12
Err = 1.0
6-35
Lux = 1.0
Pix = 1.0
lsb = 1.0
uj = 1.0E-6
Code = 1.0
LSB = 1.0
C = 1.0
[blank] = 1.0
BIN File
The BIN file (extension .bin) contains information that pertains to binning and the display of information on
the production operator's display. It allows the user to specify which bins are passing bins, which bins are
failing bins, comments for each bin, maximum consecutive fails for a bin, and maximum allowed fails for a
bin.
A typical BIN file entry will look like this:

1, PASS, Grade A PASS
2, FAIL, Continuity Fail
3, FAIL, Tri-State
Here, we are designating bin 1 as a pass and bins 2 and 3 as fails. If the command KVD >Test() fails, and
the fail bin is in this list, then the device will be "binned" as a pass or fail based on what is in this file. It is
confusing since the bin entry in the limits file is considered a FAIL BIN. What it really means is that in the
case of a limits fail, the current bin gets downgraded to the FAIL BIN from the limits file. To actually bin the
device as a fail, the corresponding bin in the BIN file must designated as a FAIL type bin.
In addition, PASS bins are displayed as a green bar in the Production Operator's Display, and FAIL bins
are shown in red.
Setting up a BIN File
BIN files allow the user to specify which bins are "passing" bins and which bins are "failing" bins. In
addition to these attributes, which MUST be defined for all bins used in the LIMITS file, there are fields
available where the user can specify the maximum consecutive fails allowed for a bin and the maximum
fails allowed for a bin during a lot.
Each field in the BIN file can have the following format. The items in angle brackets "<>"indicate that the
field is mandatory, where as the fields in square brackets "[]"are optional.
<binnum>, <passfail>, <comment>, [maxconsecutive], [maxallowed]
Binning Field Explanations
Field Description
binnum The binnum field is just a number, and can be between 1 and 63.
Passfail The passfail field can only have two values : PASS, or FAIL. This field is case
insensitive.
Comment The comment field should contain a short description of the bin. The comment
is used in the BIN summary file, and also on the CHART view of the main
screen.
6-36
Field Description
Maxconsecutive This number is stored in the library, and is an upper limit as to how many
consecutive fails for the binnum can occur before the system stops and requires
the operator to confirm. Whenever a device is binned to a bin number not equal
to binnum, this count is reset to zero.
Maxallowed In the entire run of a LOT, if there are more devices binned to binnum than this
number, testing halts, the operator will be notified, and must confirm to
continue.
The example below does the following. It sets up BIN 1 as a pass bin,. It sets up BIN 2 as a Continuity fail
bin, and only allows 100 consecutive BIN 2's, and 1000 BIN 2's in the lot run.
1, PASS, Good Device
2, FAIL, Continuity Fail, 100, 1000
Bin Description Editor
There is a tool to assist you in creating or editing Bin Files. Launch it by using the Start menu ->
Programming Tools -> Bin Description Editor.
Figure 6.34: Bin Description Editor Screen
Support has been added for a retest/reprobe signal, issued from the handler or prober instead of a START
signal. If issued, data for the preceding device is removed from the various reports (datalog, summary,
etc.) and the serial number is not incremented.
The Bin Description Editor is enhanced to add a column labeled ReProbeCnt, so you can set an maximum
number of times a reprobe can occur in a bin before halting production and alerting the operator.
6-37
Setting Up and Using Disqualify Binning

What is disqualify binning? A fancy term for downgrading a device. In some situations, you will still
consider a device as "good", or "passing", but not as good as some other devices. This is disqualify (DQ)
binning. The ability to downgrade a device, but still consider it "good".
There are three steps necessary to set this up in your test program.
The way KVD handles DQ binning is by allowing multiple limits for each test. Up to eight lower and upper
limits can be set for each test. However, you can't use the Limits Editor, since it only handles the single
limit type of tests. You will now have to use the Extended Limits Editor (see the Programming Tools
menu). This editor can handle multiple limits per test. You do not have to set up multiple limits for every
test, only those that can use then to determine the "grade" of the DUT.
Creating the New Limits File Using the Extended Limits Editor
Launch this by selecting the Start menu, then Programming Tools, then the KVD Extended Limits File
Editor. This feature is not supported by the Bin Description Editor. However, the Extended Limits Editor
can open and edit legacy .bin files.
Creating a BIN File for the Downgrade Process
You will have to decide the binning process as a DUT downgrades. To do this, you'll need to set up a BIN
file. Please note that the order of the PASS bins entered into the file is the order the KVD Library will use to
"downgrade" the device. If you need more information on setting up a BIN file, see “Setting up a BIN File”
on page 6-36.
Loading the New Limits File Using the Command
Finally, in your test program, where you would normally call the function
LOG->load_limits_data(filename);
You will now call

LOG->load_extlimits_data(filename);
This is because the file format for extended limits files has changed to incorporate the multiple lower and
upper limits for a test.
6-38
Sample Disqualify Datalog Display
When a test program is run that is using DQ binning, the datalog will show a "D#" at the outside edge of the
datalogged line, where the "#" is the number of the bin that the device is downgraded to.
Here is a sample datalog file:

----------------------------------------------------
---------------BEGIN DATA LOG ----------------------
---------------Start Log Time : 3/20/2001 2:11:24 PM
----------------------------------------------------
----------------------------------------------------
Program ID : C:\KVDCBU~1\Rev400\LibraryBuild\DebugLibApp.exe
Operator ID : Brian
Tester : MINI
Fixture :
Lot ID : 987654321
Wafer Number : 0
Comment :
LimitsFile : C:\KVDCBU~1\Rev400\LibraryBuild\extlimits.lim
BinFile : C:\KVDCBU~1\Rev400\LibraryBuild\Generic.bin
INFFile :
ParametersFile :
LibraryVersion : Version 04.48.06PR2
----------------------------------------------------
DEVICE(s) : 1
S0 T1 Debug Extended Limits -2.000 V -2.000 2.000 D2
S0 T2 Debug Extended Limits -1.000 V -1.000 1.000
S0 T3 Debug Extended Limits -5.000 V -3.000 3.000 D3 FAIL
Site 0 FAIL Bin 7
Test Time 0.400s
DEVICE(s) : 2
S0 T1 Debug Extended Limits -2.000 V -2.000 2.000 D2
S0 T2 Debug Extended Limits -1.000 V -1.000 1.000
S0 T3 Debug Extended Limits -5.000 V -3.000 3.000 D3 FAIL
Site 0 FAIL Bin 7
Test Time 0.400s
----------------------------------------------------
---------------- END DATA LOG ----------------------
---------------- End Log Time : 3/20/2001 2:11:30 PM
----------------------------------------------------
----------------------------------------------------
Interrogating the Bin Status
If you want to know the bin of the DUT at points throughout your test program, you can use the command:
LOG->CurrentBin();
It will return the actual BIN number of the DUT. If you are just wanting to know if the device is still
considered a PASS by the KVD Library, you can use the command:
LOG->IsPassing();
which returns true if the device is still considered a passing device.

LOG->IsFailing();
Is the converse.
One last note. If you have more downgrade limits on any test than you do passing bins, the DUT will bin as
a zero (0), indicating an improper binning condition.
6-39
Bin Trend Setup and Alarms

Bin Setup Tool - To Support Yield Alarms and Custom Alert Messaging
The Bin Setup Tool, whose files are saved with a new extension .btf has been enhanced with additional
columns for new features.
Figure 6.35: BIN Setup Tool
Column Description
Use Controls whether or not the bin is used in alarm calculations.
Show on Plot Controls whether or not the bin will display a line on the Yield Trend tab on the
Production GUI.
Sublot Alarm % If the alarm % is exceeded (for a fail bin) or goes below (for a pass bin), an
alarm is set. The calculation is performed on all devices in the current Sublot.
Alarm Start The number of devices that alarm calculations are suppressed for at the
beginning of a Sublot, or after an alarm is cleared, to prevent nuisance alarms.
This can be different for each bin, depending on your needs - for instance
continuity issues might be different from process monitoring issues.
Rolling Win% The percentage of the last "n" devices that will cause an alarm.
Rolling Win # The number of devices to use for the rolling window yield calculation. Note this
is the total number of devices tested, not "per site".
6-40
Column Description
Site Delta If the bin is selected to display in the Site Table, this is the required site-to-site
matching percentage. If the lowest to highest site do not match within this delta
%, an alarm will be triggered.
Show Site Table Selects if the bin will be displayed on the Site Data production GUI tab. (The
site-based delta display is separate from the Bin Trend line chart display.
Alarm Message Customizable message per bin to give instructions to the operators.
Require Sprvsr Clear If checked, a supervisor will have to enter the configurable password, AS WELL
AS the operator has to enter their ID, which is a four character MINIMUM code.
Color Configures the color of the line chart for the Bin Trend GUI.
Changing the Datalogging Mode From Program Control

The datalog options that are available on the Customer Preferences Tool allow the user to set the datalog
modes for the Screen and the File. These options, selected from the Customer Preferences Tool create
the initial conditions that the program uses. However, in the cases where the programmer wants to change
the datalogging mode, there are a group of commands from the LOG object that can do this. The
datalogging mode to Screen has three commands, and the datalogging mode to File has three commands.
By calling one of the commands (of the three for Screen, or the three for File), the other two modes are set
accordingly. Here are the six LOG commands, and then I'll explain how to use them by showing an
example.
LOG->SetScreenDatalogAll(true);
LOG->SetScreenDatalogFails(true);
LOG->SetScreenDatalogOff(true);
LOG->SetFileDatalogAll(true);
LOG->SetFileDatalogFails(true);
LOG->SetFileDatalogOff(true);
Each datalogging mode can be in one of three states. The "All" state datalogs all tests, whether they pass
or fail, to the destination (Screen or File). The "Fails" mode datalogs only the failing tests to the destination.
And the "Off" mode doesn't allow any test datalogging to be sent to the destination.
An example might help. Let's say that we have a set of tests that we always want datalogged to the File,
regardless of the mode set by the Customer Preferences Tool. Let's further assume that we know we only
want to datalog fails to File outside of this selected test group. To accomplish this, we simply have to add
two statements to the test program.
short TheSpecialTests()
{
LOG->SetFileDatalogAll(true); //sets the File datalogging mode to ALL TESTS
…
…
….tests
…
…
LOG->SetFileDatalogFails(true); //sets the File datalogging mode to FAILS only.
}
One last note. The parameter sent in is a Boolean field, and can be set to "true" or "false". The user should
always set it to "true". Setting it to false performs the exact same action as the OFF mode.
6-41
Status Memo
The status memo, a field at the bottom of the Production GUI that can be written to from the test program
with the LOG->StatusLog command, is now a top-down scrolling field to ensure the most recent messages
are always visible.
Fast Logger
flog(ansistring) - A fast logger that allows logging to a C:\_kvdco_CustFiles\flog\ text file. Should only
be used in non-time critical sections. Is always on.
Generating Data Reports From Test Program Control

There are four commands available to the user that can be called to generate the four types of data reports
(Summary, Histogram, TDA, and Datalog). The user has the option of sending the report to a file, or to the
printer. The four commands are listed below:
LOG->UserGenTDA(destination, filename)
LOG->UserGenHistogram(destination, filename)
LOG->UserGenSummary(destination, filename)
LOG->UserGenDatalog(destination, filename)
The destination parameter can be one of two values : TOPRINTER, or TOFILE.
If the destination is TOPRINTER, the filename parameter can be left blank since it will be ignored. If the
TOFILE parameter is sent in, then the filename must be a valid PATH and FILENAME with EXTENSION.
Here are a few examples.

LOG->UserGenDatalog(TOPRINTER);
LOG->UserGenSummary(TOFILE, "c:\\kvdco\\datafiles\\summary.txt");
Setting Customer Preferences From Program Code

The easiest way to set customer preferences from within the test program is to call the function
LOG->LoadCustomerPrefFile. This command loads a previously saved customer preference
configuration file (.cpc extension), and then updates the registry. If however, you want to set individual
parameters normally configured by the customer preferences tool, then please consult the list of LOG
object functions given in Chapter 11: Non-Instrument Software Command Summary.
Error Class
Error class is a special class set up to enforce a consistent reporting method for errors and warnings. It
also allows for customer selectable actions based on an error's severity.
Object Name:
ErrorLog
Primary Function Name:
Post
6-42
Primary Function Syntax:

ErrorLog->Post(RESTYPE, SeverityLevel, Message);
where RESTYPE is one of the following enumerated values

rtMPDS rtHPDS rtMPUVM
rtUPLINK rtPWD rtPWS
rtTI rtPLL rtPCIF
rtTH rtLOG rtSITE
rtUSER rtKVD rtRMX
rtDS rtDSPIO rtDIGPIN
rtBOOT rtILLUM rtPHLIC
rtRELAY rtCONNECTION rtTRACE
rtHVDS rtHVRAIL rtHVUVM
rtRELAYCON rtRELAYMAN rtDIGMOD
rtSEQUENCER rtZAP rtHANDLERDLL
rtDATADLL rtUNKNOWN
where SeverityLevel is one of the following enumerated values

slINFO - produces a formatted informational message only (with INFORMATION icon).
slWARNING - produces a formatted warning message (with WARNING icon).
slERROR - produces a formatted error message (with ERROR icon).
slHARDWAREFAIL - produces a formatted hardware failure message (with ERROR icon).
slCAT - produces a formatted catastrophic message (with ERROR icon).
This fail ALWAYS causes program termination.
The Severity level has two purposes. To convey to the operator the level of the problem (if it is a problem).
Also, the customer has the option of how to handle ErrorLog messages based on SeverityLevel. For
example, they can choose to output the slINFO and slWARNING messages to a file, and allow program
flow to continue. They can choose to have slERROR, and slHARDWAREFAIL messages output to the
screen (window) and then terminate the application.
These output and termination options are found in the Customer Preferences Tool.
Figure 6.36: Library Output Messages
6-43
Useful String Constants:

__FILE__ (two underscores) - sends the filename to the function.
__LINE__ (two underscores) - sends the line number to the function.
__FUNC__ (two underscores) - sends the function name to the function.
Example:
ErrorLog->Post(rtMPUVM, slWARNING, "File : %s , Function : %s\n\rVoltage Too
high",__FILE__,__FUNC__);
This message would show the filename and the function that produced the warning message "Voltage too
high".
General Exception Handler

A new exception handler has been added to the KVD library.
This exception handler is able to report (in most cases) the source code filename and line number of the
exception. It can also report the call stack (series of events, function calls) that lead up to the exception
being thrown. The user does not need to do anything to use this exception handler. There are only two
requirements. Do not put your code in a try…catch block since that creates a local exception handler
which will catch the exception, and make sure that the Borland project options have full debug enabled. If
an exception is caused by a KVD library routine, please report the exception type, filename, line number,
and any other pertinent information. Here is an example of a divide by zero exception (purposely caused
for this example).
Figure 6.37: Exception Handler
6-44
Correlation Mode
Correlation Mode allows data from a device to be saved, and then at a later time compared to current data.
It also allows the use of a different limits file, bin file, etc.
Initially, the data for a device must be saved. To do this, simple add a call at the end of the TUser::TSeq to
CorrMode->SaveToFile();.
The function, CorrMode->SaveToFile can take a path+filename AnsiString if the user wants to send the
data to a special file. If no filename is provided, then the default filename is the application path +
application executable filename with the extension ".COR".
To use correlation mode using a previously saved COR file, do the following:
CorrMode->Enable(); // you are now in corr mode
//
//load your correlation limits file
//
//load your correlation bin file
CorrMode->LoadFromFile(); //load the default ".COR" file, or you could have a
//path and filename to load
At this point all testing is in correlation mode. All datalogs, test statistics, etc are corr mode data. When you
are done, either exit the program (END LOT) or you can switch back to normal mode by calling
CorrMode->Disable();.
Other LOG Object Commands

There is a rich variety of commands available to interrogate and modify the state of the tester
administrative control. These should only be used by experienced test engineers who fully understand the
ramifications of assuming responsibility for these features. Others may be available from time to time, and
references to them can be found in C:\_kvdco\Include\kvdwin.h and in Chapter 11: Non-Instrument
Software Command Summary.
Some interesting ones, (whose names explain the function) include:
Examples:
//Set the lot number
LOG->LotNumber="12345678";
//now read it back into a variable
AnsiString lotnum=LOG->LotNumber;
LOG->DUTSN // DUT Serial Number
LOG->ApplicationName
LOG->UploadDataPath
LOG->OperatorID
LOG->TesterID
LOG->FixtureID
LOG->Job
LOG->Comment
LOG->WaferNumber
LOG->ComputerName
LOG->StartLotTime
LOG->BinFileName
LOG->ParameterFileName
LOG->LibraryVersion
LOG->WaferMapX
LOG->WaferMapY
LOG->StopFF
LOG->FirstTestNum
LOG->LastTestNum
LOG->GoodDieCount
LOG->BadDieCount
LOG->UsingCustomDataDLL
LOG->UsingDeviceHandler
LOG->ScreenSampleSize
LOG->FileSampleSize
6-45
LOG->ScreenSampleNum
LOG->FileSampleNum
LOG->LastDatalogString //If in NoDataCollection mode, returns the last datalog string
produced by the KVD->Test command.
LOG->NoDataCollection
LOG->HandTestModeActive
LOG->ActiveWaferTesting
LOG->RuntimeLevel //Returns flags that indicate the run time level of the program.
//Returns:
// const short RUNTIME_LEVEL_STARTUP = 0;
// const short RUNTIME_LEVEL_SYSTEMINIT = 1;
// const short RUNTIME_LEVEL_LOTINIT = 2;
// const short RUNTIME_LEVEL_SUBLOTINIT = 3;
// const short RUNTIME_LEVEL_DEVICEINIT = 4;
// const short RUNTIME_LEVEL_TSEQ = 5;
// const short RUNTIME_LEVEL_DEVICESHUTDOWN = 6;
// const short RUNTIME_LEVEL_SUBLOTSHUTDOWN = 7;
// const short RUNTIME_LEVEL_LOTSHUTDOWN = 8;
// const short RUNTIME_LEVEL_SYSTEMSHUTDOWN = 9;
LOG->SavedDatalogFileName
LOG->EngineeringMode;
LOG->StartedByKVDLauncher
LOG->WaferTestFlow
LOG->AddUserComment(AnsiString name, AnsiString desc);
LOG->ClearUserComments();
LOG->TestInProgress(AnsiString message=NULL);
Test In Progress Splash Screen

If your test times are long, you can display a TEST IN PROGRESS splash screen easily by calling the new
command LOG->TestInProgress(yourstring) where "yourstring" is the message that the splash screen
will display. To turn off the splash screen, send an empty string ( "" ). It is recommended that the call with
the string be put in the TUser::DeviceInit function (thus turning the splash screen on) and that the
command with an empty string (thus turning it off) be put into the TUser::DeviceFinish.
LOG->LimitsFileName()
LOG->SetupFileName()
High-level Classes
KVD
SYS
SITE
BOOT
Instrument Classes
TRelay, TConnection, TSiteConnection, TGroupConnection and TSConnection
TMPDS, TSiteMPDS, TGroupMPDS
TMPUVM, TSiteMPUVM
THPDS, TSiteHPDS, TGroupHPDS
TDigPin, TSiteDigital, TGroupDigital
TWS, TWD, TPWS, TPWD
TTMU
TMatrixClass
KVD Object Commands

KVD->tnum(number);//Number can have values from 1-6199
KVD->Test();
Example:
if (KVD->Test()) return(FAIL);
// tests the result that is in lastresult.value against
//the limits for the current test number
KVD->SetPriority which will change the process priority to PP_HIGH PP_REALTIME or PP_NORMAL.
6-46
SYS Object Commands

SYS->send_bits
SYS->send_value
SYS->del(time); // Delay time can be between 1uS and 5 Sec.
SYS->start_counter( );
SYS->read_counter( ); // for test time calculations
And many instrument reset commands of the form:

SYS->tmu_reset();
SYS->DelayMode=1 which only adds the delay to the transmit FIFO and continues. Should minimize
computer interruptions. Default is SYS->DelayMode=0 until fully tested in a release
Data Bus Command Pipelining Changed For Increased Consistency of Timing

There was an issue in 5.03 Release 1 where commands being sent from the PC to the test head were
going into a FIFO pipeline at the same time a PC-based hardware timer was counting down to support the
SYS->del(time) command. These commands are now properly interleaved with the delay timer so the
timer doesn't start until the command is confirmed to have arrived at the destination in the test head. This
increases consistency so your programmed delay times will not overlap unexpectedly with instrument
commands.
SITE Object Commands

SITE->dslot
SITE->setsites
SITE->lastresult.value
KVD Trace Tool

KVD has been developing this tool to help us trace test program flow throughout the library during runtime.
Some of the objects produced by the KVD Library now support tracing, along with some of the data DLLs
and handler DLLs. The trace statements can be viewed at any time while a program is running by simply
running the KVD Trace Tool, turning tracing on, and selecting the module to trace.
The tool is located under the Start menu:
Start->Debugging Tools -> KVD Trace Tool
The benefit to the engineer is realized when he/she adds trace statements to the test program. Three of
the modules that can be viewed are defined as USER modules, which turn on trace statements that the
test engineer added.
Example:
KVDTRACE->Send(BITFLG_USER0, "This is my user trace message"); //will show the message in trace
view when tracing is enabled.
[BITFLG_USER0 can also be BITFLG_USER1 or BITFLG_USER2]
For developers of handler and/or data DLLs, the same reasoning applies. Using trace statements inside
your DLL code allows those statements to be "watched" while the program is running by switching on the
HandlerDLL or DataDLL switches on the KVD Trace Tool. This can be very helpful when debugging either
a new DLL, or a new test program.
6-47
This is the display from the Trace Tool:
Figure 6.38: Trace Tool
You can save the trace output to a file, and share it with KVD in case of communication issues, especially
with handlers or probers.
Sample:
1 <TskProberMultiPass::OnLotStart> ProberGpibAddress = 5
2 <TskProberMultiPass::OnLotStart> SotDelayTime = 0
3 <TskProberMultiPass::OnLotStart> WaferNumType = 1
4 <TskProberMultiPass::OnLotStart> RetestFlaggedBins = 1
5 <TskProberMultiPass::OnLotStart> UnloadWafer = 0
6 <TskProberMultiPass::OnLotStart> LoadWafer = 0
7 <TskProberMultiPass::OnLotStart> UseProberLotNumbers = 1
8 <TskProberMultiPass::OnLotStart> UseZeroBasedReferences = 1
9 <TskProberMultiPass::OnLotStart> EnableProberAlarms = 0
10 <TskProberMultiPass::OnLotStart> SimulateProber = 0
11 <TskProberMultiPass::OpenWaferStepFile>
12 <TskProberMultiPass::OpenWaferStepFile> WaferStepFile (C:\wintester\sample\sample.csv) opened
13 <TskProberMultiPass::OnLotStart> After TheProber->Clear ()
14 <TskProberMultiPass::OnLotStart> ProberStatus = 0
15 <TskProberMultiPass::GetDieOffsets> Command H (response) = H00 (Prober location #)
16 <TskProberMultiPass::GetDieOffsets> TotalProberSites = 1
17 <TskProberMultiPass::GetDieOffsets> TotalProberSitesMask = 0x0001
18 <TskProberMultiPass::GetLotInfo>
19 <TskProberMultiPass::GetLotInfo> Command V (response) = LOTNUM12345 (Lot Number)
Meter Class
Pending.
6-48
Plotting Measurement Memory

The Measvm Plot Tool is a built in plotting mechanism that can be used to look at the individual
measurements from any of the measvm commands (HPDS, MPDS, UVM). Using it is very simple. From
either your code, or from the Borland Cbuilder Evaluate/Modify mode, use the command:
LOG->plottestnum=T;
Where "T" is an integer value of the test number to plot. Once the test sequence has triggered that test
with the KVD->Test command, the measvm plot will automatically be displayed.
For example, to plot test number 141, you could enter the command:
LOG->plottestnum=141;
Either into your code, or from the debugger, and you will see something similar to this example screen
shot.
Figure 6.39: Measvm Plot Tool
Note that when the plot is showing, the test program is temporarily halted. Closing the plot window allows
the test program to continue. Also, the test number is cleared after it is displayed to prevent continuous
showing of plots. To see a plot for the same test number, or another test number, you'll have to re-enter the
test number to plot.
Instrument Availability
These commands are actually Boolean variables that are set at run time by the KVD Library. The
programmer can use these to determine if the Test Head Configuration has the correct boards for the
application.
pTHC->available.MPDCMOD[num]
pTHC->available.HPDCMOD[num]
pTHC->available.DSPIO[num]
pTHC->available.RMX[num]
pTHC->available.UPLINK[num]
pTHC->available.TMU
pTHC->available.WS
pTHC->available.WD
pTHC->available.PWS[num]
pTHC->available.PWD[num]
If the variable returns true, the instrument is in the test head configuration.
6-49
In case your programs make use of this function, you must ensure that you are checking for each of the
three possible digital instruments, not just the DSPIO.
The variables that return true in the presence of the various digital instruments are as follows:
pTHC->available.DSPIO[n]
pTHC->available.DSPIOR4[n]
pTHC->available.DDD8[n]
Connections and Relays

A discussion of TRelay, TConnection, TSiteConnection, TGroupConnection and TSConnection (shared
connection) is pending.
RTI Support of Shared Connections
Father Cards and DUT Connections

FC Relay Setup Tool
Fathercard relays have been relatively hard to use in the past, being more of a custom resource than a
system-integrated instrument with dedicated addressing language. The addressing scheme for FC relays
is dependent on the FC board type. There is a new tool that can set the addressing scheme of a FC board,
and this integrated scheme is then specified by the TCT tool, used by the RTI tool, and finally by the test
program.
Start->Programming Tools -> FatherCard Setup Tool
The FC relays can be named with whatever name the user chooses, and these names appear in the RTI
(Real Time Interface debugging tool) next to a check box that represents the relay. Clicking the check box
on (checked) turns the corresponding relay on. Clicking it off opens the corresponding relay.
Each relay has a numbered "K" object created for use by the test program. To close or open a relay you
can simply issue commands of the form:
K2->close();
K5->open();
Saved files are given the extension .fcr, and stored in the folder C:\_kvdco\FCSetupTool, as they are
meant to be a shared resource for all users of a system, and not tied to any particular test program. We
encourage each customer of custom father cards to develop their own shared definition file.
6-50
This is the screen from the FatherCard Relay Setup Tool:
Figure 6.40: FC Relay Setup Tool
DUT Board Relays
Note: Due to component obsolescence, the standard relay driver IC 5832 is no longer readily available.
The replacement 6832 is more sensitive to a short glitch coming out of the father card Xilinx, and
may affect certain new construction customer DUT boards. The glitch can be reduced by a
suppression capacitor (0.01uF on the clock pin), and KVD has included updated Xilinx files to
eliminate it in release 5.03R4 and later.
6-51
Connections Table Tool

The ConTable Tool helps the user create Connections to be used in a test program. The tool generates a
CPP and H file that can be added/used by a test program.
Some standard files can be imported, such as Digital Pin Connections, Father Card Connections, and
Calibration Connections.
There are two options available when creating connections. Adding in the _TO_ link word, and Auto
Creating reverse connections. Files can also be saved or loaded for later use.
Why is a Connections Table Useful?

KVD relays are connected to latched register drivers, and each driver IC has a primary address noted on
the schematic for the board. Within the driver IC, there will typically be 8-32 output lines, each one with an
associated bit position. This will be clear when you study a Father Card schematic, for instance. A sample
Addr, Bit pair is 0x85,0x2. The Addr part of this is 85, and the relay drive bit is 2.
The relay addresses within KVD instruments may be addressed directly, but this is quite risky if you are not
working with full knowledge of the functions involved. For relays located on Father Cards and DUT boards,
you will typically have full control over the schematics and need to address each relay.
Figure 6.41: CON Table Screen
6-52
The Name Column

The format of the name field is NAMEA, NAMEB. These names are usually indicative of the connections
being made. As an example, the name field for the connection DS1 to the Analog bus (DDBUSA) is
DDBUSA, DS1
As another example, the name field for the DDCH13 to Digital Driver connection is
DIGITAL, DDCH13
The Array Column []

The array field allows you to declare arrays of connections and to also designate the array element
number at the same time. The number in the array field is the array element number. The ConTableTool
will automatically declare the connection as an array, with the size of the array being one greater than the
largest array element number, for that name.
As an example, if the following declaration was made:

Name [ ]
DDBUSA, DDCH 3 ...
DDBUSA, DDCH 20 ...
DIGDRV, DDCH 3 ...
DIGDRV, DDCH 4 ...
Then the ConTableTool will declare one Array as TConnection* DDBUSA_TO_DDCH[21], and another
array as DIGDRV_TO_DDCH[5]. The individual connections are then implemented using the array
element number assigned under the [] col. In this example, it would be
DDBUSA_TO_DDCH[3]=new TConnection(...);
DDBUSA_TO_DDCH[20]=new TConnection(...);
DIGDRV_TO_DDCH[3]=new TConnection(...);
DIGDRV_TO_DDCH[4]=new TConnection(...);
The Addr, Bit Columns

There are 8 address-bit fields that can be used to enter an address-bit pair for a connection. That means
that at most, 8 relay's addresses can be included in a connection. The address-bit fields should either have
an entry in the form addr,bit, or be left blank.
6-53
The Import/Export Menu Items
Figure 6.42: Import/Export Connections Menu
Import DOS Connections[] Table at Cursor Location
Use this Menu Item to import a connection table that was originally created for a KVD DOS program. The
ConTableTool will allow the user to select a file to be read in. The tool then looks for a connections[] table
entry. Upon finding one, it will attempt to convert the table into the entries that are expected in the
ConTableTool.
Import Fathercard Connections at Cursor Location
See also Placement of Data.
Import Digital Pin Connections at Cursor Location
KVD will supply a connection library that contains all digital pin to digital driver, and digital pin to analog
bus connections that reside internal to the KVD system. Because of the possibility of different digital
subsystems, there could be multiple files to choose from. Digital pin connection libraries will have the
extension DCL. See also Placement of Data.
Import Fathercard Connections at Cursor Location
Relays on the Fathercards are pre-defined in a Fathercard Connections Library file. All Fathercard
Connections Library files have the extension "fcl". All Fathercard Connections declare only one address-bit
pair, since they are associated with only one relay.
Import Calibration Connections at Cursor Location
Some special connections are needed for calibration purposes. These connections will be in a Calibration
Connections library. Again, there could be multiple files based on different test head configurations. The
Calibration Connections library files will have the extension CCL. See also Placement of Data.
Options
At this time there are only two options that are available. Both options affect the CPP and H files that are
created when the Create Connections Button is clicked.
6-54
Figure 6.43: Options Menu
Use TO as Link Word
Default = on
Since the ConTableTool expects Connections names in the format NAMEA, NAMEB , these are
concatenated using the underscore character. This option will use the _TO_ character string to
concatenate the two names. For example, if the Connection Name field has:
THISPOINT, THATPOINT
then the resulting connection that will appear in the CPP and H files (assuming this options is on/checked)
is:
THISPOINT_TO_THATPOINT
If this options is not on (unchecked) then the resulting connection in the CPP and H files will be:
THISPOINT_THATPOINT
Auto Create Reverse Connection
Default = off
This option tells the ConTableTool to automatically create two connections for each entry in the table. The
difference between the two connections (for each entry) is that the names get reversed. using the above
example, and assuming the same names and also assuming the Use _TO_ as Link Word option is on, the
CPP and H files will contain connections that look like this:
THISPOINT_TO_THATPOINT
THATPOINT_TO_THISPOINT
This allows the user to use either name to reference the same connection without having to remember the
order of the names.
6-55
Creating Connections
This is a partial example of how to create connections:
Figure 6.44: Connection Table
In this example, there are 8 connections for DDBUSA to DDCH 0 through 7. Notice that the array field ([ ])
contains the array element number. The ConTableTool will define an array big enough to contain all the
individual connections. In this example, a TConnection will be defined as:
TConnection* DDBUSA_TO_DDCH[8]
This then will hold the 0 through 7 connections.
With these 8 entries, and the address-bit fields defined as you see above, by clicking on the Create
Connections button, and selecting a filename, two files will be created. For this example, if you chose the
filename to be WinConnections.cpp, then both the CPP and H files will be created.
The resulting CPP file looks like this:
CPP FILE for Example

// Declarations Created 1/3/00 5:59:45 PM
TConnections* DDBUSA_TO_DDCH[8];
// End of Declarations
//
void CreateConnections(void);
#pragma startup CreateConnections()
void CreateConnections()
{
DDBUSA_TO_DDCH[0] = new TConnection( 0x8,0x1, 0x85,0x1, 0x87,0x1, 0x88,0x40);
}
//end of instantiations
//
void DeleteConnections(void);
#pragma exit DeleteConnections()
void DeleteConnections()
{
delete(DDBUSA_TO_DDCH[0]);
6-56
}
//end of delete list
H File for Example
The resulting .H file looks like this:

// External Declarations Created 1/3/00 5:59:45 PM
extern TConnections* DDBUSA_TO_DDCH[8];
// End of Declarations
Placement Of Data
The placement of the imported entries begins at the cursor row location. That is, if you click on a row
BEFORE selecting this menu item, the ConTableTool will start importing the entries at the selected row. If
data already exists on the row, the user is prompted whether to overwrite the data or to leave it. As an
example, if the user clicks on the 10th row (any column), and then chooses to import a pre-defined file, or
a DOS connections table, the imported data will begin at row 10, and will continue until all data has been
imported, or the maximum number of entries has been reached.
Loading and Saving Files

Connections that are defined in the grid can be saved (or loaded) in the GRID format for later use. This is
different from the connections files (CPP and H) that are created using the Create Connections button.
After defining all connections in the ConTableTool, SAVE the file under some meaningful name. This file
can then be loaded in later if any changes need to be made. Changes made directly to the CPP or H files
that were created will NOT show up when the saved CON file is loaded. Therefore, only make changes to
your connections by using the ConTableTool. Then, re-create the CPP and H files under the same name
as before.
Sample Test Program Flow- User Class.cpp

#include <vcl.h>
#include "c:\_kvdco\Include\KVDwin.h"
#pragma hdrstop
#define USER_NO_ERRORS 0
#include "UserClass.h"
#include "DCTests.h"
#include "ACTests.h"
#include "Resources.h"
#define PATDIR "c:\\"
PATDATA pat_list[] = {
//ID FILENAME BANK LOADFLAG RETESTPAT
// OFFSET LENGTH HALTFLAG
{0, "pat1.BP", 0, 0UL, 34UL, 1, 2, -1},
{1, "pat2.BP", 0, 35UL, 35UL, 1, 2, -1},
{-1, "NOPATT", 0, 0UL, 0UL, 0, 2, -1},
};
///////////////////////////////////////////////////////////////////////
short TUser::SystemInit()
{
LOG->load_limits_data("KVDTestApp.LIM");
LOG->load_bin_data("KVDTestApp.BIN");
return(USER_NO_ERRORS);
}
///////////////////////////////////////////////////////////////////////
short TUser::LotInit()
{
DIG0->patload(pat_list,"c:\\sandbox_sunnyvale\\");
}
///////////////////////////////////////////////////////////////////////
6-57
short TUser::SubLotInit()
{
}
///////////////////////////////////////////////////////////////////////
short TUser::DeviceInit()
{
}
///////////////////////////////////////////////////////////////////////
short TUser::TSeq()
{
if (Continuity()) return(FAIL);
if (DATATEST()) return(FAIL);
return(PASS);
}
///////////////////////////////////////////////////////////////////////
short TUser::DeviceFinish()
{
return(1);
}
///////////////////////////////////////////////////////////////////////
short TUser::SubLotFinish()
{
}
///////////////////////////////////////////////////////////////////////
short TUser::LotFinish()
{
}
///////////////////////////////////////////////////////////////////////////
short TUser::SystemFinish()
{
}
VirtualHandlerClass
Class:
TVirtualHandlerClass
Object:
Any Handler DLL object
void TVirtualHandler::: PostLotNumber(HANDLE winhandle, char* lotnum);
void TVirtualHandler:::PostWaferNumber(HANDLE winhandle, char* lotnum);
void TVirtualHandler:::PostEndLot(HANDLE winhandle);
void TVirtualHandler:::PostEndSubLot(HANDLE winhandle);
void TVirtualHandler:::PostWaferMapXY(HANDLE winhandle, int X, int Y);
Test Program Automation

Support has been added for command line arguments to automatically run, loop, and exit a test program.
This was intended to enable new automated KVD QA procedures in software regression testing, but they
may be useful for customers writing diagnostic tools for unattended use.
These arguments are: AutoStart (-A), AutoExit (-E) and AutoLoop(-Lnnn).
6-58
Utilization Log File

As an audit trail, or to determine what program was running when an incident occurs (such as just prior to
an instrument calibration failure), certain events are now logged to a disk file. These include launching a
test program or a diagnostic executable, and include data on the yield and lot numbers used.
These logs are kept in the folder C:\_kvdco_CustFiles\UtilizationLog. The filename includes the Tester
ID, month, and year, and the data is saved in CSV (comma separated value) format, for ease in importing
the data to Excel or another spreadsheet program.
Figure 6.45: Utilization Log File
Wafer Mapping
This document will detail all the steps that must be performed to wafer map wafers tested in production.
Creating a Wafer Description File
There are currently only two ways to create the wafer description file (WDF). You can do it manually with a
text editor, or, if you are testing wafers on an M310 system, you can you the newest feature of the
M310Direct Tool. I'll first explain the text editor method, and then quickly explain the M310Direct method.
Text Editor Method

Using any text editor that can produce unformatted text output, open up a new blank file. The first four lines
of the file will contain just the size of the wafer map. The first line should have an integer value that
represents the minimum column number on the wafer map. This is followed by line 2, the minimum row
number. Line 3 is the maximum column number. And finally, line 4 is the maximum row number. For
example, if our device had 1 as the farthest left column, 74 as the right most column, 1 as the top row, and
51 as the bottom row, the first four lines would look like this
1
1
74
51
Next, we will enter a line for each row of the wafer map. The following characters should be used for the
following type of die :
• - <dash> for untestable die.
• P for processable die
• I for Ink die
• S for skipped die.
6-59
The following lines are just an example. You would have entries that match your wafer.
1
1
74
51
-----------------------------------------------------------------
-----------------------------------------------------------------
----------PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP---------------------
-------PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP------------------
-----PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP----------------
----PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP----------------
--PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP------------
PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP-----------
This would continue for all rows on the wafer. This map will be loaded by the command
LOG->load_waferdesc_file(filename);
M310Direct Method
The latest version of M310Direct has a secondary page that pops up once the tool has successfully
connected to the M310. Click on the page to activate it. On this page you simply have to enter the TSU
(M310 trimmer Setup) filename, pick a path and filename of the wafer description file that will be created
and saved by the tool. Once this is done, click on Start. You should see the wafer description information
being generated on the lower part of the window. Once it is complete, it will be saved. If you didn't specify
a filename, you'll be prompted to enter one once the description generation is complete. Also, if you do not
specify a path when specify the output file name, then it will be saved in the root directory of the C drive.
Creating a Wafer Map Color File
The Wafer map Color File (WCF) specifies the colors that various software bins will show up as on the
wafer map. The first line of this file must always be:
[COLORS]
since this is being read in as an INI file.
Underneath this [COLORS] line, the bin number will be associated with a color constant. For example, if
you wanted BIN 1's to show up as bright green, you would want to set it to the color clLime. The entry itself
has a simple format, BIN # = COLOR. Again, as an example, if I did want to set BIN 1's to clLime, one entry
would look like this
[COLORS]
1 = clLime;
So what colors are possible? They are listed below. Please note that the color IS case sensitive.
ClAqua clBlack clBlue
ClDkGray clFuchsia clGray
ClGreen clLime clLtGray
ClMaroon clNavy clOlive
clPurple clRed clSilver
clTeal clWhite clYellow
So, your file might look like this

[COLORS]
1 = clLime
2 = clRed
3 = clNavy
6-60
Loading the Wafer Description File
Loading the WDF is done with the command

LOG->load_waferdesc_file(Filename)
Where the filename is the PATH and NAME and EXTENSION of the WDF file.
Loading the Wafer Color File
Loading the WCF is done with the command

LOG->load_wafermap_colors(Filename)
Where the filename is the PATH and NAME and EXTENSION of the WCF file.
Enabling Wafer Testing in the Customer Pref Tool
Finally, with a WDF and WCF file loaded, all you have to do is make sure that the Customer Preferences
Tool has the Wafer Test Flow selected. Also, you'll notice right below this the options to SHOW the wafer
map and to load any previous Wafer Data. If data was saved off of a wafer that never completed, and now
the wafer is being restarted, the previous data can be loaded if this option is on.
Delay Table
Due to KVD data bus speed not always being matched by certain father card resources, you may see code
such as the following in an existing, working test program:
////////////////////////////////////////////////////////////////////////
// changes delay_time for signals send to following address from default
// (8ns to 16ns) and resets the value, to enable drivers function properly.
for (int i = 0x27; i <=0x33; i++)
{
delay_table[i]=16;
SYS->send_value_slot(i, 0, 0xb, 0);
}
// DELAY TIME FOR DAC ENABLES

for (int i = 0x38; i <=0x3C; i++)
{
delay_table[i]=16;
SYS->send_value_slot(i, 0, 0xb, 0);
}
////////////////////////////////////////////////////////////////////////
Just copy this to the LotInit function of any new test program using the same father card. It's magic.
The need for this sort of code will be reduced in future releases - please keep up with KVD Release Notes
to know when.
send_value
Send_value and send_value_slot are very low-level KVD functions to send commands directly to
instrument registers in the absence of higher-level language support. When you see them, it will always be
done by KVD applications engineers to enable a new convenience feature in anticipation of later and more
readable code.
6-61
Setsites
Setsites is a function that configures the system software for the expected maximum number of sites in a
multisite program, and where in the test head the resources are. Normally, you will be using a sample
program to copy the proper configuration from.
SITE->setsites( 4, //active sites total
0xF, //active sites at startup mask
1, //dc_sides mask
2, //dd_sides mask
0, //wd_sides mask
0, //ws_sides mask
2, //tmu_sides mask
0); //hpdc_sides mask
Multisite Development
Multisite Testing
Some C++ classes have been configured to make multisite support easier.
There are multisite and group classes for Digital, MPDS, HPDS, and MPUVM classes.
These classes are:

• TSiteMPDS: combines MP DUT Sources for multi-site testing
• TGroupMPDS: combines MP DUT Sources in a group under one name
• TSiteMPUVM: combines MP UVMs for multi-site testing
• TSiteHPDS: combines HP DUT Sources for multi-site testing
• TGroupHPDS: combines HP DUT Sources in a group under one name
• TSiteDigital: combines Digital Pins for multi-site testing
• TGroupDigital: combines Digital Pins in a group under one name
• TSiteConnection: combines Connections for multi-site testing
• TGroupConnection: combines Connections in a group under one name
The idea behind these classes is simple. When the user creates an object of one of these classes, they
can pass in up to thirty-two corresponding objects. The position of the objects in the parameter list
represents the site information.
An example best illustrates this. In a program, we could use, for example, MPDS[2] as Vdd for site 0, and
MPDS[10] could be Vdd for site 1. To accomplish this, the user would create a TSiteMPDS object with
these two DUT Sources
TSiteMPDS* Vdd = new TSiteMPDS ( MPDS[2], MPDS[10] );
Note here: The first element in the declaration (constructor) it is assigned as a resource for site 0. The next
DUT Source is the second DUT Source in the list, it is assigned as a site 1 resource.
After creating a Site DUT Source, it is then used the same as a typical DUT Source. Again, using the 2
DUT Source Vdd created above, the voltage could be set to 5.0 volts with this statement:
6-62
Vdd->setv(5.00);
Or a measurement could be performed on all:

Vdd->measvm(10);
Etc.
These statements would then set MPDS[2] and [10] to 5.00v, or take a measurement on each of the DUT
Sources. However, IF a site has been disabled due to a previous fail on that site, or by the user disabling it
though a call to:
SITE->disable(sitenum)
Then any resource assigned to that disabled site would NOT be issued the command. For example, if site
1 had failed previously, and the command:
Vdd->setv(5.00)
was issued, then MPDS[2] would be set to 5.0 volts, and MPDS[10] would not be set.
This is because of the SITE class' site shutdown procedure. When a site is shutdown, and assigned DUT
Source resources are first set to zero volts, then set to a current range of 20uA, and finally turned off.
One note here about the measurements. When a TSiteMPDS object issues a measvm command (like the
above Vdd->measvm(10)) the results are stored in the SITE->results array according to the site resource
number that was assigned. In this example, the two measurements would be in SITE->results[0] through
SITE->results[1]. When the command KVD->Test() is called, it knows how many sites are being used, and
then compares the matching results (straight from SITE->results) against the limits.
So far, we've only covered the TSiteMPDS class. The other site-based classes have the same site-
resource assignment strategy, and operate the same way when issuing commands, and shutting down
sites.
For example, if a tri-site testing required an SCLK pin, then the programmer could assign three digital pins
for the three sites with this declaration
TSiteDigital* SCLK = new TSiteDigital (DDCH[0][1], DDCH[1][1], DDCH[2][1]);
This would assign DDCH0 on side 1 as the site 0 resource, DDCH1 on side 1 as the site 1 resource, and
DDCH2 on side 1 as the site 2 resource. Then, the format could be set with the following command:
SCLK->dfmt (0, CLK2, 0e-9, 100e-9, 0); //set SCLK to CLK2 format for time set 0
All three pins (if their corresponding site is enabled) will be set to this format.
The site shutdown for the TSiteDigital class simply disables the individual digital pin.
TSiteConnection, allows the user to group Connection objects together into site resources too. This class
requires that the user to create TConnection objects prior to creating the TSiteConnection object, since the
parameter list for the TSiteConnection object requires TConnection objects. An example again best
illustrates this concept.
6-63
Let's assume that the user has created three connection objects that will be used to connect or disconnect
a digital pin to the DUT pin. The three connections are for the three sites, and the DUT pin is the SCLK pin.
Let's further assume that the site 0 digital to DUT connection goes through K0, the site 1 connection goes
through K1, and the site 2 connection goes through K2. Then the TConnection objects (this is not the final
TSiteConnection object yet) would look like:
TConnection* DDCH0_TO_SCLK = new TConnection (K[0]); TConnection* DDCH1_TO_SCLK = new TConnection
(K[1]); TConnection* DDCH2_TO_SCLK = new TConnection (K[2]);
The site-based connection that will be used for tri-site testing in this case, would be something like
TSiteConnection* DIG_TO_SCLK = new TSiteConnection (DDCH0_TO_SCLK, DDCH1_TO_SCLK, DDCH2_TO_SCLK);
Then the con and discon command would be:

DIG_TO_SCLK->con();
Or
DIG_TO_SCLK->discon();
Site shutdown for a TSiteConnection object is to discon the corresponding Connections for that site.
Note: To make all this work properly, the SITE object needs to be set up to use the sites correctly. Make
sure that the first two parameters in the call to SITE->setsites takes into account the site
configuration you plan to use. The first parameter is the total number of sites (i.e.; 3 for tri site
testing, 4 for quad site testing, 2 for dual site testing, etc). The second parameter is the MASK for
the enabled sites. For dual this would be 3, for tri-site testing this would be 7, for quad site this
would be 15, etc, etc.
Limitations
All of these classes can take up to thirty-two objects, which means a limit (currently) of 32 site testing.
Group Objects
To go along with multisite objects, you can also define group objects, where functions act on the group as
a whole, but have no operational change due to sites being active or disabled.
Data Output Files
Data files (SUM, LOG, HIS, TDA) for multisite operation are available with site-separated data if desired,
with "_sites" appended to the file name, before the .his, .log, .tda, or .sum extension. Normal data files are
still generated using the traditional filenames, containing consolidated data of all sites combined.
SITE Object Control
SITE >lastresult
Final result is saved in this variable after measurements from, TMPDS, THPDS, TMPUVM classes.
RESULT lastresult;
6-64
SITE >disable
Disables a particular site. Only used in multisite testing.
short disable(short sitenum);
SITE >enable
Enables a particular site. Only used in multisite testing.
short enable(short sitenum);
SITE >IsActive
Returns true is the site passed in is considered ACTIVE.
bool IsActive(unsigned sitenum);
SITE >resetall
short resetall(void);
SITE >set_default_sites
Sets the SITE parameters to the defaults read in through the TCT.
short set_default_sites();
Description:
It is typical that the defaults supplied by the TCT are correct, and so this function is used as the default for
the SITE object created by the library.
SITE >setsites
Allows setting of the SITE parameters. This overrides the default settings.
short setsites(unsigned howmanysites, unsigned siteval, unsigned DCsides, unsigned DDsides, unsigned
WDsides, unsigned WSsides, unsigned TMUsides, unsigned HPDCsides);
Parameters:
unsigned howmanysites
The total number of active sites (1 through 8).

unsigned siteval
The mask that represents the active sites at startup.

unsigned DCsides
The mask that represents the active DCMOD or MPDCMOD board sides.
unsigned DDsides
The mask that represents the active DSPIO board sides.

unsigned WDsides
The mask that represents the active WD board sides.
6-65
unsigned WSsides
The mask that represents the active Ws board sides.

unsigned TMUsides
The mask that represents the active TMU board sides.

unsigned HPDCsides
The mask that represents the active HPDCMOD board sides Return Values.
Description:
The default site settings are typically used. However, if you need to alter those settings, you can use this
function.
SITE >sitemask
Simple function that converts a sitenum to its mask value.
short sitemask(short sitenum);
Description:
For example, sitenum 0 has a mask of 1, sitenum 1 as a mask of 2, sitenum 2 has a mask of 4, etc.
Resource Manager
In REV503, we have implemented what is known as a resource manager, with object being named
KVDRMan. The purpose of the resource manager is to make it easier to define a user resource "outside"
of the test program. Although code still has to exist inside the test program, the KVDRMan can make it
easier when using groups of resources, or when testing in multi-site mode.
The KVDRMan loads resources from a user defined INI file. This is done through the command
KVDRMan->LoadResMap(filename);
Where "filename" can contain the path and filename of the INI file, or just the filename if the file exists in
the same folder as the application.
The format of the resource file is in normal INI file format. Resources are defined in specific sections based
on the type of resource, and the type of use. All resource will follow a pre-defined format in the file based
on these rules:
Site related resources are always under a sections named [SITE_XXX] where XXX is specific to the
resource type. For example, site related RMX resources, based on the TAllRMX class, are under the
section [SITE_RMX]. Group related resources, which are not tied to any specific sites, will be under a
section named [GROUP_XXX], where the XX again is resource specific. Again, as an example, for RMX's
based on the TAllRMX class, it would be [GROUP_RMX].
The resources in each section, in general, follow the format:

RESOURCE_NAME = <pinlist>
Where resource name is a string name that uniquely identifies the resource, and the <pinlist> would be
representative of the resource being defined. As an example, using the RMX resources, a valid resource
would be defined like this:
6-66
[SITE_RMX]
MyMatrix = M0P0, M8P0, M16P0, M24P0
For this example, the resource manager KVDRMan would read in "MyMatrix" as the name to be used for
this RMX resource, and the four MxPy relays defined would be assigned to this resource. Since the
definition is under the [SITE_RMX] section, the resource manager would assign M0P0 to site 0, M8P0 to
site 1, M16P0 to site 2, and M24P0 to site 3.
In the user's application, they initially would make a call to KVDRMan->LoadResMap and pass in as the
lone parameter, the filename of the resource INI file. If, in this example, we had saved the resource file as
"MyResources.INI", then the user would load it with
KVDRMan->LoadResMap("MyResources.INI");
Once the resource file has been loaded by the resource manager, the user then uses a simple command
syntax to create their resource in the application. For RMX, and remembering that the RMX resource is
based on the TAllRMX class, the resource gets created with this command:
TAllRMX* rmxvariable = KVDRMan->RMXFromMap(<rmxresname>);
Where <rmxresname> is the resource name used in the INI file. So in our example, we might do this:
TAllRMX* MATRIX;
MATRIX = KVDRMan->RMXFromMap("MyMatrix");
From this point on, the TAllRMX variable named MATRIX would be used as any TAllRMX variable.
MATRIX->Set();
This would set all four MxPy relays defined for this resource (assuming all four sites are active).
MATRIX->Clear():
This command would clear all four MxPy relays (again, assuming that all four sites are active).
In the event a Set or Clear command is called and a site or sites are in active, then the command is
ignored for the inactive sites. If the resource was defined in the GROUP_XXX section, then the command
is issued for all the defined pins (or relays) regardless of site active states.
RMX Implementation
As explained earlier, the TAllRMX has been implemented in the KVDRMan resource manager. The
TAllRMX encapsulates all available RMX boards in the test configuration. The "MxPy" values have been
implemented to also span across all the available RMX boards in the test configuration. See the TAllRMX
class (or the TAllRMX Class write-up) for valid MxPy values.
Objects Created by the KVD Library

BootTester
Purpose:
Used to boot the test head.
6-67
Available functions:
boot_all(<confirm>);//where confirm=1 prompts the user before boot
Example:
BootTester->boot_all(1);
K[0 thru 80]

Purpose:
Test head relays, for standard (non-custom) Father Cards. Do NOT use these objects for custom father
cards. Future software libraries will include Classes for driving such custom relays.
open();
close();
Example:
K46->close();
DDBUSA_TO_DDCH[NUMDDCHANNELS];
Purpose:
Connects a Digital Pin to the Analog Bus DDBUSA.
con();
discon();
Example:
DDBUSA_TO_DDCH[6]->con();
DDDRV_TO_DDCH[NUMDDCHANNELS];
Purpose:
Connects a Digital Pin to the Digital Driver.
con();
discon();
Example:
DDDRV_TO_DDCH[6]->con();
TH
Purpose:
Performs functions related specifically to the test head.
6-68
discont_reset()
dd_reset(); //resets the digital subsystem
fc_reset(); resets the fathercard
tmu_reset();
wd_reset();
ws_reset();
Example:
TH->dd_reset();
User-defined Forms for Production Operation

Class:
TKVD
Object:
KVD
TKVD::AddUserForm(AnsiString caption, TForm* userform)
6-69
6-70
Customer Preferences Tool
Launch the Customer Preferences tool from the Start menu, to configure customer-specific options in your
preferred way.
Figure 7.1: Launching the Customer Preferences Tool
Figure 7.2: Main Customer Preferences Screen
Preferences Page
The customer preferences tool allows the customer an easy way to change some of the run time features
and/or options of the run time environment. This tool is considered by KVD to be customizable per
customer. Therefore, only the fields that would be the same for every version of this tool will be explained.
There are four pages (TABS) on this tool. The Preferences page allows the user to turn on and off different
options, or to choose certain startup conditions. The Datalog Control page offers many flexible options for
data handling. The Handler Options page is where handlers/probers are selected, and Handler Bin Tables
are chosen. The Custom Data DLL page is where you can choose to filter your datalogs or summary
information through a program that may put it into a suitable format for off-line processing.
7-1
Field Description
Run Mode The normal desired selection here is Production, to launch test program
executables. If it is set to Engineering, then the test program .ini file that the
Setup File Tool creates is searched to find a Borland Project file (.bpr) to launch
instead. This allows test programs to be debugged while the main KVD loop is
running, which may affect execution timing. If the .bpr file that is referenced by
the .ini file is missing, the library falls back to running the test program
executable only, in Production mode.
Menu Items The menu items that appear on the main KVD production screen can be
disabled or enabled, to reduce operator confusion.
Auto Boot on Startup The KVD system will begin a boot process once the Start button is clicked. If
this option is Disabled, the operator will be prompted on whether to boot, or not.
If this option is Enabled, the boot will occur automatically.
Confirm Before When an End Lot occurs in the production environment, the user is prompted to
Stopping Confirm the End Lot before testing stops. This option can be changed by
clicking on the NO radio button in this box.
Show Hand Test Hand test mode is a GUI feature where the system can be instructed to test
Mode Menu only one device at a time, with operator control over the serial number. This is
useful for setup verification, or for testing correlation devices where the serial
numbers may not start at one, or be contiguous.
Test Statistics View The real time test statistics page is sometimes more easily readable in single-
(Columns) column mode instead of double-column. You have control over this appearance
of the GUI here.
Hide Setup Info On The Launcher can display the entire setup file for each test setup it finds. The
Launcher option can be toggled between showing the info, and not showing it.
Startup View The Production runtime environment contains three or four (if wafer flow is
selected) pages on its main screen, although more are possible. The user can
select the default page that is visible when the test program is first launched.
Stop On First Fail This is a standard feature of test systems. In normal production, you wish to halt
testing and immediately bin the device to maximize tester throughput. If Stop on
First Fail is turned off, then a bad device will be tested beyond the point of
necessity, thus wasting time on a part you are going to throw away anyway.
When you are doing correlation, QA, or engineering, and wish to know all the
possible failing tests, this feature may be turned off.
Ignore Raw Data Files The KVD tester will create a raw data file whenever an End Lot occurs. The file
is saved in the chosen data path under a name associated with the Lot Number.
If another production run is started with the same data path AND the same lot
number, the system software can handle the existing raw data. Clicking on NO
in this box forces the system to handle the raw data. Clicking on Yes forces the
system to completely ignore any existing raw data files.
7-2
Operations Environment
Field Description
Raw Data Handling If the user has chosen to handle the raw data (see above), there then are three
ways it can be used. If the User chooses Automatically Show if it exists, then
the data is read in, and all counts are adjusted. The user is not prompted. If the
user chooses Automatically No Show if Exists, then the data is read in, but no
visual counters are adjusted, only the internal lot summary counts are adjusted.
Finally, if the user chooses Prompt User, the user will be prompted on how to
handle the data.
Max Lines On You can customize the screen size for the engineering screen, which looks like
Engineering Screen a historical datalog display.
Testing Flow For packaged devices, the main testing data flow involves a lot identification
only. For wafer testing, you are presented with a display of both lot and wafer
numbers, and summary files are available for both the lot and sublot level.
Wafer Map Options These are options available when you are connected to a GSI M310 laser
trimmer.
Hide Minimize/ To prevent operator errors and confusion, you may choose to hide these
Maximize Icons window control icons.
Full Screen Mode Selecting full screen mode may also prevent accidental operator mouse clicks
on unintended programs.
Library Version Check Run-time error checking to confirm that the test program being run was
compiled using the same KVD library version. Program will halt if a mismatch is
detected. Default condition for this check is ON, which may cause operator
confusion if they are presented with a program launcher with mismatched
programs to choose from. This feature may be turned off in the Customer
Preferences Tool if desired, which will emulate current system behavior, at the
slight risk of running mismatched programs that may generate fatal run-time
exceptions.
Note: This feature will not detect legacy test programs that were compiled
under older KVD libraries. It is designed as a feature to protect against
future KVD libraries being used to run test programs compiled using
5.02 or subsequent mismatched libraries.
The confirmation box that pops up if a violation is detected looks like this:
7-3
Field Description
Process Priority The test programs can implement a change in the windows process priority,
which can be overridden by the Preference option here:
Ignore
Does not allow any changes to the process priority from within the test program
code. Program code priority changes would have been programmed by the test
engineer.
Normal
This is the priority level that the windows operating system normally uses for
any windows application.
High
This is a priority level higher than the normal level. This level can keep out
some of the network traffic, and other process interruptions that can slow down
a test program. Some (not all) test programs can run faster. One note about
running in the HIGH mode. Interrupting the test program (pausing or stopping
via mouse clicks) can be affected.
Check MPDCMOD Testing can be halted until the test head temperature matches the last
temperature calibration temperature (within a chosen tolerance).
Rolling Yield Display A feature useful to production operations is available called the Rolling Yield
Display, to assist in spotting trends of yield reduction. If enabled in the
Customer Preferences Tool, the Yield Display will show the yield of the last "n"
devices, where "n" can be between 20 and 2000. The count resets itself at end
of lot or sublot.
If activated, the display window appears on the Production View tabsheet (only)
just underneath the normal lot yield display window. In this screenshot, the
display is set to show the yield of the last 20 devices.
This is a single-site feature, however, and for multisite programs, the site-based
yield GUI is more useful, which is a separate production GUI tab. (documented
later)
7-4
Datalog Control Page
Figure 7.3: Datalog Control Preferences
There are many choices for how to handle new data (data from an interrupted lot, or a possible rescreened
lot), whether or not to automatically force the data to be printed without operator intervention, and what the
default datalogging choices will be. In addition, sample datalog ratios can be specified, in case you do not
wish to save or display the datalogs for each device, but only every "nth" device.
The possible output files are:

• Summaries - Lot, Bin, and Failed Test combined into one report. See “Summaries” on page 7-40.
• Histograms - Graphical analysis of test results. See “Histograms” on page 7-41.
• TDA (Test Data Analysis) - like histograms, but data only, no graphics. See “Test Data Analysis” on
page 7-42.
• Datalogs - test-by-test measurement results output for each device selected for datalogging. See
“Datalogs” on page 7-38.
Field Description
Save Summary To prevent power interruptions or other incidents from erasing partial testing
Feature summaries, you now have an option to save data to disk between each device.
Data is buffered by one device if hand test mode is active, in case the device is
retested (which normally backs the last data out of the summaries).
Datalog data is already saved to the disk after each device, at a programmable
Sample Size.
KVD always recommends installing a UPS (uninterruptible power supply) if you
are in a region of very bad power, since the UPS also. protects against surges
and spikes as well as short power dropouts.
7-5
Field Description
ZIP Data Files By selecting YES, the data files produced by the KVD Library (summary,
histogram, datalog, and TDA files) will be combined into one zip file (named the
same way the files are named, and in the same folder.) This can be useful not
only for conserving disk space, but also speeds up transfers across networks.
Handler Options Page
Figure 7.4: Handler Options Screen
The handler options page allows to user to specify handler and prober DLLs by selecting the Disabled or
Enabled radio boxes in the Use Handler group box. On this page, the word Handler references both
Packaged Device handlers, and Wafer Probers. If a handler will be used (Enabled), then the handler DLL
listed in the Select Handler File list is the DLL file that the system will automatically use on start up. If a
handler is being used, and it is a packaged device handler which needs a software bin to SORT category
conversion, then the Bin Table selected will also be loaded. All handler/prober DLL files found in the list are
either supplied by KVD, or customer-written by modifying a generic template. If a Handler/Prober is being
used that does not show up in this list, contact KVD for instructions and sample source code. The Bin
Table files listed are generated by the user by using the Handler Bin Table Tool.
Parallel Handler Driver Instructions
These are the steps to modify the standard parallel handler/prober driver for your particular requirements.
Current KVD software supports the presence of one configuration file at a time, but this will soon be
expanded to allow easy selection from a menu of various handler models.
1. Build a cable using a 24-pin Amphenol male connector 57-30240 (or equivalent), unless your system
is using a custom interface connector.
2. Edit the file C:\_kvdco\Handlers\GenHCIF.ini (used in KVD Library Releases 5.0.0 and higher).
7-6
[If this changes in future releases, please follow instructions given in the release notes for that release.]
Do not change the first line at all. Only edit the values to the right of the = sign on each line.
[PARAMETERS]
BIN_SETUP_TIME = 15e-3
EOT_ACTIVE_TIME = 25e-3
BIN_HOLD_TIME = 15e-3
EOT_Active = 0
IsPulsed = 1
ActiveEOTBINLevels = 0
ExpectedSOTLevel = 0
ExpectedEOWLevel = 0
Debugging=0
Explanation of Parameters:
(see timing chart on following page)

BIN_SETUP_TIME
Time after activating the BIN lines, before EOT is active.

EOT_ACTIVE_TIME
Time that both EOT and BIN lines are active. Starts at the end of the BIN_SETUP_TIME.
BIN_HOLD_TIME
Time after EOT goes from active to inactive, and BIN lines remain active.
EOT_Active
1 means we expect EOT to be active high true, 0 means we expect EOT to be active low true.
IsPulsed
0 means false, the Start Of Test is expected to be a static level. 1 means true, the Start Of Test is pulsed.
(edge sensitive)
ActiveEOTBINLevels
0 means a LOW is considered active true for BIN lines. A 1 means a high is considered active true for BIN
lines.
ExpectedSOTLevel
0 means a low on SOT indicates START OF TEST (low true or low-going logic). 1 means a high on SOT
indicates START OF TEST. (high true or high-going logic).
Debugging
0 means do NOT go into interactive debugging mode. A 1 means to enter debugging mode, which stops
the DLL at various places so signals can be verified.
ExpectedEOWLevel
0 means a low on EOW indicates an End Of Wafer has occurred. 1 means a high on EOW indicates End
Of Wafer. The production software uses this signal to end the current Sublot, perform the desired action for
summaries and datalogging, increment the Sublot (wafer) number by one, and resume testing with a new
Sublot.
In the example above,
BIN_SETUP_TIME is 15mS
7-7
EOT_ACTIVE_TIME is 25mS
BIN_HOLD_TIME is 15msS
EOT will be active low
The SOT is a pulsed SOT
The KVD will output a low on BIN lines and EOT to bin the device.
The SOT (which is designated as pulsed) will be LOW when it is active.
Figure 7.5: Parallel Handler Timing Chart

3. Create a Bin Table using the KVD Bin Table Tool (under the Start menu > Programming Tools.) Bin
Tables are required to associate the KVD software bins (up to 63) with the hardware lines used by the
parallel handler interface.
For instance, in a handler with one fail device bin (let's say Bin 8), you may wish to have a device that
falls into ALL software bins from 8-63 go into that handler bin. A Bin Table that illustrates this idea is in
Figure 7.6.
7-8
Figure 7.6: Bin Table Example

4. Save this Bin Table using the Save File command. Choose your own name for it, but make sure to
keep the ".HBT" extension. The HBT files are always stored in the folder
C:\_kvdco\Handlers\BinTables.
5. Start the KVD Customer Preferences Tool (under Start menu > Customer Support), click the
Handler Options tab. Make sure you are enabling the Use Handler option, and choose the
GenHCIF.dll. Make sure you are enabling the Use Bin Table option, and choose the Bin Table you
saved in the previous step. Click the Update button to make sure the Windows registry saves your
selections.
Figure 7.7: Selecting the GenHCIF.dll
7-9
TEL
If your Customer Preferences are set in Engineering Mode (instead of Production Mode), and you are
using the most recent TSK or TEL Multipass Prober DLL, an additional Menu pull-down item appears,
labeled Handler.
Figure 7.8: Handler Menu
If you enable Handler Engineering Mode, an additional GUI form will appear with four tabs.
Figure 7.9: Prober Engineering Form Screen
Tab Description
INDEX Allows control over stepping from die to die, moving to any designated die X
and Y location, setting active sites, starting a test sequence, Z-up or Z-DOWN,
ending the lot, or exiting the engineering tool.
CONFIG This is a display only (not control) page that displays the current die location,
totalsites, reference die x and y, die height and width, and chuck temperature.
WAFERS Displays the contents of two cassettes, and allows control over wafer loading
and unloading, alignment, and a clean probe function.
PROBECARD A display GUI for probe needle layout.
7-10
Support for the TEL P8 Prober includes the following configuration settings in the file
C:\_kvdco_CustFiles\Handlers\TelP8ProberMultiPassCfg.ini.
[PARAMETERS]
; The probers primary GPIB address
GpibAddress = 5
; Time to wait after prober's SOT before testing starts

SotDelayTime = 0e-3
; WaferNumberType = 0 is to disable wafer number reading from prober
; WaferNumberType = 1 is for 12, where wafer num is 12
WaferNumberType = 1
; Offset all X/Y die location to 0,0 references

UseZeroBasedReferences = 1
; Prober lot numbers, or application based lot numbers

UseProberLotNumbers = 1
; Retest flagged bins at end of wafer before unloading

RetestFlaggedBins = 1
; Issue load wafer command at start of lot

WaitForWaferLoad = 1
; Unload wafer at end of lot if still on chuck

UnloadWafer = 0
; Turn on prober light tower on consecutive fails

EnableProberAlarms = 0
There is also a prober simulator feature in the .ini file:

; Simulate prober emulates prober hardware when no prober exists. No GPIB
; commands will be issued. A total of TotalSimulateWafers will be tested.
; The SimulateProberLocationNumber is the probe card layout. TotalProberSites
; is all possible test sites on the probe card. This is used along with the
; location number to get the probe card layout from the TelP8ProberDieOffsets.ini
; file. Use a total prober sites of 999 for "free multiple probing"
SimulateProber = 0
StartingWaferNumber = 10
TotalWafers = 1
WaferIncrement = 2
TotalProberSites = 1
ProberLocationNumber = 0
ReferenceDieX = 12
ReferenceDieY = 51
DieHeight = 5.58
DieWidth = 5.58
Additional TEL-TSK Driver Low-level Commands
Driver Commands:
short HANDLER->SetTemperature (unsigned Site, double Temperature);
double HANDLER->GetTemperature (unsigned Site);
short HANDLER->GotoLocation (int X, int Y);
short HANDLER->GetCurrentLocation (int &X, int &Y);
short HANDLER->Contact (unsigned Site);
short HANDLER->Uncontact (unsigned Site);
void HANDLER->writestring(char* TheString)'
char* HANDLER->readstring(void);
short HANDLER->getstatus(void);
Use these commands with great care. There is a large potential to cause flow problems within the handler
driver. This is especially true of the readstring and writestring commands. Only do the getstatus() to
receive a status that you expect from your writestring and readstring commands. If you get a status that
does not "belong" to your sent commands, it might cause an important status to be missed inside the driver
flow.
7-11
TSK
The TSK prober driver has been enhanced (access this mode by clicking the "Handler" button at the top
menu of the Production GUI) to offer an off-line simulator and an engineering mode for fine control over
prober functions.
Site-swapping on Multitest 93xx and Aetrium V8 Multisite Handlers
For maximum flexibility, KVD can accommodate site-swapping on these quad site handlers, and can be
configured as follows:
Site reversal is controlled by a keyword in the Cfg.ini file. Setting "ReverseSites = 1" will enable the
reversal, setting "ReverseSites = 0" will disable it. The default mode is 0 for both drivers, which will be the
Multitest default site layout.
Another launcher setup special fields keyword has also been added to these two drivers. That is
"HandlerCfgFile=". Use this to override the default Cfg.ini filename and path within the driver. This can
allow each setup file to specify a different Cfg.ini file. You can make one that has reversed sites, and one
that does not.
Multitest
Support has been added for GPIB control of the Multitest 93xx handler, with suitable trace statements for
communication debugging.
Parallel Handler/Prober Interfacing
Interfacing to a handler or prober can be accomplished in numerous ways. RS-232, GPIB, or Ethernet (via
private networking) are ways to communicate in a complex way with the handler or prober. Please contact
your local KVD applications engineer for assistance designing a software control file (DLL - Dynamically
Linked Library) for your particular model if necessary.
The choice of which DLL to use at any time is a production control issue, for which there is a Preferences
GUI (Graphical User Interface) available to test floor operators. This is documented in “Parallel Handler
Driver Instructions” on page 7-6.
For handlers using a simple parallel interface, KVD provided the optional HCIF board, located in the CPU,
designed to occupy an ISA slot.
7-12
HCIF (Handler Control Interface)
Figure 7.10: HCIF Pictorial
The HCIF is the hardware board which contains the opto-isolated interface to control the standard parallel
handler/prober port.
The cable from the HCIF to the rear panel of the CPU case plugs into the HCIF board on connector X1, a
26-pin flat cable header. Pin 1 is on the left on this view of the board.
The HCIF contains a SCSI-appearing connector on its mounting bracket - this was used for legacy
systems as the data bus connector to the test head. This function is now handled by the PCIDIS board, so
this connector should never be used.
Parallel Handler Cabling
Connector - tester side -57-40240 24-pin female Amphenol
Cable connector needed -57-30240 24-pin male Amphenol
Figure 7.11: Amphenol Connector Close-up
7-13
Signal Pin Comment
EOT 1 Output, tester done with a part
BIN1 2 Output, category line
START 10 Input, handler has part ready to test
P5VISO 13 Isolated +5 V supply in the tester
P5VISO 14 Isolated +5 V supply in the tester
GNDISO 15 Isolated tester ground for all signals
GNDISO 16 Isolated tester ground for all signals
HIN2/EOW 21 Input, spare or EOW (End of Wafer signal)
HIN3 22 Input, spare
HIN4 23 Input, spare
RETEST 24 Output, handler to reseat part without binning
Figure 7.12: Handler Parallel Interface Pinout - Amphenol
Note for hardware troubleshooting of this kind of isolated interface: All voltages are referenced to the
floating ground, and pull-ups are sourced by the floating +5V line. If you are using a DMM or oscilloscope
on the signal (bin or start) line only, you will most likely not see the desired signal.
Optional alternatives to this Amphenol connector are available. If installed on your test system,
documentation will be provided by the service engineer. One popular alternative is a DB25 (subminiature D
connector.)
The pinouts for this bracket and cable are included here for reference.
7-14
Figure 7.13: Alternate DB25 Handler Interface Bracket
From To
HCIF X1 Alternate Cable
24-pin header (DB-25 female)
KVD pin KVD Signal DB25 pin DB25 Signal
1 EOT 25 EOT
3 BIN1 1 BIN1
5 BIN2 2 BIN2
7 BIN3 3 BIN3
9 BIN4 4 BIN4
11 BIN5 5 BIN5
7-15
From To
HCIF X1 Alternate Cable
24-pin header (DB-25 female)
KVD pin KVD Signal DB25 pin DB25 Signal
13 BIN6 6 BIN6
15 BIN7 7 BIN7
17 BIN8 8 BIN8
19 START 10 START
21 BIN9 n/c
23 BIN10 n/c
2 +5 iso 11 +5V
4 +5 iso n/c
6 gnd iso 12 DGND
8 gnd iso n/c
10 n/c n/c
12 n/c n/c
14 n/c n/c
16 n/c n/c
18 HIN2/EOW 23 EOW
20 HIN3 n/c
22 HIN4 n/c
24 RETEST n/c
Figure 7.14: Alternate DB25 Handler Interface Signals
PHLIC (Prober Handler Laser Interface Card)
The PHLIC card is the replacement for the obsolete HCIF card. The reason for this is due to the PC
industry discontinuing the ISA bus standard. The HCIF card was based on the ISA system bus. The PHLIC
card has many advanced I/O features that will allow it to control a large variety of handler, probers and
laser trimmers.
7-16
PHLIC to DB25 Adapter Cable
PHLIC Line Standard
DB37 Male Pin DB-25 Female Pin
IDI0, INT0 1 START 10
IDO0 11 EOT 25
IDO1 30 BIN1 1
IDO2 12 BIN2 2
IDO3 31 BIN3 3
IDO4 13 BIN4 4
IDO5 32 BIN5 5
IDO6 14 BIN6 6
IDO7 33 BIN7 7
IDO8 15 BIN8 8
VOUT_ISO 19 +5 11
VIN 10 11
IGND 9, 28, 29 DGND 12
Handler Bin Table Tool

Most handlers have a limited set of SORT categories when compared to software bins in a test program.
Typically, software bins have to be converted to some corresponding SORT bin. The handler Bin Table
tool supports this concept. The KVD Tester has 64 possible bins (0 through 63). The handler DLLs that
KVD supplies to the customer convert the software bin to the corresponding SORT category by use of a
table.
This tool allows the user to create a conversion table, and save it to file. Then, using the Customer Setup
Tool, the Handler Bin Table file (extension HBT) can be selected for use. The following image is of the
Handler Bin Table Tool.
7-17
Figure 7.15: Bin Table Tool Screen
Shown in this image are the 64 possible software bins (BIN columns). Next to each software bin is an entry
field to put the corresponding SORT category. Files created and saved previously by this tool can be
reloaded, changed, and re-saved. The Fill All button, when clicked, will fill all 64 software bins with the
SORT category that is entered in the box below the button. The next image is an example of a Bin Table
for a product.
7-18
Handler Bin Table Example
Figure 7.16: Sample Bin Table
In this example, BIN 0's will be sorted to category 4, BIN 1's to category 1, BIN 2's to category 2, and BIN
3 to 13 sorted to category 3. All remaining bins will be sorted to category 4. On this particular handler, the
limit for the handler was 4 sort categories, thus only 4 are used. The only limit to the number of sort
categories used is based on the handler, with the KVD having a limit of 64. (Except for parallel interface
hardware, however, where the limit is 10 category lines.)
7-19
Custom Data DLLs
Custom Data DLLs are written by KVD or the customer to process, transmit, or manage data (such as
datalogs or summaries) in some flexible or customized fashion. If desired, their use can be managed by
this control screen.
Figure 7.17: Custom Data DLL Screen
CSV Format DLL
DLL Overview
The CSVFormat DLL will generate Comma Separated Value (.CSV) output files. The DLL has a default
directory for output files of C:\KVDTestData\CSV Output and a standard file naming convention of
<filename root><DLL added>.CSV.
The <filename root> portion of the filename is "Lot" by default or the user can pass in a value from the test
program. The <DLL added> portion of the filename is "#_f#p#_<time stamp>", where the first '#' is the lot
number and the <time stamp> is in "mmddhhmm" format. For example, if the user ran a test on Jan. 12 at
1:54p and didn't specify a filename root, the output file generated would reside in the C:\KVDTestData\
CSV Output directory and would be named Lot1_f1p1_01121354.CSV.
The user may pass in a <filename root> by using the following function call in the LotInit() function:
KVD->customdata->SetStringParam(100, <AnsiString>);
Where <AnsiString> is an actual string (i.e. "KVDTest_Run1_Lot"), including the quotes ("") or an
AnsiString variable. For example:
KVD->customdata->SetStringParam(100, "C:\\Lot123 Test Data\\KVDTest_Run1_Lot");
The DLL will then create an output file in the C:\Lot123 Test Data directory with the name:
KVDTest_Run1_Lot1_f1p1_01121354.CSV and place the data within the file.
7-20
Because of specific limitations with the Microsoft® Excel spreadsheet this DLL has special functions to get
around these limitations. Excel is limited in the number of rows and columns that it can display on a
spreadsheet - 256 columns and 65536 rows.
The CSVFormat DLL will create a new 'page' (p#) for every 250 tests done on a device and the DLL will
create a new 'file' (f#) for every 65500 devices tested. The CSVFormat uses the "_f#p#" in the filename to
distinguish each of the output files. For example, if there are 130,000 devices that will have 600 tests
performed on them, the output files generated will be:
Lot1_f1p1_01121354.CSV Tests 1-250 on devices 1-65500
Output File Data Format
The output file is formatted as follows:
KVD Version 1.3 Wafer: 0

Test Program: KVDTestApp.exe
Lot ID Tester:
Operator:
Tester: MINIMAX8
Date: 1/18/2001
9:02
Test #: 1 2 3 4 5 6
Test Name: Wafer X Wafer Y Source #1 Source #2 Source #3 Source #4 Source #5 Source #6
Upper Limit: 1.1 2.1 3.1 4.1 5.1 6.1

Lower Limit: .9 1.9 2.9 3.9 4.9 5.9
Site # Serial # Bin # V V V V V V
0 0 1 0 0 1 2 3 4 5 6
0 1 1 0 0 1 2 3 4 5 6
0 2 1 0 0 1 2 3 4 5 6
0 3 1 0 0 1 2 3 4 5 6
By adding the following code to the LotInit( ) function the user may pass in the Operator ID, the Computer
ID and the Test Program Name:
KVD->customdata->SetStringParam(101,LOG->OperatorID);
KVD->customdata->SetStringParam(102,LOG->ComputerName);
KVD->customdata->SetStringParam(103,ExtractFileName(Application->ExeName));
The CSVFormat DLL automatically fills in the test numbers, test names, upper and lower limits and the
units to the output file. The DLL also includes the site number, device number (Serial #), bin number and
the Wafer X and Y in the first five columns each output file.
7-21
XML Data Output Format Support
Defined per customer request, there is an XML DLL available on the Customer Preferences Tool, Custom
Data DLL tab. When selected, XML output is generated in a defined location, XMLDataPath, which you
can place in an INI file C:\_kvdco_CustFiles\Handlers\MXML.ini.
Normally, package testing uses the LOT concept only, and suppresses any mention of SUBLOTS, which
are a wafer-mode term. However, for speed of sending partial yield data to the XML manager host, there is
a Preferences Tool option on the main tab called Package Sublot Limit. If the No Limit box is
unchecked, and a number of devices chosen, then the test system will emit an XML file every "n" devices
(or a number close by the selected number in the case of multi site testing, where the exact number may
not be achievable).
Two-pass Prober Test Support and Wafer Mapping
New prober control DLLs provided to handle two-pass wafer testing using XML data transfer between
passes.
Multipass Prober Operation With XML Data Output
This section explains the setup and operation of a probe test cell with XML data output. TSK and TEL
probers are supported currently, and you need to select the "Multipass" version of the prober drivers even
if you are only running single-pass testing.
7-22
Figure 7.18: Wafer File Definition Flowchart
7-23
Instructions:
1. Setting up the TEL or TSK prober involves choosing a location for the reference die, multisite control,
and alignment.
There is a tool in beta development that may eliminate most of the work, called WaferFileMaker.exe
located in C:\_kvdco\handlers. Note there is no Start menu shortcut until this is fully tested and
released. Choose the prober type, GPIB address, and other options, then press start on its GUI:
Figure 7.19: Wafer File Maker Screen

2. Edit the .wdf file as necessary. Here is a sample file:
-12
-50
11
5
--------PPPPPP--------
-------PPPPPPPP-------
------PPPPPPPPPP------
-----PPPPPPPPPPPP-----
-----PPPPP--PPPPP-----
----PPPPP--PPPPPP----
----PPPPPP--PPPPPP----
---PPPPPPPPPPPPPPPP---
--PPPPPPPPPPPPPPPPPP--
-PPPPPPPPPPPPPPPPPPPP-
PP--PPPPPP--PPPPPP--PP
PPPPPPPPPPPPPPPPPPPPPP
7-24
----PPPPPPPPPPPPPP----
----PPPPPP--PPPPPP----
------PPPPPPPPPP------
-------PPPPPPPP-------
--------PPPPPP--------
---------PPPP---------
In this file, the "-12" is the minimum column, and the "-50" is the minimum row. The "11" is the maximum
column, and the 5 is the maximum row. The columns are the wafer "X" and the rows are the wafer "Y".
If you are using "Zero based references", you will need to adjust these values to correct for your actual
reference die location. You will also need to edit the wafermap to display any edge, ink or test die on the
wafer.
As an example of how to adjust the locations, let's say your actual reference die is at X-8, Y12. You would
do the following:
Subtract X-8 from X0 to get an offset of X8.
Subtract Y12 from Y0 to get an offset of Y-12.
Original TSK min and max numbers:

-12
-50
11
5
Add the X8 and Y-12 offsets to your TSK-provided min and max numbers to get:
-4
-62
19
-12
Edit the wafermap as needed to match your actual wafer, using the following characters:
"-" is a skip die
"P" is a processable (testable) die
"I" is a ink die
"S" is a skip die
"E" is a edge die
"T" is a test pattern
3. In the TSK process, the .csv file should not have to be edited, and it contains entries like this:
S0,P,X8,Y1
S0,P,X9,Y1
S0,P,X10,Y1
S0,P,X11,Y1
S0,P,X12,Y1
S0,P,X13,Y1
S0,P,X14,Y1
S0,P,X15,Y1
S0,P,X18,Y5
S0,P,X17,Y5
S0,P,X16,Y5
S0,P,X15,Y5
S0,P,X14,Y5
S0,P,X13,Y5
S0,P,X12,Y5
S0,P,X11,Y5
S0,P,X10,Y5
S0,P,X9,Y5
S0,P,X8,Y5
7-25
S0,P,X7,Y5
S0,P,X6,Y5
S0,P,X5,Y5
S0,P,X4,Y9
S0,P,X5,Y9
S0,P,X6,Y9
S0,P,X7,Y9
S0,P,X8,Y9
S0,P,X9,Y9
This is just a list of the actual prober site 0 index locations to be tested in order. For multisite, there will be
more than one die tested per site 0 index. The "S0,P," is not used at this time and is not required. This file
can be edited to change the index order, or can be created on a per wafer basis using a subroutine. It is
important that each of these locations are within the actual wafer area.
4. There are possibly two setup files (.ini) to configure on the KVD side for prober control for each of the
TELP8 or TSK probers, both located in the folder C:\_kvdco_CustFiles\Handlers.
ProberDieOffsets.ini
ProberMultiPasscfg.ini
For instance, the TskProberMultiPassCfg.ini file in C:\_kvdco_CustFiles\ is the file that configures the
XML based multi pass prober driver. Note XML is only required for multipass operations. Since this file is
contained within CustFiles, it remains unchanged during install of new KVD libraries. This file must be
configured correctly for production to run.
Example of the TskProberMultiPassCfg.ini file:

; ------------------------------------------
; WaferNumberType = 0 disable wafer number reading
; WaferNumberType = 1 is for X123, where wafer num is 12
[PARAMETERS]
GpibAddress = 1
WaferNumberType = 1
SotDelayTime = 0e-3
; Offset all X/Y die location to 0,0 references

UseZeroBasedReferences = 1
; Prober lot numbers, or application based lot numbers

UseProberLotNumbers = 1
; Retest flagged bins at end of wafer before unloading

RetestFlaggedBins = 1
; Issue load wafer command at start of lot

LoadWafer = 1
; Unload wafer at end of lot if still on chuck

UnloadWafer = 1
GpibAddress
This is the GPIB address used to communicate with the prober.

WaferNumberType
A value of 0 here disables reading of wafer numbers from the prober. A value of 1 gets wafer numbers.
This is essentially the cassette slot when no OCR is being used. Example: returned wafer number from the
prober is "X123", the KVD wafer number is considered "12".
SotDelayTime
The wait time from when the prober reports "Z-UP" before testing begins. This can be used as a settle time
to allow the probes to make better contact. This will add directly to the test time for every device.
7-26
UseZeroBasedReferences
When set to "1", all x/y die locations reported are offset to a reference die location of 0,0.
UseProberLotNumbers
When set to "1", lot numbers from the prober are used. When set to "0", launcher lot numbers are used.
RetestFlaggedBins
When set to "1", application bins flagged with LOG->SetProberRetestFlag(int bin) will be retested at the
end of wafer.
LoadWafer
When set to "1", a wafer load "L" command is issued at start of lot.
UnloadWafer
When set to "1", a wafer unload "U" command is issued at end of lot if a wafer is still on the prober chuck.
5. For each test program you are going to run, you will need a Setup File as well. These are not located
in C:\_kvdco_CustFiles, but in the location you have previously chosen for all test program Setup
Files. Use the Start->Customer Support->KVD Setup File Tool to create or edit these .ini files.
In the Setup File Tool, there is a new section for Special Fields:
Figure 7.20: Setup File Tool - Special Fields
Each pass will require a different Setup File, containing Special Fields such as the following:
PASS= 1
STEP_NAME= PRE_BAKE
PRODUCT_ID= UC03
In addition, wafer rotation needs to be handled here. Wafer testing can proceed properly between the
prober and the tester without regard to wafer flat orientation, but the Igs database requires the flat location
on the wafer to face "DOWN". This is toward the front of the prober. This can only be in 90 degree
increments and is a clockwise rotation. If on the prober the wafer is being tested with the flat facing
rearward, the rotation in the Special Fields of the setup file would be would be:
Rotate= 180
For a flat facing left, the rotation would be:

Rotate= 90
7-27
You can also force the use of a prober .ini file of your own design by the use of the Special Fields feature.
Just add a line like the following, where the full path to your desired .ini is on the right side of the =
character.
HandlerCfgFile=PathAndFilename
Similarly for Die Offsets, use:

DieOffsets = C:\path\filename.ini
6. Make sure you have an XML setup file C:\_kvdco_CustFiles\Handlers\MXML.ini containing all of
your test codes and desired XML output data path. Example here:
[EDC]
LSR = 3000
PRE_LSR = 3100
SAM_LSR = 3200
PRE_BAKE = 4000
PST_BAKE = 4100
PST_BUMP = 5000
INS_BUMP = 5101
RST_BUMP = 5200
INS_SORT = 6201
QC = 7000
PROBE = 7500
[WIP]
LSR = 4998
PRE_LSR = 7398
SAM_LSR = 1000
PRE_BAKE = 7409
PST_BAKE = 7400
PST_BUMP = 7420
INS_BUMP = 1000
RST_BUMP = 7420
INS_SORT = 1000
QC = 6103
PROBE = 7400
[Misc]
XMLDataPath = c:\_kvdco_CustFiles\
XMLDataPath can be a network location, which is recommended for a multiple-tester installation sharing
wafer files.
7-28
Figure 7.21: Multipass Flowchart
7-29
Engineering Options on the Preferences Tool
A new option is whether or not to auto-launch the RTI when debugging applications. This saves a few
mouse clicks if you are in a debugging session.
Figure 7.22: Preferences Tool - Engineering Options
Updating the Windows Registry
Once any changes have been made to these options, on any page, the Update button must be clicked for
these options to be saved in the Windows Registry. A test program reads these options on startup. If a test
program is running when these options are changed, and saved, they will not be in effect until the next time
the test program is started.
Figure 7.23: Updating the Registry
7-30
Setup File Tool

Executable Device Test Programs (compiled, linked, and with names of the form jobplan.exe) are
released to production use by a system manager using the Setup File Tool.
Figure 7.24: Launch the Setup File Tool from the Start Menu
Figure 7.25: Initial Setup File Tool Screen
7-31
First, select the location in which the Setup Files are to be saved:
Figure 7.26: Setup Files Location
Choose your favorite location. There must be only one folder into which all users are to save their setup
files, as this location is saved in the Windows Registry. If each user chooses a different folder, production
confusion will certainly result.
Then you enter the name you wish to display in the Launcher. This can be an easy-to-understand name for
production operators, and does not need to be identical to the name of the executable job plan.
Then you select which executable job plan (jobplan.exe) you wish to be launched when this Launcher
Name is chosen.
Figure 7.27: Job Plan Name and Executable Entered
7-32
Figure 7.28: Limits File Chosen
If you wish to associate a limits file with the job plan, select it here. The limits file may also be programmed
in the job plan code, in which case this choice would be overridden. One advantage to specifying it here is
that different limits files may be loaded using a single test program executable, saving disk space. For
instance, QA, Final Test, and Burn-in limits may all be run using one executable, with different launcher
strings (names) used to distinguish them for the production operators.
Figure 7.29: Limits File Displayed
Similarly, choose all the items you wish to have associated with this executable test program. Please feel
free to explore it on your own, and read the How To Documents under the Start menu for one named KVD
Test Program Engineering Check List.
An important selection here is that you can associate a particular Customer Preferences File with each test
program in the launcher. This is very useful in case you wish to remove any possibility that the another
development engineer or operator may leave the Customer Preferences Screen in some unwanted state.
The Customer Preferences File selected in this Setup File Tool will override any selections made
elsewhere, as it is read in just before program launch. This is flowcharted in section X.
7-33
Figure 7.30: Saving the Setup File
When all of your selections are complete, you save the setup file by using the File pulldown menu, then
the Save As selection. The extension of these files is always .ini, and you need to choose a distinctive
filename to make sure yours is not confused with others.
Also remember there can only be one central Setup File folder location chosen, for all users to share. This
will normally be defined by your system administrators.
Figure 7.31: Saved Setup File Location
7-34
Test Program Launcher

Once the executable programs have been made available to the operator via the Setup File Tool, and the
Test Head Configuration has been set (if needed) by the Configuration Tool, then the Program Launcher is
the natural place for the operator to begin to test devices.
Figure 7.32: Launching the Launcher
Figure 7.33: KVD Test Program Launcher Screen
7-35
The large blue region is where the display names are presented to the operator. They can choose one by
a mouse-click, or if there are too many to be displayed easily, typing in the box will run a filter against the
list, and only display those names beginning with the typed characters.
Figure 7.34: Entering Operator and Lot Data
An operator ID needs to be entered here, and it is saved in a LOG object variable and printed with all
summary files and datalogs. The LOT number does not have to be all numeric, but can contain alpha
characters as well. Punctuation is not recommended.
Error Checking for Lot Names
Previously, invalid characters could be entered for lot names, which would cause filename errors after the
lot was ended and summary data should have been saved. This could cause loss of report data and force
retesting. Now, the code substitutes an 'X' for the following invalid characters / * & # ! - ; :
Figure 7.35: Double-click a program name to launch it
Finally, selecting a program name, and pressing the Launch Test Program button will execute the KVD
production GUI.
Preferences Flowchart
• When the production process launches, the KVD software accepts preferences from the Windows
Registry first. This is where the Customer Preferences Tool stores its selections.
• Next, the .ini file for the test program that has been launched is consulted for more preferences, such
as the limits file to be used. Remember, these are .ini files created and saved using the Setup File
Tool.
• The Setup Files are stored in a central location, so we need a way for their data to be communicated to
the executable test program. We use a generic file called KVDStartup.ini to accomplish this. Any
items named in the Setup File are copied to KVDStartup.ini, and this file is placed into the same folder
as the executable test program.
• Variables from the Launcher such as the Operator ID and Lot Number are copied into a file called
KVDLauncher.ini, and also placed into the test program folder.
• Data from both of these files is read into the test program before the SystemInit function in
UserClass.cpp.
• You can interrogate any of these variables in the LOG object to see what was read in.
7-36
• You can at that time change any of them if you wish, since the test program always has the last
chance. You, as the test engineer, can reload limits files, change lot number, index the serial number
in unusual ways if you wish, reboot the test head, customize the datalogging choices, and override
things such as the final destination folder for summary files.
Launch Flow Overview
Figure 7.36: Program Launch Flowchart
7-37
Engineering Launcher
As a response to customer request, a hidden Engineering Launcher is available to assist in debugging pre-
released test programs using various setup (.ini) files. These setup files can be located differently from the
standard location which is saved in each tester's Windows registry, for test engineering flexibility. The
Engineering Launcher is located in C:\_kvdco\Launcher and is called EngrLauncher.exe.
It is not linked to any Start menu unless the customer decides this is useful, but KVD recommends it
should be hidden from production operators for confusion reduction.
Unlike the standard KVD Launcher, this launcher does not persist after the test program execution
completes, so it disappears automatically. When run, it brings up a query box to ask where the desired
setup file is located.
Figure 7.37: Engineering Launcher
Datalogs
Datalogs are the detailed test results display for a tested device. You can select to datalog all tests, or just
failed tests, to a file or to the printer. When saved on the disk, the files have the extension .log, and they
are stored in a folder you have previously designated in the Setup File Tool. The default folder, if you do
nothing, is C:\KVDTestData.
Example:
KVD TEST DATA LOG
Thu Sep 21 09:45:08 2000
Job Name: IMAGER EVALUATION

Program ID: IMAGER DEVICE: Sep 21 2000
Operator ID: Aurel
Tester: ACE*
Fixture ID: IMG LVDS FC #2
Fixture ID 2: 48-Pin Yamaichi Socket
Lot ID: check 20000425
Start Time: Thu Sep 21 09:44:54 2000
Elapsed Sec: 14
Comment: LVDS Test
Site: 0 Device Serial Number: 1 Bin: 1
S0 5 STD LUX ILLUMINATIO 30.502 Lux min: 29.000 max: 31.000

S0 250 CONT : 33: USBCLK -0.438 V min: -1.200 max: -0.200
S0 253 CONT : 36: SCL -0.390 V min: -1.200 max: -0.200
S0 254 CONT : 37: SDA -0.330 V min: -1.200 max: -0.200
S0 255 CONT : 38: SLEEP -0.426 V min: -1.200 max: -0.200
S0 257 CONT : 35: VSYNC -0.438 V min: -1.200 max: -0.200
S0 258 CONT : 34: HSYNC -0.376 V min: -1.200 max: -0.200
7-38
S0 259 CONT : 26: PXDO -0.418 V min: -1.200 max: -0.200

S0 260 CONT : 25: PXD1 -0.413 V min: -1.200 max: -0.200
S0 270 CONT : 32: PXCLK -0.434 V min: -1.200 max: -0.200
S0 272 CONT : 9: VDDAY -0.507 V min: -1.000 max: 1.000
S0 900 IN_LEAK LO : USBCL 0.047 uA min: -1.000 max: 1.000
S0 901 IN_LEAK HI : USBCL 0.096 uA min: -1.000 max: 1.000
S0 902 IN_LEAK LO : SLEEP -0.003 uA min: -1.000 max: 1.000
S0 903 IN_LEAK HI : SLEEP 0.089 uA min: -1.000 max: 1.000
S0 904 IN_LEAK LO : SCL -243.703 uA min: -400.000 max: 400.000
S0 905 IN_LEAK HI : SCL 0.075 uA min: -1.000 max: 1.000
S0 50 IVDDD SLEEP 1.094 mA min: 0.000 max: 2.000
S0 52 IVDDDR SLEEP 0.006 mA min: 0.000 max: 2.000
S0 55 IVDDD 28.332 mA min: 10.000 max: 30.000
S0 56 IVDDAY 0.612 mA min: 0.500 max: 1.000
S0 57 IVDDDR 8.636 mA min: 0.750 max: 10.000
S0 59 IVDDA 26.372 mA min: 15.000 max: 30.000
Recently, per customer request, we added a field to the standard report header that displays the name
(string) that was chosen in the Launcher to run the test program.
KVD LOT TEST SUMMARY REPORT
2/4/2003 5:24:08 PM
Program ID : C:\Test Programs\Billtest\KVDTestApp.exe (02/04/03 17:22:30)

Operator ID : 44
Tester : BCLAPXP
Fixture :
Lot ID : 44
Comment :
LimitsFile : C:\Test Programs\Billtest\Generic.lim (11/21/00 09:01:22)
BinFile : Generic.bin (11/21/00 09:01:22)
ParametersFile :
LibraryVersion : Version 05_02_ENGR_229
LaunchSelection: DeviceTypeHere
Lot Test Time : 17:23:56
Test Time Profiling
The KVD Library now has the capability to profile each test's test time. Simply turn on Engineering Mode in
the customer preferences tool, and enable datalogging of all tests. You will then see two new columns on
the datalog.
The CTT value is the Cumulative Test Time from the beginning of the device and the DTT is the Differential
Test Time from test to test.
You can also read the system's internal timer into a variable by the following function:
variable1 = SYS->read_counter();
Do that at the beginning and end of code you're trying to time, get the difference, assign the difference to
SITE->lastresult.value and then you can datalog it.
7-39
Summaries
Bin result and test summaries are reports of the number of devices assigned to each bin, in a sublot or lot
of devices, along with the numbers of attempts made on each device for each test in the test list. A ratio of
failed attempts is also reported, to help in yield analysis and test list profiling. For instance, a test which
always passes every device may be a candidate for removal from the test list, since it may not contribute to
fault coverage. The file extension is .sum if the summary is saved to disk.
In the production environment, the operator can take a partial summary in case of curiosity about the yield
of a lot. The final lot or sublot summary is the one that is saved to the disk if specified in the Preferences
Tool.
KVD TEST SUMMARY REPORT
Sat Dec 30 07:55:19 2000
Job Name: DSPIO

Program ID: DSPIO: Oct 16 2000
Operator ID: veets
Tester: ACE*
Fixture ID: PROTOFC
Fixture ID 2:
Lot ID: CORR10
Start Time: Fri Dec 29 13:39:05 2000
Elapsed Sec: 65774
Comment: TESTING TMU
BINNING SUMMARY
Bin No. Bin Name Devices Percent

Bin 0, Alarms and other Weirdness 5 0.50
Bin 1, Device Passed 994 99.50
Total Devices: 999 100.00% Good Device Yield: 994 99.50%
KVD TEST FAILURE REPORT

Sat Dec 30 07:55:19 2000
Job Name: DSPIO

Tester: ACE*
Lot ID: CORR10
Test Name Fails Tries Fail/Try Fails by Site
3711 DDTMU 22->7 5 999 0.005 5 0
Viewing summary data from the production GUI (for example looking at a partial lot summary) is now
accomplished in a non-editable window instead of in Wordpad. This removes the operator's ability to
modify data before it is sent to the printer.
Summary Counts Match Physical Device Counts
Depending on exactly how the handler or prober is halted or paused, the KVD summary reports could have
been low by one or more (depending on the number of active sites) devices. Now, if the operator requests
a partial summary report, the request is queued until the current device test sequence is finished, that
device (or devices, for multisite) is included in the report, which will pop up when the handler bins the
device(s).
7-40
Histograms
Histograms are a graphical way of showing the statistical results of a series of tests. The test limits are
shown as vertical lines, and the device test results are represented by asterisks. At a glance, the test
engineer can see the distribution of device results to see if there is a risk that limits are about to be
exceeded, or the distribution is skewed by process variation. Histograms use the extension .his when
saved to disk.
Note that the mean of the result data is intended to be shown by a vertical column of dots, but this is
sometimes skewed due to a bug. The text report of the mean is correct, however.
Note also that in current software, out of range measurements cannot be excluded from the analyzed data,
which could also cause skew.
KVD TEST HISTOGRAM REPORT
1/21/00 4:29:02 PM
Job Name : TEST PROGRAM

Program ID : C:\WINTESTER\program\program.exe
Operator ID : BS
Tester : ACE*
Fixture : ATODFC1
Lot ID : HISTOGRAM TEST
Comment : TESTED BY VEETS
Histogram for Test: 1 CONT + : DOUT : 15 Devices Tested: 52
Limits: 0.400 V to 1.000 V

Range: 0.654 V to 0.655 V
Mean: 0.655 V Std. Dev: 0.000 V Cpk: 512.088
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
| * . |
========================================
0.400 V 1.000 V
Histogram for Test: 1712 ADC HARM : 2.7V Devices Tested: 52
Limits: -100.000 dB to -80.000 dB

Range: -91.889 dB to -88.184 dB
Mean: -89.843 dB Std. Dev: 0.956 dB Cpk: 3.430
| ** |
| ** |
| ** |
| ** |
| ** |
| ** |
| ** |
| *** |
7-41
| *** |
| *** |
| *** |
| **** |
| **** |
| **** |
| **** |
| ***** |
| ***** |
| ****** |
| ****** |
| ****** |
| ****** |
| ****** |
| ****** |
| ******* |
| ******* |
========================================
-100.000 dB -80.000 dB
Test Data Analysis

TDA files are the tabular version of the histogram statistical data, saved with the extension .tda.
KVD TEST HISTOGRAM REPORT
1/21/00 4:29:02 PM
Job Name : TEST PROGRAM

Program ID : C:\WINTESTER\program\program.exe
Operator ID : BS
Tester : ACE*
Fixture : ATODFC1
Lot ID : HISTOGRAM TEST
Comment : TESTED BY VEETS
Total Devices = 52
Test# Name Units Lower Spec Mean-3S Minimum Mean Maximum Mean+3S Upper Spec Sigma CPK
---------------------------------------------------------------------------------------------------------
1 CONT + : DOUT : V 0.400 0.654 0.654 0.655 0.655 0.655 1.000 0.000 512.088
2 CONT + : SSTRB : V 0.400 0.653 0.654 0.654 0.654 0.654 1.000 0.000 524.543
103 CONT - : DOUT : V -1.000 -0.524 -0.525 -0.522 -0.522 -0.521 -0.200 0.001 196.435
Production Operator's Interface

After all the setups and selections have been made, and the job plan is launched and ready to run, this is
where one ends up. The default displayed page is the one you chose in the Customer Preferences Tool
earlier. Normally this is the Production View, but you can choose otherwise.
7-42
Figure 7.38: Main Production Screen
Notice the three tabs that are below the Elapsed Time, and PASS / FAIL counters. These three tabs are
labeled "Production View", "Engineering View", and "Test Statistics View". The image above is displaying
the Production View. There is a Wafer Map view which is separately documented in an on-line How To
Document.
You can click on any of the three tabs at any time during testing (or when paused) and the program will
switch to that view. Since testing devices has a higher priority for CPU cycles, this switching could be
deferred until the end of the current device. Don't be alarmed at a possible delay. One way to increase the
chance that your mouse click will be noticed by the Windows scheduler is to sprinkle some or many of the
following statements in your program between tests:
Application->ProcessMessages();
The three views are briefly explained below.
Production View
The production view, when set up in a normal test program, will show horizontal bar graphs for each of the
BINS that the test program has defined. The graph above will automatically re-scale itself as the bin
counters fill up. In the image above, the area to the left of the graph shows the bin labels that the test
engineer has assigned to the bins in the program. To the right of the graph is a vertical list of two columns.
This is a run time counter of each test that fails, and the number of devices that have failed that particular
test. This is updated as the device is testing, but not resorted to put high counts at the top of the list.
7-43
Engineering View
The Engineering View is nothing more than a datalog screen view that is similar to all tester's datalog
environment. You can switch to this view whenever running the test program, and see all tests or failing
tests only, depending on the preference you have previously chosen in the Customer Preferences Tool. If
you have chosen datalog to screen - OFF, then this page will have no datalog results, but a simple display
of device serial numbers and test time only.
Depending on the choice made in the Preferences Tool, the datalogs will be standard, with only test
results, or an engineering mode, with test time profiling time stamps included.
Note that the video screen refresh can be quite slow on this screen - on the order of dozens of milliseconds
- which could cost throughput. This should never be the default screen for viewing by operators. The scroll
window is also not very large, because of the amount of memory it could consume. Datalogs are normally
flushed to the hard drive after every device anyway, for later viewing.
Figure 7.39: Engineering View
7-44
Test Statistics View
Figure 7.40: Test Statistics View
This view is updated at the completion of each device tested. This view will show all the tests in the
program, along with their associated upper and lower limits, the last result for each test, and the mean and
standard deviation for each test. When a test fails the limits associated with it, that line of the test statistics
view will be highlighted in red. You can scroll this view down to see other tests that might be hidden if many
tests are in the program.
Wafer Map View
If in Wafer test flow (a Preference), you will see a wafer map display.
Custom Forms
Some new and very useful features have been added to the Main KVD Production Display. Some
engineers in the past have developed their own data entry or setup forms that the engineer uses at the
beginning of program execution, or sometimes during program execution. The limitation of these forms
was that the engineer had to supply some way of the user deciding when the form was visible (or shown).
Now, that same form (with no changes required) can be added as a tabbed sheet on the KVD Main Display
with the call of one simple command, which takes a pointer to the form, and the text to use as the caption
of the tab sheet.
Another tab sheet related feature that was added was the Test Tracking Form, which is accessed from the
KVD Main Display's "Quick Tools" menu. This new form also embeds itself onto the KVD Main Display as
a new tab sheet, and graphs the test result of ONE test with respect to each device tested. That is, the
result of a single test can be graphically displayed as each device is tested, for analyzing drift, jitter, or
process variation. The user can add multiple new Test Tracking forms, and can remove them at will.
7-45
Test Time Calculations, Displays, and Speed-Up Techniques
The test time that used to be datalogged, and displayed on the Production Main GUI page, was found to
be not fully representative of the test time needed to predict throughput on the test floor. Specifically, the
display was omitting the time spent in the functions DeviceInit and DeviceFinish, and only registering
time spent in Tseq.
For a better understanding of the number of devices tested per hour, we have enhanced the data
gathering to include these two functions in device test time, and also added two new fields in the
production GUI to show tester/video refresh overhead time and handler/prober index time. The total
number of devices tested per hour is always a function of the yield mix and variable laser trim activity,
since very few devices go through the exact same test sequence, and this data should always be
calculated using full wafer or lot test time reports. This is especially critical if the lot test time includes wafer
robotic handler or vision system auto-align activity.
The production GUI changes are shown here:
Figure 7.41: Changes to Production View

• Test time, as noted, now includes all three major per-device functions: DeviceInit, Tseq, and
DeviceFinish.
• Overhead time includes time the test system needs to calculate result statistics, yield information, and
refresh the video frame buffers to redraw the GUI. See explanation for more details on the components
that comprise this time.
• Handler/prober index time is the time consumed by the DLL-controlled handler driver (pulse widths
and set-up times) plus the physical time to index the next device into position.
Speed-up Techniques
There are new means to reduce the overhead associated with the production GUI. As always, achieving
the optimum test time per device involves using the minimum reasonable relay delays, optimum trim
strategies, and avoiding unnecessary hardware resets and initializations. These are under your control as
a test engineer.
7-46
Once a test program is released to production, we have provided new preferences options to minimize the
time spent redrawing the video screen and calculating test statistics.
Figure 7.42: Speed-Up Techniques
You can choose to defer updating the GUI until every Nth device, saving video refresh time. You can hold
off updating any of the three major GUI tab sheets, saving calculation time. You can add or suppress
throughput information being added to the summary report.
We have characterized the approximate system overhead times as follows:
The production tab (bar chart) window is the slowest for updating. Depending on your chosen monitor
resolution (1024X768 or higher) and number of bins, this could be 130-200mS.
Engineering view (datalogs) with datalogging to screen turned off is quite quick, around 25mS overhead.
Suppressing the GUI updates on every device can bring the per-device overhead to less than 20mS.
Test Time Report Display
If you choose to add throughput times to the reports (currently active on summary, histogram, and TDA
reports, not the datalog report), a section is added just after the header with the following information:
Summary of throughput times
Name Cumulative Average

-------------------------------------------------------
Test Time : 13.870 0.771
Overhead Time : 1.950 0.108
Handler Wait for SOT : 0.000 0.000
Handler Wait for EOT : 0.000 0.000
IDLE time : 0.000 0.000
This is also under the test engineer's control, through the LOG object:
LOG->AddToReport=1.
7-47
Running Yield Display
To improve the ability of test floor operators and managers to spot declining yields and take swift corrective
action, we have implemented a beta version of a programmable yield alarm.
The trend display can be shown in place of the former Production View (bin bar chart), with programmable
numbers of bins being monitored, with distinctive colors for the monitored bins. A scrolling display of the
last 100 devices is shown, and the graphical representation lends itself to spotting trends quickly. Future
enhancements will include site-based tracking, to assist in spotting trends such as continuity yield issues
per site.
Figure 7.43: Bin Trend Chart
Which bins are tracked is configurable with the Options tool. When you click the Options button, it
demands a password in this box:
Figure 7.44: Password Required
The default password is administrator, but that can be changed by editing the file
C:\\_kvdco_CustFiles\\supervisor.ini.
If this file does not exist, create it, with the only content being your desired new password. This file will
persist between new software installations.
When the supervisor password is correctly entered, the following screen will launch, allowing specific
control over whether a bin is plotted on the Bin Trend Chart, the alarm percentage that trips the message,
the exact alarm message, whether or not a supervisor is required to clear the alarm or not, and the desired
color of the trend line. When you click the "save" button, this data is saved to
C:\_kvdco_CustFiles\BinTrendFiles\tempmem.btf until changed again.
7-48
Real-Time Yield Alarms
Each bin can have an optional trigger value (in percent), which will cause an alarm to go off if a pass bin
falls BELOW the trigger value, or if a fail bin goes ABOVE the trigger value.
The exact message that appears when the alarm occurs is programmable, so the alarm can instruct the
operator in a variety of responses, from checking the hardware, cleaning probe tips, or calling
maintenance or test engineering.
Figure 7.45: Bin Setup Tool
Because the functionality of this is useful to save as part of a test program, so the test engineer can
program the desired initial conditions for the Bin Yield Display, the concept of the Bin Setup Tool has been
extended.
Bin files used to be stored with the extension .bin in the test program directory. Extended bin files, with the
yield alarm features, can be stored with the extension .btf, and edited with the new tool. The new Bin Setup
Tool is launched the same way as the previous version, from the Start->Programming Tools. But you
have the new features of being able to import legacy .bin files, and save the new files as .btf versions.
Note: If you use this feature, you will have to change any mention of LOG->load_bin_data in your test
program to LOG-> load_bin_setup_file and refer to the new .btf file as the argument.
7-49
Yield Alarms and Running Yield Display Tabsheet
If plotted, the selected bins will appear in a display like this, with a color legend along the left edge:
Figure 7.46: Bin Trend Chart With Legend
This is an example of an alarm window.
Figure 7.47: Alarm Window
Site-based Yield Delta Alarms
To assist in quickly detecting site-to-site differences, which may indicate contact or probe problems, the
BTF file can also be configured to trigger an alarm if the lowest to highest yield for any bin exceeds some
threshold delta. Since this is a multisite-related display, it appears only when running a multisite program,
on the "Site Data" production GUI tab, on a sub-tab called "Bins per Site".
7-50
Figure 7.48: Site Data - Bins Per Site
Last "N" Yield per Site
To assist in determining if a site-based repair (contact cleaning, overtravel adjustment, etc.) is immediately
effective, the Site Data GUI was enhanced to add two columns on the Statistics Per Site tab. One for the
yield per site for the last "N" devices, and the other a display of what the "N" is defined to be. The default is
100 devices, but you can change it in your test program to be a different number per site if you wish, with
the command:
KVD->siteyield_lastn[site]=#;
// # is the rolling yield per site window.
Figure 7.49: Site Data - Statistics Per Site
Cleared Alarms
Cleared alarms are now added to the utilization log for an audit trail. First added in Release 5.02 R6, here
are some details about this log:
These logs are kept in the folder C:\_kvdco_CustFiles\UtilizationLog. The filename includes the Tester
ID, month, and year, and the data is saved in CSV (comma separated value) format, for ease in importing
the data to Excel or another spreadsheet program.
C:\Test Programs\DeviceBinner\DeviceBinner.exe 10/14/2003 13:11.34 STARTUP

C:\Test Programs\DeviceBinner\DeviceBinner.exe 10/14/2003 13:11.51 END LOT LOT=NOLOTNUM PASS=77 FAIL=11
C:\Test Programs\DeviceBinner\DeviceBinner.exe 10/14/2003 13:11.53 SHUTDOWN
C:\Test Programs\DeviceBinner\DeviceBinner.exe 10/14/2003 13:13.41 STARTUP
C:\Test Programs\DeviceBinner\DeviceBinner.exe 10/14/2003 13:13.53 END LOT LOT=222 PASS=77 FAIL=11
C:\Test Programs\DeviceBinner\DeviceBinner.exe 10/14/2003 13:13.54 SHUTDOWN
7-51
Yield alarm data are formatted as these examples:

C:\__debug\VerifyBinTrend\VerifyBinTrend.exe 4/13/2005 15:08.46 Bin Trend Alarm <Bin 2 Threshold
Alarm> ACTION=CONTINUE OperID=<1234> StartAlarm=4/13/2005 3:08:42 PM ClearAlarm=4/13/2005 3:08:46
PM Supervisor Password Not Reqrd
C:\__debug\VerifyBinTrend\VerifyBinTrend.exe 4/13/2005 15:09.07 Bin Trend Alarm <Bin 3 Threshold

Alarm> ACTION=EXITJOB OperID=<1234> StartAlarm=4/13/2005 3:08:48 PM ClearAlarm=4/13/2005 3:09:01
PM Supervisor Password Required
Operator ID
Clearing an alarm will always require the operator to enter an ID string (a minimum of 4 up to 10 characters
long). If the "Supervisor Clear" requirement is also set, the Supervisor Password box on the GUI is active.
Figure 7.50: Clearing an Alarm
If the Supervisor Clear requirement is not set, that box is grayed out.
Figure 7.51: Clearing an Alarm - No Supervisor Required
Exiting the job using the Yield Alarm GUI is a supervisor function, and proceeds through the entire End Lot
process to ensure summaries are retained and not lost.
7-52
Alarm Holdoff And Retriggering Algorithms
Pending.
Test Statistics Page Enhancements
Changes to the GUI support new choices.
Figure 7.52: Changes to Test Statistics
Limited view - the user can now selected test to view and test to hide on the test statistics view. To do
this, click on the View Options button located on the Test Statistics View page.
Figure 7.53: Test Statistics View
You are then presented with a page of check boxes for each test (based on a loaded limits file) that can be
viewed, or hidden.
Note that the tests that are selected are the tests to HIDE. After selecting the tests to hide, click on OK.
After the current DUT is finished testing, and as the next device starts testing, the view will change.
7-53
Figure 7.54: Test Statistics - Hidden Tests Options
Highlighted View - the highlighted view allows the user to select tests that will be highlighted with a blue
background, and white font. This makes it easier to spot specific tests of interest. After clicking on the
Highlight Options button, you are presented with a screen similar to the hidden view options form.
The test you select (checked) are then highlighted the next time a DUT starts testing.
Figure 7.55: Engineering View
Obtaining Datalogs, Summaries, Histograms, and TDA Files
At any time during testing, the operator can click on the Partial Summary button and obtain any of these
data files. You can save these partial files, or print them out.
7-54
Running the Test Program
You can click on the Start button and the test program should start up. You may be prompted to whether
you want to Boot the test head or not, depending on the preset Customer Preferences. If you haven't yet
booted the tester, it will automatically force a boot. Once the boot is completed (assuming you selected
YES if given a choice), the test program will begin. If you are still using a BLANK generic test program, you
should get BIN 1 and passing 100%. To STOP the test program, click on the End Lot or the Pause button.
You'll be asked to confirm this before the lot is ended, if the preferences were so set. To exit the test
program, click on the Exit button. That's it, you're done.
Other Custom Tab Sheets - Quick Tool Pull-down Menu
Voltmeter Memory Plots

In previous library versions, only one test could have its measvm results viewed in a plot. This plot was
also a modal plot, that is, it halted the application and waited for the user to close the form before the test
program continued. Now in rev503, the user can select as many tests as they desire to watch the measvm
results. Further, the plots are refreshed each time through a test loop, and the test program does not stop
and wait for the user to close any forms. That is because the measvm plots that are being viewed are part
of the KVD Main GUI. To select tests to view the measvm results, go to the Quick Tools menu item, then
select the MEASVM Plot menu item. It brings up a dialog similar to the histogram dialog.
Figure 7.56: Select Tests to Plot MEASVM
7-55
As expected, select the tests you want to view by checking the appropriate box, or cancel viewing a test by
unchecking the appropriate box. Click on OK, and you'll see a plot like the example below.
Figure 7.57: MEASVM Results
The plot can be saved or printed. You can also view the individual measurement values by turning on the
Show Value Labels options. The plot will change each time the test is executed.
Graphical Histograms
We've added the capability to watch histograms of any test number in real time. The graphical histograms
are easy to use. Under the Quick Tools menu item, select the Histogram By Test Number menu item.
This brings up the following dialog screen.
Figure 7.58: Histogram Plot Selection
7-56
Select the tests that you want to view histograms on. As data is collected, if the test is selected (checked)
then the histogram plot will be updated in real time. You can view as many histograms as you want. To
remove a histogram plot, just bring up this dialog again, and uncheck that test. Here is an example:
Figure 7.59: Test Results
The Options button brings up a dialog box that allows you to change the upper and lower boundaries (for
viewing) and the number of bins (slots) for the histogram plot. You can also print a histogram to the current
default windows printer by clicking on the Print button. In the case of really bad low data, or really bad high
data (data which falls far outside the predefined test limits), the plot will record these in the upper or lower
ERROR slots.
Conditional Breakpoints
Runtime Breakpoint Events
A test program can be halted, and the operator/engineer notified, if the test program encounters any of the
three following events:
• On Test Number
This event is launched whenever the test number selected becomes the current test number.
Figure 7.60: Break on Test Number
7-57
The event will trigger the following screen to appear.
Figure 7.61: Runtime Breakpoint Event

At this point, the test program is halted, and the engineer can determine whatever course of action he
so chooses.
• On Fail Any Test
Occurs if ANY test fails. As soon as the test is completed, and the determination has been made that
the result is outside the test limits, this event is triggered. The page seen above will be displayed.
• On Fail Test Number
This is a combination of the previous two events. When a test fails, and the test number failing is the
selected test number, the above screen will be shown.
Figure 7.62: Break on Failing Test Number
7-58
Figure 7.63: Runtime Breakpoint Event
Track Result by Test Number

This is a previously undocumented improvement to the production GUI, also under the Quick Tools.
Figure 7.64: Track Result by Test Number
7-59
7-60
MPDCMOD (Octal DUT Source)
MPDCMOD Pictorial
Figure 8.1: MPDCMOD
The MPDC Module (MPDCMOD) contains eight ground referenced DC Sources and one floating user
voltmeter. Each DC source is an independently programmable, four quadrant, Kelvin, DC voltage and
current source which can be connected to the device directly or through relay networks on the Father
Card. Sources are numbered beginning at 0 (zero) not 1 (one).
Figure 8.2: MPDCMOD DC Sources
The sources offer four voltage ranges +/- 40V, +/- 20V, +/- 10V and +/- 5V, and five current ranges:
200mA, 20mA, 2mA, 20uA, and 200nA. The force and sense line of each source connect to the Father
Card through a Hypertronics connector. Each DUT Source has a voltmeter/ammeter that is dedicated to
making voltage and current measurements. This meter is a 16 bit sampling converter (4K sample memory)
with variable clocking. Because this voltmeter is designed to measure the state of each of the DC sources,
it has no connections to the Father Card. This is commonly known as the SVM, or Source VM.
8-1
There is also a precision differential voltmeter located on the MPDCMOD. This voltmeter is the commonly
referred to as a UVM, for User Voltmeter. This voltmeter has its inputs routed directly to the Fathercard
through the Hypertronics connector and can be connected to the device directly or through relay networks
on the Father Card, or a mux on the instrument itself to internal points. The floating voltmeter features a 16
bit A/D, variable sampling rate, differential or single-ended input stage, programmable DC offset and
multiple gain stages.
Figure 8.3: MPDCMOD Block Diagram With Software Commands
Physical Description
The MPDC Module is composed of a D/A converter which feeds a high power operational amplifier. This
power op amp has two possible feedback loops. The first feedback path is used when the source is forcing
voltage and connects the op-amp's output to its own negative input. This feedback path senses the output
voltage and holds it constant. The output of the power amplifier is referred to as the force line and the
voltage feedback path is called the sense (or Kelvin) line. The force and sense lines can be connected
directly at the output connector by a relay or can be wired independently and tied together close to the
device to eliminate the effects of path resistance.
The second op amp feedback path is used to force (source or sink) current. This path uses a differential
amplifier to sense the voltage drop across a selectable resistor in series with the power op amp output.
Due to the nature of this sense connection, the feedback path does not require any type of remote
connection to ensure accuracy. Current ranges on the MPDCMOD are defined by a resistor network on the
output of the power op amp.
8-2
DC Instruments
Voltage clamps are independently user-programmable and current limiting is also user programmable.
Control logic, including address decoding and serial data return bus generation, are contained within a
single on-board FPGA. The MPDC Module FPGA must be booted with a firmware data file each time the
test head is turned on, and this is normally handled automatically with no user intervention required.
MPDCMOD Objects
The MPDS class defines MPDCMOD source objects as one of three types:
• TMPDS - used for individual control
• TGroupMPDS - used to control a group of sources with one defined name
• TSiteMPDS - used to control a set of sources in a multisite test program
And the User Voltmeters are one of two types:

• TMPUVM
• TSiteMPUVM
You are free to declare your own name for a resource, as many test engineers do in a file named
connections.cpp, such as declaring:
TMPDS *VREF;
void UserConnections() {
VREF = MPDS[4];
VREF->setname("VREF");
}
The setname command is designed to allow the RTI to display your designated name instead of the
system resource name for ease of debugging.
Force Voltage
Once the Kelvin connection has been selected, the source can be used to force a voltage up to it
maximum output specification, subject to the programmed voltage clamp.
Note: Amplifier limitations reduce the maximum forced voltage to somewhat less than the DC supplies in
your particular configuration. In the typical configuration, with +40V, -20V DC supplies, you will
obtain a maximum voltage capability of +36V to -16V.
Example:
MPDS[1]->setv(1.20);
The argument [1] is the DUT Source within the test head (1 of 32, but they are numbered [0] through [31]).
Force Current
The MPDCMOD may be set to force any current up to 190mA, subject to the programmed current clamp.
Always make sure the clamps are programmed to be "out of the way" of the forced value, which means
slightly higher, outside the guardband of the specifications.
Example:
MPDS[1]->seti(0.100);
8-3
Voltage Ranges
Range Index Maximum Variable Names
0 +/- 40V mpvr_40v
1 +/- 20V mpvr_20v
2 +/- 10V mpvr_10v
3 +/-5V mpvr_5v
You can set the voltage range explicitly if you wish using the range index, or its alternate variable name, in
the setvr and vrange commands. Setvr sets both the value and the range in one command, while vrange
affects only the desired range. These are examples of valid statements only; please also see “MPDCMOD
and HPDCMOD Ranging Lockout” on page 8-9 for an important discussion of the order in which you are
required to perform certain ranging functions.
Example:
MPDS[1]->setvr(1.20,3);
MPDS[1]->setvr(1.20,mpvr_5v);
MPDS[1]->vrange(3);
MPDS[1]->vrange(mpvr_5v);
Current Ranges
The current range setting is handled automatically when forcing current using the seti command, however,
when using setv to force a voltage it may be desirable to change the current range. Note there are two
gaps in the ranging, at 200uA and 2uA, due to space limitation on the instrument.
Range Index MPDCMOD Variable Names
0 200mA mpir_200ma
1 20mA mpir_20ma
2 2mA mpir_2ma
3 20uA mpir_20ua
4 200nA mpir_200na
Example:
MPDS[1]->setir(0.018,1);
MPDS[1]->setir(0.018,mpir_20ma);
MPDS[1]->irange(1);
MPDS[1]->irange(mpir_20ma);
Warning! The test engineer MUST take extreme care to avoid hot-switching any range relays. For
enhanced execution speed, KVD software drivers do not enforce supply disabling or
discharging, or include any built-in delays, trusting the test engineer to know when they are
safe from the risk of hot-switching. Enlightened use of delays is REQUIRED to avoid the
possibility of instrument or DUT damage.
8-4
DC Instruments
Driver Improvements for Increased Reliability Since Release 5.02
KVD instrument drivers now include make-before-break current range changing. Using the previous break-
before-make algorithm, the driver was slightly faster, but at the risk of opening the current feedback loop
during a range change event. This could cause an internal transient if the range was being changed while
hot. Since KVD cannot control whether or not hot switching is occurring, this transient could be a cause of
reduced range resistor and relay reliability.
By closing the relay for the new range 200uS before the previous range relay is opened, the open-loop
transients should be eliminated.
Since this change could affect the dynamics of a currently running test program, we offer a backwards
compatibility mode. The default state of this boolean is to force the new behavior of the driver, to
encourage test engineers to requalify their program if necessary, and examine their range changes for hot-
switching events.
To temporarily force the previous driver behavior, define the following variable as extern bool:
IRange502 = true;
Voltage and Current Clamps
For each source, the voltage and current clamps are programmable. Current clamps are symmetrical (one
programmed value is used for both positive and negative current clamps) while the voltage clamps require
the user to program two values, a lower and an upper clamp.
Example:
MPDS[1]->vclamp(-4.0,12.0);
MPDS[1]->iclamp(0.50);
Note: Clamps in the KVD sources are not used for programming precision levels of current or voltage.
They are meant for protecting against uncontrolled transients (current spikes into a short or
voltage spikes into an open). Note also the accuracy specs of the clamps, which makes the lowest
reasonable current clamp to be 20mA. Any time your clamps are set too closely (within the spec
guardband) to the programmed seti or setv values, you run the risk of having the clamps activate
and prevent your level from being achieved.
Kelvin Connections
Each source has separate Force and Sense relays, and a separate relay to short them out locally in case
the user does not wish to being both lines separately to the DUT. They can be configured in flexible ways,
depending on your design for the Father Card and DUT boards.
Example:
MPDS[1]->on(); //closes both force and sense
MPDS[1]->off(); //opens both force and sense
MPDS[1]->off_force(); //opens force ONLY
MPDS[1]->off_sense(); //OPENS sense only
MPDS[1]->on_force(); //CLOSES force ONLY
MPDS[1]->on_sense(); //closes sense only
MPDS[1]->local_kelvin(); //shorts F & S locally
MPDS[1]->remote_kelvin(); //opens F & S short
8-5
Warning! The on and off commands are not electronic enables as on some other testers. They close
and open relays on a source that may be running, and they should not be hot-switched.
Include a delay after using any of these commands to allow the relays to settle, then turn on
the current or voltage from the source. Also note that the source requires local_kelvin to be
stable in forcev mode, so whenever you command the output connect relays to go off, make
sure you program local_kelvin first, with a suitable (0.5mS) delay. After commanding the
output connect relays on, and waiting a delay for them to close, you can command
remote_kelvin if you need full force and sense connections to your DUT.
Administrative Commands
To place an MPDCMOD channel into a known safe state, issue the reset command.
Example:
MPDS[1]->reset();
//sets local kelvin, opens
//F & S RELAYS, SETS IRANGE
//to 3, current clamp to 10ma
//VOLTAGE CLAMPS -35V, +35V,
//fast loop comp, force 0.0V
//acquire rate to 15000, and
//sets meter to measure v,
Earlier versions of the system software supported an inhibit/enable function, but that support has been
deleted because of unintended (and possibly damaging) side effects from the source feedback loop being
disconnected.
For a slower loop settling time, in case of high load capacitance that might encourage oscillation, use the
loopcomp command. Slew rate is dependent on the voltage range in use, and should be characterized by
the test engineer if it's critical, but generally, fast is about 1mS slew rate for a normal voltage delta, and 7-
10mS for slow.
Example:
MPDS[1]->loopcomp(0); // 0 = fast, 1 = slower
To use Ground Sense (the defined Zero Voltage Reference for the "ground" side of the source and A/D
converters) from the Father Card (which should be connected at the proper place on the DUT), you want to
use the remote_groundsense command. For using a local analog ground instead, use local_groundsense.
Issuing either command for any one channel on a board will act upon all channels of that board, and affect
all channels in the system.
The hardware implementation of this is shown on the block diagram in Figure 8.3. The DUT Ground Sense
is clamped to one diode drop from Analog Ground, and the relay shorts the two together. Thus you can
see that a short on one instrument will affect all instruments via their common father card connections.
Typically, this command is only required in calibration and diagnostic programs where a father card is not
guaranteed to be present. For best forcing and measurement accuracy, the test engineer should be
managing their own DUT Ground Sense connections properly.
Example:
MPDS[1]->remote_groundsense();
MPDS[1]->local_groundsense();
8-6
DC Instruments
Measure
Each DUT source can measure the voltage or current present at its I/O pins using the Source VM.
You first have to set up the converter to be connected in voltage mode or current mode, choose an acquire
rate (between 200 and 66000 samples/sec.), then issue the measvm command, with a number of samples
(1 to 4096) to average. For a single-site test program, the result is placed in the variable SITE-
>lastresult.value. This is automatically the variable that the KVD->Test(); command checks against the
upper and lower limits for the test. If you are running a multi-site program, then the result is placed in the
SITE->results array for your later use.
Example:
MPDS[1]->vmeter();
or
MPDS[1]->imeter();
then
MPDS[1]->acquire_rate(15000);
then
MPDS[1]->measvm(200);
Note: There is a single A/D converter for measuring source voltage, and another for measuring source
current. Each one is switched among the eight channels by its own mux. Therefore, you must
remember to make a measurement and process the result after you choose a channel, and before
you configure the SVM to measure the next channel.
Note: Measurement errors and alarms are as follows ---

Overrange positive: +999
Overrange negative: -999
Timeout during one or more conversions: -998
Currently in 5.03 software, these readings are included in statistical analysis reports.
Note: Due to software implementation, the calibration factors for any range are latched into the
measurement routine at the time the vmeter or imeter command is executed, not when the meavm
is executed. Therefore it is very important to not change the V or I range AFTER issuing the
vmeter or imeter statement.
Thus the following code would NOT work:

Source0->setvr(0.0,3);
Source0->vmeter(); // set the v mux for source0

Source0->measvm(10); // BREAKS!!! uses the cal factors for source0,

// but mux is connected to source1 !!!
Source1->measvm(10); // correct measurement of source1
The following code WOULD work:


KVD->Test();
8-7

KVD->Test();


Source1->imeter(); // set the i mux for source1
Source0->measvm(10); // correct v measurement of source0
KVD->Test();
Source1->measvm(10); // correct i measurement of source1

KVD->Test();
ABUS Connection to Digital Pins
One MP source on each instrument can be connected to a test head motherboard bus called the ABus,
which also goes across to each of the instruments in the digital subsystem, either DSPIO or DIGMOD. Any
digital channel can connect to the ABus by way of a pin-level command or a defined TConnection, and
then you can connect MPDS[0] to the bus or disconnect it from the bus by issuing the following:
Example:
MPDS[0]->aux_relay(8,8); //connects
MPDS[0]->aux_relay(0,8); //disconnects
This is useful for continuity or parametric measurements on digital pins, although the DIGMOD instruments
also have built-in PMUs for the same purpose. You can also use the ABus as a cross-connect to short out
multiple digital pins and also to an MP source - do this with extreme care.
New MPDCMOD Functions

start_measvm, read_measvm
MPUVM objects already had this undocumented function, but it has been extended to the MP channels.
The standard measvm command waits until the measurement completes before returning a result and
moving on. If you initiate a measurement with start_measvm, control comes back right away so you can
perform parallel measurements (on different MPDCMOD instruments - remember there is only one ADC
per instrument), or do other operations such as burst a pattern for IDDQ measurements. When you wish to
read back the calculated results, just issue the read_measvm command.
Example:
MPDS[n]->start_measvm(num, delay);
MPDS[n]->read_measvm(num);
8-8
DC Instruments
Note: The resulting measurements are available in variables owned by the object: result, result_rms,
result_min, result_max.
MPDCMOD and HPDCMOD Ranging Lockout
There is a ranging lock out feature on the MP and HP instruments, such that when you are in a particular
force mode (voltage or current) you can not change the range of that mode; you can however change the
range of the mode opposite of that being forced; thus the following:
// place the source into force voltage mode
MPDS[1]->setvr(6.5, mpvr_10v); // we are now in vrange 2
MPDS[1]->irange(mpir_20ma); // this is legal, we are now in irange 1
// place the source into force current mode

MPDS[1]->setir(15e-3, mpir_20ma); // we are now in irange 1
MPDS[1]->vrange(mpvr_40v); // this is legal, we are now in vrange 0
// place the source into force voltage mode

MPDS[1]->setvr(6.5, mpvr_10v); // we are now in vrange 2
MPDS[1]->vrange(mpvr_20v); // ILLEGAL!, error code returned, no action taken
// place the source into force current mode

MPDS[1]->setir(15e-3, mpir_20ma); // we are now in irange 1
MPDS[1]->irange(mpir_200ma); // ILLEGAL!, error code returned, no action taken
Additionally the acquire rate register applies to ALL sources and the UVM, but can be modified by ANY
source or the UVM.
Thus the following code would NOT work:

Source0->acquire_rate(10000); // set the sample rate register


Source0->measvm(10); // BREAKS!!, measurements taken at 15000 rate



8-9
Readback Functions
MPDS[i] >actual_sample_rate
double actual_sample_rate;
MPDS[i] >Exists
unsigned Exists;
Description:
Boolean that returns true if the source channel exists in the TCT (Tester Configuration Tool).
MPDS[i] >mpdsirange
unsigned mpdsirange;
Description:
Presently active Irange.
MPDS[i] >mpdsloopcomp
unsigned mpdsloopcomp;
Description:
Presently active loopcomp.
MPDS[i] >mpdsmode
dsfmode mpdsmode;
Description:
Presently active MPDSMode (ForceV, ForceI).
MPDS[i] >mpdsval
double mpdsval;
Description:
Presently active Force MPDSValue.
MPDS[i] >mpdsvrange
unsigned mpdsvrange;
Description:
Presently active Vrange.
8-10
DC Instruments
MPDS[i] >ResourceSide
unsigned ResourceSide;
MPDS[i] >ResourceSlot
unsigned ResourceSlot;
MPDS[i] >result
RESULT result;
Description:
Each DS will hold its own measured results.
MPDS[i] >vmmode
vmconmode vmmode;
Description:
Presently active Voltmeter Connection.
MPDS[i] >get_board_local_groundsense
bool get_board_local_groundsense();
MPDS[i] >getname
AnsiString getname();
Description:
getname returns the name of the resource
MPDS[i] >read_temperature
Reads one sample from the ds1722 temperature sensor; returns value in degrees Centigrade.
double read_temperature(void);
Returns:
0 - success
Description:
Value returned is from the single temperature sensor on the respective MPDCMOD circuit board (only one
sensor per board). The sensor is located centrally on the circuit board.
8-11
User Voltmeter (UVM)

A wide range of flexible ranges are available for this resource.
Figure 8.5: MPDCMOD User Voltmeter With Software Commands
Each floating User Voltmeter (UVM) can measure voltage only, on multiple ranges, that appear on
separate pins brought out to the Hypertronics connector, or various points internal to the instrument.
The gain stages are programmed in ranges as follows, with predefined constants available for ease of
reading the code later, and modification in the debugger.
Range Index Maximum Signal Variable Names
0 +/- 10 V uvmvr_10v
1 +/- 5 V uvmvr_5v
2 +/- 2.5 V uvmvr_2p5v
3 +/- 1.25 V uvmvr_1p25v
4 +/- 625 mV uvmvr_625mv
5 +/- 312 mV uvmvr_312mv
6 +/- 156 mV uvmvr_156mv
The offset DAC can be programmed over a dynamic range of +/- 40 V.
8-12
DC Instruments
Connections can be made either single-ended (with a pre-defined name "se"), or differentially ("diff"). If you
choose single-ended, you can program a constant offset for the low side comparison, or allow it to be the
default 0.0 V by not entering an optional value in the uvmeter statement.
The high side connections must be chosen from a list as follows:
1. User HI Input (from Hypertronics)

2. Any of the eight channels of the MPDS (sense lines) - numbered 0-7
3. MPDS0 - Force line
The low side connections can be chosen from a list as follows, if you are using a differential scheme:
1. User LO Input (from Hypertronics)

2. Any of the eight channels of the MPDS (sense lines) - numbered 0-7
3. MPDS1 - Force line
The internal connections to the sense lines are not a calibrated or normalized/scaled path unless you
perform a focused cal yourself, so this is a non-standard use of the instrument. By far the most common
use is the Father Card User connections.
MPUVM Objects
There is one UVM per MPDCMOD instrument board (typically four per test head maximum), so the index
number on the object such as MPUVM[0] refers to the instrument, not one of the MPDS sources. The
MPDS class defines MPUVMs as one of two types:
• TMPUVM
• TSiteMPUVM
You are free to declare your own name for this resource, as many test engineers do in a file named
TMPUVM *VOUT;
VOUT = MPUVM[0];
VOUT->setname("VOUT");
}
MP UVM Measure
The User Voltmeters are defined as to the MP Instrument they are located on. Thus there are four typical
UVMs in a test head, numbered MPUVM[0] through MPUVM[3].
You must set up the UVM input connections, and program the measurement mode (single-ended or a
differential) and range, choose an acquire rate if you desire something different from the default 15000
samples/sec. (between 200 and 66000 samples/sec.), then issue the measvm command, with a number of
samples (1 to 4096) to average. For a single-site test program, the result is placed in the variable SITE
>lastresult.value.
This is automatically the variable that the KVD->Test(); command checks against the upper and lower
limits for the test. If you are running a multi-site program, then the result is placed in the SITE >results
array for your later use.
8-13
There is a single uvmeter command that also allows the reference (offset) voltage of the UVM to be
programmed as the [optional] third argument. If omitted, the offset is set to 0.0V.
If differential mode is active, for improved accuracy, the third argument may be set to the expected
common-mode voltage level of the UVM. The first argument is the mode (0 or diff for differential, 1 or se for
single-ended), and the second argument is the measurement voltage range index or the associated
variable name from the chart above.
Examples:
MPUVM[0]->uvmeter(1,2,+10.0); //se mode,vrange 2,
// 10.0V Offset
is equivalent to
MPUVM[0]->uvmeter(se,uvmvr_2p5v,+10.0);
MPUVM[0]->uvmeter(0,4);
is equivalent to
MPUVM[0]->uvmeter(diff,uvmvr_625mv);
MPUVM[0]->uvmeter(diff,uvmvr_312mv,+7.5);
The command cmmeter is available with the following features:
It determines the common-mode voltage of the UVM's inputs, then calls uvmeter() using the Vcm just
determined. The search algorithm requires that the differential voltage between the UVM's inputs be less
than the voltage supported by the specified Vrange (specified via the only input parameter to the
cmmeter() function). After determination of the actual common-mode voltage of the inputs a uvmeter()
function is automatically called specifying differential mode, the same Vrange as specified in the presently
active cmmeter() function call, and the common-mode voltage just determined.
The purpose of this command is to allow a semi-automated way to compensate for a common-mode
accuracy factor included in the specifications of the instrument. By measuring the common mode factor
first, the accuracy of the gain amplifiers can be enhanced by this predictive algorithm. For the utmost
accuracy, a focused calibration done by the test engineer with your exact DUT board hardware and relay
connection paths is always recommended.
Example:
MPUVM[0]->cmmeter(uvmvr_625mv);
The series of detailed commands for accomplishing UVM functions are given here:
Example:
First issue the reset command if you are not certain what state the UVM is when you are starting to use it.
The reset state is the 10V measurement range, differential, User inputs.
MPUVM[0]->reset(0);
Then set up the mode and range:

MPUVM[0]->uvmeter(se,<range>,[optional offset]);
OR
MPUVM[0]->uvmeter(diff,<range>,[optional commonmode value]);
Then if you need to, select which of the high inputs are to be used. In almost all cases, this will be the
"user" input, which is the Hypertronics connection to the Father Card.
MPUVM[0]->uvmhi_is_user();
OR
8-14
DC Instruments
MPUVM[0]->uvmhi_is_source(4);
OR
MPUVM[0]->uvmhi_is_ds0f();
Then if you are using differential mode, select the low side input:
MPUVM[0]->uvmlo_is_user();
OR
MPUVM[0]->uvmlo_is_source(4);
OR
MPUVM[0]->uvmlo_is_ds1f();
Then, in case you wish to change the sample rate:

MPUVM[0]->acquire_rate(15000);
Finally, issue the measurement command:

MPUVM[0]->measvm(200);

Readback Functions
MPUVM[i] >getname
AnsiString getname(void);
Description:
getname returns the name of the resource.
Semi-parallel Measurements
Starts UVM measuring <nummeas> samples after <delay>. Can start multiple UVM boards sampling in
parallel. Read back can be started on the first board as soon as all the other boards are started. The first
board is read back at the sample rate speed. The other boards are read back at data bus rates.
Example:
MPUVM[n]->start_measvm(num, delay);
MPUVM[n]->read_measvm(num);
Note: The resulting measurements are available in variables owned by the object: result, result_rms,
result_min, result_max.
8-15
Pinouts
Figure 8.6: MPDCMOD I/O Pinout
QUVM (Quad User Voltmeter instrument)

QUVM Pictorial
Pending - about 6 pages
8-16
DC Instruments
HPDCMOD (High Power DUT Source)

HPDCMOD Pictorial
Figure 8.7: HPDCMOD Pictorial
The HPDC Module (HPDCMOD) contains two independent DC Sources. Each DC source is an
independently programmable, four quadrant, Kelvin, DC voltage and current source which can be
connected to the device directly or through relay networks on the Father Card. The sources offer four
voltage ranges of +/- 40V, +/- 20V, +/- 10 V, and +/- 5 V, and four current ranges: 5A, 50mA, 500uA, and
5uA. Currents on the 5A range are power limited. The force and sense line of each source connect to the
Father Card through a Hypertronics connector. Each DUT Source has a voltmeter/ammeter that is
dedicated to making voltage and current measurements. This meter is a 16 bit sampling voltmeter with
variable clocking, differential input, as well as input gain and offset. Because this voltmeter is designed to
measure the state of each of the DC sources, it has no connections to the Father Card. This is commonly
known as the SVM, for Source Voltmeter. Sources are numbered beginning at 0 (zero) not 1 (one), which
is similar to DD Channel resources.
The HPDCMOD has user programmable clamp registers for positive voltage, negative voltage, and source
and sink current. All registers are independently programmable. Future releases will include status
registers, board level temperature information, pulse mode operation, and user programmable power
dissipation monitoring.
HPDCMOD Support for Low Voltage Rails
To reduce unwanted power dissipation in the HPDCMOD instrument, a new version is offered with 12 Volt
maximum output. This also requires support in the Tester Configuration Tool, where the new instrument is
called HPDCMODLV. Running calibration or checkers on this board using releases before 5.02 Release 6
will fail.
For Rel 8, minor issues were fixed in the Checker, and in configurations with a mixture of normal and LV
HPDCMOD instruments.
8-17
Figure 8.8: HPDC Module Block Diagram with Software Commands
Physical Description
The HPDC Module is composed of a D/A converter which feeds a high power operational amplifier. This
power op amp has two possible feedback loops. The first feedback path is used when the source is forcing
voltage and connects the op-amp's output to its own negative input. This feedback path senses the output
voltage and holds it constant. The output of the power amplifier is referred to as the force line and the
voltage feedback path is called the sense (or Kelvin) line. The force and sense lines can be connected
directly at the DC Module output connector or can be wired independently and tied together close to the
device to eliminate the effects of path resistance.
The second op amp feedback path is used to force (source or sink) current. This path uses a differential
amplifier to sense the voltage drop across a resistor in series with the power op amp output. Due to the
nature of this sense connection, the feedback path does not require any type of remote connection to
ensure accuracy. Current ranges are defined by a resistor network on the output of the power op amp.
Voltage clamps are independently user-programmable and current limiting is also user programmable. DC
Module control logic, including address decoding and serial data return bus generation, are contained
within a single on-board FPGA. The HPDC Module FPGA must be booted with a special firmware data file
each time the test head is turned on.
8-18
DC Instruments
Force Voltage
Once the Kelvin connection has been selected, the source can be used to force a voltage up to its
maximum output specification, subject to the programmed voltage clamp.
Note: Amplifier limitations reduce the maximum forced voltage to somewhat less than the DC supplies in
your particular configuration. The Laser Trim configuration uses +/- 30V supplies, so the HP will
operate between +/- 26V only, even on the 40 V software range. In the M2m configuration (PW+),
with +40V, -20V DC supplies, you will obtain a maximum voltage capability of +36V to -16V.
Example:
HPDS[1]->setv(5.50);
The argument [1] is the DUT Source within the test head (1 of 12, but they are numbered [0] through [11]).
You are free to declare your own name for this resource, as many test engineers do in a file named
THPDS *VDD;
VDD = HPDS[1];
VDD->setname("VDD");
}
Force Current
The HPDCMOD may be set to force any current up to 5A, subject to the programmed current clamp, and to
specified power and energy limits (Instantaneous Watts and cumulative Watt-seconds). Always make sure
the clamps are programmed to be "out of the way" of the forced value, which means slightly higher, outside
the guardband of the specifications. Current versions of the hardware are however limited to 1 Amp
steady-state.
Example:
HPDS[1]->seti(0.850);
Voltage Ranges
0 +/- 40V hpvr_40v
1 +/- 20V hpvr_20v
2 +/- 10V hpvr_10v
3 +/- 5V hpvr_5v
You can set the voltage range explicitly if you wish using the range index, or its alternate variable name, in
the setvr and vrange commands. Setvr sets both the value and the range in one command, while vrange
affects only the desired range. These are examples of valid statements only; please also see “MPDCMOD
and HPDCMOD Ranging Lockout” on page 8-9 for an important discussion of the order in which you are
required to perform certain ranging functions.
8-19
Example:
HPDS[1]->setvr(4.50,3);
HPDS[1]->setvr(4.50,hpvr_5v);
HPDS[1]->vrange(3);
HPDS[1]->vrange(hpvr_5v);
Current Ranges
Four ranges are available: 5A, 50mA, 500uA, and 5uA. The current range setting is handled automatically
when forcing current using the seti command, however, when using setv to force a voltage it may be
desirable to change the current range.
0 5A hpir_5a
1 50mA hpir_50ma
2 500uA hpir_500ua
3 5uA hpir_5ua
Example:
HPDS[1]->setir(0.275,0);
HPDS[1]->setir(0.275,hpir_5a);
HPDS[1]->irange(1);
HPDS[1]->irange(hpir_50ma);
Warning! The test engineer MUST take extreme care to avoid hot-switching any range relays. For
enhanced execution speed, KVD software drivers do not enforce supply disabling or
discharging, or include built-in delays, trusting the test engineer to know when they are safe
from the risk of hot-switching. Enlightened use of delays is REQUIRED to avoid the possibility
of instrument or DUT damage.
Driver Improvements for Increased Reliability
KVD instrument drivers now include make-before-break current range changing. Using the previous break-
before-make algorithm, the driver was slightly faster, but at the risk of opening the current feedback loop
during a range change event. This could cause an internal transient if the range was being changed while
hot. Since KVD cannot control whether or not hot switching is occurring, this transient could be a cause of
reduced range resistor and relay reliability.
By closing the relay for the new range 200uS before the previous range relay is opened, the open-loop
transients should be eliminated.
Since this change could affect the dynamics of a currently running test program, we offer a backwards
compatibility mode. The default state of this boolean is to force the new behavior of the driver, to
encourage test engineers to requalify their program if necessary, and examine their range changes for hot-
switching events.
8-20
DC Instruments
To temporarily force the previous driver behavior, define the following variable as extern bool:
IRange502 = true;
Note: Due to hardware implementation, the 5A range resistor is always connected to the output force
connection when this highest current range (range 0) is selected. If you need to disconnect the
instrument totally from the father card, you will need to select current ranges 1, 2, or 3 (not 0).
Voltage and Current Clamps
For each source, the voltage and current clamps are programmable. Current clamps are symmetrical (one
programmed value is used for both positive and negative current clamps) while the voltage clamps require
the user to program two values.
Example:
HPDS[1]->vclamp(-4.0,12.0);
HPDS[1]->iclamp(0.50);
Kelvin Connections
Each source has separate Force and Sense relays, and a separate relay to short them out locally in case
the user does not wish to being both lines separately to the DUT.
Example:
HPDS[1]->on(); //closes both force and sense
HPDS[1]->off(); //opens both force and sense
HPDS[1]->off_force(); //opens force ONLY
HPDS[1]->off_sense(); //OPENS sense only
HPDS[1]->on_force(); //CLOSES force ONLY
HPDS[1]->on_sense(); //closes sense only
HPDS[1]->local_kelvin(); //shorts F & S locally
HPDS[1]->remote_kelvin(); //opens F & S short
Administrative Commands
To place an HPDCMOD channel into a known safe state, issue the reset command.
Example:
HPDS[1]->reset();
//sets local kelvin, opens
//F & S RELAYS, SETS IRANGE
//to 3,current clamp to 250ma
//VOLTAGE CLAMPS -35, +35,
//fast loop comp, force 0.0V
//acquire rate to 15000, and
//sets meter to measure v,
Earlier versions of the system software supported an inhibit/enable function, but that support has been
deleted because of unintended (and possibly damaging) side effects from the source feedback loop being
disconnected.
For a slower loop settling time, in case of high load capacitance that might encourage oscillation, use the
loopcomp command.
8-21
Example:
HPDS[1]->loopcomp(0); // 0 = fast, 1 = slower
To use Ground Sense (the defined Zero Voltage Reference for the "ground" side of the source and A/D
converters) from the Father Card (which should be connected at the proper place on the DUT), you want to
use the remote_groundsense command. For using a local analog ground instead, use local_groundsense.
Issuing either command for either channel on a board will act upon both channels of that board, and affect
all channels in the system.
The hardware implementation of this is shown on the block diagram in Figure 8.8. The DUT Ground Sense
is clamped to one diode drop from Analog Ground, and the relay shorts the two together. Thus you can
see that a short on one instrument will affect all instruments via their common father card connections.
Typically, this command is only required in calibration and diagnostic programs where a father card is not
guaranteed to be present. For best forcing and measurement accuracy, the test engineer should be
managing their own DUT Ground Sense connections properly.
Example:
HPDS[1]->remote_groundsense();
HPDS[1]->local_groundsense();
Measure
Each DUT source can measure the voltage or current present at its I/O pins using the Source VM. The
HPDCMOD does not contain a User Voltmeter.
You first have to set up the converter to be connected in voltage mode or current mode, choose an acquire
rate (between 7000 and 35000 samples/sec.), then issue the measvm command, with a number of
samples (1 to 255) to average. (More than 255 samples may be programmed, but the behavior of taking
the samples and averaging them is not guaranteed of this writing) For a single-site test program, the result
is placed in the variable SITE->lastresult.value. This is automatically the variable that the KVD->Test();
command checks against the upper and lower limits for the test. If you are running a multi-site program,
then the result is placed in the SITE->results array for your later use.
Example:
HPDS[1]->vmeter();
or
HPDS[1]->imeter();
then
HPDS[1]->acquire_rate(15000);
then
HPDS[1]->measvm(200);
Note: Due to software implementation, the calibration factors for any range are latched into the
measurement routine at the time the vmeter or imeter command is executed, not when the meavm
is executed. Therefore it is very important to not change the V or I range AFTER issuing the
vmeter or imeter statement.

8-22
DC Instruments
Readback Functions
HPDS[i] >actual_sample_rate
double actual_sample_rate;
HPDS[i] >Exists
unsigned Exists;
Description:
Boolean that returns true if the source channel exists in the TCT (Tester Configuration Tool).
HPDS[i] >hpdsirange
unsigned hpdsirange;
Description:
Presently active Irange.
HPDS[i] >hpdsloopcomp
unsigned hpdsloopcomp;
Description:
Presently active loopcomp speed.
HPDS[i] >hpdsmode
dsfmode hpdsmode;
Description:
Presently active HPDS Mode (ForceV, ForceI).
HPDS[i] >hpdsval
double hpdsval;
Description:
Presently active Force HPDS Value.
HPDS[i] >hpdsvrange
unsigned hpdsvrange;
Description:
Presently active Vrange.
8-23
HPDS[i] >getname
Description:
getname returns the name of the resource.
Pinouts
Figure 8.9: HPDCMOD I/O Pinout
Keithley and HP Meter

Some father cards contain a connector to route signals to the external precision meter, where you can
measure them using code from the TKeithleyMeter2000, TKeithleyMeter2002, or THP3458A classes.
There is also a generic TMeterClass if you don't know precisely which external meter is configured on your
system.
Contact KVD applications engineers for assistance and code examples for this sort of use.
8-24
DC Instruments
Relays and Reliability

There is a PowerPoint training presentation that addresses how KVD testers obtain higher speed by
exposing the hardware to some risk of abuse by hot switching. Please obtain a copy of this presentation
from KVD or your local file server and pay close attention to the details of this important tradeoff. Here are
some of the bullets from that presentation:
• ATE: Relays, Resistors, and Reliability
• Your test system's inner workings
• Instruments
• Relays
• Resistors
• Software
• How KVD may be different
• Advantages
• Disadvantages
• Instruments
• KVD instruments are extremely high density
• Surface mount components
• 8-12 layer PC boards
• Small geometry layout
• BGA Xilinx often used
• Engineering is the art of compromise
• An Engineer is somebody who can do for a dollar what any fool can do for ten.
• Relays
• Electromechanical devices
• Contact blades must be iron-based (to attract each other in a
magnetic field)
• Gold-plated/low resistance, but gold is soft
• Ruthenium plated (sputtered) for hardness and contact
resistance uniformity over time.
• Thermal effects are very important when working with less than
100uV - thermocouple effect (EMF)
• Contact closure effects (bounce and vibration)
• Reliability extremely dependent on avoiding hot-switching
• Resistors
• Surface mount (chip) resistors used extensively
• Can handle heat to their rated wattage
• But sometimes sensitive to thermal shock (rapid increase in temperature from the inside)
• Rapid application of voltage can be similar to the shock of pouring boiling water into a drinking
glass
8-25
• Software
• Drivers
• No built-in delays
• No inherent protection against hot-switching
• Totally trusting of the user
• User Code
• The User must be aware of any relay movements
• Relay movements include both close and open
• Take care cleaning up in DeviceFinish because of Stop on First Fail
• KVD Design Philosophy
• Reduce the cost of testing
• Lower tester cost
• Highest possible speed
• High instrument density
• Trusting the Test Engineer
• You know best when you can go fast
• Insert delays only when necessary
• Avoid hot switching events
• Hot Switching
• Closing relays with voltage across them causes inrush current limited only by circuit impedance
• Opening relays with current flowing through them causes voltage spikes, which may damage other
relays or the DUT
• Relay locations:
• Output (force and sense) relays on the instruments
• Current range relays
• Father Card
• DUT board
• KVD Software Drivers
• Could force soft switching, but at the expense of:
• Longer test times
• Glitches
• Unpredictable behavior
• Allow the test engineer to issue a string of commands, and take one delay at the end
• Assume the engineer has a good knowledge of the instrument hardware
• Coto relay specs
• Typically rated for 1.5 A carry current
• Max switched current rating 0.5A
• Lifetime test conditions: 1V/10mA
8-26
DC Instruments
• 1,000,000,000 (one billion) operations

• Lifetime can be less than 1% of maximum if abused
• Relay closing physics
• Bounces (chatter)
• Inrush current
• (tens of Amps for nanoseconds)
• Load impedance determines the spikes
• Energy dissipated in blade arcing creates micro welds, pits, and molten metal balls, often broken by
blade vibration
• Ruthenium and gold plating damage
• Results in erratic and high contact resistance
• Or welds the relay so it never opens
• Relay bounce (Coto chart)
• What to avoid
• Closing any relay with voltage across it
• If there is a chance of instantaneous
current flow, such as to charge a capacitor
(cables are also capacitors)
• Inrush current is NOT limited by source
clamps for the first few microseconds, only
the inductance of the wiring (which could be
nanohenries)
• v = L * di/dt implies if L is low, di/dt is
extremely high!
• Opening any relay which is carrying current
• Voltage will fly up. Energy must go somewhere.
• i = C * dv/dt implies if C is low, dv/dt is extremely high!
• Specifically:
• Turn sources down (voltage or currents to zero) before changing connections anywhere in the
path to the DUT
• Include adequate delays (1-2mS)
• You can combine multiple relay commands in a string and then take one delay at the end. If you
know you are not hot switching
• NEVER change the Irange of a running source without good reason
• Like shifting a transmission without using the clutch!
• Downshifting is especially dangerous, because there may be current flowing in the higher range
that would cause an instantaneous spike on the lower range. (And could crack the lower range
resistor)
• And…
• Measurement paths are usually safer than source paths, because they should be high impedance
• Don't let a source feedback loop go open
8-27
• Use local Kelvin before you turn a source off, if you intend to connect it later and depend on there
not being a glitch.
• Go back to remote kelvin if you need accuracy on a high-current source path.
• Safe techniques for DUT power pins
• When charging the bypass cap for a supply pin, use a high current range.
• Then reduce the range for a leakage measurement after the voltage has stabilized and charging
current has decayed
• Before opening the connect relays for that source, if device supply current is flowing, make sure to
discharge the bypass cap to ground again with adequate delay and a high enough current range.
• If you don't, the bypass cap will be a ticking bomb set to damage the next instrument or DUT that
touches it.
• Other critical considerations
• Clean-up, discharge supplies, and open relays in the function DeviceFinish
• This function is always executed, even if the device bins out early due to Stop on First Fail
• Guarantees that bypass caps and instruments are not left in a charged-up state.
• Helps prevent QA failures from unanticipated conditions
Relay Matrix Board (RMX)
Figure 8.10: Relay Matrix (RMX) Pictorial
The Relay Switching Matrix (RMX) provides the user with programmable relays located on a small (single
DIN size) module.
Features
The matrix consist of 64 relays and is designed in an array of eight lines, each with six pins. Each line has
a disconnect relay to isolate it from the father card, and there are eight line-to-line shorting relays to
connect lines in banks if desired.
8-28
DC Instruments
RMX Block Diagram
Figure 8.11: RMX Block Diagram
Using the Relay Matrix Class
There are 4 Relay matrix objects, RMX0 through RMX3.
There is also an enumerated list of connection types.

typedef enum {L0, L1, L2, L3, L4, L5, L6, L7,
L0P0, L0P1, L0P2, L0P3, L0P4, L0P5,
L1P0, L1P1, L1P2, L1P3, L1P4, L1P5,
L2P0, L2P1, L2P2, L2P3, L2P4, L2P5,
L3P0, L3P1, L3P2, L3P3, L3P4, L3P5,
L4P0, L4P1, L4P2, L4P3, L4P4, L4P5,
L5P0, L5P1, L5P2, L5P3, L5P4, L5P5,
L6P0, L6P1, L6P2, L6P3, L6P4, L6P5,
L7P0, L7P1, L7P2, L7P3, L7P4, L7P5,
L0L1, L1L2, L2L3, L3L4, L4L5, L5L6, L6L7, L7L0} RMXCONNECTIONS;
8-29
RMX Commands
There are two commands that can be used to make or break connections. Set, and Clear. Set makes the
connection, Clear opens the connection. You can pass in to each command up to 8 connections from the
above enumerated list.
For example to connect Line 0 Pin 0 to Line 1 Pin 2
Example:
RMX0->Set(L0l1, l0p0, l1p2);
To connect Line 2 Pin 0 to Line 2 Pin 3
Example:
RMX0->Set(L2p0, l2p3);
Finally, to open a connection between Line 5 Pin 5 and Line 6 Pin 5
Example:
RMX0->Clear(l5, l6, l5p5, l6p5);
To open an entire BANK of relays (all pins associated with a line, and the line relay)
Example:
RMX0->resetline(<linenumber>);
To open all relays on an RMX board
Example:
RMX0->resetall();
Up to 256 named RMX (Relay Matrix) connections can now defined, increased from 48, and the number of
relays that each connection can contain is now 16, increased from 8.
Other Commands and Readback Syntax
RMX0 >Clear
Clears (opens) up to 8 relays on a matrix board.
short Clear(unsigned RMXparam1 = NORMXCON, unsigned RMXparam2 = NORMXCON, unsigned RMXparam3 =
NORMXCON, unsigned RMXparam4 = NORMXCON, unsigned RMXparam5 = NORMXCON, unsigned RMXparam6 =
NORMXCON, unsigned RMXparam7 = NORMXCON, unsigned RMXparam8 = NORMXCON);
Parameters:
unsigned RMXparam1 = NORMXCON
The first relay on the matrix board to open.

The second relay on the matrix board to open.

The third relay on the matrix board to open.
8-30
DC Instruments
The fourth relay on the matrix board to open.

The fifth relay on the matrix board to open.

The sixth relay on the matrix board to open.

The seventh relay on the matrix board to open.

The eighth relay on the matrix board to open.
Returns:
Always returns 0.
Description:
This routine is the only available routine in the matrix class that the user can call to open relays on any
pins, lines, or line to line relays on a matrix board. The user can open between one and eight relays with
one call.
RMX0 >CreateNamedConnection
Creates a relationship between a string and a series of connections.
short CreateNamedConnection(char* initname, RMXCONNECTIONS RMXparam1 = NORMXCONNECTION,
RMXCONNECTIONS RMXparam2 = NORMXCONNECTION, RMXCONNECTIONS RMXparam3 = NORMXCONNECTION,
RMXCONNECTIONS RMXparam8 = NORMXCONNECTION);
Parameters:
char* initname
A character string that will be used with the NSet and NClear commands.
RMXCONNECTIONS RMXparam1 = NORMXCONNECTION
Returns:
-4 = Max number of Named Connections exceeded
-3 = RMX board not available
-2 = no connections sent in
-1 = no name sent int
8-31
0 = success
Description:
The user can associate a name with a series of RMX connections so that the code is more readable. By
creating a named connection, the user can call the NSet or NClear commands by passing in the more
readable string.
RMX0 >GetLineStatus
Returns the state of the line relay on the bank of relays.
bool GetLineStatus(unsigned banknum);
Parameters:
unsigned banknum
The bank number (1..8)
Returns:
true - the line relay is closed. false - the line relay is open.
RMX0 >GetLineToLineStatus
Returns the state of the line to line relays.
bool GetLineToLineStatus(unsigned banknum);
Parameters:
unsigned banknum
The first line number of the line to line relay. 0 - line 0 to line 1 relay. 1 - line 1 to line 2 relay. 2 - line 2 to
line 3 relay. 3 - line 3 to line 4 relay. 4 - line 4 to line 5 relay. 5 - line 5 to line 6 relay. 6 - line 6 to line 7 relay.
7 - line 7 to line 0 relay.
Returns:
true - the relays is closed. false - the relay is opened.
RMX0 >GetPinStatus
Returns the state of one pin on a chosen bank (line) on the matrix board.
bool GetPinStatus(unsigned banknum, unsigned pinnum);
Parameters:
unsigned banknum
The line being referenced.

unsigned pinnum
The pin number on the bank.
Returns:
true - the pin is closed. false - the pin is open.
8-32
DC Instruments
RMX0 >NClear
Clears (opens) up to 8 relays on a matrix board, referenced by name
short NClear(char* conname);
Parameters:
char* conname
The name used in the SetNamedConnection function (case sensitive) Return Value.
Returns:
1 if the name cannot be found, 0 on success.
RMX0 >NSet
Sets (closes) up to 8 relays on a matrix board, referenced by name
short NSet(char* conname);
Parameters:
char* conname
The name used in the SetNamedConnection function (case sensitive) Return Value:
Returns:
1 if the name cannot be found, 0 on success.
RMX0 >resetall
Opens all relays on the matrix board.
short resetall();
RMX0 >resetline
Opens all the relays on one line, including the line relay.
short resetline(unsigned line);
Parameters:
unsigned line
The line number to reset.
RMX0 >ResetNamedList
Resets and clears ALL previously created named lists.
short ResetNamedList();
RMX0 >Set
Sets (closes) up to 8 relays on a matrix board.
8-33
short Set(unsigned RMXparam1 = NORMXCON, unsigned RMXparam2 = NORMXCON, unsigned RMXparam3 =

NORMXCON, unsigned RMXparam4 = NORMXCON, unsigned RMXparam5 = NORMXCON, unsigned RMXparam6 =
NORMXCON, unsigned RMXparam7 = NORMXCON, unsigned RMXparam8 = NORMXCON);
Parameters:
The first relay on the matrix board to close.

The second relay on the matrix board to close.

The third relay on the matrix board to close.

The fourth relay on the matrix board to close.

The fifth relay on the matrix board to close.

The sixth relay on the matrix board to close.

The seventh relay on the matrix board to close.

The eighth relay on the matrix board to close.
Returns:
always returns 0.
Description:
This routine is the only available routine in the matrix class that the user can use to close relays on any
pins, lines, or line to line relays on a matrix board. The user can close between one and eight relays with
one call.
8-34
DC Instruments
RMX I/O Pinout
Figure 8.12: RMX I/O Pinout
8-35
8-36
This section provides detailed information about the Digital Subsystem in the KVD test system. Included in
the discussion are functional and hardware descriptions, block diagrams, programming examples, and
command definitions. There are two major architectures of digital resources at KVD, the DSPIO family
(includes DSPIO, DSPIOR4, and DDD8 instruments) and the DIGMOD family (includes DIGMOD16 and
DIGMOD32).
Topics Covered:
• Instrument Block Diagram and Description
• Overview of Digital Test Concepts
• Patterns
• Clocking
• Sequencer commands
• Channel commands
Figure 9.1: DSPIO Pictorial
Figure 9.2: DSPIO Board Block Diagram
9-1
DSPIO Family
Support for DSPIOR4 Instruments
The DSPIO Instrument was redesigned during the production run for improved speed and parts
availability, and the software drivers are slightly different. This requires the TCT (Tester Configuration
Tool) to be filled in by the customer with the locations of any DSPIOR4 versus DSPIO instruments. No
matter which kind of instrument is in a slot, the first instrument in a test head will have the suffix "0", the
second one "1", and so forth. DSPIO and DSPIOR4 instrument MAY be mixed together in a test head, so
long as the TCT is properly configured.
Note: Once the TCT has been configured, and the instruments calibrated, the user programming
language is identical, and no user code changes will be necessary. Moving boards from slot to slot
is a maintenance function, so it will usually be of interest only to maintenance staff which boards
are in which slot. This should be invisible to the test engineer.
Figure 9.3: DSPIO Rev. 4 Photo
The instrument can be distinguished by a label on the board extractor flipper (request stickers from the
factory if yours do not have them) and by the TI voltage regulator heat sink on the right side of the board as
in the photo above.
Details of the improvements:
1. Newer Xilinx Spartan XL technology. This change was made for part availability and also additional
speed in the sequencer.
2. Change from 8 bit to 16 Bit DACs for the pin levels.
3. Temperature/Voltage monitoring circuitry (software language support will follow)
4. Change Drive Delay Lines for higher bandwidth.
As a result of these changes, DSPIOR4 data rate is now 20MHz instead of the published 18MHz spec that
is met by all DSPIO variants.
9-2
Digital Instruments
Support for DDD8 Instruments
For certain customer configurations, only 8 digital channels are necessary. For an economical instrument
offering, we provide a de-populated DSPIO instrument called DDD8. Only one of these can exist in a test
head.
This is a TCT option, and no software language changes are required. The calibration program and
various checkers were updated to support the DDD8. Serial send/receive memory was also removed from
the instrument, so this is a pattern-based instrument only.
DSPIO Functional Description

The KVD Test System generates high speed digital I/O signals using its DSPIO Subsystem. Each DSPIO
Module contains 16 I/O Channels with the following features:
Maximum Data Rate 18 MHz
Pattern Memory 512K
VIH Range 0 to 10V
VIL Range 0 to 5V
Compare Level Range 0 to 5V
Drive Formats RZ, NRZ, CS, RO and their complements, plus HI, LO, MCLK/2, MCLK/
4, MCLK/8
Time Measure Capability Internal Muxing to TMU Module per Pin
DC Measure Capability Internal switching to DUT Source (DS1 or MPDS[0]) per Pin.
Edge Resolution 12.5nS (assuming 80MHz Master Clock)
Edge Accuracy 2nS

250pS vernier available for focused calibration
Max Time Sets 2
Data Capture Mode DSPIO's have independent Serial/Parallel Capability
Up to 5 DSPIO Modules can be configured in a KVD Test System for a maximum channel count of 80.
9-3
Figure 9.4: DSPIO Master Block Diagram
Overview of Digital Test Concepts

The experienced test engineer may wish to skip this section if digital testing is not a new technology. To
those transitioning from simpler test systems, or linear-only systems, please make sure to thoroughly
absorb these concepts. The feature set of the KVD DSPIO subsystem is quite rich, and will be presented
here in layers.
In the interests of simplicity in the earlier sections, certain information will be concealed until the time is
right. If you are an experienced digital test engineer, please don't get impatient, just skip ahead. In later
sections you will find the information you need on how to make the KVD do what you need it to do.
Pattern Driving
At the core of any digital subsystem is the ability to generate digital high and low voltages, and stimulate
the DUT input pins. Each DSPIO instrument has 16 output channel drivers to accomplish this. Behind each
channel is as much as 512K of what is called pattern memory.
When the test program is initialized, this memory needs to be pre-loaded with the desired data (ones and
zeros) [the method of doing this is explained later]. When you are testing each device, upon command, this
data is sent to the pin drivers that force your desired high and low voltage levels onto the DUT pins.
9-4
Digital Instruments
Data is sent at a rate called the T0 (Tee-Zero) rate, which is also called your pattern rate. In the simplest
view, your data moves from pattern memory one address each T0 time period, and the address
increments up by one each time. The data goes from memory to the pin drivers, and then to the DUT pins.
In the following diagram, pattern memory is on the left, 512K words long, and 16 bits wide. (one bit for each
of the 16 pin drivers). DSPIO instruments can be ganged together for wider than 16-bit operation, but we
will limit our discussion to one instrument at a time for now.
Memory address 0 is on the right of its box, and is the first data sent to the pin drivers at the first T0 time
period. If we look at the data being sent, with Channel 0 on the left, and Channel 15 on the right, the first
word being sent would be this:
0 1 1 0 1 0 1 0 1 1 1 0 0 0 0 0
For historical reason, this word is called a test vector.
Figure 9.5: Digital Drive Memory
Looking at the data being stored in the first six addresses, the pattern file would look like this. The memory
address (the first column) is not part of the file itself as it's written.
000000 0 1 1 0 1 0 1 0 1 1 1 0 0 0 0 0
000001 0 0 1 0 1 0 1 0 1 1 1 0 0 0 0 0
000002 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0
000003 1 0 1 1 1 1 1 0 1 1 1 0 1 1 0 0
000004 1 1 1 0 1 0 1 0 1 1 1 0 0 0 0 0
000005 0 0 1 0 1 0 1 0 1 1 1 0 0 0 0 0
9-5
Looking at the right side of the diagram, the pin drivers accept this data, and drive the DUT pin high or low
for each one or zero that they get from pattern memory. Each T0 represents a new piece of data, or test
vector. A scope or logic analyzer view of the pin driver output waveform is shown to the far right.
A view of channels 0-7 is shown here.
Figure 9.6: Digital Drive Vector
Besides 1 and 0, you can disable the driver and allow the output to float by using code X (don't care) or M
(mask).
Pattern Comparing
Each digital channel is also connected to a programmable level comparator, if the DUT is driving the pin
instead of the DSPIO instrument. We can receive this data and compare it to data in pattern memory, to
see if it is a match to what we expect the DUT to send us. Instead of zeros and ones, we program code H
for an expected high, and L for an expected low, into pattern memory.
9-6
Digital Instruments
Figure 9.7: Compare Pattern Data
In this diagram, all 16 channels are sending data from the DUT to the DSPIO instrument.
For each T0 time period, the input voltage level is compared to a programmed level (covered later). If it is
high, and the pattern memory contains an H, then the data is a match, and it is not a fail. If it is low, and the
pattern memory is expecting an L, then it also is not a fail. If any channel is a mismatch, and does not
equal the expected data, then the fail flag is set. The fail flag is set for any mismatch in any of the vectors
executed, and can be interrogated later for use in a test statement. If the channel state does not mater, you
can enter code X (don't care) or M (mask) and it will be ignored at the fail register.
In most test programs, you will have a mixture of inputs and outputs, and the pattern file will have a
combination of 1, 0, H, L, X, and M codes.
The vector address that causes the fail to occur is also saved in the Fail Address Register, in case you
wish to know for debugging or to datalog it.
The first line of the vector file that this figure represents is given here:
L H H L H L H L H H H L L L L L
Send Serial Memory
For flexibility, the pattern memory we have been discussing is augmented by another memory called the
Send/Capture memory. The normal pattern memory sends data in parallel to the pin drivers and
comparators, but many devices require serial I/O. It can be tedious to write the patterns and wasteful of
pattern memory to use it for serial I/O pins.
9-7
This second bank of memory is also 512K words in size per pin, and the data being sent to the DUT is first
sent to a 16-bit shift register. Ignoring the normal pattern memory for now, this is a diagram of the Send
memory being used to source data to the DUT.
The Send memory is loaded with data, usually predefined as an array of data, not the typical vector file
discussed earlier. It is often easier to create this kind of data with an algorithm than write it out in full in text
format.
The data to be sent is loaded a word at a time into the shift register. The command to do this is written into
the pattern vector file at a particular address: W=LOAD. Precisely how to do this is covered later.
Once the data word is in the shift register, it can be sent to the pin drivers beginning at the next T0 period.
Typically, one channel is used to send the serial data, and the drivers of the adjacent channels are not
used. Once a bit is sent to the driver during one T0 period, the command W=SHIFT is sent, and the shift
register moves data from LSB to MSB, and the next bit is available during the next T0 period. This can be
repeated 8 or 16 times as necessary to shift out all the desired data in the shift register.
The pattern memory needs to have the code W entered to use the shift register as the source of driver data
instead of the normal pattern memory 1 or 0. This can be changed on the fly, on a vector-by-vector basis.
You need to make sure the shift register contains the desired data by using the W=LOAD command first,
then on the next or a subsequent vector, code W will send this data to the pin driver. The code W was
chosen to designate Write data.
Eight bits of data are highlighted in the diagram. One entire 16-bit word is loaded into the shift register on
one vector, then sent one bit at a time via one or more drivers, in this case we will examine eight bits being
sent out channel 15, and the serial data being sent is:
0 0 0 0 0 1 1 1
Again, shifting is always done in the LSB to MSB direction. This can be used for sending serial bus
commands such as for the I2C bus, ramp data for testing DACs, or any testing purpose.
9-8
Digital Instruments
Figure 9.8: Serial Send Memory
Capture Serial Memory
In an analogous way to the use of Send/Capture memory data going to the pin drivers, the DSPIO
instrument can also capture (detect) serial data streams and place them into the same memory. The
destination memory region needs to be set up so as to not conflict with send data regions, and that
memory management is discussed later.
In the next diagram, data coming from the device is sent to the comparators, and the use of the code V in
a pattern memory vector is the signal to send incoming data to the capture shift register instead of using it
for a fail comparison. This capture shift register is separate from the send shift register, although it
operates in the same direction, from LSB to MSB.
The data to be captured is loaded a bit at a time into the shift register. The pattern file then issues the
command to shift the acquired data: A=SHIFT. Once the data has begun to move towards the MSB in the
shift register, the next bit can be captured in the next T0 period. Typically, one channel is used to capture
the serial data, and the comparators of the adjacent channels are not used.
Once a series of bits is captured and arranged as desired in the capture shift register, the command
A=STORE is sent from the pattern vector file, and the word moves into the destination address of the
capture memory. Each A=STORE command moves another word into memory, at a subsequent address.
The pattern memory needs to have the code V entered to use the shift register as the destination for
comparator data instead of the normal pattern memory H or L. This can be changed on the fly, on a vector-
by-vector basis. The code V was chosen to designate Valid data.
9-9
Figure 9.9: Serial Capture Memory
Putting It All Together - Pattern and Send/Capture Memory
All four of the previous concepts are present concurrently in the DSPIO instrument, arranged as in the
following diagram. 512K of pattern memory per pin is loaded with parallel data and control commands, and
512K of serial send/capture memory per pin is also ready to be used on a vector-by-vector basis.
You can see that the Memory MUX control comes from pattern memory, as well as the control for SHIFT,
LOAD, and STORE. Pattern memory is significantly wider than 16 bits due to these extra features; the
actual memory word is 64 bits wide, and will be explained soon.
9-10
Digital Instruments
Figure 9.10: Memory Banks in the DSPIO
Memory Address Sequencer
So far, we have assumed that vectors are issued from pattern memory one at a time, one per T0 time
period, in sequential order starting at address zero. If this was strictly true, the instrument would not be as
useful as one where the test engineer can control the start address, and exercise more control over the
order (or sequence) that the vectors are issued.
So there is a microcoded memory address sequencer, with its own language, called op codes, for this
purpose. Further details of this language are explained in the section on Patterns, but here is a short
summary.
9-11
When testing devices, patterns are executed, or burst, beginning at start addresses noted by labels which
are embedded in the pattern source code. Digital patterns are written in a text-based form, but these are
not usable by the DSPIO hardware as is. Test systems traditionally include what's called a pattern
compiler to convert pattern source code (easy-to-read) format into a hex or binary format usable by the
instrument. The examples given so far in this chapter have all been in source code format. The pattern
compiler is detailed in a later section, but suffice it to say here that the source code files are the ones
generated by human typing.
Our original drive data sample pattern looked something like this:
000000 0 1 1
000001 0 0 1
000002 1 1 1
000003 1 0 1
000004 1 1 1
000005 0 0 1
The truth is that a full source code pattern has more possible fields, and the first column (the memory
address) is not part of the source code file.
; LABEL OP CODE CONDITIONAL ARGUMENT CHANNEL DATA OTHERS
STRT: 0 1 1
JMP (!U1) STRT 0 0 1
1 1 1 W=LOAD
1 W 1 W=SHIFT
1 1 1
HALT 0 0 1
These additional fields exercise the sequencer control and memory control commands. The commands
W=LOAD and W=SHIFT were introduced in the section concerning Send/Capture memory. They will be
more fully explained with examples, in sections to follow. The line beginning with the semicolon (;) is a
comment.
The Label field is a way to indicate where a pattern should begin its execution. When you load patterns
into memory, you may have a collection of many short useful series of vectors. You almost never wish to
execute them all at once, but instead specify where to begin a series of vectors. The memory address
could be specified for each pattern fragment that needs to be executed, but using labels is an easier-to-
read technique.
Op codes are the programming language that tell the sequencer to chose another address (perhaps)
other than the next one in order. You can repeat vectors, saving valuable pattern memory space. You can
have conditional op codes, that only operate if some condition is true. And some op codes take
arguments, which are usually the address to go to if the op code involves a jump.
Patterns are compiled using a KVD-supplied software tool, and saved to the hard drive. They are listed in
a structure called the PATLIST, loaded into the instrument pattern memory at the beginning of the test
program, and executed, or burst, when needed by the patexe command.
Clocking
All of this discussion so far has assumed that the DSPIO instrument is executing vectors at some data rate
called the T0 rate. To accomplish this, the instrument must first be programmed with a Master Clock, which
is always running at some multiple of the T0 rate. It is best if the multiplier can be 32 times T0, but it can be
as little as 4 times T0 or as high as 64. Hardware requirements insist that the Master Clock be between 15
MHz and 72 MHz.
When the instrument comes up in the reset state, it is automatically set to use an internal 40 MHz crystal
oscillator as the Master Clock. This may be perfectly sufficient for many test specifications. An alternate
phase-locked-loop is available in case you need frequencies other than those available by dividing down
the 40 MHz crystal.
9-12
Digital Instruments
The normal condition if you have multiple DSPIO instruments on each side of your test head is that the
lower number instrument (DSPIO0) is the Master, and others are Slaves, meaning that the Master Clock of
DSPIO0 synchronizes all instruments. This can be changed if necessary, since each DSPIO instrument
can act independently of the others.
Drive and Compare Voltage Levels
So far, we have also ignored the driver and comparator programming, but there are commands for each
channel (pin) available. Each pin can have a different high and low drive voltage, and comparator
threshold. You will see the DACs used for this function in the block diagram coming soon.
Formats and Edge Timing
Another deferred issue is one of the Data Formats. Before now, we have assumed that when the pattern
memory contains a 1, we will command the driver to go high, and a 0 will mean a drive low. As you know,
not all data formats are defined this way, and some go low for a 1, and high for a 0, as well as patterns that
are defined (such as RZ - Return to Zero) by their action before and after their valid time.
Also, one essential feature of a test system is to be able to place start and stop edges within a T0 time
period. The actual rising or falling edge of a driver may not occur at the exact beginning of the T0 cycle, but
there is often a START delay before the initial edge, and a STOP delay to define the trailing edge. The
comparator strobe is also located somewhere inside the T0 cycle, and can be programmed.
Therefore, there is a section of circuitry located between the memory data and the driver/comparator (pin
electronics) that handles the data formatting and timing edge placement. The actual data formats are
explained later, with examples of placing the edges. Basically, you can program a different data format for
each pin if you require, and place a timing edge at each boundary of the Master Clock.
So if you use a large multiple of T0 to define your master clock, such as 32, you will be able to place your
edges with the most resolution within your T0 time period. In this case every 1/32 of a T0. This is more fully
explained in the section on data formats.
DSPIO Patterns
DSPIO Patterns define the driver and comparator data, and control the Sequencer function. Each vector
has an independent Op-Code field with the following options supported:
1. Conditional or Unconditional Branching.

2. 16 deep Loop Counter Stack for Loops.
3. Subroutines.
4. 2 independent User Flags which can be used in conditional jumps and written from the test program.
5. Match Mode.
6. Serial or Parallel Drive/Capture Data Capability.
7. Time Set and Format Set Switching on the fly.
This section provides detailed information about the tool that will convert ASCII vector files into KVD vector
files.
9-13
KVD Pattern Editor/Compiler
The KVD Editor Compiler is a stand alone vector translation tool that will translate an ASCII pattern file to a
.bp file that can be loaded into the DSPIO pattern memory. By default this utility will be saved in the
"Programming Tools" directory as "KVD Pattern Editor and Compiler", which can be launched from the
Windows Start menu.
Input
This tool can be used to translate a single vector file or many at a time.
Output
All files that are translated will generate an output file. This file will retain the base filename of the input file
and will also have a .bp extension. (example: testfile.xx translates to testfile.bp). The translation process
is non destructive to the input file.
Rules
The format of the input file must adhere to several rules. Below is a list of the basic rules.
1. The first vector must contain a label. All lines prior to the first vector are tested for other information but
can contain no drive/compare information.
2. Comments are allowed, however no comment may contain a ':' character.
3. Channel lists are defined before the first test vector. The order in which the channels are defined will
determine the order that they should appear in the ASCII test vector. The complete channel list can be
comprised of groups of channels. Each channel in a group is delimited by a tab, space, or comma.
Channel numbers are limited to 0-63. A group of channels is preceded by the syntax .chmap as well as
a single field description of the pins.
4. Timesets can be defined prior to the first vector. There can be a maximum of 2 timesets defined. The
order that the timeset labels appear in the input file will determine their designation throughout the
pattern. The first timeset label defined will be designated as timeset "0" in the .bp file. If timesets are
not defined, the default timeset 0 will be used. A timeset is preceded by the syntax .tset.
5. Labels can be lower and upper case alpha-numeric combinations, however a label must start with an
alpha character.
6. The flag field must be delimited by simple parentheses. A '(' indicates the start of a flag field and a ')'
indicates the end of a flag field. No whitespace is allowed inside the field.
Vector Information
Mandatory Input Vector Fields

Channel Groups
Each input vector must contain drive, compare, or mask information for all channels defined in the header.
The format of this drive/compare information should be such that each channel group that is defined in the
header should have its own vector channel segment, delimited from the following and preceding segment
by a space or tab.
9-14
Digital Instruments
Example:
If the header contained:

.chmap name1 = {1,2,3}
.chmap name2 = {9,10,0,12}
then the input vector should contain 7 vector characters split into 2 groups, like this:
101 HLHL
000 LLLL
111 MMHL
Note that the .chmap designator is separated from the channel list by some descriptive name for the list.
Note that drive/compare characters are limited to the following:

1,0,h,l,m,x,H,L,M,X,v,V,w,W.
1 = Drive a digital HIGH (Driver Enabled)

0 = Drive a digital LOW (Driver Enabled)
h,H = Compare for digital HIGH (Driver = high impedance)
l,L = Compare for digital LOW (Driver = high impedance)
x,X = Don't care (Driver = high impedance)
m,M = same as "X" (Driver = high impedance)
v,V = Capture Data (Driver = high impedance)
w,W = Drive (Send) Data (Driver Enabled)
The upper and lower case 'x' and 'm' characters can be used to represent a high impedance state for the
driver, with no data comparison ("don't care"). The 'v' and 'w' characters are used for driving or capturing
data in the send/receive memory. Send/Receive is described later in this document.
Alternate Drive Format

It is possible to represent drive data for a group of channels as a hexadecimal number. This representation
should be preceded by a "dx" or "Dx" indicator.
Example:
For the header:

.chmap apins = {1,2,3}
.chmap bpins = {9,10,0,12,13,14,15,16}
Then the data:

101 00101001
could also be represented as:

101 Dx29
or
101 dx29
Optional Input Vector Fields

Label Info:
If the input vector contains a label representation, the label must be terminated with a colon character ':'.
The label must be the first character field of the input vector. Labels must start with an alpha (upper or
lower case) and can contain alpha-numeric characters.
9-15
Example of valid labels:

Vmax:
Foo42:
XyZZY:
Examples of invalid labels:

42Foo:
Start
Opcode Info:
The input vector may contain an opcode. This opcode should be represented by lower case. Most opcodes
can be conditionally executed, depending on flag conditions. Some opcodes are standalone, while others
require an operand.
Stand-Alone Opcodes:
halt
wait
return (can also be represented by "rtn")
Opcodes Requiring an Operand:

jmp
jmpr
repeat (can also be represented by "rpt" or "rep")
loadcnt (can also be represented by "lcnt")
call
callr
along
rlong
flags
control
note
Sequencer OpCodes
Note: In each of these cases the opcode should be followed by an operand (if called for) that represents
a label, an absolute address (in decimal) or a step index forward or backward from the current
vector. The relative addressing opcodes (jmpr and callr) must be followed by a relative operand,
not a label.
Opcode Function Conditional Operand
wait wait for condition Y None
halt halt execution optional none
jmp jump to vector optional address
jmpr jump to vector (relative) optional relative address
repeat repeat vector optional repeat count
loadcnt load the loop counter optional Loop counter value
call call subroutine optional address
callr call subroutine (relative) optional relative address
9-16
Digital Instruments
Opcode Function Conditional Operand
return subroutine return optional none
along extend absolute N address

address
rlong extend relative address N relative offset
flags set or clear flags optional flag bits
control set control bits for fail optional control bits

record
note store fail fifo registers optional register
Table 9-1: Description of Opcodes
Examples of relative addresses:

. (also called dot), defined to be the current vector address
.+n the vector address "n" beyond the current vector
.-m the vector address "m" previous to the current vector
Opcodes are executed AFTER the vector data is used (driven or compared).
Flags
The condition of several flags can be used to determine pattern execution. The most common flags are the
User Flags (U1 and U2) and the Loop Counter Flag (L). All flags can be tested for being set or not-set.
(Place a "!" in front of the flag to test it for being not-set.)
The normal status of User Flags is not-set, and if set true by the external dflags command, the next time
they are evaluated in the pattern, they are automatically reset to false.
Flags must be surrounded by parentheses, and there can be no spaces included.
Flag Name Set true by Clear
U1 User 1 dflags Command Use or Flag Control Bits
U2 User 2 dflags Command Use or Flag Control Bits
M Match Formatter Match No Match
LM Latched Match Previous Match Use or Flag Control Bits
L Loop Counter Loop Counter=0 Use or Flag Control Bits
F Fail Formatter Fail Control Bits
V Vector Flag Control Bits Use or Flag Control Bits
Table 9-2: Flag Bits
Example:
operation result
wait (U1) wait on this vector until User Flag U1 is set
jmp (!L) .-5 jump back 5 vectors if loop counter flag is not set (counter!=0)
9-17
Note: Each time the loop counter flag is tested, the loop counter is decremented by one.
Pattern Syntax
Examples of Proper Pattern Syntax:

.chmap MYCHAN = {1,3,6}
.chmap XYZ = {7,8,9,10}
strt: MMM LLLL
loadcnt 100 MMM LLLL (could also be "lcnt")
jmp (!L) . MMM 1010
jmp strt MMM LLLL
Examples of Incorrect Syntax:

.chmap MYCHAN = [1,3,6](incorrect brackets)
.chmap XYZ = {7,8,9,99}(99 exceeds max channel #)
MMM LLLL (first vector needs a label)
loadcnt 100 MMM LLDL (wrong drive-compare character)
jmp ( !L) . MMM 1010 (whitespace in flag field)
jmp strt MMM LLLL (no "strt" label)
Timeset Info
Each input vector may contain timeset information. The timeset field should follow the last vector field and
should start with a 'T=' character set. If the input vector contains no timeset, the previous timeset is loaded
into the .bp file for this vector. If the timeset is not defined in the header, an error will result. If no timesets
are provided in the pattern vectors, timeset 0 will be loaded for all vectors. The actual edge placement
information for the timeset is defined outside the pattern, by the dfmt command.
Note: Hardware implementation is currently limited to two timesets.
Example:
In header:
.tset write
.tset read1
MMM LLLL T=write
MMM LLLL (uses the "write" tset)
MMM HHHH T=read1
Note: Formats and timesets may be switched on the fly (i.e.: from vector to vector) UNLESS you are
switching to or from NRZ format. This is due to a limitation of the hardware implementation of the
NRZ format.
Fail Disabling
It is possible to disable the fail flag and fail register on a vector-by-vector basis. This will allow for the
execution of a vector without changing the fail flag or fail register, regardless of data. The Fail Disable (FD)
bit is automatically set on vectors where a match condition is qualified. The FD bit can also be set on an
arbitrary vector basis. To set the FD bit, the syntax "F=off" should follow the timeset information (or the
data where no timeset is given). See the later example for details.
9-18
Digital Instruments
Serial/Parallel Send/Receive
Note there is also a send/receive capability. If this feature is used, the appropriate extended microcode
should be included after a timeset (or after a fail disable statement if applicable) but before a comment.
For the most part, common conventions were followed for the send/receive syntax. Channels that will
receive data from the device are represented by a 'v' or a 'V' character. Channels that will send data to a
device are represented by a 'w' or a 'W' character. The control operation of the send and receive shift
registers are represented as follows:
W=load (or W1=load) ;loads a parallel word to the shift register from memory
W=shift (or W1=shift) ;shifts left all bits in the drive register (DDCH0 = lsb)
A=store (or A1=store) ;stores a parallel word from the shift register to memory
A=shift (or A1=shift) ;shifts left all bits in the capture register (DDCH0=lsb)
Note that there are some constraints on using the send and receive memory. Since the drive (send) and
capture (receive) shift registers share the same bus, it is not possible to 'load' and 'store' on the same
vector cycle. All other combinations are valid.
It is best to visualize the shift register operation as occurring at the end of the T0 cycle. Also, do not
perform a capture on the last two vectors of a pattern, but pad with at least two dummy vectors.
Channel Default
Normal operation of this translator will only operate on the channels that are defined in the header portion
of the file. All undefined channels will be set in a high impedance mode when the pattern is run. There
could possibly be a case where it is desirable to set all the undefined channels to either a high or low drive
condition. The following syntax, when added to the header, will accomplish this.
.chdefault HIGH
.chdefault LOW
Note that it is also possible, although not necessary, to define the .chdefault as HIZ or MASK.
The user should be advised that although this feature is present, it should be used with extreme caution.
Use this feature sparingly when there are no alternatives ( example: a pattern exists that uses 15 channels
but all the undefined channels need to be set to drive low and there are 30K vectors to modify).
Improper consideration when using this feature could result in damaged devices or DSPIO drivers and is
not normally a reasonable way to treat your ATE system.
9-19
Pattern Example
;
;****************************************
;
;DEFINE GROUPS
;--------------------
.chmap INDATA = {7,6,5,4,3,2,1,0}
.chmap OUTDATA = {23,22,21,20,19,18,17,16}
.chmap TRIG = {8}
.tset t0
.chdefault HIZ
;****************************************
;
;
;
; IN OUT
; M M
; S S
; B B
;----------------------------------------
TEST_PATTERN: 00000000 XXXXXXXX 0
00000000 XXXXXXXX 1
00000000 LLLLLLLL 1
00000001 LLLLLLLH 1
00000010 LLLLLLHL 1
00000011 LLLLLLHH 1
00000100 LLLLLHLL 1
00000100 LLLLLHLH 1 F=off ; comment
rpt 10 00000000 XXXXXXXX 0
HALT 00000000 XXXXXXXX 0
;----------------------------------------
CAPTURE_DATA: 00000000 XXXXXXXX 0
lcnt 256 00000000 XXXXXXXX 0
WWWWWWWW XXXXXXXX 1 W=LOAD ;
jmp (!L) .-1 WWWWWWWW VVVVVVVV 1 A=STORE ;
WWWWWWWW XXXXXXXX 0
HALT WWWWWWWW XXXXXXXX 0
Compiled Pattern
.bp file (binary pattern)

CHANNELS 32
VECTOR
00000000 00000000 22222222 00000002 00000000 00000000
00000001 00000000 22222222 00000003 00000000 00000000
00000002 00000000 22222222 00000003 88888888 00000000
00000003 00000000 22222223 00000003 8888888C 00000000
00000004 00000000 22222232 00000003 888888C8 00000000
00000005 00000000 22222233 00000003 888888CC 00000000
00000006 00000000 22222322 00000003 88888C88 00000000
00000007 80000000 22222322 00000003 88888C8C 00000000 ;comment
00000008 0040000a 22222222 00000002 00000000 00000000
00000009 00100000 22222222 00000002 00000000 00000000
0000000a 00000000 22222222 00000002 00000000 00000000
0000000b 00500100 22222222 00000002 00000000 00000000
0000000c 06000000 11111111 00000003 00000000 00000000 ;
0000000d 022d000c 11111111 00000003 44444444 00000000 ;
0000000e 00000000 11111111 00000002 00000000 00000000
0000000f 00100000 11111111 00000002 00000000 00000000
Note: The *.bp file format is shown here as an example.
The first column is the memory address for the vector.
The second column is the 32-bit (8 byte) control word for the vector. The first 16 bits represent the Fail
Disable bit, TSet select, Negative Offset bit, Shift Register control, Opcode, and Conditional Flag. The
second 16 bits represent the address and control bits of the Operand.
9-20
Digital Instruments
The rest of the file, in this case four columns for 32 DSPIO channels, is the vector data, arranged as
follows:
DSPIO 0 DSPIO 0 DSPIO 1 DSPIO 1
Low 8 Channels High 8 Channels Low 8 Channels High 8 Channels
76543210 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
.sym (Symbol Table)
A symbol table is also generated by the pattern compiler, for ease in starting a pattern burst at a named
label, instead of needing to define the physical memory start address. Use of the symbols is explained
later.
For the sample pattern given above, this is the symbol table:
TEST_PATTERN = 0
CAPTURE_DATA = 10
Pattern Editor/Compiler Screens
Figure 9.11: Pattern Editor Screen
9-21
Figure 9.12: Pattern Compiler Screen
Pattern Editor
The KVD Pattern editor and compiler has many new features than in previous releases. Starting with rev
5.01, digital pin information (format, timing, and levels) can be set up with the pattern. The timing and the
pattern can then be viewed graphically, as you would see it on a logic analyzer.
Start->Programming Tools->Pattern Editor and Compiler
This is the code view display of the new Pattern Editor and Compiler Tool, which appears very similar to
the previous tool:
Figure 9.13: Pattern Editor and Compiler Tool - Code View
9-22
Digital Instruments
This is the editor, using column edit mode (click the box to activate this mode):
Figure 9.14: Pattern Editor and Compiler Tool - Column Edit Mode
This is a new FIND dialog box:
Figure 9.15: Find Text Dialog Box
9-23
And this is a new REPLACE dialog box:
Figure 9.16: Replace Text Dialog Box
And a GOTO LINE # dialog box, to make it easier to jump around in large pattern files:
Figure 9.17: Go To Line Number Dialog Box
9-24
Digital Instruments
This is the new Graphical View, with the vectors increasing horizontally, in contrast to the code view, where
the list of vectors is vertical.
Figure 9.18: Pattern Editor and Compiler Tool - Graphical View
In this Digital Pin Format View, each channel's mnemonic name, format, timing (for each time set) and
level is summarized.
Figure 9.19: Pattern Editor and Compiler Tool - Digital Pin Format View
9-25
Finally, if you click the Master Clock Setup button, you will see this tool to aid you in connecting the
various clock sources.
Figure 9.20: Master Clock Setup Tool
The goal of the pattern tool has changed to more of a comprehensive digital setup tool, since now it can be
used for all digital setups.
Online help has also been added. Complete documentation will be provided in an upcoming manual
release, or contact your KVD Applications Engineer for personal assistance.
DSPIO Program Structure

Here is a list of required steps when using the DSPIO, and the frequency at which they should be
performed. Several tasks need only be done during program initialization, while others might require more
frequent adjustment.
One Time (in SystemInit or LotInit)
• Define PATDATA
• Loading compiled patterns into Pattern memory
• Assigning Pattern Symbols
• Loading Send/Capture Memory if applicable
9-26
Digital Instruments
At Least One Time (Location of Your Choice)
• Set up clocking - frequency and master/slave relationships

• Pin driver and comparator levels
• Pin formats and edge timing
• Enabling the desired pin drivers
• Set up send/capture memory
Every Time (Inside TSeq, the Mainloop Test Sequencer)
• Ensure DSPIO Connections through Father Card to the DUT

• Parametric/continuity measurements
• DSPIO functional operation
• Bursting (executing) the Patterns
• Pattern comparisons for fails
• Check fail flag if applicable
• Serial send/capture activity
Defining PATDATA
PATDATA is a structure that you use to manage your pattern memory. More than one compiled pattern file
can be loaded into the DSPIO vector RAM, and they need to be enumerated just once in your test
program, typically in SystemInit.
// PATDATA Structure
/*
typedef struct {int id;
char filename[1000];
unsigned bank;
unsigned long address;
long length;
int loadflag;
int haltflag;
int retestpat;
} PATDATA;
Here is a sample definition:

{0, "Demo1.BP", 0, 0UL, 100UL, 1, 2, -1},
{1, "Demo2.BP", 0, 200UL, 50UL, 1, 2, -1},
{-1, "NOPATT", 0, 0UL, 0UL, 0, 2, -1}
};
The lines beginning with // are comments, to aid remembering in what order the arguments appear. You
will find a template for this in your typical blank program, in UserClass.cpp.
The ID number should be an integer starting at 0, and increment by one for every entry. If you wish to load
multiple compiled patterns into your pattern RAM, you will need to manage the start addresses and lengths
to make sure they don't overlap each other in your bank of memory.
The line that begins with an ID of -1 is a dummy entry, defining the end of the list. Always just copy this at
the end of your own list without modification.
9-27
The filename is the name of the valid .bp file you wish to use. They are assumed to reside in the local test
program folder unless you change the PATDIR variable, or explicitly name the folder in the patload
command.
The BANK field is currently not used, and is ignored. Please leave it as 0.
OFFSET is the start address in memory where the pattern is to be loaded.
LENGTH represents your entry of the size of the pattern file in vectors. pat_load fills in the actual number
of vectors stored.
LOADFLAG needs to be a 1 for pat_load to load the pattern (useful only for skipping large patterns while
debugging).
HALTFLAG, RETESTPAT are legacy flags, left over from a previous KVD digital implementation, retained
for backwards compatibility. They can be safely ignored.
DSPIO Pattern Loading into Send Memory
At one time, usually in an initialization section of the program such as LotInit, you need to load the pattern
memory of the DSPIO instrument with your compiled pattern. Do not do this within Tseq, since that
function is executed once per device, and loading the patterns repetitively would be a waste of time.
Loading the pat_list into DSPIO Memory

Once defined, the pat_list needs to be loaded from its hard disk (or network) location using the patload
command. The arguments are pat_list (the array you have previously defined) and the patdir (the
directory containing the named .bp files). This is usually executed in LotInit.
Example:
DIG0->patload(pat_list,"c:\\your_test_program\\");
You should normally add a delay after this of a few hundred milliseconds to allow the command to
complete before continuing along in your program.
Set Object Variable DIG0->peekmode = 0 to have the patload command not verify pattern loads to speed
pattern loads.
9-28
Digital Instruments
This is a picture of what your pattern RAM would contain after you loaded the pat_list defined by the
previous example:
Figure 9.21: Pattern RAM Memory Management
DSPIO Clocking & Synchronization

There are several methods for providing coherent clocking between the various system modules (DSPIO,
WS, and WD). It is important to note that any one of these modules can provide the "master" clock for the
system. It is equally important to note that once the master clock source has been determined, the user is
responsible for connecting the master clock to each "slaved" module. This connection is differential ECL
for the WD and WS inputs and outputs. The connection is differential LVDS for the DSPIO module. The
hardware connections are made on the Fathercard. Note that it is important to run the module DSP clocks
(TICLK) as fast as possible to insure fastest DSP processing times. The TI processor clock can run as fast
as 30MHz (TICLK up to 60MHz).
Notes:
1. The DSPIO system cannot operate properly with an MCLK less than 15MHz.
2. The DSPIO system cannot operate properly with an MCLK greater than 72MHz (unless you have all
DSPIOR4 instruments, in which case it is 80MHz).
3. The Maximum MCLK to Pattern divide-down ratio is 64, minimum is 4.
• The slowest Pattern rate (t0) is 15Mhz/64 = 234Khz.
• The fastest Pattern rate (t0) is 72Mhz/4 = 18Mhz.
9-29
Figure 9.22: Digital Clocking Block Diagram
Instrument-level Software Commands
DSPIO instrument commands are issued to the DIG0 object for the first instrument Master and any slaves
can be addressed as DIG1-3. The DIG0 object will also operate correctly for reading back the fail register
for the first 32 channels, even though it crosses a board boundary.
Reset
The reset function initializes the instrument.
Example:
DIG0->reset();
These are the clock defaults:

DIG0->dconfig(DDMASTER); // the first DSPIO board is the master
DIG0->dmclkconfig(DDMCLK_SOURCE); // first board is the master clock source
DIG0->ddclock(NOCLK, REFCK0); // turn off clock to PLL
DIG0->ddclkena(0); // disable clock to fathercard
DIG0->ddclock(OSCCLK, MCLK); // 40MHz OSCCLK is the master clock
// All other boards are SLAVES
9-30
Digital Instruments
These are the channel defaults:

Format = RZ
Driver Disabled
Timing at 0.0nS
Patload
The patload function loads your predefined pat_list into the pattern memory. Large patterns can take some
time to load, so you should characterize this in your debugging, and add a suitable delay so as to not
continue on prematurely.
Example:
DIG0->patload(pat_list,"c:\\your_test_program\\");
You may define a variable PATDIR to be the second argument, especially if you are loading patterns from
a location other than the folder containing your test program executable.
Patexe
The patexe function bursts your desired pattern at some starting offset address. Typically, you use some
file to assign names to these index numbers and offset addresses.
Example:
DIG0->patexe(<index number>,<offset address>);
The index number is the integer given the pattern file in the loaded pat_list. The offset address is the
beginning relative memory address of the vector at which you wish to begin the burst. However, this is not
very easy to read later, and convention suggests that these be assigned names in some module of your
test program.
For instance, if your file contained the following:

unsigned SIMPLEPATT = 0;
unsigned CLK_ON;
unsigned CLK_OFF;
unsigned BINARY;
And you included and called some function such as:

short GetPatternSymbols()
{
CLK_ON = DIG0->getsym(SIMPLEPATT,"CLK_ON");
CLK_OFF = DIG0->getsym(SIMPLEPATT,"CLK_OFF");
BINARY = DIG0->getsym(SIMPLEPATT,"BINARY");
return(0);
}
The getsym command reads the symbols from the <pattern>.sym file, created by the Pattern Compiler,
and located in the local test program folder.
Then you could issue much easier to read patexe commands of the form:
Example:
DIG0->patexe(SIMPLEPATT, CLK_ON);
9-31
Dstop
The dstop function halts any running pattern, whether or not the pattern has halted on its own.
Example:
DIG0->dstop();
Dwait
The dwait function waits for the execution of a running pattern to finish by itself, or timeout. Normally, when
you burst a pattern with patexe, control returns immediately to your C code. If you wish for the pattern to
finish before executing any more code, use dwait. The timeout value is specified by the DIG0-
>dwaittimeout variable, whose default value is 1 second. You need to specify the side of the test head that
you are addressing in this command.
Example:
DIG0->dwait(1);
Failure Results
There are three functions that return information from the fail registers. One is the simple dfail, which
returns a non-zero number if there was any pattern comparator failure in a burst pattern. Note: the fail
pipeline is ten vectors long, so at the end of any pattern where you make a comparison, you need to add at
least ten dummy vectors after the last comparison, in order to flush out the pipeline. These commands take
the test head side as the argument.
Example:
status0=DIG0->dfail(1);
SITE->lastresult.value=status0;
If you need to know the raw address of the first failing vector, use the dfailaddr function.
Example:
addr0=DIG0->dfailaddr(1);
SITE->lastresult.value=addr0; // for datalogging
If you need the list of failing channels in the first failing vector, use the dreadfail function.
Example:
chanfail0=DIG0->dreadfail(1);
SITE->lastresult.value=chanfail0; // for datalogging
Dclr
The dclr function needs to be called to clear the fail flags of all instruments, because the dfail function by
itself does not.
Example:
DIG0->dclr();
9-32
Digital Instruments
Dflags
The dflags function sets the User Flags U1 and or U2. These flags can be used in patterns as conditional
operands for jumps or waits, expecting the user flag to be set from C code or from the debugger outside
the pattern. Using 1 as the argument sets U1, 2 sets U2, and 3 sets both flags. Once set, the conditional
evaluation inside the pattern clears the flags so they can be reused right away in the pattern.
Example:
DIG0->dflags(1);
Master Clock Selection

As shown on the clocking block diagram, there are three major choices for the clock MUXes. If you are
using the PLL, you need to choose one source for its input REFCK0 from the three choices OSCCLK,
DISCLK, or XCLKIN. For the MCLK mux, you need to choose among PLLMCLK0, OSCCLK, DISCLK, or
XCLKIN. If you are using the XCLKOUT mux to send a master clock up to the father card for distribution to
other modules, you have the same four choices as the MCLK mux.
Example:
DIG0->ddclock(<source>,<destination>);
DIG0->ddclock(OSCCLK,MCLK);
If you are using the PLL to obtain frequencies other than those available from the 40MHz crystal OSCCLK,
you will be entering P, Q, and M parameters to program the PLL. These parameters can be obtained using
the Bitcalc utility, or preferentially through the use of a function we are distributing recently called findpq.
See your KVD applications engineer if you don't already have a copy of this function in your standard local
libraries.
Basically, the PLL will output a frequency that is the input reference frequency (typically 40MHz if you are
using the OSCCLK) * P / Q / 2M, when programmed by the ddpllbits command.
Example:
DIG0->ddpllbits(P,Q,M);
DIG0->ddpllbits(96,60,1); // gives you 64 MHz
dt0t
The dt0t function sets the pattern burst rate for a specified time set. It assumes you have previously
selected a master clock source, and programmed its frequency (if you chose the PLL), and then issued the
command DIG0->set_DDXTALFREQ();. This sets all of the software registers to your desired MCLK
frequency. Then, the dt0t function is what calculates the integer divisor that we are to use to divide down
the Master Clock.
Example:
DIG0->dt0t(<timeset>,<T0 frequency>);
You have two possible timesets, which can be chosen on the fly by the pattern file. The actual edge
placement definitions are handled in the per-channel command dfmt, explained later.
Example:
DIG0->set_DDXTALFREQ();
DIG0->dt0t(0,2e6);
9-33
The Master Clock should be chosen as high as possible, to provide the maximum number of edges per T0
period at which the formatter can place timing transitions, and in any event must be between 15MHz and
72 MHz. The minimum divide-down ratio is 4, while the maximum is 64. At ratios above 32, you lose the
use of the second timeset due to command word limitations, so use this feature with care. If you require an
extremely slow T0 time period, you may wish to use vector stretching techniques such as adding op codes
such as RPT 10 or RPT 100 to each vector.
Send/Capture Memory Setup

The send memory is not loaded from a hard disk-based pattern file, but typically is loaded from a data
array, defined by the test engineer or loaded by an algorithm. You need to specify the beginning address in
memory, the number of addresses you are loading, and the name of the data array. Here is an example
where the array is called ddata, it contains 256 elements, each with a value equal to its address, and it is
being loaded into send memory starting at address 0.
Example:
unsigned ddata[256];
for (int i=0;i<256;i++)
ddata[i]= i;
DIG0->ddrv_load(0L, 256, ddata);
Once loaded with data, the send memory is configured to be the source of data to the send shift register by
the use of the ddrv_setup command. Each W=LOAD command in the pattern file will take data from send
memory beginning at the initial address.
Example:
DIG0->ddrv_setup(0L,256);
The sequencing of memory addresses within send/capture memory is under control of the TI DSP
controller, and can be set up in three major modes. These are explained in a little more detail in a later
section, but almost universally are used in AUTOMODE, which operates at the highest frequencies, and
sequences purely serially through send memory without jumping. When the sequencer comes to the end
of the predefined setup send memory, it wraps back to the beginning address in a repeating fashion.
This command applies to both send and capture memory control, since there is only one TI DSP controller.
Example:
DIG0->dcap_drv_en(AUTOMODE);
If you are also capturing serial data into capture memory, you need to configure the destination memory
region in a similar way, with a start address and vector count. Good practice is to separate the capture
destination region from any send region. A=STORE commands from the pattern file will write words of data
into this setup memory region.
Example:
DIG0->dcap_setup(512L,256);
Once you start the data capture process by bursting a pattern, you will probably want to wait until the
proper number of words have been captured. This command requires the side argument.
Example:
DIG0->dcap_wait(1);
Finally, to reclaim the captured data for use in your code, you use the dcap_read command to fill a
destination data array. The arguments are: side, start address, length, and array name.
9-34
Digital Instruments
Example:
DIG0->dcap_read(1,512L,256,cdata);
DSPIO Channel Commands

Once you have programmed the DSPIO using the instrument-level (DIG0) set of commands, you need to
set up the individual channel attributes using the DDCH objects.
Data Formats
Plus HIGH, LOW, CLOCK/2, CLOCK/4, and CLOCK/8

Figure 9.23: Timing Diagrams of the Various Formats
Main Formats
• NRZ - Non-Return to Zero (Between the start and stop edge, the data is high or low, and it stays where
it was after the stop edge.)
• RZ - Return to Zero (Data always goes or stays low after the stop edge)
• RZC - Return to Zero Complement (The inverse of RZ)
• RO - Return to One (Data always goes or stays high after the stop edge.)
• ROC - Return to One Complement (The inverse of RO)
• CS - Complement Surround (No matter what the data is, high or low, during its valid time between start
and stop, it goes to the opposite level. Guaranteed to have at least two transitions per T0.)
• CSC - Complement Surround Complement (inverse of CS)
• T0 - T Zero - the typical name for the Data Rate of a Digital Subsystem. Every T0 tick means another
vector has been executed from pattern or send/receive RAM.
9-35
Master Clock must be running at least four times faster than your T0 rate. Start and Stop edges can placed
only at the next available transition of the Master Clock, which basically means your edge timing is
rounded up to the next available MC edge. If possible, use a MCLK of 32 times your T0 rate. If you use 64
times, the second time set is unavailable.
Each T0 contains one vector's worth of formatted data. The data is defined in the pattern. The levels are
defined in the dlevel command and edge placement is defined in the dfmt command.
Other Formats
• High
• Low
• Master Clock/2
• Master Clock/4
• Master Clock/8
Note that these additional formats are "pattern independent" meaning that a static format will be generated
regardless of the pattern content, but only if one of the following two statements is true:
• Pattern is halted and the channel is enabled
Or
• Pattern is running and a valid drive symbol (0,1) is being sent (in other words, not tri-state)
Start and Stop Timing for the above waveforms are derived from the Master Clock and a per pin fine delay
line. Likewise for the per pin Comparator Edge Strobe.
Pin Electronics
The Pin Electronics/MUX of the DSPIO allows the following connections:

• A DUT Source through "DD Bus A" on the Motherboard backplane (MPDS[0])
• I/O digital functional
• Calibration Path for level calibration
9-36
Digital Instruments
Figure 9.24: Pin Electronics Block Diagram
Channel Software Functions
DSPIO channel objects are of the form DDCH[<channel number>][<side>], and of type TDigPin.
Example:
DDCH[1][0]
Multisite Objects
Channel objects may be declared of type TGroupDigital, if you wish to send them commands as a group,
or TSiteDigital, if you are writing a multisite test program. Site-aware objects can be enabled and disabled
when needed by the site management feature of the KVD library.
Example declaration in resources.cpp:

TSiteDigital* CLKIN;
Example declaration in resources.h:

extern TSiteDigital* CLKIN;
Example definition in InitUserResources():

CLKIN = new TSiteDigital (DDCH[12][1], DDCH[44][1]);
9-37
Enable or Disable the Driver
You should ensure through connection commands that the output relays of the DSPIO channels are
connected to their Hypertronics pins. These will typically be defined in a module like connections.cpp, and
the names are normally similar (but do not need to be identical) to DDDRV_TO_DDCH[1][1]->con();.
To electronically enable or disable the pin driver, you need to issue these commands for any channel of
interest:
Example:
DDCH[1][0]->enable();
DDCH[1][0]->disable();
Format and Timing
The dfmt command handles the definition for each of the two possible timesets for each channel. The
arguments are as follows: timeset (0 or 1), format (RZ, NRZ, CS, RO, RZC, CSC, ROC, HIGH, LOW,
CLK2, CLK4, CLK8, NOFORM), start edge timing (delay from beginning of T0), stop edge (delay from
beginning of T0), keepalive (0 or 1).
Example:
DS[1][0]->dfmt(0,NRZ,100e-9,800e-9,0);
Keepalive is a feature of a pin where it may be programmed to continue to generate edges even after a
pattern finished bursting. If the keepalive bit is one, and the data format is such that it generates transitions
even when the data is a continuous one (such as RZ format), then a pin in keepalive mode can be used as
a continuous DUT clock.
Note:Note that the last argument - KEEPALIVE - is NOT a keepalive enable control. KEEPALIVE mode is
always enabled whenever a pattern is not bursting. The argument is only the data (1 or 0) sent to the
formatter during KEEPALIVE time.
Comparator Strobe Time
The dcomp command handles the definition for each of the two possible timesets for the comparator
strobe time.
Example:
DS[1][0]->dcomp(0,500e-9);
Drive and Compare Levels
The dlevel command defines the VIL (drive low), VIH (drive high), and [optionally] the comparator level.
KVD comparators are a single-level compare, not a window.
Example:
DS[1][0]->dlevel(0.7,4.5,2.2);
RTI Support
The setname command defines the string that will replace the DDCH object name on the RTI debug
display. For each channel, you can assign meaningful names for use in the test program with a simple
assignment. To also modify the RTI debug display, use setname.
9-38
Digital Instruments
Example:
SCLK = DDCH[8][1]; SCLK->setname("SCLK");
SDATA = DDCH[7][1]; SDATA->setname("SDATA");
INCLK = DDCH[0][1]; INCLK->setname("INCLK");
SDATB = DDCH[24][1]; SDATB->setname("SDATB");
Summary of Other Commands
DIG0 >dcap_drv_en
short dcap_drv_en(DIG0TIMODE mode);
DIG0 >dcap_read
short dcap_read(unsigned side, unsigned long cap_adr, unsigned long cap_count, unsigned
cap_data[]);
DIG0 >dcap_setup
short dcap_setup(unsigned long cap_adr, unsigned long cap_count);
DIG0 >dcap_wait
short dcap_wait(unsigned side);
Returns:
DIG0 >dclr
Clears the pattern fail flags for all DSPIO boards.
short dclr();
DIG0 >dconfig
Sets the MASTER/SLAVE configuration of the DSPIO board
unsigned dconfig(DCONFIG config);
DIG0 >dd_xclkinfreq
Returns the xclkin frequency via the array parameter passed in. The values represent the xclkin for each
side.
void dd_xclkinfreq(double freq[]);
DIG0 >dd_xclkoutfreq
Returns the xclkout frequency for both sides. The values are passed back in the array passed in.
void dd_xclkoutfreq(double freq[]);
DIG0 >ddclock
Creates one of several paths that clock generation can be used throughout the system. See the Digital
Clock setup tool to view the possible MUX connections.
unsigned ddclock(DSPCLOCK src, DSPCLOCK dest);
9-39
DIG0 >ddpllbits
Function used to set the p, q, and m bits obtained by using bitcalc.
unsigned ddpllbits(unsigned p, unsigned q, unsigned m);
DIG0 >ddrv_load
short ddrv_load(unsigned long drv_adr, unsigned long drv_count, unsigned drv_data[]);
DIG0 >ddrv_load_side
short ddrv_load_side(unsigned side, unsigned long drv_adr, unsigned long drv_count, unsigned
drv_data[]);
DIG0 >ddrv_load_side_mask
short ddrv_load_side_mask(unsigned side_mask, unsigned long drv_adr, unsigned long drv_count,
unsigned drv_data[]);
DIG0 >ddrv_setup
short ddrv_setup(unsigned long drv_adr, unsigned long drv_length);
DIG0 >dfail
Returns a non-zero number indicating a pattern fail on the side selected.
short dfail(unsigned side);
DIG0 >dfailaddr
Returns the RAW address of the last pattern address to cause a fail.
unsigned long dfailaddr(unsigned side);
DIG0 >dflags
Sets the U1, U2, or both flags.
short dflags(unsigned value);
Description:
Patterns can be written with loops that occur, or execution paths that occur based on User flags U1 and
U2. The test program can set these flags at the appropriate time in the test flow with a cal to this function.
DIG0 >dmclkconfig
Sets the master clock configuration.
unsigned dmclkconfig(DMCLKCONFIG mclkconfig);
Parameters:
DMCLKCONFIG mclkconfig
One of the valid values in DMCLKCONFIG
9-40
Digital Instruments
DIG0 >dreadfail
unsigned long dreadfail(unsigned side);
Description:
Can now be called by the individual DIG[x] and return those failed channels for backwards compatibility
DIG[0]->dreadfail will return both DIG[0] and DIG[1] channels.
DIG0 >dstatus
short dstatus(unsigned side);
DIG0 >dstop
Stops any currently running pattern.
short dstop();
DIG0 >dt0t
Set the pattern burst rate (t0) for a specified time set.
unsigned dt0t(unsigned tset, double t0freq);
DIG0 >dwait
Wait for the execution of a pattern to complete, or time out.
short dwait(unsigned side);
Description:
The function waits until it see either the pattern finish, or times out. The time out value is specified by the
DIG0 >dwaittimeout variables value. If the time out happens the pattern fail flag will be set.
DIG0 >dwaitfail
Combines the dwait function and the dfail function into one command.
double dwaitfail(unsigned side);
DIG0 >dwaitnofail
Same as the dwait command, but will not set the dfail flag on pattern time out.
short dwaitnofail(unsigned side);
DIG0 >dxclkena
unsigned dxclkena(unsigned ena);
DIG0 >getsym
Looks in the symbol file generated by the pattern compiler for the address of the symbol.
int getsym(unsigned pattern, AnsiString symbol);
9-41
Parameters:
unsigned pattern
The index number of the pattern in the pat_list.

AnsiString symbol
The string that corresponds to the symbol. This is the same string as was in the pattern.
Description:
When patterns are compiled with the KVD Pattern compiler, a symbol file is generated with the same name
as the pattern file, but with the .SYM extension. The getsym function looks up the pattern file name and
path that were entered when the patterns were loaded with the patload command. It then looks for the
corresponding SYM file, and then looks in the file for the SYMBOL requested (see second parameter). If
the symbol is found in the file, the address offset of that symbol will then be returned.
DIG0 >patexe
Executes a pattern by index, at a specified offset.
short patexe(unsigned pattern, unsigned offset);
Parameters:
unsigned pattern
A value that is the index number of the pattern in the pat_list loaded.
unsigned offset
The offset from the beginning of the pattern.
Description:
The pattern index refers to the index number in the pat_list loaded in.
DIG0 >patexe_sym
Executes a pattern by index and symbol offset.
int patexe_sym(unsigned pattern, AnsiString symbol);
Parameters:
unsigned pattern
The index number of the pattern in the pat_list.

AnsiString symbol
The string that corresponds to the symbol. This is the same string as was in the pattern. symbol.
Description:
This function is the same as calling the getsym command, followed by calling the patexe command.
However, by looking up the symbol from a file before execution, the total execution time is considerably
slower.
9-42
Digital Instruments
DIG0 >patload
Loads an array of patterns.
short patload(PATDATA* pat_list, char* pat_dir);
Parameters:
PATDATA* pat_list
An array of patterns to be loaded.

char* pat_dir
The path to the pattern files to be loaded.
DIG0 >patload1
Loads one pattern specified in the pattern list.
short patload1(PATDATA* pat_list, char* pat_dir, int i);
Parameters:
PATDATA* pat_list
An array of patterns to be loaded.

char* pat_dir
The path to the pattern files to be loaded.

int i
The number (index) of the pattern to load.
DIG0 >reset
DIG0
short reset(void);
DIG0 >set_DDXTALFREQ
Sets the ddcont->DDXTALFREQ for each side by reading parameters from ddcont->ddclk and ddcont-
>ddclkfreq.
void set_DDXTALFREQ(void);
DDCH[i][1] >dcomp
Sets the comparator strobe time for a specific time set.
short dcomp(unsigned tset, double strobe);
Parameters:
unsigned tset
The time set, either 0 or 1.

double strobe
The strobe time value.
9-43
DDCH[i][1] >dfmt
Command used to format the digital pin timing.
short dfmt(unsigned tset, FORMAT format, double start, double stop, unsigned keepalive);
Parameters:
unsigned tset
The time set, either 0 or 1

FORMAT format
RZ, NRZ, CS, RO, RZC, CSC, ROC, HIGH, LOW, CLK2, CLK4, CLK8, NOFORM
double start
The time of the start edge.

double stop
The time of the trailing edge.

unsigned keepalive
The keepalive mode, either 0 or 1.
DDCH[i][1] >dfmt_long
short dfmt_long(unsigned tset, FORMAT format, double start, double stop, unsigned keepalive);
DDCH[i][1] >disable
Disables the drive capability of the digital pin.
short disable();
Returns:
Always 0.
DDCH[i][1] >dka
Sets the keepalive mode for the digital pin.
short dka(unsigned keepalive);
Returns:
Always 0
Description:
When a digital pattern is NOT running, the digital pin stays at a constant logical state. This state is
determined by the keepalive value. A value of 1 keeps the digital pin at a logical 1 state, a value of 0 keeps
the digital pin at a logical 0 state. The formatting of the digital pin is active when a digital pattern is not
running, and the digital pin is in the keepalive state.
9-44
Digital Instruments
DDCH[i][1] >dlevel
Set the VIL, VIH, and comparator levels for a digital pin.
short dlevel(double lo, double hi, double cmplevel = -1);
Parameters:
double lo
The VIL level.

double hi
The VIH level.

double cmplevel = -1
The comparator level (Optional, can be left out).
Returns:
-2 for invalid low level. -3 for invalid hi level. otherwise 0.
DDCH[i][1] >dmatch
Enables match mode for the digital pin.
short dmatch();
Returns:
Always 0
DDCH[i][1] >dstrb
Sets the comparator strobe time, enables the comparator.
short dstrb(unsigned comp, unsigned ena, unsigned tset, double strobe);
DDCH[i][1] >enable
Enables the drive capability of the digital pin.
short enable();
Returns:
Always 0
DDCH[i][1] >getcomplev
Returns the comparator level for the digital pin.
double getcomplev();
DDCH[i][1] >getformat
Returns a FORMAT type indicating the current format of the digital pin.
FORMAT getformat(unsigned tset);
9-45
DDCH[i][1] >gethighlev
Return the vih level for the digital pin.
double gethighlev();
DDCH[i][1] >getkeepalive
Returns the current keepalive mode for the digital pin for a particular time set.
unsigned getkeepalive(unsigned tset);
DDCH[i][1] >getlowlev
Returns the vil level for the digital pin.
double getlowlev();
DDCH[i][1] >getname
Returns the display name for the digital pin.
Description:
The Real Time interface uses the digital pin name in its display. The user can read back the name currently
assigned to this dut source.
DDCH[i][1] >getstarttime
Returns the start edge time for the digital pin.
double getstarttime(unsigned tset);
DDCH[i][1] >getstate
Returns true if the digital pin is enabled, false for disabled.
bool getstate();
DDCH[i][1] >getstoptime
Returns the stop edge time for the digital pin.
double getstoptime(unsigned tset);
DDCH[i][1] >getstrobe
Returns the strobe time for a digital pin.
double getstrobe(unsigned tset);
9-46
Digital Instruments
DDCH[i][1] >setname
Sets the display name for this digital pin.
void setname(AnsiString newname);
Description:
The Real Time interface uses the digital pin name in its display. The user can change the name to
something more meaningful.
Test Program Examples
Below is a procedure taken from a KVD Test Program which performs DSPIO Master Clock Generation,
Format and Timing Specification and Driver/Comparator Voltage Level Selection. The procedure is aptly
named "DDSetupEveryPart". A procedure of this name should exist in every KVD Test Program that uses
the DSPIO. Many Test Programs call these functions many times because changes in Test Frequency,
Format, Timing and Voltage Levels are required.
Basic DSPIO Channel Setup Example:

void DDSetupEveryPart(double dt0freq)
{
double t0period;
// must reset clocks for each device - TestHeadReset goes to default 40Mhz
// clocking note - make this data rate*32 if possible
DIG0->ddclock(OSCCLK, REFCK0);
DIG0->ddclock(PLLMCLK0, MCLK);
DIG0->ddpllbits(96,60,1);
// if master is not 40MHZ must tell DSPIO.
masterclk = 40e06*96.0/60.0/2.0; //master clock = 64MHZ
ddcont-> DDXTALFREQ[1] = masterclk;
t0period = 1.0/dt0freq;
DIG0->dt0t(0,dt0freq);
DIG0->dt0t(1,dt0freq);
dhiz(0); // Disable all Drivers
SetDDLevels(0.0,5.00);
SCLK-> dfmt(0, RZ, t0period/4.0, 3.0*t0period/4.0, 0);
SCLK-> dfmt(1, RZ, t0period/4.0, 3.0*t0period/4.0, 0);
SDATA->dfmt(0, NRZ, 0e-9, t0period/2.0, 1);
SDATA->dfmt(1, NRZ, 0e-9, t0period/2.0, 1);
INCLK->dfmt(0, RZ, 0e-9, t0period/2.0, 0);
INCLK->dfmt(1, RZ, 0e-9, t0period/2.0, 0);
DDCH8_TO_SCLK ->con();
DDCH7_TO_SDATA->con();
DDCH0_TO_INCLK->con();
SCLK->enable();
SDATA->enable();
INCLK->enable();
DIG0->dxclkena(1);
}
void SetDDLevels(double vlo, double vhi) {
double half = (vlo + vhi) / 2.0;
SCLK->dlevel(vlo, vhi, half);
SDATA->dlevel(vlo, vhi, half);
INCLK->dlevel(vlo, vhi, half);
SDATB->dlevel(vlo, vhi, half);
for(int i=0; i<8; i++) {

SBUS[i]->dlevel(vlo, vhi, half);
RBUS[i]->dlevel(vlo, vhi, half);
}
}
9-47
DD Serial Data Source and Capture Example:
When the DSPIOTI chip is placed into AUTOMODE, the internal state machine takes over and
automatically fills the drive FIFO with data from the TISRAM. This makes the drive data available to the
DRIVE shift-register whenever a LOAD command is issued. Since the state machine is started once the
chip is placed in AUTOMODE it is important that all of the capture and drive registers and address
generators have been set prior to initiating AUTOMODE.
short TEST3(unsigned t) {
unsigned cdata[256];
KVD->tnum(t);
DIG0->ddrv_setup(0L, 256);
DIG1->dcap_setup(512L, 256); // note could have been address 0L
SYS->del(1e-3);
DIG0->patexe(SND_RCV, CAPTURE_DATA);
DIG1->dcap_wait(1);
DIG1->dcap_read(1, 512L, 256, cdata);
for (int i=0;i<256;i++)

cdata[i] &= 0xff;
SITE->lastresult.value=cdata[139];
if (KVD->Test())
return(FAIL);
return(PASS);
}
DD Serial Data Source and Capture PATTERN Example

Pattern (snd_rcv.ds)
;
;****************************************
;
;DEFINE GROUPS
;--------------------
.chmap SENDDATA = {7,6,5,4,3,2,1,0}
.chmap RECVDATA = {23,22,21,20,19,18,17,16}
.chmap TRIG = {8}
.tset t0
.chdefault HIZ
;****************************************
;
;
;
; SEND RECV
; M M
; S S
; B B
;----------------------------------------
CAPTURE_DATA: 00000000 XXXXXXXX 0

lcnt 256 00000000 XXXXXXXX 0
WWWWWWWW XXXXXXXX 1 W=LOAD ;
jmp (!L) .-1 WWWWWWWW VVVVVVVV 1 A=STORE ;
WWWWWWWW XXXXXXXX 0 ; don't do a recv on the last 2 vectors
HALT WWWWWWWW XXXXXXXX 0
9-48
Digital Instruments
DSPIO Pinouts
Figure 9.25: DSPIO Father Card Pin Assignments
9-49
DSPIO Drive and Capture

DSPIO Capture and Drive Shift Registers
Each digital pin on the DSPIO is attached to two separate shift registers. One is the DRIVE shift register
and the other a CAPTURE shift register. These shift registers share a data path to a DSP processor and
memory. The combination of DSP processor, extra memory (TISRAM) and shift registers give the DSPIO
unique capabilities not available with standard pattern-driven digital pins.
The CAPTURE shift register allows data from the compare input to be captured in a parallel or serial
fashion. This captured data can then be passed on to the user's program or to the on-board DSP
processor for further processing. This enables the DSPIO board to perform FFTs and other complex signal
measurements, on captured data, in real time.
Figure 9.26: Block Diagram of CAPTURE and DRIVE Shift Registers
The DRIVE shift register gives the digital formatter another source of data. This data can come from the
external memory (TISRAM) or the DSP processor. In many situations this additional data can be used to
save a significant amount of regular pattern vector memory. For example; applications that require testing
serial devices can utilize the DRIVE shift register. Serial drive data can be stored efficiently in the TISRAM
memory, and transferred to the formatter pins, instead of using less efficient pattern vector memory. The
TISRAM memory can also act as a circular buffer. Data representing one cycle of a sine wave can be
stored in the TISRAM, and then shifted out in a continuous loop.
The combination of the DSP processor, TISRAM memory, and the CAPTURE and Drive shift registers
greatly expand the capabilities of the DSPIO.
9-50
Digital Instruments
Figure 9.27: Details of CAPTURE and DRIVE Shift Registers
9-51
OPCODE Shift Register Control

The SHIFT REGISTER CONTROL bits of the OPCODE control both the capture and drive shift registers.
The drive and capture shift registers are controlled by the OPCODE SR[2:0] bits. Each shift register can
'hold', or 'shift' independently. The drive shift register can 'load' data from DSPIOTI chip, and the capture
shift register can 'store' data to the DSPIOTI chip. Since there is only one bus between the shift registers
and the DSPIOTI chip, only one data move is allowed in a T0 cycle. This restricts the two shift-registers to
one LOAD or STORE during a T0 cycle.
SR[2:0] DRIVE COMPARE
000 HOLD HOLD
001 HOLD CAPSHIFT
010 HOLD STORE
011 DRVSHIFT HOLD
100 DRVSHIFT CAPSHIFT
101 DRVSHIFT STORE
110 LOAD HOLD
111 LOAD CAPSHIFT
Figure 9.28: OPCODE SHIFT REGISTER CONTROL
CAPTURE Shift Register

There is a 16-bit CAPTURE shift register connected to the digital channel compare inputs. Each digital
channel corresponds to one bit in the shift register. Channel 0 connects to the LSB of the shift register and
channel 15 connects to the MSB of the shift register. Each channel can individually capture data into the
shift register. The contents of the shift register can also be 'left shifted' (lsb to msb) one bit at time, or a
copy of the contents of the shift register can be transferred or 'stored' into the DSPIOTI chip. Once a copy
of the shift register is stored into the DSPIOTI chip, it can then be stored into the TISRAM or accessed by
either the DSP processor, or the users program.
Capturing data is individually controlled for each channel by the pattern vector. Each channel can either
compare the input data against the pattern vector for a fail or match condition, or it can capture the input in
the shift register.
The pattern vector compare bits, for each channel decode in the following way.
x 00 ignore
V 01 capture data into shift register
L 10 compare to a '0'
H 11 compare to a '1'
While capturing data is controlled individually for each channel, shifting and storing operations act on the
entire shift register and are controlled by the pattern vectors OPCODE. For each vector the user chooses
to hold, shift or store the contents of the CAPTURE shift register. The shift operation initiates a 'left-shift' of
the CAPTURE shift register. The store operation transfers a copy of the shift register contents to the
DSPIOTI chip. Note: the store operation does not effect the contents of the shift register.
9-52
Digital Instruments
The shift register is designed to capture data, and to execute a store or shift operation in the same T0
cycle. In order to accomplish both actions (a capture and a store/shift) in the same T0 cycle, they must
execute at different clock cycles. The shift and store operations execute at a specific clock cycle at the end
of the T0 cycle. Technically, the shift/store operations execute at the start of the next T0 cycle. To allow
time for the shift/store operation, there is a dead zone at the beginning of each T0 cycle where a capture
cannot occur. This dead cycle is only one clock period, the rest of the T0 cycle can then be used to
schedule the capture operation.
The channel input is latched into the CAPTURE shift register on the falling edge of the compare strobe
signal. This allows the user to choose where in the T0 cycle to capture data. The only restriction is that a
capture cannot occur on the first clock of a T0 cycle.
In this example 64 bytes of data are captured from a two channel 8-bit serial ADC (128 bytes total) , and
passed on to the DSPIOTI chip were it is then stored into the TISRAM memory. One channel of the ADC is
connected to the digital pin CH0, and the other ADC channel is connected to digital pin CH8.
Two Channel 8-bit Serial ADC Example

The program setup, to store the captured data into the TISRAM will be covered later. This is the pattern
vector that will capture the data and pass it on to the DSPIOTI chip.
Pattern Vector
CHANNEL 15 13 11 09 07 05 03 01
14 12 10 08 06 04 02 00
08 LOADCNT 64 x x x x x x x x x x x x x x x x
09 A=SHIFT REPEAT 7 x x x x x x x C x x x x x x x C
10 A=STORE JMP (!L) 09 x x x x x x x C x x x x x x x C
Where:
'x' don't care
'C' capture data
In step 09, data from the ADC is captured on channels 0 & 8, which correspond to bits 0 & 8 of the
CAPTURE shift register. This data is then 'left-shifted' one bit at the end of the T0 cycle.
Figure 9.29: Two Channel 8-bit ADC CAPTURE
After 7 capture and shift operations, step 10 captures the final bit, and the whole 16 bits is stored into the
DSPIOTI chip. The process is then repeated 64 times to capture a total of 128 bytes from the two channel
serial ADC.
DRIVE Shift Register

There is a 16-bit DRIVE shift register connected to the channel drive outputs. Each digital channel
corresponds to one bit in the shift register. Channel 0 connects to the LSB of the shift register and channel
15 connects to the MSB of the shift register. The DRIVE shift register can perform three functions. The
channel can drive data from the shift register. The shift register can 'left-shift' (lsb to msb) one bit at time,
and the shift register can be loaded from the DSPIOTI chip.
9-53
For each channel, there are two possible sources of drive data; one is the pattern vector, and the other the
DRIVE shift register. The pattern vector controls which source is used.
The pattern vector drive bits, for each channel decode in the following way.
x 00 Hi Z
W 01 Drive SR data
0 10 Drive '0'
1 11 Drive '1'
The SR bits in the OPCODE word control loading and shifting of the entire DRIVE shift register. The 'hold'
opcode does not effect the DRIVE shift register in any way. The 'shift' opcode executes a single 'left-shift'
(lsb to msb) on the shift register. The 'load' opcode loads the DRIVE shift register with data from the
DSPIOTI. The source of the load data is controlled by the users program and can come from the DSP
processor, the TISRAM or the users program.
The 'load' and 'shift' operations occur at the end of a T0 cycle. Loading the drive shift register must be done
at least one T0 cycle before the data is available to the drive formatter. Data can be loaded or shifted into
the drive shift register on every T0 cycle if needed, the only restriction is that a load of the drive shift
register and a store of the capture shift register cannot occur during the same T0 cycle.
In this example a two channel 8-bit serial DAC is driven by the DRIVE shift-register. 128 bytes of data (64
16-bit words) are supplied by the TISRAM thought the DSPIOTI chip. One channel of the DAC is
connected to the digital pin CH7, and the other DAC channel is connected to digital pin CH15.
Two Channel 8-bit Serial DAC Example

The program setup to load the drive data from the TISRAM will be covered later. This is the pattern vector
that will load drive data from the DSPIOTI chip and shift it out the digital pins to the DAC:
Pattern Vector
CHANNEL 15 13 11 09 07 05 03 01
14 12 10 08 06 04 02 00
08 W=LOAD LOADCNT 64 x x x x x x x x x x x x x x x x
09 W=SHIFT REPEAT 7 D x x x x x x x D x x x x x x x
10 W=LOAD JMP (!L) 09 D x x x x x x x D x x x x x x x
Where:
'x' don't care
'W' drive data
In step 08, the DRIVE shift-register is loaded with 16-bits of data from the DSPIOTI chip. In step 09,
channels 7 & 15, drive levels according to the values stored in the DRIVE shift-register. At the end of step
09, the DRIVE shift-register executes a 'left-shift' operation. The drive & shift operation is repeated 7 times,
shifting out the 7 MSB bits of the serial word.
Figure 9.30: Two Channel 8-bit DAC & DRIVE Shift Register
Step 10 drives the final bits, and reloads the DRIVE shift-register with the next word. The entire sequence
is repeated 64 times, transferring 64 bytes of data to each DAC channel.
9-54
Digital Instruments
DSPIOTI Chip
Data is transferred to and from the capture and drive shift registers through the CAPDAT bus. This bus
connects the shift registers and the DSPIOTI chip. The DSPIOTI chip is responsible for storing data from
the capture shift register and loading data into the drive shift register. Since there is only one bus between
the shift registers and the DSPIOTI chip, only one load or store operation can occur per T0 cycle.
There is one FIFO in the DSPIOTI chip for each of the capture and drive shift registers. The DSPIOTI chip
keeps the drive FIFO full, so that data is always available for the drive shift register. Likewise, the DSPIOTI
chip keeps the capture FIFO empty, so that data can always be received from the capture shift register.
Data to keep the drive FIFO full can come from three sources, the DSP processor, the TISRAM or the DIS
interface. Likewise, data from the capture FIFO can be stored in any of these three places.
To accommodate the possibility of three sources, the DSPIOTI chip has three modes of operation.
1. DISMODE; The DIS interface can write to the drive FIFO, read the capture FIFO, and status register,
as well as write to all the internal control registers.
2. TIMODE; TI DSP can write to the drive FIFO, and read from the capture FIFO, and the status register.
3. AUTOMODE, The DSPIOTI chip keeps the drive FIFO full by automatically reading data from the
TISRAM, and keeps the capture FIFO empty by automatically writing captured data to the TISRAM.
Figure 9.31: Block Diagram of DSPIOTI Chip
DISMODE
In order to communicate with the DSPIOTI chip through the DIS interface, the chip must be in DISMODE.
Once in DISMODE the user has access to all of the internal control registers as well as the FIFO's and
status register. The DIS interface is much slower than the possible drive and capture rates, and is
therefore not usually suitable for data transfer during a pattern. But the ability to put data in the drive FIFO
and read data out of the capture FIFO gives the user a powerful debug tool. Using DISMODE, the user
could control the digital formatter pins independent of the pattern vectors.
9-55
TIMODE
In TIMODE the Texas Instruments DSP processor has accesses to the FIFOs and the status register. By
reading the status register, the DSP processor knows the status of the FIFOs and can transfer data in and
out as needed. In some cases at maximum T0 rates, the DSP processor will not be fast enough to
maintain the FIFOs. AUTOMODE must be used at fast T0 rates, to keep the FIFOs from overrunning.
AUTOMODE
In AUTOMODE the DSPIOTI chip takes over the address and data bus, and automatically transfers data in
and out of the TISRAM. In AUTOMODE, one load or store operation is allowed per T0 cycle. This allows
the shift registers to operate at the maximum T0 rate.
In AUTOMODE, there are two address generators, one for storing captured data, and one for reading drive
data. The separate address generators allow for separate address spaces in the TISRAM, so data can be
stored from the capture shift register without affecting the data being transferred into the drive shift
registers.
The drive address generator can operate in a circular mode. Along with specifying the starting address of
the drive data, a count is provided. After reaching the end of the count, the drive address generator is
reloaded with the starting address.
To limit the number of data points captured, a maximum capture counter is used. The user sets the
number of data points to be captured. After this number is reached, data is no longer stored in the
TISRAM, and a flag is set in the status register.
Details of the Control Word
The Data Pattern Memory of the DSPIO is 512K deep by 64 bits wide. Each DSPIO Channel has 4 bits of
pattern data per vector (16 channels per board). There are 16 possible channel states per vector.
Presently, DSPIO patterns make use of 7 Driver/Comparator States. They are:
ASCII State Character Driver Comparator
X HIZ MASK
0 Drive Lo MASK
1 Drive Hi MASK
L HIZ Compare Lo
H HIZ Compare Hi
V HIZ Capture Data
W Drive SR Data MASK
Figure 9.32: Pattern State Controls
9-56
Digital Instruments
The Sequencer is the heart of the DSPIO Subsystem. It can be viewed as a custom controller which has a
memory depth of 512K and can operate up to the maximum t0 Vector Rate. (presently 20MHz, the
maximum Vector Rate for a given Master Clock equals Master Clock Freq / 4) The Sequencer has 2
functions. The first is to provide the current vector address to the Data Pattern Memory. The second is to
provide the Time Set Address to the Format/Timing FPGA. The Op-Code field of the Op-Code Memory
has 4 bits. Available Op-Codes are:
Opcode Function Conditional (Y/N) Operand
wait, nop wait for condition Y None
halt halt execution optional none
jmp jump to vector optional address
jmpr jump to vector optional relative address
repeat repeat vector optional repeat count
loadcnt load counter optional counter value
call call subroutine optional address
callr call subroutine optional relative address
return subroutine return optional none
along extend absolute N address

address
rlong extend relative address N relative offset
flags set or clear flags optional flag bits
control set control bits for fail optional control bits

record
note store fail fifo registers optional register
Figure 9.33: Sequencer Opcodes
Many of the opcode commands can be conditionally executed. The 4-bits of the FLAG field determines,
what flag the opcode will be conditioned on, and the flag's polarity. Most of the flags are cleared when they
are tested or 'used'. The exception to this is the fail 'F' and match 'M' flags. The flags can also be set and
cleared using the FLAGS opcode. The FLAGS opcode can individually set and clear every flag with the
exception of the match and unconditional flags.
Bit FLAG[2:0] Name SET CLEAR
0 - Unconditional Always Set Cannot Clear
1 U1 User 1 DIS Command use or FLAGS bits
3 M Match Match from No Match

Formatter
4 reserved
9-57
Bit FLAG[2:0] Name SET CLEAR
5 L Loop Counter Loop Counter = 0 use or FLAGS bits
6 F Fail Fail from FLAGS bits only

Formatter
7 V Vector CONTROL bits use or FLAGS bits

only
Figure 9.34: Flag Opcodes
FLAG bit-3 sets the flags polarity. So for example if FLAG[3:0] was set to 1101, then the command would
execute only if the loop counter flag 'L' was not set.
The DSPIO shapes and provide "edge placement timing" to the digital waveforms in the Format/Timing
Block. 4 bits of data come from the Data Pattern Memory and are decoded by the Format/Timing Block to
create the proper channel state during each cycle. The per channel Format/Timing generates states for
each cycle. The DSPIO supports the industry standard NRZ, RZ, RO, CS (and their complements, NRZC
not available) plus HIGH, LO, OFF and clock formats (Clock/2, Clock/4, and Clock/8). Timing diagrams of
the most commonly used Drive Formats are shown below.
Patterns
The DSPIO performs digital functional testing in the following manner. The Driver sends input stimulus to
the DUT. It can have 3 states (hi, lo and hiZ). After comparing the DUT output to the Compare Level
Note: Only a single level compare, not a window.
the Comparator sends the results to the Format/Timing Block FAIL Logic which will latch the FAIL and
Address if one is present. Comparator Outputs can also be sent to the TMU for parametric time
measurements.
Note: If dynamic loads are required, they must be added to the Father Card, or connect a DUT Source
via DDBUSA.
DSPIO patterns are composed of addresses, opcodes, operands, and channel data. Once started, pattern
execution is controlled by the opcode and operand fields. The opcodes and operands are combined to
form a part of a 32 bit Control word.
9-58
Digital Instruments
ADDR 32 bit Control Word
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FD TSET[2:0] NR SR[2:0] OPCODE[3:0] FLAG[3:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPERAND[15:0]
FD Fail Disable
TSET[2:0] Time set select
NR Used to indicate negative relative offsets
SR[2:0] Shift Register Control
OPCODE[3:0] Opcode
FLAG[3:0] Select conditional flag
OPERAND[15:0] Address and control bits field
FD FAIL DISABLE
When this bit is '0' the fail flag 'F' is set, and the channel fail register is set whenever a fail condition exists.
When this bit is '1' the fail flag and the fail channel register are not set when a fail condition exists. The Fail
Disable bit is used during a match sequence. The match 'M' flag is the inverse of the fail 'F' flag. To wait for
a match condition, the Fail Disable 'FD' bit is set in the opcode. The match condition is true ('M' is set)
when there is no longer a fail condition. The Fail Disable bit allows a match sequence to occur without
setting any fail bits.
9-59
TSET[2:0] TIME SET

The 3-bit TSET field is used to select which of the eight available time sets that will be used during this
vector. (Only two time sets are presently supported by hardware).
SR[2:0] SHIFT REGISTER CONTROL

The DRIVE and CAPTURE shift registers are controlled by the SR[2:0] bits. Each shift register can HOLD,
or SHIFT independently. The DRIVE shift register can LOAD data from TI SRAM memory, and the
CAPTURE shift register can STORE data to the TI SRAM memory. Since there is only one bus between
the TI SRAM and the formatter Xilinx, only one data move is allowed in a T0 cycle. This restricts the two
shift registers to one LOAD or STORE during a T0 cycle.
SR[2:0] DRIVE CAPTURE
000 HOLD HOLD
001 HOLD SHIFT
010 HOLD STORE
011 SHIFT HOLD
100 SHIFT SHIFT
101 SHIFT STORE
110 LOAD HOLD
111 LOAD SHIFT
OPCODE[3:0] VECTOR OPCODE

The four bit OPCODE command decodes into 16 possible commands. The table below lists the 16
opcodes.
# OPCODE CONDITIONAL OPERAND FIELD
0 NOP, WAIT C
1 HALT C
2 JMP C LSW Absolute Address
3 JMPR C LSW Relative Offset
4 REPEAT Count
5 LOADCNT 16bit Counter value
6 CALL C LSW Absolute Address
7 CALLR C LSW Relative Offset
8 RETURN C
9 ALONG MSW Absolute Address
10 RLONG MSW Relative Offset
9-60
Digital Instruments
# OPCODE CONDITIONAL OPERAND FIELD
11 FLAGS C Control bits
12 CONTROL C Control bits
13 NOTE C Register
14 reserved
15 reserved
FLAG[3:0] CONDITIONAL FLAG

Many of the opcode commands can be conditionally executed. The 4-bits of the FLAG field determines,
what flag the opcode will be conditioned on, and the flags polarity. The table below lists the conditional
flags, and how they are set and cleared. Most of the flags are cleared when they are tested or 'used'. The
exception to this is the fail 'F' and match 'M' flags. The flags can also be set and cleared using the FLAGS
opcode. The FLAGS opcode can individually set and clear every flag with the exception of the match and
unconditional flags.
FLAG[2:0] Name SET CLEAR
0 - Unconditional Always Set Cannot Clear
3 M Match Match from No Match

Formatter
4 reserved
5 L Loop Counter Loop Counter = 0 use or FLAGS bits
6 F Fail Fail from FLAGS bits only

Formatter
7 V Vector CONTROL bits use or FLAGS bits

only
FLAG bit-3 sets the flags polarity. So for example if FLAG[3:0] was set to 1101, then the command would
execute only if the loop counter flag 'L' was not set.
NR NEGATIVE RELATIVE ADDRESSING

Relative addressing uses this bit to determine which direction it should jump. If the NR bit is set then a
relative jump will move backwards.
9-61
DIGMOD16/32
Description
The DIGMOD16 module includes 16 high speed digital bi-directional channels, while the DIGMOD32
supports 32 channels per instrument. The KVD test head can be populated with as many as 6 DIGMOD
boards, for a total of 96 or 192 high speed pins. A custom power supply and enhanced test head air
cooling are required to support the DIGMOD option, compared to a system with the DSPIO configuration.
Figure 9.35: DIGMOD 16
Figure 9.36: DIGMOD 32
Features and Basic Specifications
Compared to the DSPIO instrument, the DIGMOD architecture offers much higher speed, larger memory
per pin, increased numbers of time and format sets (16), built-in PMU and programmable loads per pin, a
built-in frequency measurement feature, and a window (not level) comparator. Added features include
same cycle drive/compare, vernier timing control with 50pS resolution, a "no change" drive/compare
command, and combine mode.
9-62
Digital Instruments
Drive/Compare
Channels Per Board 16/32
Drive Control 3 (drive high, drive low, hiz)
Compare Control 3 (compare high, compare low,

mid-level)
Drive Level Range -2V to 7V
Resistive Load (per pin) 8 available
PMU
Channels Per Board 16/32 (one per pin)
ForceV Ranges 2 ranges (8V/4V)
ForceI Ranges 8 ranges (32mA, 8mA, 2mA,

512uA, 128uA, 32uA, 8uA, 2uA)
Pattern Formatting
Master Clock Rate 120MHz
Pattern Rate 60MHz
Combine and Clock Rates 120MHz
Pattern Depth 16MB
Timesets 16 (per board)
Edge Placement (on the fly) 5nS
Skew Adjust Resolution 50pS
• Board-to-board timing skew is in the process of being improved when in the Master->Slave
configuration. Expected board to board edge placement accuracy will be 1nS. Please contact KVD if
board-to-board timing is a critical requirement for applications advice.
• Serial Send memory setup command ddrv_setup operates on a MINIMUM vector sequence of 16
addresses, and will cause an error if this minimum is not observed.
9-63
Block Diagram
Figure 9.37: DIGMOD Block Diagram
The DIGMOD is implemented with two-channel-per-package pin electronics ICs, a 2 million gate FPGA,
multiple on-board voltage regulators and clock distribution circuits. The FPGA-based architecture allows
for simple file transfer updates of the logic configuration definition, to allow customization and feature
updates without removing instruments from the test head or performing hardware change orders.
9-64
Digital Instruments
Figure 9.38: Pin Electronics
High Speed Link

New cabling and Xilinx support is now available for a high speed link option. Pattern loading formerly was
routed through the PCIDIS->DISCONT 12.5MHz serial data bus along with analog instrument commands
and test results. The High Speed Link is a separate path using serial LVDS, using CAT5 network cables
from the KVD CPU to the test head. The system auto-detects the presence of this path, but the current
default is OFF, for program compatibility.
Burst DMA readback modes are being implemented for certain functions where speed is of great impact to
test time. These include readback from Capture/Send Memory, Fail information readback, ADC data
readback.
9-65
To allow the program to auto detect whether the HSL is present and working change the
ModuleInitDigmod() function to ModuleInitDigmod(1) in the LotInit() function.
You must select the highest level DIGMOD16 Xilinx in your TCT for this HSL support, as of Release 2 it will
be DIGMOD16R7. Do not use DIGMOD16 default Xilinx if you desire HSL. Other features included in R7
Xilinx are:
• 5ns Edge placement on the fly
• Full Capture/Send memory support (bi-directional shifting)
• 60MHZ Sequencer operation
• Combine mode
• Fix PEC119 Sequencer Bug (subroutine from page boundary)
• Master/Slave synchronization
Figure 9.39: Select DIGMOD16R7
For backwards compatibility with legacy test programs, selecting the existing DIGMOD16 Xilinx files in the
TCT (Tester Configuration Tool) will use the existing 12.5MHz lower speed DIS Bus. You can also add the
line useHslAsDefault = false; after DIGMOD initialization in your test program.
The DIGMOD checker includes a test for the presence of the HSL - tests 7, 107, etc.
DIGMOD Calibration and Checker

The DIGMOD cal and diagnostic checker are in the usual location in the Cal & Checker Launcher, with one
current special issue.
Cal verification also serves as a specification checker. Other functions are verified in the checker, but
voltage and current accuracy can be verified without a re-calibration by going into the Options tab,
expanding the DIGMOD (16 or 32) selection, expanding the Calibration box, then selecting the Verify box.
Note this verification is currently not in the typical location under the Checker selection.
9-66
Digital Instruments
Figure 9.40: Calibration and Checker Options
DIGMOD Programming
Programming the DIGMOD instrument is divided into 4 basic types:
• DIGMOD Pin Definition
• DIGMOD Pin Programming
• DIGMOD Sequencer Definition
• DIGMOD Sequencer Programming
DIGMOD Pin Definition

Basics
The KVD Operating System defines a DIGMOD pin as type TDMDigPin. There are system defined pins
DMCH[0]->DMCH[191]. It is important to note that DIGMOD16 pins ARE NOT defined contiguously. This
numbering feature will allow for simple program portability between DIGMOD16 based systems and
DIGMOD32 based systems.
For DIGMOD16 boards the pins are defined as follows:

DIGMOD0 : DMCH[0] - DMCH[15]
Total of 96 pins if the system is populated with DIGMOD16 boards.
9-67
Pin Definition & Grouping
While it is possible to construct an entire program using the system defined pin names, most test program
developers will want to assign a pin naming structure that closely mimics the DUT pin names, and will also
want to create groups of pins. The following text contains a brief explanation of pin naming. This will prove
helpful in understanding the DMCH pin programming syntax.
Single Pin Naming

TDMDigPin *SCLK;
SCLK = DMCH[6];
DMCH[6]->setname("SCLK");
Now the test engineer only has to remember the name 'SCLK' and not the actual DMCH number. The
setname command changes the RTI (Real Time Interface) pin labeling to the more memorable 'SCLK'.
Grouping Pins
Pins can also be 'grouped' together in order to simplify programming. Each group can contain between 1
and 32 DMCH pins. Groups of pins can consist of other groups of pins, so long as the group total does not
exceed 32.
TDMDigPin *data0;
TDMDigPin *data1;
data0 = DMCHCreate("data0", DMCH[0], DMCH[16], DMCH[32], DMCH[48]);

data1 = DMCHCreate("data1", DMCH[1], DMCH[17], DMCH[33], DMCH[49]);
This will create 2 pin groups of 4 pins each.
Group definitions also cause changes in the RTI (Real Time Interface) debugging tool display, for
decluttering and ease of issuing commands to the group. This is shown in section 17 of this chapter.
Grouping of Groups
Assuming two groups have been defined as outlined in the previous example, these groups can then be
combined to form a third group:
TDMDigPin *alldata
data0 = DMCHCreate("alldata", data0, data1);
Now the group "alldata" will consist of 8 DMCH pins.
It is important to note that the more detailed command syntax description that follows applies to both single
pins (DMCH) or groups of pins (more than one DMCH), and that a group can consist of a maximum of 32
DMCH pins.
9-68
Digital Instruments
DIGMOD Pin (DMCH) Programming

Here is a quick listing of commands that can be applied to the TDMDigPin Class.
SetSiteMode setv pmucompi drvfeskew

enable seti l1abus_con cmphiskew
disable irange l1abus_discon cmphifeskew
forcemode vrange dtiming cmploskew
forceenable imeter dfmt cmplofeskew
force vmeter tset enaskew
dlevel measvm fmt enafeskew
cmplevel loaddisable format keepalive
vil load start dka
vih dig_con stop dcmp
vol dig_discon enastart dcomp
voh abus_con enastop tmucon
trm abus_discon cmpstart measfreq
trmenable dtimingT0 cmpstop vclamps
pmuenable pmucompv drvskew
DMCH Pin Programming Functions
Examples are given here.
DMCH[x]->SetSiteMode
Example:
DMCH[0]->SetSiteMode(TRUE, 1);
This will assign DIGMOD channel 0 to site 1.

void TDMDigPin::SetSiteMode(bool _sitemode, short site)
Arguments:
bool _sitemode // TRUE or FALSE
short site // 1-16
DMCH[x]->enable
Enables or disables a pin or group of pins. Enabling a pin means that when pattern execution is stopped
the pin continues to drive to the keep alive data. Otherwise it will tri-state (or go to the termination voltage if
termination enabled). When the pattern executes the pin is enabled if the data is set to a drive 0 or 1. At
initialization all pins are disabled.
Example:
DMCH[2]->enable(1);
DMCH[2]->enable();
The above 2 statements are effectively the same and will enable the driver on channel 2.
short TDMDigPin::enable(unsigned value)
Arguments:
unsigned value // 0=disable 1=enable
9-69
DMCH[x]->disable
At initialization all pins are disabled.
Example:
DMCH[3]->disable();
DMCH[3]->enable(0);
Note the above 2 statements are effectively the same and will disable the driver on DIGMOD channel 3.
short TDMDigPin::disable(void)
Arguments:
none
DMCH[x]->forcemode
This mode will override the formatter pattern logic and allow the DIGMOD channel to be set to a static logic
condition. This is different from keepalive in that the forced state is a high or low level, where the keepalive
argument is the data presented to the formatter.
Example:
myGroup->forcemode(1);
short TDMDigPin::forcemode(unsigned value)
Arguments:
unsigned value // 0=pattern 1=static
DMCH[x]->forceenable
This mode will work with the forcemode statement and will enable the driver for static forcing. Assuming
the pin has been set to forcemode, this statement will effectively set the pins in 'myGroup' to a static state
that is determined by the 'force' statement.
Example:
myGroup->forceenable(1); // 0=hiz 1=drive
short TDMDigPin::forceenable(unsigned value)
Arguments:
unsigned value // 0=hiz 1=drive
DMCH[x]->force
This mode will work with the forcemode and forceenable statements and will set the state (high or low) of
the pin or group that has previously been set to forcemode.
Example:
myGroup->force(0); // 0=low 1=high
9-70
Digital Instruments
Assuming the pin has been set to forcemode, and the forcemode has been enabled this statement will
effectively set the pins in 'myGroup' to a static state low. The table below shows pin state with forcemode
on.
Forceenable force Pin State
0 0 hiz
0 1 hiz
1 0 low
1 1 high
short TDMDigPin::force(unsigned value)
Arguments:
unsigned value // 0=low 1=high
DMCH[x]->dlevel
This will set the DIGMOD pin drive and compare levels; both low and high drive levels as well as low and
high compare levels.
Example:
DMCH[7]->dlevel(0.4, 2.8, 1.0, 1.4);
short TDMDigPin::dlevel (double lo,double hi,double cmplo,double cmphi)
Arguments:
double lo // drive low level
double hi // drive high level
double cmplo // compare low level
double cmphi // compare high level
DMCH[x]->cmplevel
This will set the DIGMOD compare levels only. Typically the all levels will be set with the 'dlevel' statement,
however it is sometimes necessary to change only one of the compare levels.
Example:
DMCH[7]->cmplevel(1.0, 1.4); //cmplo, cmphi
short TDMDigPin::cmplevel (double cmplo, double cmphi)
Arguments:
DMCH[x]->vil
This will set the DIGMOD drive low level only. Typically the all levels will be set with the 'dlevel' statement,
however it is sometimes necessary to change only one level.
Example:
myGroup2->vil(0.4);
short TDMDigPin::vil (double vil)
9-71
Arguments:
double vil // drive low level
DMCH[x]->vih
This will set the DIGMOD drive high level only. Typically the all levels will be set with the 'dlevel' statement,
however it is sometimes necessary to change only one level.
Example:
myGroup2->vih(2.8);
short TDMDigPin::vih (double vih)
Arguments:
double vih // drive high level
DMCH[x]->vol
This will set the DIGMOD compare low level only. Typically the all levels will be set with the 'dlevel'
statement, however it is sometimes necessary to change only one level.
Example:
myGroup2->vol(1.0);
short TDMDigPin::vol (double cmplo)
Arguments:
DMCH[x]->voh
This will set the DIGMOD compare high level only. Typically the all levels will be set with the 'dlevel'
statement, however it is sometimes necessary to change only one level.
Example:
myGroup2->voh(1.5);
short TDMDigPin::vol (double cmphi)
Arguments:
DMCH[x]->trm
This will set a termination voltage on a DIGMOD channel using the pin driver (not the PMU). This
statement is used with the 'trmenable' statement to allow for termination through 50 Ohm to a specific
voltage.
Example:
myGroup2->trm(1.5);
short TDMDigPin::trm (double value)
Arguments:
double value // termination voltage level
9-72
Digital Instruments
DMCH[x]->trmenable
This statement is used to allow for termination through 50 Ohm to a specific voltage as defined by the 'trm'
statement.
Example:
myGroup2->trmenable(1);
Note that the DIGMOD channel will now be terminated thru 50ohm to a voltage defined by the 'trm'
statement. This means the whenever the DIGMOD driver is HIZ (disabled), the pin will go to this
termination level.
short TDMDigPin::trmenable(unsigned value)
Arguments:
unsigned value // 0=termination off, 1=termination on
DMCH[x]->pmuenable
Each DIGMOD channel has a built in PMU (parametric measurement unit) that will allow for analog force
and measure directly through the 'digital' pin connection. This allows for high speed contact and leakage
measurements on many pins at the same time, static settings that exceed the normal drivel level, and so
forth.
Example:
myGroup2->pmuenable(1); // 0=pmu disabled, 1=pmu enabled
It is important to note that if the PMU is enabled, the DIGMOD driver is automatically disabled. It is not
possible to have both enabled at the same time.
short TDMDigPin::pmuenable(unsigned value)
Arguments:
unsigned value // 0=pmu disabled, 1=pmu enabled
DMCH[x]->setv
This will set the voltage level for an 'enabled' PMU, and set the PMU to force voltage mode
Example:
myGroup3->setv(3.0);
short TDMDigPin::setv(double value)
Arguments:
double value // range -2V to +10V
DMCH[x]->seti
This will set the current level for an 'enabled' PMU, and set the PMU to force current mode.
Example:
myGroup3->seti(10e-6);
short TDMDigPin::seti(double value)
9-73
Arguments:
double value // limits depend on 'irange'
DMCH[x]->irange
Each PMU is limited to 2 voltage ranges, however there are 8 defined current ranges.
Example:
myGroup3->irange(1);
myGroup3->irange(PMU_8MA);
short TDMDigPin::irange(unsigned range)
Arguments:
unsigned range // valid current ranges are 0-7 and are also defined // as follows:
// 0 = PMU_32MA
// 1 = PMU_8MA
// 2 = PMU_2MA
// 3 = PMU_512UA
// 4 = PMU_128UA
// 5 = PMU_32UA
// 6 = PMU_8UA
// 7 = PMU_2UA
DMCH[x]->vrange
Each PMU has 2 voltage ranges.
Example:
myGroup3->vrange(1);
short TDMDigPin::vrange(unsigned range)
Arguments:
unsigned range // valid current ranges are 0-1 and are also defined as follows:
// 0 : -2V->10V
// 1 : -1V->7V
DMCH[x]->imeter
Each PMU can force voltage or current and measure voltage or current. This statement is used to set up
the PMU to measure current.
Example:
myGroup3->imeter();
short TDMDigPin::imeter(void)
Arguments:
none
DMCH[x]->vmeter
Each PMU can force voltage or current and measure voltage or current. This statement is used to set up
the PMU to measure voltage.
Example:
myGroup3->vmeter();
short TDMDigPin::vmeter(void)
9-74
Digital Instruments
Arguments:
none
DMCH[x]->measvm
Each PMU can force voltage or current and measure voltage or current. This statement is used to measure
voltage or current on a PMU channel(s) as previously set by the 'imeter' or 'vmeter' statement.
Example:
DMCH[8]->measvm(100); // numsamples 1-1023
The average result of 100 measures on DIGMOD channel 8 PMU is returned by this function. In addition
the result will be saved in SITE->lastresult.value if the pin is NOT in 'SiteMode'. If the pin is in 'SiteMode',
the result will be saved in SITE->results[site].value, where site is the preassigned site for the DIGMOD
channel - in this case DMCH[8].
double TDMDigPin::measvm(unsigned numsamples)
Arguments:
unsigned numsamples // 1-1023
DMCH[x]->ldenable
In addition to performing typical PMU functions of force and measure, the DIGMOD PMU can also be used
to provide a static resistive load. This is particularly useful if a device pin requires a pullup to some voltage
level. This pullup can be enabled on the DIGMOD pin using the PMU range resistors.
Example:
myPins->ldenable(1);
short TDMDigPin::ldenable(unsigned value)
Arguments:
unsigned value // 0=disable load, 1=enable load
This is not the same as termination, for termination see 'trmenable' and 'trm'.
DMCH[x]->loaddisable
This will disable the PMU resistive load.
Example:
myPins->loaddisable();
short TDMDigPin::loaddisable(void)
Arguments:
none
This is not the same as termination, for termination see 'trmenable' and 'trm'.
DMCH[x]->load
The load resistor and voltage are programmed with this command.
9-75
Example:
myPins->load(3, 3.4); // range, voltage
myPins->load(PMU_2KOHM, 3.4);
Both of these examples will accomplish the same goal. The 2Kohm load will be set and the voltage load
will be set to 3.4 volts. This will effectively 'pullup' the DIGMOD channels defined in 'myPins' to 3.4 volts
through a 2K Ohm resistor.
short TDMDigPin::load(unsigned range,double voltage)
Arguments:
unsigned range // valid load values are 0-7 and are also defined as follows:
// 0 = PMU_80OHM
// 1 = PMU_180OHM
// 2 = PMU_500OHM
// 3 = PMU_2KOHM
// 4 = PMU_8KOHM
// 5 = PMU_32KOHM
// 6 = PMU_128KOHM
// 7 = PMU_500KOHM
DMCH[x]->dig_con
By default all DIGMOD channels are isolated from the Fathercard with a dedicated relay per channel. In
order to connect the driver/comparator or PMU resource to the DUT, this relay connection must be closed.
Example:
myPins5->dig_con();
short TDMDigPin::dig_con(void)
Arguments:
none
DMCH[x]->dig_discon
Likewise, this connection must be opened if isolation is desired.
Example:
myPins5->dig_discon();
short TDMDigPin::dig_discon(void)
Arguments:
none
DMCH[x]->abus_con
In addition to connecting the DIGMOD pin electronics up to the Fathercard, it is also possible to connect an
alternate analog resource for higher voltage and current capability. This resource is typically MPDS[0]. A
relay is provided that will connect a DIGMOD pin to the 'ABUS'. Further effort will be needed to connect
this internal ABUS to the motherboard and then to MPDS[0] if you wish to use MPDS[0] for parametric
measurements.
Example:
myPins5->abus_con();
9-76
Digital Instruments
Caution is urged when using this command as any number of pins can simultaneously be connected to this
bus, effectively shorting DUT pins together.
short TDMDigPin::abus_con(void)
Arguments:
none
DMCH[x]->abus_discon
Opposite of abus_con (opens relay to ABUS)
Example:
myPins5->abus_discon();
short TDMDigPin::abus_discon(void)
Arguments:
none
DMCH[x]->l1abus_con
Once a connection is made between the on board ABUS and a pin or group of pins, this bus will need to be
connected to the motherboard so it can connect to MPDS[0] via a connection called Line1 (or l1) on the
motherboard schematic.
Example:
DMCH[5]->l1abus_con();
short TDMDigPin::l1abus_con(void)
Arguments:
none
DMCH[x]->l1abus_discon
Disconnects the connection made by the l1abus_con command.
Example:
DMCH[5]->l1abus_con();
short TDMDigPin::l1abus_con(void)
Arguments:
none
DMCH[x]->dtiming
There are many parameters involved in setting up timing for a DIGMOD channel. This is the master
command that will allows setting all timing for a single timeset. It is also possible to set each parameter
individually.
Example:
digbus->dtiming( 2,
RZ,
10e-9,
9-77
50e-9,
0e-9,
80e-9,
60e-9,
70e-9,
0);
short TDMDigPin::dtiming( unsigned tset,

FORMAT format,
double start,
double stop,
double enastart,
double enastop,
double cmpstart,
double cmpstop,
unsigned dka)
Arguments:
unsigned tset // timeset range 0-15
FORMAT format // drive format (see sequencer section)
// available formats:
RZ (return to zero)
RO (return to one)
CS (complement surround)
RZC (RZ complement)
ROC (RO complement)
CSC (CS complement)
HIGH (high)
LOW (low)
CLK2 (2xtimeset rate)
NRZ (non return to zero)
HIZ (high impedance)
double start // driver start edge
double stop // driver stop edge (ignored for NRZ format)
double enastart// driver enable start edge
double enastop // driver enable stop edge
double cmpstart// compare start edge
double cmpstop // compare stop edge
unsigned dka // keep alive data (0 or 1)
Available formats: RZ (return to zero)

RO (return to one)
RZC (RZ complement)
ROC (RO complement)
CSC (CS complement)
HIGH (high)
LOW (low)
CLK2 (high at start time,
low at stop time,
high at start time*2,
low at stop time*2, …)
CLK4 (same as CLK2)
New Timing Setup Command: dtimingT0
Time is programmed as a multiplier of the T0 rate for the current timeset.

0 = Time 0
0.1 = 10% of T0 rate
1 = 100% of T0 rate
short dtimingT0(unsigned tset,FORMAT format, double start,double stop, double enastart=-1., double
enastop=-1, double cmpstart=-1., double cmpstop=-1., unsigned ka=0xFFFF);
Example:
WE ->dtimingT0(1, RO, 0.1, 0.6 ,0, 1, 0.50, 0.55, 1);
OE ->dtimingT0(1, HIGH, 0.0, 0.6 ,0, 1, 0.50, 0.55, 1);
CE ->dtimingT0(1, RO, 0.0, 0.7 ,0, 1, 0.50, 0.55, 1);
DATA->dtimingT0(1, NRZ, 0.0, 1.0 ,0, 1, 0.50, 0.55, 0);
ADDR->dtimingT0(1, NRZ, 0.0, 1.0 ,0, 1, 0.50, 0.55, 0);
9-78
Digital Instruments
DMCH[x]->dtiming_combine
Special variant of dtiming, which puts the pin into combine mode where the data from the next higher
channel is combined with the data from the existing channel to provide double the data rate of the
sequencer. This mode is only supported when the T0 Divider is set to 2. The data from the programmed
channel is used for the first MCLK cycle and the data from the adjacent channel is used for the second
cycle. Note that the adjacent channel can still be used in a static mode by using forcemode.
short TDMDigPin::dtiming_combine(unsigned tset,
FORMAT format,
double start,
double stop,
double enastart,
double enastop,
double cmpstart,
double cmpstop,
unsigned dka)
DMCH[x]->dfmt
The 'dfmt' command is similar to the 'dtiming' command except that only the drive edges are set.
Example:
digbus->dfmt(2,
RZ,
10e-9,
50e-9,
0);
short TDMDigPin::dfmt(unsigned tset,
FORMAT format,
double start,
double stop,
unsigned dka)
Arguments:
unsigned tset // timeset range 0-15
FORMAT format // drive format (see sequencer section)
// available formats:
RZ (return to zero)
RO (return to one)
RZC (RZ complement)
ROC (RO complement)
CSC (CS complement)
HIGH (high)
LOW (low)
double start // driver start edge
double stop // driver stop edge (ignored for NRZ format)
unsigned dka // keep alive data (0 or 1)
DMCH[x]->dcmp
The 'dcmp' command can be used to set the enable and comparator timing edges for the defined timeset.
No drive edges are set.
Example:
digbus->dcmp( 3, 40e-9, 60e-9, 70e-9);
short TDMDigPin::dcmp(unsigned _tset,

double _start,
double _stop,
double _ioswitch)
9-79
Arguments:
unsigned _tset // range = 0-15
double _start // 0-timeset max
double _stop // 0-timeset max (_stop>_start)
double _ioswitch // 0-timeset max
DMCH[x]->dcomp
The 'dcomp' command is similar to 'dcmp' except only the compare start edge is programmed. It is
assumed that the compare window will be open for 2 master clock cycles (MCLK - see PLL setting). It is
also assumed that the driver will be enabled at 0nS.
Example:
digbus->dcomp( 3, 40e-9);
short TDMDigPin::dcomp(unsigned _tset,
double _start)
Arguments:
unsigned _tset // range = 0-15
double _start // compare start edge
DMCH[x]->tset
If it is necessary to program individual timing for a specific timeset, this command will simply set a variable
that will define the timeset for subsequent timing commands that do not pass a 'timeset' argument.
Example:
DMCH[5]->tset(2);
short TDMDigPin::tset(double value)
Arguments:
double value // range = 0-15
DMCH[x]->fmt , DMCH[x]->format
This will set the drive format for the current timeset defined by the 'tset' command.
Example:
DMCH[5]->fmt(RZC);
DMCH[5]->format(RZC);
short TDMDigPin::fmt(FORMAT value)
Arguments:
FORMAT value // see 'dtiming' for available formats
DMCH[x]->start
This will set the drive start edge for the current timeset defined by the 'tset' command.
Example:
allpins->start(20e-9);
short TDMDigPin::start(double value)
Arguments:
double value // range=0-timeset rate
9-80
Digital Instruments
DMCH[x]->stop
This will set the drive stop edge for the current timeset defined by the 'tset' command.
Example:
allpins->stop(40e-9);
short TDMDigPin::stop(double value)
Arguments:
// (must be greater than start)
DMCH[x]->enastart
This will set the driver enable start edge for the current timeset defined by the 'tset' command.
Example:
allpins->enastart(0e-9);
short TDMDigPin::enastart(double value)
Arguments:
DMCH[x]->enastop
This will set the driver enable stop edge for the current timeset defined by the 'tset' command.
Example:
allpins->enastop(60e-9);
short TDMDigPin::enastop(double value)
Arguments:
double value // range=0-timeset rate (must be greater than the enastart edge)
DMCH[x]->cmpstart
This will set the comparator start edge for the current timeset defined by the 'tset' command.
Example:
allpins->cmpstart(70e-9);
short TDMDigPin::cmpstart(double value)
Arguments:
DMCH[x]->cmpstop
This will set the comparator stop edge for the current timeset defined by the 'tset' command.
Example:
allpins->cmpstop(80e-9);
short TDMDigPin::cmpstop(double value)
9-81
Arguments:
double value // range=0-timeset rate (must be greater than cmpstart edge)
DMCH[x]->keepalive
This will set the keepalive data for the current timeset defined by the 'tset' command.
Example:
allpins->keepalive(1); // 0=zero, 1=one
short TDMDigPin::keepalive(unsigned value)
Arguments:
unsigned value // 0=low, 1=high
Whether the driver drives high or low is a combination of the keepalive data and the pin's format. Note that
in KVD architecture, Keepalive mode is always active when a pattern is not bursting. This command does
NOT control whether or not Keepalive mode is active.
DMCH[x]->dka
This will set the keepalive data for the current timeset defined by the 'tset' command. It will also 'enable/
disable' the driver if desired.
Example:
allpins->dka(1,1);
short TDMDigPin::dka(unsigned value, unsigned _enable)
Arguments:
unsigned value // 0=low, 1=high
unsigned _enable // 0=disabled, 1=enabled
DMCH[x]->tmucon
Each DIGMOD board has a mux that can connect the high or low comparator buffered output to the
backplane to the KVD TMU Module, via the DDTMUA or DDTMUB bus.
Example:
XCLK->tmucon(DDTMUA, 1);
short TDMDigPin::tmucon(TMUCHAN tchan, unsigned hilo)
Arguments:
TMUCHAN tchan // DDTMUA or DDTMUB
unsigned hilo // 0=low comparator, 1=high comparator
Be extremely careful to not apply this command to pin groups so you do not short channels out.
DMCH[x]->measfreq
Each DIGMOD board has a built in TMU (time measurement unit) that allows for accurate measurements
of digital frequency. This is a useful feature for the measurement/adjustment of DUT built-in oscillator
circuits. The 'measfreq' command will return the measured frequency. Results will be placed in the proper
SITE->results[site].value array location for each site if the pins are setup in SiteMode. Otherwise the
results will be placed in SITE->lastresult.value. This is for convenience for the datalogging KVD->Test()
command.
9-82
Digital Instruments
Example:
XCLK->measfreq(DDTMUA, 1, 32, 10e-3);
double TDMDigPin::measfreq(TMUCHAN tchan,
unsigned hilo,
unsigned cycles,
double timeout)
Arguments:
unsigned cycles // cycles to measure over (2-65535)
double timeout // timeout (default timeout=500e-3)
DMCH[x]->start_measfreq
Each DIGMOD has a built in TMU on it, so to start parallel frequency measurements on pins that are on
separate DIGMOD boards the start_measfreq is used to start the measurement. A subsequent measfreq
command will readback the measurements from each of the boards.
Example:
XCLK->start_measfreq(DDTMUA, 1, 32, 10e-3);
Unsigned start_measfreq(TMUCHAN tchan, unsigned hilo, unsigned cycles, double timeout);
Arguments:
unsigned cycles // cycles to measure over (2-65535)
double timeout // timeout (default timeout=500e-3)
PMU Comparator Enables

short pmucompv(double lo, double hi); // Set PMU comparator levels for comparing voltage
short pmucompi(double lo, double hi); // Set PMU comparator levels for comparing current
The pmucompv and pmucompi statements setup "limits" for the voltage and current on the PMU. The PMU
comparators are routed to the functional comparators allowing either a pattern to verify status or for it to be
done via a snap() function.
These comparators are not calibrated or very accurate (10-20%) and to be used for a quick snap of
continuity or leakage. For example if your leakage specs are ±1uA then programming ±800nA on the 2uA
range would give you sufficient coverage on whether you are above or below the threshold. If you fail the
rough comparator test then the pins should individually be tested. The accuracy could somewhat be
improved with calibration, but in current mode the full scale voltage range to the comparators is only ±1V.
This could be effected by noise and resolution. Note that the snap() function for a group returns two bits
per group entry with the MSBs being the first entry in the mask.
Here is an example of 8 pins being measured in parallel for continuity:

unsigned contstatus;
ALLPINS->dig_con();
ALLPINS->setv(0);
ALLPINS->pmucompv(-0.8, -0.15);
ALLPINS->vclamps(-3,4);
ALLPINS->irange(3);
ALLPINS->vrange(0); // Needed to set lower V limit to below -1
ALLPINS->pmuenable(1);
SYS->del(3.0e-3);
// xtime1 = SYS->read_counter();
LOG->tnum(testnum+0);
DATA->seti(-100e-6);
SITE->lastresult.value = contstatus = DATA->snap();
9-83
if (KVD->Test())
return(FAIL);
DATA->setv(0);
contstatus = DATA->snap();
--------------------------------------------------------------------------
A grouped leakage example:

unsigned leakstatus;
ALLPINS->setv(0);
ALLPINS->irange(PMU_2UA);
ALLPINS->pmucompi(-0.8e-6, 0.8e-6);
ALLPINS->pmuenable(1);
SYS->del(3.0e-3);
// xtime1 = SYS->read_counter();
LOG->tnum(testnum);
SITE->lastresult.value = leakstatus = DATA->snap();
if (KVD->Test())
DIGMOD Sequencer Definition

Basics
The KVD Operating System defines a Sequencer as a single DIGMOD board, or a grouping of DIGMOD
boards. It is possible to slave all DIGMOD boards together for testing a single DUT with higher pin count,
or make each board independent and dedicated to a specific site.
Sequencer Definition & Grouping
While it is possible (and common practice) to construct an entire program using the system defined
sequencer (SEQ0), it is also possible to create a specific sequencer name that applies to a single
DIGMOD board, or a group of DIGMOD boards.
Single Board Sequencer

TSEQUENCER *JEFF_SEQ;
JEFF_SEQ = DMSEQCreate("JEFF_SEQ",0);
Now when the program executes a command that references 'JEFF_SEQ', only DIGMOD0 will run.
Grouping Boards
DIGMOD boards can also be 'grouped' together into one 'SEQUENCER'. This will allow for a single
sequencer command to act upon multiple DIGMOD boards. By default all installed boards are grouped to
the system defined sequencer 'SEQ0'.
TSEQUENCER *XYZ_SEQ;
XYZ_SEQ = DMSEQCreate("XYZ_SEQ", 0, 1, 2, 3);
This will group together DIGMOD0-DIGMOD3 and allow XYZ_SEQ commands to operate on all boards (0-
3).
9-84
Digital Instruments
DIGMOD Sequencer Programming

Here is a quick listing of commands that can be applied to the TSEQUENCER Class.
SetSiteMode keepalive_timeset update_status patexe_array

SetMode dstop status patexe_parallel
mclk_sel dflags set_wait_timeout getsym
MasterSlave read_status patload dcap_setup
SetupMCLK dwait patload_parallel
dt0t dfail patload_pformat
dt0div cycle_count patexe
Sequencer Programming Functions
SEQ0->SetSiteMode
Assigns a DIGMOD board to a specific site. The default is FALSE and all boards will not be assigned to
specific sites, instead all will be assigned to a site 0. A multisite program must assign boards of a
SEQUENCER group to specific sites.
Example:
SEQ0->SetSiteMode(TRUE, 0,1,2,3);
This will sequentially assign each DIGMOD board in the SEQ0 group to a specific site. Since SEQ0 is a
system defined group, this example will map out as follows:
DIGMOD0 -> site0
DIGMOD1 -> site1
DIGMOD2 -> site2
DIGMOD3 -> site3
void TSEQUENCER::SetSiteMode(bool _sitemode,
short _site0,
short _site1,
short _site2,
short _site3,
short _site4,
short _site5)
Arguments:
bool _sitemode // TRUE or FALSE
short _site0 // 0-5
short _site1 // 0-5
short _site2 // 0-5
short _site3 // 0-5
short _site4 // 0-5
short _site5 // 0-5
SEQ0->SetMode
This will set the operational mode of all boards that are included in the SEQUENCER.
Example:
SEQ0->SetMode(DM_INDEPENDENT,
DM_INDEPENDENT,
DM_INDEPENDENT,
DM_INDEPENDENT,
DM_INACTIVE,
DM_INACTIVE);
9-85
Options:
DM_NOTPRESENT - if DIGMOD is not loaded in test head
DM_MASTER - this board will be the master of all boards
DM_SLAVE - this board will sync to the MASTER
DM_INDEPENDENT - will run on its own clock, not a master or slave
DM_INACTIVE - board loaded in test head but not active for device test.
This example will set the first 4 DIGMOD boards of the SEQUENCER group to independent mode of
operation. All boards will have their own clock setup and will not be synchronous in any way. The last 2
boards in the SEQUENCER group are present in the head but are not used for this example.
void TSEQUENCER::SetMode(DMMODE _mode0,
DMMODE _mode1,
DMMODE _mode2,
DMMODE _mode3,
DMMODE _mode4,
DMMODE _mode5)
Arguments:
DMMODE _mode0
DMMODE _mode1
DMMODE _mode2
DMMODE _mode3
DMMODE _mode4
DMMODE _mode5 // following options for all:
// DM_NOTPRESENT
// DM_MASTER
// DM_SINGLEMASTER
// DM_SLAVE
// DM_INDEPENDENT
// DM_INACTIVE
DM_NOTPRESENT - if DIGMOD is not loaded in test head
DM_MASTER - this board will be the master of all boards
DM_SINGLEMASTER - ?
DM_SLAVE - this board will sync to the MASTER
DM_INDEPENDENT - will run on it's own clock, not a master or slave
DM_INACTIVE - board loaded in test head but not active for device test
SEQ0->mclk_sel
Selects a clock source for a DIGMOD defined as a MASTER in the SEQUENCER group, then configures
all 'SLAVE' boards to sync off of the MASTER. The master clock can come from several sources. Most
common and with most programmability would be the DM_PLLCLK. Other options include an external
clock derived on the Fathercard. All slave boards will use the DM_XSICLK that is produced on the
MASTER but that is handled by KVD library code.
Example:
SEQ0->mclk_sel(DM_PLLCLK);
void TSEQUENCER::mclk_sel(DM_CLK source)
Arguments:
DM_CLK source // following options
// DM_100MHZCLK= on board 100MHZ clock
// DM_PLLCLK = on board PLL clock
// DM_FCINCLK = clock from Fathercard
// DM_XSICLK = not allowed here
Note that if DM_PLLCLK is selected, it is necessary to program the PLL frequency.
SEQ0->MasterSlave
Selects the MASTER and connects others as SLAVE. For this example DIGMOD0 is the Master, other
active boards will be connected as SLAVE.
9-86
Digital Instruments
Example:
SEQ0->MasterSlave(0);
void TSEQUENCER::MasterSlave(unsigned _master)
Arguments:
unsigned _master // which DIGMOD board is the MASTER
SEQ0->SetupMCLK
Sets up the PLLCLK on ALL boards in the SEQUENCER, regardless of configuration. This will set the PLL
for all boards in the SEQUENCER as close to 100 MHz as possible, given the PLL limitations. If the
frequency is specified as 100MHz, the oscillator will be selected instead of the PLL. For most applications
this command will adequately setup the Master Clock.
Example:
SEQ0->SetupMCLK(100e6);
double TSEQUENCER::SetupMCLK(double freq)
Arguments:
double freq // which DIGMOD board is the MASTER
SEQ0->dt0t
Sets the T0 cycle rate for a specific timeset. Operates on all boards in the SEQUENCER. This will set the
rate for timeset 2 to 12.5 MHz, or as close as possible given the current MCLK settings. A alternate and
more reliable approach might be to program the timeset rate as a divider of MCLK. See 'dt0div'.
Example:
SEQ0->dt0t(2, 12.5e6);
short TSEQUENCER::dt0div(unsigned timeset, double freq)
Arguments:
unsigned timeset // 0-15
double freq // programmed in Hz
SEQ0->dt0div
Sets the T0 cycle rate for a specific timeset. Operates on all boards in the SEQUENCER as a divider ratio
of the master clock (MCLK). The divisor is an integer between 2 and 128. If the MCLK has been set to
100MHz, this command will adjust timeset 2 to be MCLK/100 = 1MHz.
Example:
SEQ0->dt0div(2, 100);
short TSEQUENCER::dt0div(unsigned timeset, unsigned t0div)
Arguments:
unsigned t0div // 2-128
SEQ0->keepalive_timeset
Sets the timeset to be used when the pattern is halted. This will set the keepalive timeset to 6. This
command is useful if the device requires an external clock running continuously after the pattern stops. By
changing the timeset, the clock rate can be modified without running a pattern.
9-87
Example:
SEQ0->keepalive_timeset(6);
short TSEQUENCER::keepalive_timeset(unsigned timeset)
Arguments:
SEQ0->dflags
This function gives the ability to set the User Flags, most often referred to as U1 and U2. This function has
the ability to set both flags simultaneously if desired. This will set the U1 flag. If the pattern is at a point
where it is waiting (using a conditional flag test) for the flag, it will continue after the flag is set.
Example:
SEQ0->dflags(1);
short TSEQUENCER::dflags(unsigned value)
Arguments:
unsigned value // 1=U1 flag, 2=U2 flag, 3=both
SEQ0->running
Checks to see if a pattern is running or halted.
Example:
short i;
i=SEQ0->running();
If the pattern is running, i=1, if halted i=0.
short TSEQUENCER::running(void)
Arguments:
none
SEQ0->dwait
Waits for the pattern to finish execution. The wait time is determined by the 'set_wait_timeout' command.
The default is 1 Sec. The test program will effectively halt here until the pattern has completed execution.
Note that the 'side' argument is not required but included for backwards (DSPIO) compatibility.
Example:
SEQ0->dwait();
short TSEQUENCER::dwait(unsigned __side)
Arguments:
unsigned __side // tester "side" 0-1
SEQ0->dfail
Returns the number of fails after pattern execution. Most often the user will favor the 'status' command as
it will provide more detailed fail information, and will also include the number of fails. After pattern
execution, the number of fails is returned. Note that the 'side' argument is not required but included for
backwards (DSPIO) compatibility.
9-88
Digital Instruments
Example:
unsigned xfail=SEQ0->fail();
short TSEQUENCER::dfail(unsigned __side)
Arguments:
unsigned __side // tester "side" 0-1
SEQ0->cycle_count
Returns the number of cycles after pattern execution. Most often the user will favor the 'status' command
as it will provide more detailed information, and will also include the number of executed cycles.
Example:
unsigned xcycle=SEQ0->cycle_count();
short TSEQUENCER::cycle_count(void)
Arguments:
none
SEQ0->status
This function should be executed after each pattern execution. The updated status information is
determined by the setting of the StatusControl variable (SEQ0->StatusControl). The default setting for
StatusControl is 1. The following listing briefly indicates information provided with the allowed settings. It is
important to note that if more information is required (higher StatusControl setting) program execution time
will increase. For production operation, StatusControl setting of "1" or "2" is usually sufficient. Other
settings are useful for pattern/program debug.
StatusControl Setting Status Results
1 Read Failcounter, Cycle Counter, Note Register, and Running
2 Read all fail addresses (in addition to above)
3 Write Pat.stat file (in addition to above)
4 Write Fail[x].stat file (in addition to above)
5 Create FDUMP file with Fail information
6 Write Status bits
Example:
SEQ0->StatusControl=2;
SEQ0->pat_exe(mystart, mypattern);
SEQ0->dwait();
SEQ0->status();
SEQ0->StatusControl=1;
This example sets the StatusControl variable to 2 which will allow the user to examine the following:
number of fails, number of executed cycles, value of the 'NOTE' register, running status, and all fail
address information (up to 512 fails). It is usually desirable to set StatusControl back to "1" after reading
status.
short TSEQUENCER::status(void)
9-89
Arguments:
none
Note: The 'status' function should only be executed one time after pattern execution. Multiple 'status'
commands will produce unknown results.
SEQ0->set_wait_timeout
Sets the amount of time that the 'dwait' command will actually wait for the pattern to finish. The default is 1
second.
Example:
SEQ0->set_wait_timeout(0.20);
void TSEQUENCER::set_wait_timeout(double timeout)
Arguments:
double timeout// 0-?
SEQ0->get_wait_timeout
Reads back the current dwait timeout setting.
Example:
double xwait;
xwait=SEQ0->get_wait_timeout();
double TSEQUENCER::det_wait_timeout(void)
Arguments:
none
Pattern Management and Execution
SEQ0->patloadmap
Launches the Pattern Manager to read the <application>.map file. The pattern manager will automatically
load the patterns in the map file if in production mode. In Engineering mode the Pattern Manager will wait
for the user to select which patterns to load.
Example:
SEQ0->patloadmap();
short TSEQUENCER::patloadmap(void)
Arguments:
none
9-90
Digital Instruments
Figure 9.41: Pattern Manager
SEQ0->createpatmap
Creates a Pattern Map file (<application>.map) from the traditional pat_list structure. The function stores
the actual pattern length in the map file.
Example:
SEQ0->createpatmap(pat_list, PATDIR, 1);
short TSEQUENCER::patload(PATDATA* pat_list, char* pat_dir, int parallel_flag)
Arguments:
PATDATA* pat_list // listing of patterns to be loaded
char* pat_dir // directory where patterns are located
int parallel_flag // specifies if the same pattern should
// be loaded into multiple DIGMOD
// boards for multisite
SEQ0->patload
Loads a list of patterns that are contained in the pattern list structure. The pattern list structure is detailed
elsewhere in this manual.
Example:
SEQ0->patload(pat_list, PATDIR);
short TSEQUENCER::patload(PATDATA* pat_list, char* pat_dir)
Arguments:
9-91
SEQ0->patload_parallel
Loads a list of patterns that are contained in the pattern list structure. The patload_parallel function has the
capability to load the same patterns on multiple DIGMOD boards.
Example:
SEQ0->patload(pat_list, PATDIR, 0xf);
SEQ0->patload(pat_list, PATDIR, 0x3);
The first line of the above example will load a list of patterns on the first 4 DIGMOD boards defined in the
Test Head Configuration. The second line above will load the list of patterns on only the first 2 DIGMOD
boards.
short TSEQUENCER::patload(PATDATA* pat_list,
char* pat_dir,
unsigned slotmask)
Arguments:
unsigned slotmask // mask of DIGMOD boards
SEQ0->patload_pformat
Loads a list of pformat-style patterns that are contained in the pattern list structure. The pattern list
structure is detailed elsewhere in this manual.
Example:
SEQ0->patload_pformat(pat_list, PATDIR);
short TSEQUENCER::patload_pformat(PATDATA* pat_list, char* pat_dir)
Arguments:
SEQ0->patexe
Executes a DIGMOD pattern contained in a specific pattern file. The pattern can be run from any starting
point label or offset.
Example:
SEQ0->patexe("PATTERN2", "START2");
This will simply execute the "PATTERN2" pattern from the "START2" label
short TSEQUENCER::patexe(AnsiString patternname,
AnsiString asymbol)
Arguments:
AnsiString patternname // the pattern name
AnsiString asymbol // starting point represented
// by a label
Alternate 1: using the pattern index

Example:
unsigned PATTERN2=2; // pattern index
SEQ0->patexe(PATTERN2, "START2");
9-92
Digital Instruments
short TSEQUENCER::patexe(unsigned pattern,

AnsiString asymbol)
Arguments:
unsigned pattern // pattern index
AnsiString asymbol // starting point represented by a label
Alternate 2: using the pattern index and offset

Example:
unsigned START2= SEQ0->getsym(PATTERN2, "START2"); // starting offset
SEQ0->patexe(PATTERN2, START2);
short TSEQUENCER::patexe(unsigned pattern,

unsigned offset)
Arguments:
unsigned offset // starting offset
Note that in almost all cases it is preferable to use the string arguments for this command. Alternative
methods are for reference only.
SEQ0->patexe_array
Executes a DIGMOD pattern contained in a specific pattern file. The pattern can be run from any point
(offset). In addition this function adds the capability to run each DIGMOD board from a different offset if
desired.
Example:
unsigned startoff[4]; // starting offset array
unsigned startoff[0]= SEQ0->getsym(PATTERN2, "START0");
SEQ0->patexe_array(PATTERN2, startoff);
In the above example the first 4 DIGMOD boards that are defined in the SEQUENCER will run from
different starting points, determined by the array 'startoff'. The first board will run from 'startoff[0]' the 4th
board will run from 'startoff[3].
short TSEQUENCER::patexe_array(unsigned pattern,
unsigned offset[])
Arguments:
unsigned offset[] // starting offset array
SEQ0->patexe_parallel
Executes a DIGMOD pattern contained in a specific pattern file. The pattern can be run from any point
(offset). In addition this function adds the capability to run only those DIGMOD boards that are represented
in the 'slotmask'.
Example:
unsigned PATTERN2=2;
unsigned START2= SEQ0->getsym(PATTERN2, "START2");
SEQ0->patexe_parallel(PATTERN2, START2, 0x7);
9-93
In the above example only the first 3 DIGMOD boards that are defined in the SEQUENCER will run. If
other DIGMOD boards are included in the SEQUENCER, they will be idle.
short TSEQUENCER::patexe_parallel(unsigned pattern,
unsigned offset,
unsigned slotmask)
Arguments:
unsigned offset // starting offset
unsigned slotmask // board mask
SEQ0->getsym
When patterns are compiled using the KVD Pattern Compiler, a SYM file (patternname.sym) is created.
This file contains all of the patterns 'symbols' also referred to as 'labels', and a relative offset of each
symbol from the beginning of the pattern. If the programmer wishes to run a pattern from an 'unsigned'
offset (as opposed to AnsiString representation) then the 'getsym' function is used to read the offset.
Example:
unsigned PATTERN2=2;
unsigned START2= SEQ0->getsym(PATTERN2, "START2");
SEQ0->patexe(PATTERN2, START2);
int TSEQUENCER::getsym(unsigned pattern,

AnsiString symbol)
Arguments:
AnsiString symbol // actual label (symbol) in the pattern
SEQ0->dcap_setup
Sets up the 'capture memory' for each DIGMOD board defined in the SEQUENCER. This will set up each
DIGMOD board in the SEQUENCER to capture 1024 digital samples, and will save the results starting with
address 100 of the capture memory.
Example:
SEQ0->dcap_setup(100, 1024);
short TSEQUENCER::dcap_setup(unsigned long cap_adr,

unsigned long cap_count)
Arguments:
unsigned long cap_adr // starting address (0-16M)
unsigned long cap_count // number of captures
// (1-16M-starting address)
DIGMOD[x]->dcap_setup
Sets up capture memory on an individual DIGMOD board.
Example:
DIGMOD[x]->dcap_setup(100,1024);
short TDIGMOD::dcap_setup(unsigned long cap_adr,
unsigned long cap_count)
9-94
Digital Instruments
Arguments:
unsigned long cap_adr // starting address (0-16M)
unsigned long cap_count // number of captures
// (1-16M-starting address)
DIGMOD[x]->dcap_read
Reading back capture memory is best handled on an individual DIGMOD basis instead of as a group. The
command dcap_read reads back the data from an individual DIGMOD board into array cap_data. Note the
side parameter is ignored and is a relic of the DSPIO.
Example:
DIGMOD[x]->dcap_read(1, 100, 1024, cap_data);
short TDIGMOD::dcap_read(unsigned _side, unsigned long cap_adr, unsigned long cap_count, unsigned
cap_data[])
DIGMOD[x]->ddrv_setup
Sets up send memory to start at drv_adr and to loop after drv_length addresses. Note send memory is
shared with capture memory, so you need to manage the address space to avoid collisions.
Example:
DIGMOD[x]->ddrv_setup(1500, 1024);
short TDIGMOD::ddrv_setup(unsigned long drv_adr, unsigned long drv_length)
DIGMOD[x]->ddrv_load
Loads the drive memory for the DIGMOD board. Since the test engineer is likely sending different data to
each DUT in a multisite environment, this typically needs to be handled per DIGMOD instrument instead of
as a group.
Example:
DIGMOD[x]->ddrv_load(1500, 1024, drv_data[]);
short TDIGMOD::ddrv_load(unsigned long drv_adr, unsigned long drv_count, unsigned drv_data[])
DIGMOD .pformat Pattern File Structure

PFORMAT Pattern Structure
The DIGMOD instrument is capable of loading a binary formatted file which has a .pformat extension. This
is a streamlined file that is significantly smaller in physical size than the .bp format. These binary pattern
files contain only relevant pin information, if a pin is not active, or not changing, no information is stored.
The other benefit of the new compiled pattern format is that many new features of DIGMOD are supported.
Some of these new features include:
• Drive/Compare SHIFTR, SHIFTR2 and SHIFTL, SHIFTL2 (previously only SHIFTL)
• Compare for mid level
• Same Cycle Drive/Compare
• No change
• Scope Trigger
9-95
The reduction in file size is can be significant. In several example cases, a .bp file required 8.775MB, while
the corresponding .pformat file was just 1.894MB. In another case the file size changed from 2.01MB to
435KB.
Loading .pformat Files
The pattern file structure and pattern loading are similar to the previous structure and loading. See the
examples below for details:
Old Pattern Structure

{0, "UC06SPI.BP", 0, 0x30000UL, 10000UL, 1, 2, -1},

{1, "UC06_PATTERN3.BP", 0, 0UL, 0x2ffffUL, 1, 2, -1},
{2, "UC06_PATTERN4.BP", 0, 0x20000UL, 20000UL, 1, 2, -1},
{3, "SERVICEPATT.BP", 0, 0x23000UL, 10000UL, 1, 2, -1},
{4, "UC06_PATTERN3_BIT_CAPTURE.BP", 0, 0x40000UL, 10000UL, 1, 2, -1},
{5, "UC06_PATTERN4_BIT_CAPTURE.BP", 0, 0x50000UL, 10000UL, 1, 2, -1},
{6, "F0F7CHECK.BP", 0, 0x60000UL, 10000UL, 1, 2, -1},
{7, "F0F7CHECK_NEW.BP", 0, 0x70000UL, 10000UL, 1, 2, -1},
{-1, "NOPATT", 0, 0UL, 0UL, 0, 2, -1}
};
New Pattern Structure

PATDATA pat_list2[] = {
{0, "UC06SPI.PFORMAT", 0, 0x30000UL, 10000UL, 1, 2, -1},

{1, "UC06_PATTERN3.PFORMAT", 0, 0UL, 0x2ffffUL, 1, 2, -1},
{2, "UC06_PATTERN4.PFORMAT", 0, 0x20000UL, 20000UL, 1, 2, -1},
{3, "SERVICEPATT.PFORMAT", 0, 0x23000UL, 10000UL, 1, 2, -1},
{4, "UC06_PATTERN3_BIT_CAPTURE.PFORMAT", 0, 0x40000UL, 10000UL, 1, 2, -1},
{5, "UC06_PATTERN4_BIT_CAPTURE.PFORMAT", 0, 0x50000UL, 10000UL, 1, 2, -1},
{6, "F0F7CHECK.PFORMAT", 0, 0x60000UL, 10000UL, 1, 2, -1},
{7, "F0F7CHECK_NEW.PFORMAT", 0, 0x70000UL, 10000UL, 1, 2, -1},
{-1, "NOPATT", 0, 0UL, 0UL, 0, 2, -1}
};
// Note pat_list2 difference is only .PFORMAT extension
Pattern Loading
The loading of .pformat files is very similar to loading .bp files. The significant advantage is that the .bp files
typically included information for only one site. The user was required to specify with a loadmask which
boards would be loaded with the same pattern information.
.bp Pattern Loading (multisite):

SEQ0->patload_parallel(pat_list, PATDIR, 0xf);
//load all 4 dspio
.pformat Loading:
SEQ0->patload_pformat(pat_list2, PATDIR); //load all pins
9-96
Digital Instruments
DIGMOD Resource Manager (DMRMan)
In the past it has been necessary to include DIGMOD (and DSPIO) pins in several places including each
pattern file and also in the test program - usually in a resource.cpp or connections.cpp file. While it is still
possible to map pin names to DIGMOD pin numbers in the test program, it is now possible to map these
names and channels in one .ini files that is read by the test program. This new approach will simplify pin
definition and reduce errors.
The DIGMOD Resource File
Here is a typical .ini file containing DIGMOD resources mapped to names.

[SITE_DMCH]
PA0_SCLK = 1, 33, 65, 97
PA1_SO = 0, 32, 64, 96
PA2_SI = 15, 47, 79, 111
PA3_CS = 2, 34, 66, 98
PA4 = 3, 35, 67, 99
PA5 = 4, 36, 68, 100
PA6 = 5, 37, 69, 101
PA7 = 6, 38, 70, 102
CHG = 7, 39, 71, 103
NEG = 8, 40, 72, 104
DIS = 9, 41, 73, 105
MCLRB = 10, 42, 74, 106
XCLK = 11, 43, 75, 107
IDDQ = 12, 44, 76, 108
ODI = 13, 45, 77, 109
TXRX = 14, 46, 78, 110
[GROUP_DMCH]
SITEPINS0 = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
SITEPINS1 = 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47
SITEPINS2 = 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79
SITEPINS3 = 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111
------------------------------
There are 3 possible options for mapping channels. Two of these options, [SITE_DMCH] and
[GROUP_DMCH] can be seen in the above file. Pins that are mapped in he [SITE_DMCH] section will be
mapped according to site. For this example there are four sites and each name contains a pin for each
site. The pins can also be mapped into groups using the [GROUP_DMCH] section. In addition to these
groupings it is also possible to individually map pin names to DIGMOD pins. This would require a third
section not seen in the above example and would be used mostly in single site test programs. A short
example is shown below:
[SINGLE_DMCH]
mypin1 = 45
mypin2 = 6
mypin3 = 9
Loading the DMResources ini File
Once the resources file has been created, it is necessary to load the file so the pin-to-name mapping can
occur. This loading is done in the test program and it is important that the loading occur BEFORE any
pattern loading, otherwise the pattern will not map/load correctly.
DMRMan->LoadResMap("MAP_FILENAME.INI");
Typically the filename will have some relation to the test program, for example in the UC06 program we
might use "UC06_DMRESOURCES.INI".
9-97
Mapping Names to Pins
Once the file is loaded, the names defined in the test program can be correctly mapped to the DIGMOD pin
resources. The required syntax is as follows:
DMRMan->DMCHFromMap("pin_site_group_name");
Example:
PA0_SCLK = DMRMan->DMCHFromMap("PA0_SCLK");
PA1_SO = DMRMan->DMCHFromMap("PA1_SO");
PA2_SI = DMRMan->DMCHFromMap("PA2_SI");
PA3_CS = DMRMan->DMCHFromMap("PA3_CS");
PA4 = DMRMan->DMCHFromMap("PA4");
CHG = DMRMan->DMCHFromMap("CHG");
NEG = DMRMan->DMCHFromMap("NEG");
DIS = DMRMan->DMCHFromMap("DIS");
MCLRB = DMRMan->DMCHFromMap("MCLRB");
XCLK = DMRMan->DMCHFromMap("XCLK");
IDDQ = DMRMan->DMCHFromMap("IDDQ");
ODI = DMRMan->DMCHFromMap("ODI");
TXRX = DMRMan->DMCHFromMap("TXRX");
SITEPINS[0] = DMRMan->DMCHFromMap("SITEPINS0");
It is still possible to map channels the "old" way, but for future program simplicity, it is recommended that
resources are mapped through the DMResource manager.
DIGMOD Pattern Editor

DIGMOD Pattern Editor
There is significant new functionality in a Pattern Editor designed for DIGMOD support. Failure data is
communicated back into the tool from the instruments, graphical displays are improved over the DSPIO
tool, and it supports the .pformat channel description structure.
New features:
• Ability to create a pattern from scratch
• Inserting and deleting vectors: right click in the left most column (the vector num column) and then
choose insert or delete rows. When inserting the user specifies how many new vectors to add, and
then adds them prior to the current vector. When deleting vectors: the current vector is the start vector,
and the user inputs the last vector number to delete. The deletion is inclusive of the start and end
vector numbers.
• More editable opcodes
• Better navigation and scrolling
9-98
Digital Instruments
The editor has three main display tabs. The plain vector view:
Figure 9.42: Main DM Pattern Editor screen
At the bottom of the left side pane, tabs are available for switching support displays between:
• Fail Control (shown above)
• File Info (header info for revision control and size)
• Command Line Interface
• Functions (find label and go to vector)
• Symbols (makes it possible to jump to a symbol)
• Pin Groups (easier display of defined names)
• Static Pins (to display pins not being controlled by vector data)
9-99
A graphical view:
Figure 9.43: DM Pattern Editor Graphical View
9-100
Digital Instruments
And a display of the pin formats:
Figure 9.44: DM Pattern Editor Format View
If you double-click on a column label such as OPCODE, it will pop up a list of allowable values. These are
the lists for:
OPCODE FLAGS and SR (Shift Register)
9-101
There is on-line help available from the top-level menu item HELP.
Figure 9.45: Help Screen
Logic Analyzer Mode for the DIGMOD Pattern Editor
The Logic Analyzer tool is a component of KVD DM Pattern Editor. This tool is useful when debugging DM
patterns. To properly use Logic Analyzer, several steps are required, and some caution is necessary.
Necessary Steps
1. The pattern to be debugged must include the "LOGIC" opcode at the point in the pattern where debug
will start. The operand must be "1".
2. A "LOGIC" opcode with a "0" operand must be included in the pattern where debug will stop. Note that
once these opcodes are included, the pattern will NOT fail at any point between the LOGIC 1 and the
LOGIC 0 vectors.
3. The pattern should be run normally using the "patexe" function:
SEQ0->patexe("PATTERN1", "START1");
4. After executing the pattern, Logic analyzer must be setup and run before the results can be viewed.
9-102
Digital Instruments
Cautions
The pattern that is being debugged will not fail between the LOGIC opcodes. It will be necessary to change
the pattern back to original for normal program operation.
The pattern must be repeatable - each execution must produce the same results or the Logic Analyzer
display will not be very helpful. Logic Analyzer works by setting the compare strobes at the beginning of
the cycle, executing the pattern, saving the data for pins of interest (send/capture memory is used), moving
the compare strobes, and then re executing the pattern, save etc. etc. If the results from the DUT are not
repeatable from one run to the next (if the pattern does not "FAIL" the same way each run), Logic Analyzer
is not going to be a useful debug tool.
The Send/Capture memory is used to save pattern information. The default memory start address is
0x800000 (8388608). This is at ½ of the total Send/Capture memory. It is important to note that if the test
program uses this part of the send memory (unlikely since 8M is available) then the programmer must
indicate an alternate start point.
Logic Analyzer Class User Functions

short TLogicAnalyzer::Setup (TDMDigPin *pins,
double T0period,
unsigned vectors,
unsigned tsmin,
unsigned tsmax,
unsigned capmemstart,
unsigned finediv );
where:
*pins = a group of DIGMOD pins to be displayed in the Logic Analyzer tool.
T0period = the tester cycle of interest
vectors = the number of vectors to be analyzed.
tsmin = the minimum timeset to be analyzed.
tsmax = the maximum timeset to be analyzed.
capmemstart = the starting capture memory location (default = 0x800000)
finediv = the compare strobe step for each capture (default =1 which is ½ MCLK cycle)
9-103
void TlogicAnalyzer::Run();
This function should be executed after setting up the Logic Analyzer using the "Setup" function.
Figure 9.46: Logic Analyzer
9-104
Digital Instruments
This shows the results for the pins of interest after logic analyzer has executed. Note that Logic Analyzer is
a tab of the DM Pattern Editor tool.
Figure 9.47: Results for Pins of Interest
9-105
This shows the same capture, but the "SPAN" and "POSITION" sliders at the bottom of the tool have been
used to zoom in to the desired resolution and the scroll to the area of interest.
Figure 9.48: Use the Span and Position Sliders to Adjust Resolution
This is a program file block that shows typical C++ steps for using Logic Analyzer:
1. Run pattern normally.

2. Setup logic analyzer.
3. Run logic analyzer.
9-106
Digital Instruments
Note that the logic analyzer tool is updated after the LogicAnalyzer->Run() has executed. Results can be
viewed using DM Pattern Editor.
Figure 9.49: Results Shown in the DM Pattern Editor
This shows the inclusion of the "LOGIC 1" opcode/operand combination in the pattern.
DIGMOD SHMOO
Note: This function operates with the DIGMOD instrument commands only.
Shmoo plots allow the engineer to plot results of a test while two parameters, that may affect the test, are
altered. Following some simple rules, practically any parameters can be used. The shmoo plot is
implemented on the KVD tester in the following manner. The shmoo plot is generated, then a function is
assigned for the x axis, with parameters that indicate the start, stop, and increment values to be used. The
same thing applies to the y axis. Then, a 'main' function is assigned as the test routine that will determine
the pass or fail status for each x and y point on the plot. Setting up the axis' is made with one command for
the x axis, and another for the y axis. Setting up the main parts of the plot are done using another routine.
9-107
To get started, the engineer calls the NewShmoo command to create a shmoo plot framework. This
framework will be used for all interactions with the plot. The NewShmoo command returns a pointer
variable of type TFORMshmoochild ;
TFORMshmoochild* myshmoo;
myshmoo=ShmooMan->NewShmoo(<AnsiString tabsheet_caption>);
The parameter <AnsiString tabsheet_caption> is a string that will be displayed on the tabsheet that will
hold the shmoo plot.
Figure 9.50: Schmoo Plot

TFORMshmoochild* myshmoo;
myshmoo = ShmooMan->NewShmoo("How To Shmoo");
Once you have a handle to your shmoo, the next step is to set up the look of the shmoo, along with the
boundaries and functions that the shmoo will use to produce the plot.
X Axis
• Xfunc - the function that will be called, with a parameter of type double passed in. This value is
determined by the next three variables.
• XMin - the start value used by the x axis function.
• XMax - the stop value used by the x axis function.
• XInc - the increment used to scan from the xmin value up to the xmax value, inclusive.
• Xtitle - the title that appears on the x axis.
• Xunits - the units that will be assumed for the x axis.
Y Axis
• Yfunc - the function that will be called, with a parameter of type double passed in. This value is
determined by the next three variables.
• YMin - the start value used by the y axis function
• YMax - the stop value used by the y axis function
• YInc - the increment used to scan from the ymin value up to the ymax value, inclusive.
• Ytitle - the title that appears on the y axis.
• Yunits - the units that will be assumed for the y axis.
9-108
Digital Instruments
Main
• ExeFunction - the function the shmoo plot will call to run the test (for each unique x/y value
combination). The function format must be that it takes a 'short' type parameter, which is the site
number, and returns a short value ( where a value of 0 indicates a fail, and any other value indicates a
pass).
• MainTitle - the shmoo plot's main title line.
• SecondaryTitle - another text line that appears below the MainTitle line.
General Fields
• Xfastmode - when Xfastmode is set to true (which is the default), the Xfunc function is called with all of
x values, for each y value. If Xfastmode is false, then the plot calls the Yfunc function with all y values,
for each x value.
• Disablerepaint - drawing each plot result in real time can be done, but will slow down the process. The
user has the option of disabling the repaint of the screen until ALL x and y values for the plot have
been tested. Once all testing has finished, the results are then displayed. In contrast, if DisableRepaint
is set to false, each result is plotted as it happens.
• InteractiveMode - if the engineer wants to have the process stalled at the calling of the shmoo's 'Run()'
call, then set InteractiveMode to true. The plot can then be run, and x and y axis valued altered. If
InteractiveMode is set to false, then when the RUN() function is called, the plot is executed (all x and y
value combinations are tested and plotted) and then the test program continues.
The commands to setup the plot are as follows.

TFORMshmoochild ::SetupXAxis(double xmin, double xmax, AnsiString xtitle, AnsiString xunits,
ShortFuncDouble* xfunc, TAXISTTYPE xaxistype);
The ShortFuncDouble * type is simple a function pointer. It must point to a function which takes one double
value as a parameter, and returns a short result value. The shmoo plot ignores the return value.
TAXISTYPE is an enumerator type that can be used to tell the shmoo plot whether the x axis represents
time, frequency, or volts, amps, or something else. The allowed values for xaxistype are saTIME,
saVOLTS, saFREQ, saAMPS, saUNDEF, saNONE.
In our example, this was the command used for the x axis setup:
myshmoo ->SetupXAxis(100e-3, 200e-3, 2e-3, "XTitle", "mV", DMCH[0]->vil, saVOLTS);
TFORMshmoochild ::SetupYAxis(double ymin, double ymax, AnsiString ytitle, AnsiString yunits,

ShortFuncDouble* yfunc, TAXISTTYPE yaxistype);
For our example, the function call was

myshmoo->SetupYAxis(200e-3, 400e-3, 20e-3, "YTitle", "mV",DMCH[0]->vih, saVOLTS);
TFORMshmoochild::SetupChart(AnsiString MainTitle, AnsiString SecondaryTitle, bool xfastmode, bool

disablerepaint);
For our example, we used :

myshmoo->SetupChart("This is the chart main title","second verse",false,false);
This was not run in xfast mode (thus running in what would be yfast mode), and not repainting the screen
after each test, but to show the results after ALL the points have been tested.
SetExeFunction(ShortFuncShort* exefunction);
9-109
The ShortFuncShort* type is a function pointer to a function that takes one short type as a parameter
(which will be equal to the site value) and returns a short (0 for fail, any other for passing). In our example,
we just set up our own function that would randomly generate a pass or fail. This was out main function:
short MyExecute();
short MyExecute(short site=0)
{
int x=random(10);
if (x>5) return 1;
return 0;
}
and our setup call was

myshmoo->SetExeFunction=MyExecute;
Once the shmoo has been setup, you simply need to call TFORMshmoochild::Run() whenever you want
the shmoo to run, or enter in interactive mode (if it has been set). Again, for this example, we used:
myshmoo->Run();
How it Works
When run is called, internal variables are set to the xmin and ymin values. Then, in a loop that is either
calling the x axis function for all x value (in xfastmode) or vice versa (if in yfastmode), the x and y values
are set, the x and y functions are called, and then the exefunction is called. When the exefunction returns,
we use the return value to determine whether that point on the plot would be red(fail) or green(pass). We
also determine at this time whether to show the result (disablerepaint is false) or not. This loop continues
for all x and y values.
A Word About the GUI Interface
If you look on the screen shot, notice that there are RUN SHMOO and a CONTINUE buttons on the right
side. These only appear if Enable Interactive Mode is checked (interactivemode is true). Clicking on RUN
forces the Run() function to be called. Clicking on CONTINUE forces the shmoo to jump out of interactive
mode, and return to the main program flow. On the next device to be tested, the shmoo will enter
interactive mode again, and this will continue until the Enable Interactive Mode checkbox is cleared, or
interactivemode is cleared programmatically.
Other Commands
Some value can be entered directly, and are not limited to being a parameter in one of the above function
calls.
TFORMshmoochild::DisableRepaint = true or false.
TFORMshmoochild::InteractiveMode = true or false.
TFORMshmoochild::SetDelay = <double value>.
The SetDelay command allows the engineer to program in a delay value that gets used after the xfunc is
called, and after the yfunc is called.
myshmoo->DataToCSV(filename);
DataToCSV(filename) will dump the data to a csv file. The filename should contain the path and filename.
There is a corresponding button on the GUI when in InteractiveMode.
Finally, the raw data can be accessed as an array.

ShmooData[x][y] will return a TShmooData*
struct TShmooData
9-110
Digital Instruments
{
double xvalue;
double yvalue;
bool ispass;
};
If you specify an [x][y] pair out of range, the return value is NULL.
Margin Shmoos
Margin shmoos are identical to the standard 2 dimensional shmoo described above, but only vary one axis
(x) instead of two. The commands and usage are identical also, with the following exceptions.
The class type for a Margin Shmoo is:

TFormshmoomargin;
To create a Margin Shmoo, call the Shmoo Manager's NewMarginShmoo routine:

TFormshmoomargin * myshmoo;
myshmoo=ShmooMan->NewMarginShmoo(<AnsiString tabsheet_caption>);
There is only an x axis in the shmoo, so any references to the y axis setups will cause a compile error. The
SetXAxis commands are identical.
There is no xfast mode, since the plot is always xfast.
9-111
DIGMOD RTI Support

The DIGMOD resource tab has seven sub-tabs: CONFIG, LEVELS, TIMING, PMU, FREQ, SEQUENCER,
and SHOW CHANS.
The SHOW CHANS screen is a simple way to declutter your display, and ensure that only the channels of
interest are displayed. Uncheck the channels you wish to suppress.
System-defined channel names are displayed if they have not been renamed with the setname command,
and if you have defined multisite groups with the DDCHCreate command, the group names appear at the
end of the SHOW CHANS list.
Figure 9.51: SHOW CHANS Screen
9-112
Digital Instruments
The CONFIG screen shows the mode that each of the instruments are set to, timeset frequency
information, and the masterclock source and frequency.
In this case each board is set to "INDEPENDENT" mode of operation, with the on board PLL as the
source. Also displayed is the MCLK frequency setting (in this case the PLL frequency). The divider for
each timeset is also displayed and the right hand scroll bar allows the user to scroll through all 16 timesets
per board if required.
Note that the configuration mode and MClk Source cannot be changed from this display - they are just
reporting the state of the instruments as set by test program code.
The (KA) indicator next to a timeset shows that this timeset has been selected to be active in Keep Alive
time (which is whenever a pattern is not bursting).
Figure 9.52: CONFIG Screen
9-113
The LEVELS screen is an overview of all the pin driver and comparator setpoints. There is a column to
indicate if a pin is ACTive (meaning its SITE is still enabled - this parameter is a display-only, and not a
clickable control on this page), programmed levels for Drive Hi, Drive Lo, and the Termination voltage, an
indicator for TENA (Termination Enabled), comparator Low and High levels, and click boxes for relay
connections from a pin to the father card (CON), the Analog tie-line bus (ABUS), whether the driver is
ENAbled, if you have set a pin into ForceMODe, what the Forced VALue is, whether it's been Force
ENAbled (not the same as driver enabled), a SNAPshot of whether the driver is sending a high or a low to
the outside world, and finally, an indicator if the pin has been Fail Disabled.
Figure 9.53: LEVELS Screen

• In the left most column is a space for a "+" symbol. If present, this indicates that the "PIN" is actually a
group of pins. Clicking the + symbol will expand the group into all of the included pins (DMCH).
• The next field represents the pin or group name. For setting individual pin names, the 'setname'
function is used. For setting a group name, the 'DMCHCreate' function is used.
• A defined pin group can be modified in real time, all channels in the group at once, by modifying an
attribute field such as voltage level, connection relay, timing edge, and so forth. Note that changing a
value at the pin level will operate on that pin as expected, but the RTI tool does not currently ripple this
change automatically to all instances of this pin in other possible groups of which this pin is a member.
• Individual channel numbers are displayed in the third column.
9-114
Digital Instruments
The TIMING screen displays the programmed edge placements for the driver data valid time, the driver
enable time, comparator edges, and skew values, plus the Keep Alive data. Since there are 16 time sets
now, the time set selection is a tab column at the right edge of the screen. Falling edge skew is
programmable by the test program, but has been suppressed from this RTI screen to reduce display
clutter.
Figure 9.54: TIMING Screen
9-115
The PMU (Parametric Measurement Unit) screen shows the forcing and measurement functions for each
desired pin, and allows an instant measurement to be made if you press the MEASURE button.
Figure 9.55: PMU Screen

• The first 4 columns are the same as those on the LEVELS tab.
• MODE - Indicates if the forcing mode of the PMU, V = force voltage, I = force current.
• FORCE - This is the actual force value on the DIGMOD pin.
• IRANGE - The programmed current range.
• VRANGE - The programmed voltage range, 0=-2V to 7V, 1=-1V to 10V.
• VCLMP-MIN - The low voltage clamp value.
• VCLMP-MAX - The high voltage clamp value.
• MODE - This is the measure mode setting. When a measure is made, the PMU will measure either
voltage or current.
• DOMEAS - The user can make immediate voltage or current measurements using this button.
• ENA - Indicates if the PMU is enabled. Note that the PMU can not be enabled at the same time as the
DIGMOD driver.
• RESULT - The last PMU measure result as made on an individual channel.
• ALRM - Indicates if an clamp alarm condition existed during the last measurement.
The FREQ screen supports the on-board connection from comparator HI and LO channels to the DIGMOD
TMU (Time Measurement Unit) instrument, for frequency measurements. To change the measured result
field from frequency mode to period mode, click in the RESULT box and it will toggle the display.
9-116
Digital Instruments
Note that the built-in TMU measures frequency only. The output display can change to a period mode by
calculating the inverse (1/X), but there is no feature to directly measure pulse widths, rise times or
intervals.
Figure 9.56: FREQ Screen
9-117
The SEQUENCER screen displays patterns available in the test program (whether or not they've been
loaded at run time into memory), available symbols, a STATUS readback display and control pull-down
menu, and buttons to control pattern bursting, halt, and User Flags (dflags1 and 2).
Figure 9.57: SEQUENCER Screen

• PAT DIR - Indicates the directory that contains the patterns for a given test program.
• SEQUENCER SELECT - Indicates which SEQUENCER is currently active. Default sequencers are
SEQ0, SEQ1, SEQ2, SEQ3, SEQ4, SEQ5.
• PATTERNS LOADED - A listing of all patterns that could loaded for the test program. (It does not
reflect whether or not they have actually been loaded at run time, so be cautious when using this
feature)
• SYMBOLS - This is a listing of all 'SYMBOLS' that exist in the currently highlighted pattern selection.
The user can highlight a SYMBOL and then 'EXECUTE' a pattern from that symbol location.
• ADDR - Shows the starting location of the highlighted pattern in physical memory.
• LEN - Shows the actual length of the highlighted pattern.
• OFFSET - Shows the offset of the highlighted SYMBOL, relative to the start of the pattern.
• Execute - When selected, this will start the highlighted PATTERN from the highlighted SYMBOL.
• Stop - Stops pattern execution if a pattern is currently running.
• Dflags Select - 0 sets neither flag, 1 sets Dflag1, 2 sets Dflag2, and 3 sets both. The DLFAGS button
must be pressed to send any changes to the test system.
• PATTERN STATUS - Shows the pattern failure information for the previously executed pattern. If all
fields are blank, this indicates that the previous pattern run was successful, with no failures. If a pattern
9-118
Digital Instruments
failed, the first 0-512 failures will be displayed in the table. The failures are separated by DIGMOD
boards, DM0-DM5. The following are displayed for each failure in the fail table: Physical failing
address, Failing cycle, Failing pins.
• The rightmost section of SEQUENCER RTI shows the current DIGMOD status by board. This
information is for the previous pattern execution and includes the following: PATTERN STATUS,
CYCLE COUNT, The value of the 'NOTE' register, Fail Count. The rightmost scroll bar will allow for
scrolling through all present DIGMOD boards.
Time Measurement Unit
Figure 9.58: TMU Pictorial
The KVD test system is capable of making interval and frequency measurements using the TMU.
Measurements of pulse width, frequency, and timing between two signals are all possible with the TMU.
There are two high speed analog input channels as well as direct connections to any digital channel
through the KVD DSPIO module. Any combination (analog or digital) of start/stop triggering is possible.
Theory of Operation
The TMU module is designed to make accurate time measurements with 1nS resolution. The heart of the
TMU is a 1GHz clock. The clock is gated to a prescalar (divide by 64) and FPGA (Xilinx) by the incoming
start/stop signals. The FPGA will flush the measurement prescalar and count the number of gated clocks,
returning the appropriate count. For measurements that are greater than 250mS, a 40MHz (25nS
resolution) clock is substituted for the 1GHz clock. The TMU has the capability to measure either time
interval or frequency. The start/stop signals can come from either the digital subsystem (DSPIO via a
motherboard TMU bus) or directly from the Fathercard.
9-119
Figure 9.59: TMU Block Diagram
9-120
Digital Instruments
Pinouts
Connections between the TMU module and the Father Card are made through a 33 pin Hypertronics
connector. Below is a listing and description of the connections.
Figure 9.60: TMU I/O Pinout
TMU Object
There is typically only one TMU in a system, although two are possible. Of type TTMU, the object name is
TMU0. Since it is a single resource, there are no group or site objects, so if you have a multisite program,
you will be scanning the TMU among the signals to be measured serially (using a relay tree on the father
card, an RMX instrument or digital channel connections), and storing results in the multisite results array.
SITE->lastresult[n].value
TMU Commands
To make a TMU measurement, you must choose your inputs first, either the Analog connections from the
Father Card, or the backplane motherboard connections to the TMU bus, which can connect to the
comparators of any Digital channel. If you choose the analog inputs, you must also program a comparator
threshold. (The Digital backplane connection uses the comparators on the DSPIO instruments, which are
independently programmed).
The input function requires you to specify what will be the start event, then the stop event. Either event can
be a rising edge or a falling edge, from either of the inputs, Channel A or B. (or from the DD Channels).
9-121
Example:
TMU0->level(CHANA, 1.0, 1.0);
TMU0->input(CHANA, RISING, CHANA, FALLING);
If you wish to use a digital channel connection, you must program which digital channel will be connected
to the motherboard backplane buses, DDTMUA and DDTMUB, and then select one or both of those
busses as the source of the start and stop events.
Example:
TMU0->ddchan(DDCH4, DDCH11);
TMU0->input(DDTMUA, RISING, DDTMUB, FALLING);
To set yourself up for making a measure, you need to choose either frequency or interval mode.
Measuring frequency involves programming the minimum frequency you are interested in measuring, so
the TMU will use the correct clock. (40MHz or 1GHz), giving it a timeout selection, so the TMU will not
hang forever waiting for the signal to change state, and programming the number of cycles of the signal to
measure, and the number of measurements to average. The number of cycles can be between 64 and 4
Meg, and the number of measures to average can be between 1 and 32. Note: since you can include many
cycles in the measurement window with the third argument, it's not usually useful to perform any averaging
in the fourth argument.
Example:
TMU0->freq(18e3, 250e-3, 100, 1);
An interval measurement involves programming the maximum expected interval time, the timeout, and
number of events to average (between 1-32).
Example:
TMU0->interval(450e-9, 10e-3, 10);
Note that in interval mode between two different signal inputs, or between rising and falling edge of the
same signal, there may be timing calibration issues that affect the measurement accuracy. Your DUT
board circuits and father card signal paths may need to be deskewed by you if you require the utmost
accuracy. Generally speaking, frequency measurements are not affected by the same issues, since a
rising edge to rising edge measurement would not be affected by any delay applied equally to both edges.
9-122
Digital Instruments
Last, you need to enable the TMU and make the measurement. The enable can be either normal, which
means the next start event will begin the measurement, or external, which means the TMU must be armed
by an external signal. You can also enable the TMU to measure negative time, in case your stop event
may occur ahead of the start event. The measurement function will place the result in a named variable,
which is different from the behavior of the DC Source measurements. To use the measurement variable for
a KVD->Test(); you will need to place it in the SITE->lastresult.value variable yourself.
Example:
TMU0->enable(NORMAL, POSITIVE);
TMU0->meas(my_result_variable);
Here is some sample code to make a TMU measurement.

TMU0->ddchan(SSTRB, SSTRB);
TMU0->input(DDTMUA, FALLING, DDTMUA, RISING);
DIG0->patexe(SETUP,TIME_TCONV); // Burst Pattern
TMU0->interval(1e-3, 10e-03, 1);
SYS->del(1e-3);
TMU0->enable(NORMAL, POSITIVE);
SYS->del(1e-3);
TMU0->meas(time_result);
DIG0->dstop(); // Halt Pattern
SITE->lastresult.value = time_result[1].value;
if (KVD->Test())
return(FAIL);
Data Types Used by the TMU

TMUCHAN = CHANA, CHANB, DDTMUA, DDTMUB
TMUEDGE = RISING, FALLING
MEASTYPE = INTERVAL, FREQ
TRIG = NORMAL, EXTERNAL
NEGTIME = POSITIVE, NEGATIVE
TMU Commands
TMU >ddchan
Sets the TMU's CHANA and CHANB to the digital pin inputs.
unsigned ddchan(TDigPin * etmua, TDigPin * etmub);
Parameters:
TDigPin * etmua
The Digital channel to be connected to CHANA.

TDigPin * etmub
The Digital channel to be connected to CHANB.
TMU >enable
Enables/resets the TMU trigger before the next measurement.
unsigned enable(TRIG trigg, NEGTIME ntime);
Parameters:
TRIG trigg
Valid values are NORMAL or EXTERNAL.
9-123
NEGTIME ntime
Valid values are POSITIVE or NEGATIVE.
TMU >freq
unsigned freq(double minfreq, double timeo, unsigned cycles, unsigned events);
Description:
Forces the next TMU measurement to be a frequency type measurement.
TMU >input
Sets up the TMU so that the proper edges (RISING and FALLING) for each channel will be recognized.
unsigned input(TMUCHAN strtch, TMUEDGE strtedge, TMUCHAN stopch, TMUEDGE stopedge);
Parameters:
TMUCHAN strtch
Start channel, can be CHANA or CHANB - this is a TMU channel, not a Digital Pin Channel.
TMUEDGE strtedge
Start channel edge, can be RISING or FALLING only.

TMUCHAN stopch
Start channel, can be CHANA or CHANB - this is a TMU channel, not a Digital Pin Channel.
TMUEDGE stopedge
Start channel edge, can be RISING or FALLING only.
Returns:
0 for no error, -6 for catastrophic error
TMU >interval
Sets up the number of samples, the sample rate, and the timeout value for the next measurement.
unsigned interval(double maxtime, double timeo, unsigned events);
Parameters:
double maxtime
If > 260ms, sample rate is 25ns, otherwise sample rate is 1ns.

double timeo
Timeout value - must be > = 1 mS

unsigned events
Number of samples to measure - must be >= 1 and <= 32
Description:
Forces the next TMU measurement to be an interval type measurement between two edges.
9-124
Digital Instruments
TMU >level
unsigned level(TMUCHAN chan, double hidac, double lodac);
Parameters:
TMUCHAN chan
Can only be CHANA or CHANB. These are TMU channels, not the Digital Pin Channels.
double hidac
Maximum of 5.0, minimum of -2.5

double lodac
Maximum of 5.0, minimum of -2.5
TMU >meas
Performs the measurement (interval or frequency) and stores the result in the RESULT parameter
unsigned meas(RESULT result[]);
TMU >meas_array
unsigned meas_array(RESULT result[], RESULT resarray[][EVENTS]);
TMU >meas_neg
unsigned meas_neg(RESULT result[], double tmax);
TMU >reset
Resets the TMU to default values, channels, levels, and timing.
unsigned reset(void);
9-125
9-126
DSP Testing on KVD M2 Test System
This section will discuss the setup that is required for the PWS and PWD DSP instruments. These
instruments allow for the generation and measurement of arbitrary analog waveforms, although we will
primarily discuss techniques for sine wave generation and analysis. Actual KVD test system syntax is
discussed later.
Clocking
It is necessary to provide a coherent clock setup for these instruments. There are several possible clock
options that will satisfy the need for coherency: the PWS can provide the 'masterclock' for both
instruments, the PWD can provide the 'masterclock' for both instruments, or the digital subsystem (DSPIO)
can provide the 'masterclock' for both instruments. Since most DSP testing is mixed-signal in nature, the
most logical choice will be to use the DSPIO as the master clock for all instrumentation. For this discussion
the assumption is made that the DSPIO will provide an external clock for both PWS and PWD. This
document will not discuss the use of internal PWS and PWD clock generators.
Example
An example can best often illustrate instrument operation. The following example will show basic setup
and operation of the PWS and PWD. For this example the PWS will be setup to source a 1KHz sine wave.
Ideal Conditions
Standard Audio test setup
Test Frequency = Ft = 1KHz
Sample Frequency = Fs = 40KHz
PWD Clock Setup

Start with setting up the PWD. The PWD has the following clock limitations:
Fswd = xclock_in / DIV / 256
decimation_clk = 256 * Fswd
Where DIV = 1, 2, 4, 8, 16, 32, 64, or 128
As always with DSP based test equipment, some assumptions are made for the ideal situation, and then
compromises are made:
For Fswd = 40KS/s, then decimation_clk = 40KS/s*256 = 10.240 MHz
This satisfies the max decimation_clk of 12.288MHz. Since the DSP Processor will run well at about
40Mhz, then the DIV ratio will be set to 4, giving roughly 10.24Mhz * 4 = 40.96Mhz master clock.
Figure 10.1 shows the relationship between external clock (xclock_in) and the PWD clock.
10-1
Figure 10.1: Simplified PWD, Single Channel, Clock Relationships
DSPIO Clock Setup

Now it has been determined that the xclock_in will need to run at roughly 40.96MHz. Since it has been
determined that the DSPIO will be the master clock source for both the PWS and PWD, this clock should
be set accordingly. After reviewing the possible clock options for setting the DSPIO PLL, the following
clock rate is possible:
xclock_in = 40Mhz * PLL_P / PLL_Q/ 2^PLL_M
xclock_in = 40MHz * 127 / 62 / 2;
xclock_in = 40.967742MHz;
The first compromise in DSP testing has been made, the exact ideal master clock of 40.96MHz is not quite
achievable, a close value is chosen.
With this master clock, the sample rate of the PWD will change somewhat from the ideal of 40KS/s. With
an xclock_in of 40.967742Mhz, and a divide ratio (DIV) of 4, the decimation clock will be 40.967742Mhz/4
= 10.241935Mhz. With a decimation (clock division) of 256, the final PWD sample clock will be as follows:
Fswd = xclock_in/DIV/256:
Fswd = 40.967742Mhz / 4 / 256 = 40,007.56Hz
This is very close to the ideal of 40000Hz, and will allow for frequency analysis out to 20003.78Hz. This will
satisfy the typical audio device specification of 20000Hz. Of course this approach has been simplified for
this example, but is also typical of the approach required for deriving clocks for DSP based systems.
10-2
AC Instruments
PWS Clock Setup

Now that the PWD sample clock has been determined, it is necessary to setup the PWS clock. This clock
will be driven from the same reference (master clock) as the PWD, so we already know the xclock_in rate
(40.967742MHz). The clocking for the WS differs from that of the WD. The WS clock is determined by
dividing the DSP clock (xclock_in/2 in this case) by some integer value that is greater than 14. Why 14?
The PWS sample update rate is determined by a program that runs in the on-board DSP processor. The
program takes 14 clock cycles to complete, and the users can add a number of dummy clocks
(DACLOOP) to the program so the sample rate can be adjusted accordingly. For the remainder of this
discussion the value of 14 will be the value of DACLOOPBASE.
Figure 10.2 shows a simplified relationship between the PWS sample clock and the master clock, in this
case xclock_in.
Figure 10.2: Simplified PWS, Single Channel, Clock Relationships
The sample rate of the PWS is determined by the xclock_in rate and the DSP "DAC" program as follows:
Fswd = xclock_in / 2 / (DACLOOP + DACLOOPBASE);
Since we will likely source with the WS at the same rate that we sampled with the WD, the assumption is
made as follows:
Fsws = Fswd = 40,007.56Hz, and since xclock_in is known to be 40.967742MHz, then the following is true:
Fsws = xclock_in / 2 / (DACLOOP + DACLOOPBASE);
DACLOOP + DACLOOPBASE = 512;
If DACLOOPBASE = 14, then DACLOOP = 498;
10-3
This seems overly complicated, the logical question is: Why run a DSP program just to source a
waveform? Why not just divide the xclock_in and get the desired sample rate? This is a valid question and
will lead to the next topic - Direct Digital Synthesis. The DSP program is in fact very powerful and allows
the user to store a single nominal waveform (single cycle, full scale amplitude, for example) and use the
DSP program to manipulate frequency and final amplitude.
The Test Frequency

The concept of waveform synthesis is relatively simple. A digital representation of a sine wave is stored in
waveform memory, and the memory is stepped through and sent to a D/A converter which is filtered and
then sent to the DUT. To continue with the example, the clock problems have been solved and we'll move
on to the signal generation. The basic relationship for Fourier analysis of sampled signals is as follows:
Ft / Fs = M / N
Where:
Ft = test frequency
Fs = sample frequency (40.007.56Hz for this example)
M = the integer number of test cycles
N = the number of samples
This is a basic relationship that will be used for the remainder of the example. This example assumes that
the reader has some DSP test experience. There are several good references that detail these principles.
To continue with the example, the next step is to choose the number of samples that will make up the
source waveform (and typically the sampled waveform as well). Since the principles of Fourier analysis
dictate that we use 2^X number of samples, a good starting point is 1024 samples. To store a single cycle
of the waveform in memory, the following equation is used:
For ( i=0; i<N; I++)
sample = sin(I*2*PI/N);
For the chosen value N=1024, a single cycle of 1024 points will be created. Now we can go back to the
equation:
Ft / Fs = M / N
If we step through the source memory point-by-point we will generate the following frequency:
Ft = Fs*M / N
Ft = 40,007.56*1/1024 = 39.06988 Hz
This is also known as the 'Fourier frequency', typically indicated as Ff . This will also be the frequency
resolution for sine wave generation as well as frequency spectrum analysis. We now have the basis for
completing the equation. Back to the example, the desired test frequency Ft is 1KHz. With the known
frequency resolution of 39.06988Hz, the next step will determine the actual test frequency:
M (number of cycles) = 1000Hz/Ff ;
M = 1000/39.06988 = 25.6 ;
10-4
AC Instruments
The principles of Fourier analysis state that M and N must be 'mutually prime', in other words M/N can not
be further reduced, or even simpler if N is always even, then M has to be odd. If for example we picked M
= 26, this would reduce as follows:
26 / 1024 = 13 / 512;
This simply states that if we were to generate 26 cycles of the 1024 point waveform, it is the same as
reducing the waveform to 512 points, and generating 13 cycles. Back to the example, the next logical
choice is M=25, this will give the following:
Ft / Fs = M / N ;
Ft = 40007.56 * 25 / 1024 ;
Ft = 976.747Hz ;
The next step is to determine how to generate this test frequency. Without Direct Digital Synthesis it is
certainly not difficult to generate this waveform. The equation that is used to generate the stored waveform
could be modified as follows:
For ( i=0; i<N; I++)
sample = sin(I*2*PI*M/N);
Where M is the number of cycles. This is acceptable, but does not allow for much flexibility. If we needed
several different test frequencies, we would need to store a different waveform for each individual
frequency and amplitude.
Direct Digital Synthesis

The program running in the PWS DSP processor allows for significant flexibility (frequency and amplitude
modification) by just storing a single sine cycle. This is known as Direct Digital Synthesis (DDS). A single
sine cycle is stored using the following:
For ( i=0; i<N; I++)
sample = sin(I*2*PI/N);
This will allow the user to single step through the waveform memory and generate a sine wave, for our
example parameters this will generate a 39.069Hz signal. The desired test frequency is 25X this number,
and we can easily generate the correct Ff with DDS. The DSP program that is running in the PWS will
allow the user to indicate the memory address 'step rate'. In other words, instead of stepping through
memory point-by-point, we can skip points at a predetermined rate. For example we know that if we step
point-by-point we will generate a 39.069Hz signal. What happens if we skip every other memory location?
We will actually generate 2*39.096Hz = 78.139Hz! So if we go back to the original Fourier equation:
Ft / Fs = M / N ;
M=2
To generate our desired Ft = 976.747Hz, we simply have to cycle through the memory to every 25th
location, and we will generate our desired Ft.
The DSP program that runs in the PWS processor will also allow for us to modify the signal amplitude.
10-5
Conclusion
The intent of this document is to show some of the clocking and signal generation techniques used for
DSP test on the KVD test system. The user should understand these techniques prior to test program
generation.
Waveform Source
There are two current versions of the Waveform Source, the original WS and the PWS (Precision
Waveform Source - originally described as the WS2000).
Figure 10.3: Waveform Source Pictorial
The KVD Test System is capable of generating arbitrary waveforms using the Waveform Source. This
source is a DSP based instrument comprised of three channels, 2 low frequency and 1 high frequency.
The low frequency ports are fully differential with adjustable offset and choice of 5KHz or 50KHz low pass
filtering. The high speed output is single ended and can be updated at speeds up to 30MS/S. The
waveform memory is 128K X 32 bits.
Control
The WS is controlled by the TI TMS320C32 DSP processor. The rate at which the processor runs
determines the update rate of the source. There are several clocking options for the WS. This clock can
originate internally or come from another system module including the system 12.5MHz clock, DSPIO
module, or WD module. The DSP processor allows for an important capability of the Waveform Source
called Direct Digital Synthesis (DDS). A single sine wave (or square wave) is stored in waveform memory.
This one waveform memory block can be used to source waveforms of varying frequency and amplitude
(including calibration factors) without modifying the waveform memory. This is a powerful feature that
minimizes waveform memory use and simplifies many housekeeping functions that are required of devices
that require many sine wave tests of varying amplitude and frequency.
10-6
AC Instruments
Figure 10.4: WS Block Diagram
WS Connections
In order to use the Waveform Source, the proper connections must be made. Below is a list of typical
connections.
Connection Description
WG1P WS Channel 1 Non-Inverted Low Speed DAC output
WG1N WS Channel 1 Inverted Low Speed DAC output
WG2P WS Channel 2 Non-Inverted Low Speed DAC output
WG2N WS Channel 2 Inverted Low Speed DAC output
HFOUT WS High Speed DAC output
CALVM Internal connection to Calibration Meter (for cal)
ICHI Internal interconnect to motherboard (for con to WD)
WG1P1 Connection on Fathercard
WG1N1 Connection on Fathercard
10-7
Pinouts
Connections between the WS module and the Father Card are made through a 33 pin Hypertronics
Figure 10.5: WS I/O Pinout
10-8
AC Instruments
Waveform Source Commands

WS->start (<waveform>,<frequency>,<amplitude>);
Start waveform generation.
Objects: WS0 or WS1
Effect: Starts a ws waveform. The frequency and amplitude are determined by sample
clock frequency and calibration factors. If frequency is greater than 0, the
function will modify the rate at which the WS waveform RAM is indexed,
otherwise the RAM index will be 1 (necessary for multitone waveforms). The
amplitude will be scaled according to user derived calibration factors.
Prototype: unsigned start(DSPTEST x, double testfreq, double testamp);
WS->clock (<source>,<destination>);
Setup the sample clock for the WS.
Objects: WS0 or WS1
Value range: OSCCLK, DISCLK, PLLMCLK0, XCLKIN, NOCLOCK, H1

TICLK, REFCK0, REFCK1, XCLKOUT
Effect: Connects the appropriate clock resources for sampling the WS waveform RAM,
running the WS DSP processor, and driving an external clock to other system
resources (WD, DSPIO) for system synchronization.
Prototype: unsigned clock(DSPCLOCK src, DSPCLOCK dest);
Note: To operate, the WS instrument must have a clock source connected to TICLK.
The input to WS pll is designated REFCK0
the output from WS pll is designated PLLMCLK0.
WS->init ( )
Initialize the WS.
Objects: WS0 or WS1
Effect: Allocates the necessary memory for the WS_context structure. This routine
should only be called once during initialization. It is called by the system
command UserClass >SystemInit().
Prototype: unsigned init(void);
10-9
WS->reset ( )
Reset the WS.
Objects: WS0 or WS1
Effect: Resets the WS to a known default state - zero offset, no filtering, default clock
settings (Note DSPCLOCKSETUP structures section). Necessary for proper
booting of the WS. Need not be called when testing devices, only during
initialization (UserClass >SystemInit, UserClass >LotInit),
Prototype: unsigned reset(void);
Note: This function is called after each DUT from the system function reset_hardware.
WS->pllbits ( <numerator>,<denominator>,<divisor>)
Set up the WS PLL.
Objects: WS0 or WS1
Effect: Sets the WS pll parameters. It is necessary to setup the WS PLL circuit if the
WS will be used as the master clock source for the test system. The PLL clock
frequency is derived as follows: clock_freq*2*numerator/demominator/
pow(2,divisor).
Prototype: unsigned pllbits(unsigned p, unsigned q, unsigned m);
Note: clock_freq*2*p/q must be in the range of 50Mhz to 120Mhz

call only if the WS is the system master clock
the input to WS pll is designated REFCK0
the output from WS pll is designated PLLMCLK0.
WS -> xclkinfreq (<frequency>);

Set the WS input clock frequency.
Objects: WS0 or WS1
Effect: If a module other than the WS is the WS clock resource, a call to this function
will set the clock frequency for the WS external clock input. This function does
not set WS hardware.
Prototype: unsigned xclkinfreq(freq[]);
Note: call only if the WS is being clocked externally

the elements of <frequency> array correspond to the sides of the test head
which may contain a WS instrument.
10-10
AC Instruments
WS->xclkoutfreq (<frequency>);
Return value of WS output clock frequency.
Objects: WS0 or WS1
Effect: If the WS is used to clock other system resources (DSPIO, WD) this routine
should be called after a call to pllbits. This returns the output frequency of the
WS external clock in the array <frequency>.
Prototype: unsigned xclkoutfreq(double freq[]);
Note: call if the WS is used to clock other modules

call after pllbits.
WS->offset ( <ws>,<offset>)
Set the WS output offset voltage.
Objects: WS0 or WS1
Value range: LFWSP0 , LFWSN0, LFWSP1, LFWSN1
Effect: Typically the waveform that is generated by the WS does not have a built in DC
offset. If an offset is required, this function will set the appropriate value in the
source output DAC. No waveform RAM modification is required.
Prototype: unsigned offset(WSCHANNEL ws, double offset);
Note: the user is required to calibrate the WS offset DAC in UserClass >SystemInit or
UserClass >LotInit
WS->filter (<source>, <filter>)

Set the WS output filter.
Objects: WS0 or WS1
Value range: LFWS0, LFWS1

WS5KHZ, WS50KHZ, WSNOFIL
Effect: Sets the post DAC low-pass filter for the WS channel. The HFWS does not
have a filter option.
Prototype: unsigned filter(WSTYPE ws, WSFILTER fil);
Note: No filtering in the high frequency source. It is strongly recommended that if

filtering is required, the WS is amplitude calibrated with the same filter setting.
10-11
WS->atten (<source>,<attenuation>)
Set the WS output attenuation
Objects: WS0 or WS1
Value range: (LFWS0, LFWS1) (greater than or equal to 0)
Effect: Sets the post DAC signal attenuation. The attenuation settings are 0dB, 20dB,
40dB, and 60dB. There is no attenuation on the high frequency source. The
setting applied is the greatest value which is less than or equal to
<attenuation>.
Prototype: unsigned atten(WSTYPE ws, double atten);
Note: No filtering in the high frequency source. Although it is possible to use nominal
attenuation settings, it is strongly recommended that the WS attenuators be
calibrated at some time during UserClass >LotInit.
WS->store_sine20bit (<address>, <length>,<amplitude>,<offset>);

Store a source waveform.
Objects: WS0 or WS1
Effect: Computes and stores a sine wave in the WS RAM. Note that the amplitude and
offset can be digitally stored as part of the waveform. This is for LF sine wave
generation only. This routine is intended for backwards compatibility only. New
test programs should use the function store_wave20bit, which can store more
complex multi-tone waveforms.
Prototype: short store_sine20bit(unsigned long start_adr, unsigned len, double amp,

double off);
Note: for backwards compatibility only, new programs should use the function
store_wave20bit.
WS->store_wave20bit (<wave structure>);

Objects: WS0 or WS1
Effect: Computes and stores a single tone or multi-tone sine wave to be generated by
a LFWS channel. The waveform structure must be "initialized" and loaded at
some time during UserClass >SystemInit. This function is capable of computing
and storing multi-tone waveforms.
Prototype: short store_wave20bit(DSPTEST x);
Note: waveform structures must be initialized at some time during UserClass

>SystemInit.
waveform structure elements tones, bins[], and amps[] described in the
DSPTEST Structure section of this manual.
10-12
AC Instruments
WS->store_sine16bit_hs (<address>,<length>,<amp>,<offset>)
Store a hs source waveform.
Objects: WS0 or WS1
Effect: Computes and stores a sine wave in the WS RAM. Note that the amplitude and
offset can be digitally stored as part of the waveform. This is for HF sine wave
generation only.
Prototype: short store_sine16bit_hs(unsigned long start_adr, unsigned len, double amp,

double off);
Note: for generating and storing of high frequency sine waves.
WS->store_ramp20bit (<address>,<length>,<amplitude>,<offset>)
Objects: WS0 or WS1
Effect: Computes and stores a ramp wave in the WS RAM. Note that the amplitude
and offset can be digitally stored as part of the waveform.
Prototype: short store_ramp20bit(unsigned long start_adr, unsigned len, double amp,

double off);
Precision WS
Figure 10.6: Precision Waveform Source Pictorial
The PWS (Precision Waveform Synthesizer) is an improved version of the KVD Arbitrary Waveform
Synthesizer, with updated converters and programmable filters.
The PWS offers two low frequency output channels, each using a 24-bit DAC as the basic building block,
and a high frequency channel offering 16 bit resolution. Waveform memory is 256K 32-bit words, and 256K
of 8-bit NVRAM to store code for the on-board TI DSP processor.
10-13
Programmable output filtering for the low frequency channels is provided by a daughter board. Low
frequency output voltage limits are +/- 5V, but application circuits can significantly extend that range if
necessary, with a maximum sample clock frequency of 768KHz. The High frequency output channel offers
+/- 2V, with a maximum sample clock of 30MHz.
Clocking can be internal, or synchronized with other instruments such as the DSPIO Digital Subsystem, or
any of the available Waveform Digitizers.
Below is a list of the basic features:
Number of Output 2
Channels
Resolution 24 bits
Voltage Range +/- 5V
Maximum Sample 768Khz

Rate
Memory Depth 256K
Low Pass Filter Programmable

1K25,2K5,5K
12K5,25K
or 50K 8-pole
Output Single Ended
Signal to Noise > 100db
10-14
AC Instruments
Figure 10.7: WS2000 Precision Waveform Synthesizer Block Diagram
PWS Commands
Connection
void con(PWSCHAN chan);
void con_to_switch_bus(PWSCHAN chan);
void con_to_cal_bus(PWSCHAN chan);
void con_to_l1(PWSCHAN chan);
void con_to_ic(PWSCHAN chan);
void con_to_agnd(PWSCHAN chan);
void discon(PWSCHAN chan = NONE);
void discon_from_agnd(void);
void discon_from_cal_bus(void);
void discon_from_l1(void);
void discon_from_ic(void);
Clocking
unsigned dds_setup(DSPCLOCK ddsnum, double freqval);
unsigned dds_reset(void);
void clock_reset(unsigned resetval);
double xclkoutfreq(void);
void xclkinfreq(double freq);
unsigned clock(DSPCLOCK source,DSPCLOCK dest);
Filter/Level(DC)
unsigned offset(PWSCHAN ws, double offset);
unsigned filter(PWSCHAN channel,double filval);
unsigned atten(PWSCHAN ws,double atten);
unsigned setv(PWSCHAN ws, double val);
10-15
General
short reset(void);
unsigned init(void);
PWS Connection Syntax

PWSx = PWS0, PWS1, PWS2, or PWS3 ***
*** This references a BOARD, not a CHANNEL!
PWSx -> con

Connect a channel on a PWS Board
void con(PWSCHAN chan);
Parameters:
PWSCHAN chan // connect a channel (usually PWSCHAN1) to the outside world.
PWSx -> con_to_switch_bus

void con_to_switch_bus (PWSCHAN chan);
Parameters:
PWSCHAN chan // connect a channel (usually PWSCHAN1) to the switch bus (whatever that is).
PWSx -> con_to_cal_bus

void con_to_cal_bus (PWSCHAN chan);
Parameters:
PWSCHAN chan // connect a channel to the cal bus (Keithley meter).
PWSx -> con_to_l1

Connect a channel on a PWS Board to Motherboard Line 1
void con_to_l1 (PWSCHAN chan);
Parameters:
PWSCHAN chan // connect a channel to the DC bus, allowing DC measurement with MPDS[0].
PWSx -> con_to_ic

void con_to_ic (PWSCHAN chan);
Parameters:
PWSCHAN chan // connect a channel to the interconnect bus, internal connections
of different instruments
10-16
AC Instruments
PWSx -> con_to_agnd

void con_to_agnd (PWSCHAN chan);
Parameters:
PWSCHAN chan // connect a channel to analog ground
PWSx -> discon

Disconnect a channel on a PWS Board
void discon(PWSCHAN chan);
Parameters:
PWSCHAN chan // disconnect a channel from the outside world.
PWSx -> discon_from_switch_bus

Disconnect all channels on a PWS Board
void discon_from_switch_bus (void);
Parameters:
None - disconnects all channels on a given board
PWSx -> discon_from_cal_bus

void discon_from_cal_bus (void);
Parameters:
PWSx -> discon_from_l1

void discon_from_l1 (void);
Parameters:
PWSx -> discon_from_ic

void discon_from_ic (void);
Parameters:
10-17
PWSx -> discon_from_agnd

void discon_from_agnd (void);
Parameters:
PWS Clocking Syntax

PWSx -> dds_setup

Set a frequency on one of the on board *DDS clocks
unsigned dds_setup(DSPCLOCK ddsnum, double freqval);
Parameters:
DSPCLOCK ddsnum // DDS1CLK or DDS2CLK
double freqval // sets the clock frequency (up to 45MHz)
Note: This is an on-board clocking option. Typically the DSPIO will be used to clock the PWS board, and
it will not be necessary to set this clock.
PWSx -> dds_reset

Reset the DDS clocks on a PWS board
unsigned dds_reset(void);
Parameters:
None
Resets the board DDS1CLOCK and DDS2CLK to default values.
PWSx -> clock_reset

Reset all clocking to default on a PWS board
void clock_reset(unsigned resetvalue);
Parameters:
unsigned resetvalue // either 0 or greater
Note: Changes all programmed clock connections back to the on-board defaults if resetvalue>0. Set this
to 1 before calling PWSx->reset(); if you want to default the DC conditions but leave the clocking
intact.
10-18
AC Instruments
PWSx -> xclockoutfreq

Tells the rest of the system what freq is coming out of the external clock output on a PWS board.
double xclkoutfreq(void);
Parameters:
None
Returns the value of the external clock output on a PWS board. This is only necessary if the PWS board is
serving as the master clock for other instruments (DSPIO, PWS, PWD etc).
PWSx -> xclockinfreq

If another system instrument (PWS, PWD, DSPIO) is serving as the master clock for the PWS board, it
needs to know what frequency is coming in on its external clock input.
void xclkinfreq(double freq);
Parameters:
double freq
Note: Must do this so the DDS clocking is set up correctly by having the correct DACLOOP setting
programmed.
PWSx -> clock

Set the internal clocks on a PWS board. There are many options.
void clock(DSPCLOCK source, DSPCLOCK dest);
Parameters:
DSPCLOCK source // source = OSCLK2, DISCLK, XCLKIN, H1, DDS1CLK, DDS2CLK
DSPCLOCK dest // destination = DAC1CLK, DAC2CLK, XCLKOUT, TICLK
Example:
PWS0->clock(XCLKIN, TICLK);
PWS0->clock(H1, DAC1CLK);
This example will accomplish the following:

• Set the clock for the TI DSP processor to come form the external clock input
• Set the DAC clock for channel 1 to come from H1 clock (which is ½ of the TICLK)
Other source options:
OSCLK = on-board 40MHz xtal
DISCLK = 12.5Mhz system wide clock
DDS1CLK = on-board DDS1 clock
DDS2CLK = on-board DDS2 clock
Other dest options:
10-19
DAC2CLK = DAC clock for channel 2
XCLKOUT = output to other modules
PWS Filter/DC Syntax

PWSx -> offset

Set a DC offset on a PWS channel
unsigned offset(PWSCHAN ws, double offset);
Parameters:
PWSCHAN ws // PWSCHAN1 or PWSCHAN2
double offset // -5V to +5V
PWSx -> filter

Set a filter for a PWS channel
unsigned filter(PWSCHAN ws, double filval);
Parameters:
double filval // 0 to infinite
Note: Setting the filval to 0.0 will apply NO FILTER to the PWS output, all other settings will round up to
the next logical choice.
Example:
Filval = 0 NO FILTER
Filval = 1 to 1250 1250Hz LPF
Filval = 5000 to 12500 12.5Khz LPF
Filval = 12500 to 25000 25Khz LPF
Filval = 25000 and beyond 50Khz LPF
PWSx -> atten

Attenuate the PWS channel output
unsigned atten(PWSCHAN ws, double atten);
Parameters:
double atten // value of attenuation
Note: Currently does not operate on the PWS board.
10-20
AC Instruments
PWSx -> setv

Set a steady DC output on a PWS channel
unsigned setv(PWSCHAN ws, double val);
Parameters:
double val // DC output value
Note: Sets a PWS output channel to a steady state DC level. This will also stop any TI program that is
running in the PWS DSP processor.
PWS General Syntax

PWSx -> reset

Reset a PWS board
short reset(void);
Parameters:
None
Note: This will reset a PWS board to a known state as follows:

1. Disconnect everything
2. No filters (all channels)
3. No offset (all channels)
4. Clock with 40Mhz internal on-board xtal (unless a call has previously been made as follows:
PWSx->clock_reset(0), which would keep all current clocking intact.
PWSx -> init

Initialize a PWS board
short init(void);
Parameters:
None
Note: Don't do this.
10-21
Waveform Digitizer
Figure 10.8: Waveform Digitizer Pictorial
There are two current versions of the Waveform Digitizer, the original WD and the PWD. The WD is
described first.
The KVD Test System is capable of digitizing arbitrary waveforms using the Waveform Digitizer. The WD
is a DSP based instrument comprised of 2 analog channels, 1 low frequency and 1 high frequency. The
current WD also has a direct digital input 'channel' that can be used to send digital data to memory and the
DSP processor. The low frequency port is fully differential with adjustable offset and choice of 5KHz or
50KHz low pass filtering. The high speed input is single ended and can be sampled at speeds up 30MS/S.
The digital port is currently used for testing CMOS imager devices. The waveform memory is 1M X 32 bits
of SRAM.
Processing and Control
The WD is controlled by the on-board TI TMS320C32 DSP processor. The rate at which the processor
runs determines the speed of calculation. There are several clocking options for the WD. This clock can
originate internally or come from another system module including the system 12.5MHz clock, DSPIO
module, or WS module. These clocks will be discussed in detail in a later section.
10-22
AC Instruments
Figure 10.9: WD Block Diagram
WD Connections
In order to use the Waveform Digitizer, the proper connections must be made.
LSADCP Low Speed ADC Non-Inverting Input
LSADCN Low Speed ADC Inverting Input
HSADC High Speed ADC Input
AGND Analog Ground - (Ground LSADCN to run single ended)
ICHI Connection to Motherboard (to connect to WS)
WD1P1 Fathercard Connection
WD1N1 Fathercard connection
10-23
Pinouts
Connections between the WD module and the Father Card are made through a 33 pin Hypertronics
Figure 10.10: Waveform Digitizer Hypertronics Pinout
Waveform Digitizer Commands

WD->start (< source >,<waveform>);
Start waveform capture.
Object: WD0, WD1
Value range: LFWD0, LFWD1, HFWD
Effect: Starts the waveform digitizer. The sample clock must be running.
Prototype: short start(RESOURCE ws, DSPTEST x);
WD->clock (<source>,<destination>);
Set up the sample clock for the WD.
Object: WD0, WD1
Value range: OSCCLK, DISCLK, PLLMCLK0, XCLKIN, H1, NOCLOCK

TICLK, REFCK0, REFCK1, XCLKOUT, LFCLK0, LFCLK1, HFCLOCK,
CALCLOCK
Effect: Connects the appropriate clock resources for sampling the WD input signal,
running the WD DSP processor, and driving an external clock to other system
resources (WS, DSPIO) for system synchronization.
10-24
AC Instruments
Prototype: unsigned clock(DSPCLOCK src, DSPCLOCK dest);
Note: To operate, the WD instrument must have a clock source connected to TICLK
and a clock source connected to LFCLK0.
The input to WD pll is designated REFCK0
the output from WD pll is designated PLLMCLK0.
WD->init
Initialize the WD.
Object: WD0, WD1
Effect: Allocates the necessary memory for the WD_context structure. This routine is
called during system boot and need not be called by the user. It is called by the
system command UserClass >SystemInit()
Prototype: unsigned init(void);
WD->reset
Reset the WD.
Object: WD0, WD1
Effect: Resets the WD to a known default state - zero offset, no filtering, default clock
settings. This function is called by the operating system prior to testing each
device. It need not be called by the user.
Prototype: unsigned reset(void);
Note: This function is called after each DUT from the system function reset_hardware.
WD -> pllbits (<numerator>,<denominator>,<divisor>)

Set up the WD PLL.
Object: WD0, WD1
Effect: Sets the WD pll parameters. It is necessary to set up the WD PLL circuit if the
WD will be used as the master clock source for the KVD test system. The PLL
clock frequency is derived as follows: clock_freq*2*numerator/demominator/
pow(2,divisor).
Prototype: unsigned pllbits(unsigned p, unsigned q, unsigned m);
Note: clock_freq*2*p/q must be in the range of 50MHz to 120MHz

call only if the WD is the system master clock
the input to WD pll is designated REFCK0
the output from WD pll is designated PLLMCLK0.
10-25
WD->xclkinfreq (<frequency>)
Set the WD input clock frequency.
Object: WD0, WD1
Effect: If a module other than the WD is the WD master clock resource, a call to this
function will set the clock frequency for the WD external clock input. This
function does not set WD hardware.
Prototype: unsigned xclkinfreq(double freq[]);
Note: call only if the WD is being clocked externally

WD->xclkoutfreq (<frequency>)
Return value of WD output clock frequency.
Object: WD0, WD1
Effect: If the WD is used to clock other system resources (DSPIO, WD) this routine
should be called after a call to pllbits. This returns the output frequency of the
WD external clock in the array <frequency>.
Prototype: unsigned xclkoutfreq(double freq[]);
Note: call if the WD is used to clock other modules

call after pllbits.
which may contain a WD instrument.
WD->offset (<source>,<offset>);
Set the WD input offset voltage.
Object: WD0, WD1
Value range: LFWD0, LFWD1, HFWD
Effect: This function will set the appropriate input offset DAC on the WD. A call to this
function may be required if the signal to be digitized is a low-level signal with a
DC component. The signal may need amplification for accurate measurement,
but first the DC component must be removed.
Prototype: unsigned offset(WDTYPE wd, double offset);
Note: the user is required to calibrate the wd offset DAC in UserClass >SystemInit()
10-26
AC Instruments
WD->filter (<source>,<filter>);
Set the WD input filter.
Object: WD0, WD1
Value range: (LFWD0, LFWD1) (WD5KHZ, WD50KHZ, WDNOFIL)
Effect: Sets the pre ADC filter for the appropriate WD channel. There is no filtering or
conditioning of any type in the HFWD path.
Prototype: unsigned filter(WDTYPE wd, WDFILTER fil);
Note: No filtering in the high frequency path. It is strongly recommended that if filtering
is required, the WD is amplitude calibrated with the same filter setting.
WD->gain (<source>,<gain1>,<gain2>)
Set the WD input gain.
Object: WD0, WD1
Value range: LFWD0, LFWD1
Effect: Sets the input gain stages for the WD channel. There are 2 gain stages that are
cascaded together. The final gain setting will be in the range of 1 to 64. Note
there is no gain conditioning for the HFWD input.
Prototype: unsigned gain(RESOURCE ws, double gain1, double gain2);
Note: No gain setting in the high frequency path.
WD->lfadc (<adcclock>,<sample rate>)

Set the WD low frequency clock and sample rates.
Object: WD0, WD1
Value range: (less than 2.5MHz) (less than clock rate / 16)
Effect: Sets clock and sample rate for the low frequency WD paths. The clock rate
must not exceed 2.5MHz and the sample rate must be no greater than the clock
rate / 16. The actual setting will be determined by the input clock frequency.
Prototype: unsigned lfadc(double adcclock, double srate);
Note: Actual settings are determined by the input clock frequency.

Actual adcclock setting determined by dividing the input clock frequency with an
integer value.
Actual sample rate setting determined by dividing the adcclock setting with an
integer value.
10-27
WD->hfadc (<sample rate>);

Set the WD high frequency sample rate.
Object: WD0, WD1
Effect: Sets the sample rate for the high frequency WD path.
Prototype: unsigned lfadc(double srate);
Note: Actual setting is determined by dividing the input clock frequency with an
integer value.
Precision WD
Figure 10.11: Precision Waveform Digitizer Pictorial
The PWD (Precision Waveform Digitizer) is an improved version of the KVD Waveform Digitizer, with
updated converters and programmable filters.
The PWS offers four low frequency input channels, each using a 20-bit DAC as the basic building block.
Waveform memory is 256K 32-bit words, and 256K of 8-bit NVRAM to store code for the on-board TI DSP
processor. Built-in DSP routines include FFT,SNR,THD,THD+N.
Programmable low-pass filtering for the input channels is provided by two daughter boards, along with
various gain stages. Basic input voltage limits are +/- 2.5V, but application circuits can significantly extend
that range if necessary. Maximum sampling frequency is 48KHz.
Clocking can be internal, or synchronized with other instruments such as the DSPIO Digital Subsystem, or
any of the available Waveform Synthesizers.
Below is a list of basic features:
Number of Input Channels 4
Resolution 20 bits
Voltage Range +/- 2.5V
Maximum Sample Rate 48Khz
Memory Depth 256K
10-28
AC Instruments
Gain Selections
Stage 1 1x or 10x
Stage 2 1x,2x,4x or 8x
Stage 3 1x or 16x
Offset Control +/- 2.5v 20 bits
Low Pass Filter Programmable

1K25,2K5,5K
12K5,25K
or 50K 8-pole
Input Differential
Signal to Noise > 100db
Data Acquisition Dedicated State
Machine per Channel
DSP Processor TMS320C32

40mhz Clock Rate
Frequency Synthesizer 4 per board

45mhz max frequency
32 bit resolution
Clock Modes Internal or External
DSP Algorithms FFT,SNR,THD,THD+N
10-29
Figure 10.12: WD2000 QUAD Audio Digitizer Block Diagram
PWD Commands
Connection
short instr_con(pLFWD_Instr instr,WD_Input wdinput);
short input_con(WD_Input wdinput);
short instr_discon(pLFWD_Instr instr,WD_Input wdinput);
short input_discon(WD_Input wdinput);
Clocking
short dds_setup(pLFWD_DDS ddsnum, double freqval);
short dds_reset();
void clock_reset(unsigned resetval);
short clock_div(pLFWD_Chan Chan,pLFWD_Div div);
short clock(pLFWD_Clksrc source, pLFWD_Clk dest);
short clockselect(pLFWD_Clk clock, pLFWD_Clksrc source);
General
short reset();
short start(pLFWD_Chan channel,short numpts);
short stop();
short wait();
DSP
short setup_fft(pLFWD_Chan Chan,unsigned numpts);
short fft_exec(pLFWD_Chan Chan,unsigned bin,unsigned points);
short fft(pLFWD_Chan Chan,unsigned points);
double thd(pLFWD_Chan Chan, unsigned fund, unsigned numpts);
double snr(pLFWD_Chan Chan, unsigned fund, unsigned numpts);
double sinad(pLFWD_Chan Chan, unsigned fund, unsigned numpts);
double thd_filter(pLFWD_Chan Chan,
10-30
AC Instruments
unsigned fund,
unsigned numpts,
double fsample,
double ffilt);
double snr_filter(pLFWD_Chan Chan,
unsigned fund,
unsigned numpts,
double fsample,
double ffilt);
double sinad_filter(pLFWD_Chan Chan,
unsigned fund,
unsigned numpts,
double fsample,
double ffilt);
Filter/Level(DC)
short offset (pLFWD_Chan chan, double value);
unsigned filter(pLFWD_Chan channel,double filval);
short gain (pLFWD_Chan chan, pLFWD_Gain value);
double read_wd2000_dc(pLFWD_Chan Chan);
PWD Connection Syntax

PWDx = PWD0, PWD1, PWD2, or PWD3 ***
PWDx -> instr_con

Connect a PWD input channel to a tester instrument
short instr_con(pLFWD_Instr instr, WD_Input wdinput);
Parameters:
pLFWD_Instr instr // WD_KEITHLEY, WD_AGND, WD_IC1A4, or WD_DUTSRC1
WD_Input wdinput // PWD_WD1P, PWD_WD1N, PWD_WD2P, PWD_WD2N
PWD_WD3P, PWD_WD3N, PWD_WD4P, PWD_WD4N
Note: Allows the user to connect various tester instruments to a PWD channel input. These resources
include GND, the Keithley meter, MPDS[0], or the interconnect bus (IC1A4).
PWDx -> input_con

Connect a PWD input channel up to the FatherCard
short input_con(WD_Input wdinput);
Parameters:
Connects the input of a WD Channel to the outside world (need to do both for a differential measure).
PWDx -> instr_discon

Disconnect a PWD input channel from a tester instrument
10-31
short instr_discon(pLFWD_Instr instr, WD_Input wdinput);
Parameters:
pLFWD_Instr instr // WD_KEITHLEY, WD_AGND, WD_IC1A4, or WD_DUTSRC1
Note: Disconnect a previously 'connected' instrument.
PWDx -> input_discon

Disconnect a PWD input channel from the FatherCard
short input_discon(WD_Input wdinput);
Parameters:
Disconnect a previously 'connected' PWD channel.
PWD Clocking Syntax

PWDx -> dds_setup

Set a frequency on one of the on board *DDS clocks
short dds_setup(pLFWD_DDS ddsnum, double freqval);
Parameters:
pLFWD_DDS ddsnum // DDS1_WD, DDS2_WD, DDS3_WD, DDS4_WD
double freqval // sets the clock frequency (up to 45MHz)
Note: This is an on-board clocking option. Typically the DSPIO will be used to clock the PWD board, and
it will not be necessary to set this clock.
PWDx -> dds_reset

Reset the DDS clocks on a PWS board
short dds_reset();
Parameters:
None
Resets the board DDS1_WD, DDS2_WD, DDS3_WD, DDS4_WD to default values.
10-32
AC Instruments
PWDx -> clock_reset

Reset all clocking to default on a PWD board
void clock_reset(unsigned resetvalue);
Parameters:
unsigned resetvalue // either 0 or greater
Note: Changes all programmed clock connections back to the on-board defaults if resetvalue>0. Set this
to 1 before calling PWDx->reset(); if you want to default the DC conditions but leave the clocking
intact.
PWDx -> clock_div

Sets the PWD channel Decimation clock divider value, to satisfy the constraints of the TI DSP processor,
as well as the ADC clock, this will typically be set to 4
short clock_div(pLFWD_Chan Chan, pLFWD_Div div);
Parameters:
pLFWD_Chan Chan// LFADC1, LFADC2, LFADC3, or LFADC4
pLFWD_Div div// DIV1, DIV2, DIV4, DIV8, DIV16, DIV32, DIV64,
or DIV128
PWDx -> clock

Set the internal clocks on a PWD board. There are many options.
short clock(pLFWD_Clksrc source, pLFWD_Clk dest);
Parameters:
pLFWD_Clksrc source // source = WD_DDS1, WD_DDS2, pLFWD_H1, pLFWD_XIN
pLFWD_Clk dest //dest = ADC1CLK, ADC2CLK, ADC3CLK, ADC4CLK
pLFWD_XOUT, pLFWD_TICLK, or pLFWD_SMCLK
Example:
PWD0->clock(pLFWD_XIN, pLFWD_TICLK);
PWD0->clock(pLFWD_XIN, pLFWD_ADC4CLK);
PWD0->clock(pLFWD_XIN, pLFWD_SMCLK);
This example will accomplish the following:
1. Run the TI DSP from external clock input.

2. Run channel 4 clock from the external clock input.
3. Run the "State Machine" clock from external clock input.
Note: There are many clocking options, allowing for configurations that may not make sense; choose
wisely (follow the example).
10-33
PWDx -> clockselect

Set the internal clocks on a PWD board. There are many options. Note this is legacy code and should not
be used for new applications, operates the same as PWDx->clock syntax, except source and dest are
switched in the parameters.
short clockselect(pLFWD_Clk dest, pLFWD_Clksrc source);
Parameters:
pLFWD_Clk dest //dest = ADC1CLK, ADC2CLK, ADC3CLK, ADC4CLK
pLFWD_XOUT, pLFWD_TICLK, or pLFWD_SMCLK
pLFWD_Clksrc source // source = WD_DDS1, WD_DDS2, pLFWD_H1, pLFWD_XIN
PWD General Syntax

PWDx -> reset

Reset a PWD board
short reset(void);
Parameters:
None
Note: This will reset a PWD board to a known state as follows:

1. Disconnect everything.
2. Set all channels clock div to DIV4.
3. Set ADC clocks on all channels to XCLKIN.
4. Set TI and SM clocks to on-board 40Mhz xtal.
5. Offset to 0.0 on all channels.
6. Disconnect all filters.
7. Disconnect all inputs.
8. Set gain to 1.0.
PWDx -> start

Start sampling the input on a PWD channel
short start(pLFWD_Chan channel,short numpts);
Parameters:
pLFWD_Chan channel// LFADC1, LFADC2, LFADC3, LFADC4, LFADC1_4
short numpts // captures a number of samples
Note: This will start the capture of a number of samples on a PWD channel (assuming the clocks are
running).
10-34
AC Instruments
PWDx -> stop

Reset a PWD board
short stop(void);
Parameters:
None
Note: This will stop the capture of all PWD channels, even if the clocks are running and the channels are
in the process of storing captured data.
PWDx -> wait

Wait for a board to finish capturing the requested number of points
short wait(void);
Parameters:
None
PWD DSP Processing Syntax

PWDx -> setup_fft

Setup a PWD channel to perform an FFT
short setup_fft(pLFWD_Chan Chan,unsigned numpts);
Parameters:
pLFWD_Chan instr // LFADC1, LFADC2, LFADC3, LFADC4
unsigned numpts // 64, 128, 256, 512, 1024, 2048, 4096
Note: This function stores important information in the PWD DSP memory, including but not limited to
the following:
1. How many points in the FFT.
2. Where will the data be stored.
3. Which DSP function will be run (FFT in this case).
This function is called by PWDx->fft and PWDx->fft_exec, and does not need to be called by the
user.
10-35
PWDx -> fft_exec

Execute an fft on a captured sample set, and execute a
PWDx->thd and PWD->snr
short fft_exec(pLFWD_Chan Chan,unsigned bin,unsigned points);
Parameters:
unsigned bin // number of cycles (M)
unsigned numpts // 64, 128, 256, 512, 1024, 2048, 4096
PWDx -> fft

Same as PWDx->fft_exec except more general, does not execute thd and snr command, these must be
executed post PWDx->fft.
short fft_exec(pLFWD_Chan Chan, unsigned points);
Parameters:
unsigned numpts // 64, 128, 256, 512, 1024, 2048, 4096
PWDx -> thd

Must execute fft_exec or fft prior to this function. This will calculate and return the total harmonic distortion
of a captured waveform.
Parameters:
unsigned fund // fundamental bin (M)
unsigned numpts // 64, 128, 256, 512, 1024, 2048, 4096
Note: Returns the thd value.
PWDx -> snr

Must execute fft_exec or fft prior to this function. This will calculate and return the signal to noise ratio of a
captured waveform, excluding harmonic content.
double snr(pLFWD_Chan Chan, unsigned fund, unsigned numpts);
Parameters:
unsigned numpts // 64, 128, 256, 512, 1024, 2048, 4096
Note: Returns the snr value.
10-36
AC Instruments
PWDx -> sinad

Must execute fft_exec or fft prior to this function. This will calculate and return the signal-to-noise ratio of a
captured waveform, INCLUDING harmonic content.
double sinad(pLFWD_Chan Chan, unsigned fund, unsigned numpts);
Parameters:
unsigned numpts // 64, 128, 256, 512, 1024, 2048, 4096
Note: Returns the THN+NOISE value.
PWDx -> thd_filter

Must execute fft_exec or fft prior to this function. This function will calculate the total harmonic distortion of
a measured signal, but will exclude certain harmonics as specified by the last parameter (ffilt) by applying
a digital filter.
double thd_filter(pLFWD_Chan Chan,
unsigned fund,
unsigned numpts,
double fsample,
double ffilt);
Parameters:
unsigned numpts // 64, 128, 256, 512, 1024, 2048, 4096
double fsample // what was the sample frequency??
double ffilt // digital filter frequency (Low Pass)
Note: Returns the thd value of the captured signal, but will filter upper harmonics if required.
Example:
If the sample rate Fs=40Khz and the test frequency was 1Khz, if the ffilt parameter was set to 5000, the
result would include only harmonics 2 (2Khz), 3 (3khz), 4 (4Khz) and 5 (5Khz).
PWDx -> snr_filter

Must execute fft_exec or fft prior to this function. This function will calculate the signal-to-noise ratio
(excluding harmonics) of a measured signal, but will only include a certain frequency band as specified by
the last parameter (ffilt) by applying a digital filter.
double snr_filter(pLFWD_Chan Chan,
unsigned fund,
unsigned numpts,
double fsample,
double ffilt);
Parameters:
unsigned numpts // 64, 128, 256, 512, 1024, 2048, 4096
10-37
Note: Returns the snr value of the captured signal, but will filter upper harmonics if required.
Example:
result would include noise from 0Hz-10Khz.
PWDx -> sinad_filter

Must execute fft_exec or fft prior to this function. This function will calculate the signal-to-noise ratio
(including harmonics) of a measured signal, but will only include a certain frequency band as specified by
the last parameter (ffilt) by applying a digital filter.
double sinad_filter(pLFWD_Chan Chan,
unsigned fund,
unsigned numpts,
double fsample,
double ffilt);
Parameters:
unsigned numpts // 64, 128, 256, 512, 1024, 2048, 4096
Note: Returns the snr value of the captured signal, but will filter upper harmonics if required.
Example:
result would include noise from 0Hz-10Khz.
PWD Filter/DC Syntax

PWDx -> offset

Set a DC offset on a PWD channel
short offset (pLFWD_Chan chan, double value);
Parameters:
pLFWD_Chan chan // LFADC1, LFADC2, LFADC3 or LFADC4
double value // -5V to +5V
10-38
AC Instruments
PWDx -> filter

Set a filter for a PWD channel
unsigned filter(pLFWD_Chan channel,double filval);
Parameters:
double filval // 0 to infinite
Note: Setting the filval to 0.0 will apply NO FILTER to the PWD input, all other settings will round up to
the next logical choice.
Example:
filval = 0 NO FILTER
filval = 1 to 1250 1250Hz LPF
filval = 5000 to 12500 12.5Khz LPF
filval = 12500 to 25000 25Khz LPF
filval = 25000 and beyond 50Khz LPF
PWDx -> gain

Apply GAIN to the PWD input channel
short gain (pLFWD_Chan chan, pLFWD_Gain value);
Parameters:
pLFWD_Gain value // WDGAIN1, WDGAIN2, WDGAIN4, WDGAIN8, WDGAIN16
PWDx -> read_wd2000_dc

Read the DC value of a number of samples, after the sample set has been collected.
double read_wd2000_dc(pLFWD_Chan Chan);
Parameters:
Note: Only returns the first sample DC value.
10-39
DSP (Digital Signal Processing)

Defining Waveforms
Waveforms can be defined and loaded at program initialization time (UserClass::SystemInit). An important
part of the software involves a structure that defines a waveform. This structure of type DSPTEST provides
much information regarding the waveform. The structure DSPTEST is currently defined in kvdwin.h as
follows:
typedef struct {
char descrip[50];
WDTYPE wdsel;
WSTYPE wssel;
WSCHANNEL wschan;
double waveamp;
double waveoff;
unsigned long wavestrt;
unsigned long wavesize;
double wavewait;
unsigned long dacloop;
unsigned long indexreg;
unsigned long digbuff;
unsigned long digsize;
unsigned long digoff;
unsigned long digstart;
double digwait;
unsigned long fltbuff;
TIPROG dacprog;
TIPROG convprog;
TIPROG fftprog;
double fftwait;
unsigned long fftout;
unsigned fund;
unsigned fundskirt;
double adcclk;
double adcsam;
unsigned rel;
DSPCLOCK refck;
unsigned pll_p;
unsigned pll_q;
unsigned pll_m;
WDFILTER wdfil;
double wsoff;
double atten;
WSFILTER wsfil;
double wdoff;
double gain1;
double gain2;
unsigned hsswitch;
unsigned tones;
double bins[10];
double amps[10];
long int dcap_adr;
long int ddrv_adr;
} DSPTEST;
TI DSP Programs
When using the PWS and PWD instruments, it is important to remember that much of the flexibility of these
instruments is derived from the on-board DSP processors. These processors run micro-code that is
necessary to source and measure various types of waveforms.
While it is not necessary for the user to understand the exact content of these programs, it is up to the user
to store these programs in "TI Memory". These programs are run as required, but it is possible that the
user could see a reference to various TI DSP functions in a test program.
Below is a list of the programs necessary for the examples contained in these pages:
10-40
AC Instruments
PWS Programs
NAME: dac25
System Location: _kvdco\TIPROGS\dac25
USE: load once at system or lot initialization
TI Mem Location: 0x900000
Function: source a stored waveform from the PWS
Special features: includes the ability to scale (amplitude) the waveform

As well as generate different frequency waveforms (Direct Digital Synthesis).
PWD Programs
NAME: pwdfft
System Location: _kvdco\TIPROGS\pwdfft
TI Mem Location: 0x900000
Function: execute an fft (Fast Fourier Transform) on a sampled waveform
Special features: adjustable number of points
NAME: wd2kconv
System Location: _kvdco\TIPROGS\wd2kconv
TI Mem Location: 0x93a000
Function: capture a sample set with the PWD
Special features: adjustable number of points
TI Memory Locations
Each TI DSP processor has access to its own internal memory as well as on-board memory. The on-board
memory is shared by the TI micro-code and the stored/captured digital representation of a waveform. For
KVD usage the memory is mapped roughly as follows:
PWS Instrument
TI Internal memory start address: 0x87ff00
Size: 512
TI External Memory Start address: 0x900000
Waveform Start Address (typical): 0x902000
Size: 256K
10-41
Notes: Stored waveforms must not overwrite the TI micro-code. With

the given default locations shown above, the TI Programs (only
dac25 for now) are allowed to be 0x2000 (8K) in size before
they bump into the default waveform memory. Actual size of
the TI Program is much smaller than 8K (about 0x8f = 143).
PWD Instrument
TI Internal memory start address: 0x87ff00
Size: 512
TI External Memory Start address: pwdfft =0x900000

wd2kconv= 0x93a000
Channel 1 ADC samples start: 0x904000
Channel 1 float samples start: 0x908000
Channel 1 fft results start: 0x90c000
Channel 2 fft results start: 0x918000
Channel 3 ADC samples start: 0x91c000
Channel 4 float samples start: 0x92c000
Waveform Start Address (typical): 0x902000
Size: 256K
Notes: Stored waveforms must not overwrite the TI micro-code. With

the given default locations shown above, the TI Programs
(pwdfft) is allowed to be 0x4000 (16K) in size before it bumps
into the default waveform capture and fft memory. It actually
takes up 0x138a (decimal 5002).The wd2kconv program is
stored near the end of the memory space, allowing it to be
0x6000 (24576) in size. It actually takes up 0x4a of space
(decimal 74 locations).
Each channel is allowed 16K locations for the ADC sampled
waveform, 16K for the same samples converted to "float" for
DSP math (fft), and 16K locations for the fft results. Max
required for 4096 point fft is 4K for each.
10-42
AC Instruments
WS Specific Declarations
Note that this structure defines a waveform in terms of both the waveform source (WS) and waveform
digitizer (WD). The definitions specific to the WS are discussed in this section.
wssel: WSTYPE = LFWS0,LFWS1, or HFWS
wschan: WSCHANNEL = LFWSP0,LFWSN0,LFWSP1,LFWSN1, HFWS
waveoff: Useful for signal generation, allows an offset to be embedded in the waveform,
rather than supplied by the offset DAC.
waveamp: Used mainly with HF source. Allows a c function to derive and store a waveform
of some amplitude. Not used for multi-tone generation. Because the DSP
processor will scale the amplitude value, this should be set to 1 for all LF
waveforms.
wavestart: Starting address of waveform. The waveform memory starting address is

0x900000. This address has been saved for the user in the global variable
ws0_dsp.wavestrt. If using the low frequency source use wavestart locations
above 0x900000. Another bit has been provided to allow for automatically
sending the data from waveform memory to the DSP and on to the WS DAC. To
use this feature use locations above 0x940000. Note that the same memory
location is used (0x900001 is the same location as 940001) however an extra
bit is set that indicates that the word gets sent directly to the DAC without
further processing. This is useful when using the HFWS to get maximum
throughput.
wavesize: Size of the source waveform
dacloop: Used by the DSP. Indicates the number of clocks that will be added to the
sample loop in addition to the number of steps of microcode that already exist.
Only used in the LF sources. The current number of steps in the DSP
microcode for clocking the LFDAC is 20, therefore the data rate for the WS is
determined by the TICLOCK/2/(20 + dacloop).
example if TICLK=46.078MHz, and dacloop = 52, the LFDAC Clock =

46.078e06/2/(20+52)= 319,986 Samp/Sec
indexreg: The index rate at which the DSP will step through the waveform. Applies to
LFWS only. The use of indexreg is important for DDS signal generation. For
example if the loaded waveform is a single cycle sine wave of 1000 points, if the
indexreg is set to 1 then running the waveform at 320KS/s a sine wave of
320Hz will be generated. Changing the indexreg to 3 will generate 3*320000/
1000 = 960Hz, etc. Note that for the initial WS application the value of indexreg
is always set to 1 in the defining structure. The actual index is determined at a
later time, this will be discussed in more detail in a later section. Note that for
HF waveforms, this value should always be set to 1.
dacprog: The TIPROGRAM that the WS DSP will run is currently called "DAC". The start
address for the WS TIPROGRAM has been saved for the user in the global
variable ws0_dsp.dacprog.start.
refck: The clock that is selected to run the synthesizer. This clock can be internal
(OSCCLK), system (DISCLK), or external (XCLKIN).
pll_p: Numerator for the WS on-board pll.
10-43
pll_q: Denominator for the WS on-board pll.
pll_m: Divider for the o- board pll (2^pll_m).
pll example input clock = 12.5e06

pll_p = 94
pll_q= 51
pll_m= 3
DSP clock freq = 12.5e06*2*94/51/(2^3) = 5.759e06
wsoff: The value loaded to the WS offset DAC. Independent of any offset loaded as
part of the waveform. Note that the offset DACS must currently be calibrated as
part of the application. Detail provided in a later section.
atten: Selects the level of attenuation for the WS. Note - the attenuators are calibrated
as part of AC calibration.
wsfil: The filter that is selected, WS5KHZ, WS50KHZ, or WSNOFIL.
tones: If the waveform is a multi-tone this indicates the number of tones.
bins[ 0..tones-1]: If the waveform is a multi-tone, each tone has an associated bin based on the
sample rate and number of points. Each tones bin must be defined.
amps[ 0..tones-1]: If the waveform is a multi-tone, each tone has an associated amplitude. Each
amps bin must be defined. Note - this amplitude should include a cal factor for
that tone.
multitone example: Need the following:

1KHz @ 1V
2KHz @ 0.5V
3.75KHz @ .1V
Solution:
wavesize = 5120
dacloop = 52
DAC clock = 12.5e06*94/51/(20 +dacloop) =319,989.1 Samp/Sec
Fourier freq = 319989.1/5120 = 62.498 Hz
bin for tone 1 = 1KHz/62.498Hz = 16 16*62.498 = 999.968Hz
bin for tone 2 = 2KHz/62.498 Hz = 32 32*62.498 = 1,999.936Hz
bin for tone 3 = 3750KHz/62.49KHz = 60 60*62.498 = 3749.88Hz
therefore the items in the structure would be defined ;
xxx.tones = 3;
xxx.bins[0] = 16;
xxx.bins[1] = 32;
xxx.bins[2] = 60;
xxx.amps[0] = 1.0*wscal[16]; ****
xxx.amps[1] = 0.5*wscal[32];
xxx.amps[2] = 0.1*wscal[60];
Note the calfactor wscal is included to show that waveforms should be adjusted
before loading into memory. Details of calibration factors and actual calfactor
arrays are provided later.
10-44
AC Instruments
WD Specific Declarations
The structure declarations that are specific to the WD are discussed in this section.
wdsel: WDTYPE=LFWD0, LFWD1, or HFWD
digsize: The number of samples to be captured and analyzed by the WD DSP

processor.
convprog: The TIPROGRAM run by the WD DSP processor when sampling a signal.
Current program is 'CONVERT'. The start address for this WD TIPROGRAM
has been saved for the user in the global variable ws0_dsp.convprog.start. The
file name for this WD TIPROGRAM has been saved for the user in the global
variable ws0_dsp.convprog.fil.
fftprog: The current TIPROGRAM run by the WD DSP processor when processing a
digitized signal for Fourier analysis. Current program is 'FFT'. The start address
for this WD TIPROGRAM has been saved for the user in the global variable
ws0_dsp.fftprog.start.
fund: The bin of the fundamental frequency to be evaluated by the DSP processor.
Note that the function actest in dspdrv.c will override the fund argument if DDS
is used.
adcclk: The rate at which the LFWD clock will run. Upper limit is 2.5MS/Sec. Note that
this parameter should be passed to the function wdlfadc in file wddrv.c.
adcsam: The rate at which the LFWD or HFWD will sample. Note that this parameter
should be passed to the function wdlfadc or wdhfadc located in file wddrv.c.
wdfil: The value of the filter setting for the LF WD channel. Valid arguments are
WD5KHZ, WD50KHZ, and WDNOFIL. Should be passed to the function wdfilt
in file wddrv.c.
wdoff: The value to be programmed in the WD input offset DAC. Should be passed to
the function wdoff in file wddrv.c.
gain1: The value of gain of the first gain stage of the LFWD. Values are 1,2,4,8. This
value should be passed to the function wdgain in file wddrv.c.
gain2: The value of gain of the second gain stage of the LFWD. Values are 1,2,4,8.
This value should be passed to the function wdgain in file wddrv.c.
digbuff: The starting address in the WD RAM for storing sample data from the digitizer.
This address has been saved for the user in the global variable
ws0_dsp.digbuff.
digoff: An offset value required by the FFT program in addressing the WD RAM for
stored sample data. This address has been saved for the user in the global
variable ws0_dsp.digoff.
digstart: The starting address for the WD TIPROGRAM program for digitizing
waveforms. This address has been saved for the user in the global variable
ws0_dsp.digstart.
10-45
fltbuff: The starting address in the WD RAM for storing floating point sample data. This
is data that has been converted from the integer format output from the digitizer
DAC. This address has been saved for the user in the global variable
ws0_dsp.fltbuff. This address is used to designate the starting location of input
data for the FFT calculations.
fftout: The starting address in the WD RAM for storing FFT result data. This address
has been saved for the user in the global variable ws0_dsp.fftout. This address
is used to designate the starting location of output data from the FFT
calculations.
Note that although the structure defines many of the WD sampling parameters, it is up to the user to see
that these parameters are actually set correctly in the WD.
Dspclocksetup
Default Clock Setup

To ensure proper operation, the WS and WD clock scheme resets automatically. The setup criteria are
defined by a structure wsclock_reset or wdclock_reset of type DSPCLOCKSETUP. The structure
DSPCLOCKSETUP is currently defined in dsp.h as follows:
typedef struct {
DSPCLOCK from;
DSPCLOCK to;
short pllsetup;
unsigned pll_p;
unsigned pll_q;
unsigned pll_m;
} DSPCLOCKSETUP
Definitions:
from: DSPCLOCK =XCLKIN,DISCLK,OSCCLK,PLLMCLK0, or NOCLOCK

This is a source clock. A source clock can be either a source for the DSP
PLL(REFCK0) or a source for the clock distribution on the FPGA.
to: DSPCLOCK =REFCK0,TICLK, LFCLK0, XCLKOUT, MCLK or NOCLOCK

This is a destination clock. A destination clock can be either a source for the
DSP PLL, a clock for the on board DSP, a clock for a digitizer, or an external
clock sourced to another DSP instrument.
pllsetup: Setting this to 1 will setup the PLL on the appropriate board (WS or WD).
Setting to 0 will not setup a PLL.
pll_p: The value for the 'p' parameter of the PLL.
pll_q: The value for the 'q' parameter of the PLL.
pll_m: The value for the 'm' parameter of the PLL.
10-46
AC Instruments
Example for Setting WS0->clock_reset

// WS Clock Initializers. Setup during ws_reset
DSPCLOCKSETUP wsclock_reset[] = {
// Settings for 46.08MHZ from DISCLK
{DISCLK, REFCK0, 0, 0, 0, 0},
{PLLMCLK0, TICLK, 1, 94, 51, 0},
{PLLMCLK0, XCLKOUT, 0, 0, 0, 0},
{NOCLOCK, NOCLOCK, -1, 0, 0, 0}
};
This example structure will set the WS as follows:
PLL Input clock: DISCLK = 12.5MHz input to REFCK0
PLL output clock: PLLMCLK0 = 12.5MHz*2*94/51/2^0=46.08MHz
TICLK to DSP: 46.08MHz
XCLKOUT to FC: 46.08MHz
Note that the last line (NOCLOCK,NOCLOCK) is necessary to terminate the clock setup.
The structure WD0->clock_reset should be setup in a similar way. Note that there is significant flexibility in
clocking the DSP instruments. The example above illustrates only one of many possible configurations.
Clocking and Synchronization
There are several methods for providing coherent clocking between the various system modules (DSPIO,
WS, and WD). It is important to note that any one of these modules can provide the "master" clock for the
system. It is equally important to note that once the master clock source has been determined, the user is
responsible for connecting the master clock to each "slaved" module. This connection is differential ECL
for the WD and WS inputs and outputs. The connection is differential LVDS for the DSPIO module. The
hardware connections are made on the Fathercard. Note that it is important to run the module DSP clocks
(TICLK) as fast as possible to insure fastest DSP processing times. The TI internal processor clock can run
as fast as 30MHz (TICLK up to 60Mhz).
An example best illustrates the syntax flow required to insure proper clock coherence and setup.
Clocking Example
For this example assume the following:
1. The WS internal clock is used as the master clock for both the WS and the WD.
2. The system DISCLK (12.5MHz) will be used as the master reference clock.
3. There is a hardwired connection between the WS output clock and the WD input clock on the
Fathercard.
double temp[SIDES];
..
..
WD0->clock(DISCLK, REFCK0); // select 12.5mhz clock as reference to PLL;
WS0->clock(PLLMCLK0, TICLK); // select output of PLL as WS DSP processor clock;
WS0->clock(PLLMCLK0, XCLKOUT); // select output of PLL as external clock out ( to WD)
// note - the above setting are the current defaults

WS0->pllbits(PLLMCLK0,94,51,0); // p=94 q=51 m=0
WS0->xclkoutfreq(temp); // sets temp array to correct frequencies
10-47
WD0->xclkinfreq(temp); // sets correct value for wdclkfreq
WD0->clock(XCLKIN, TICLK); // selects external clock as WD DSP clock

WD0->clock(XCLKIN, LFCLK0); // selects external clock as ref for the LFWD
// note - the above settings are the current defaults
WD0->lfadc(LFWD0,1.92e06,32000); // will get as close as possible based on value of wdclkfreq
Here's how the DSP system is set based on the above syntax:
WS TICLK = 12.5e06*2*94/51/1 = 46,078,431.3Hz
WS XCLKOUT = 46,078,431.3Hz
WS Sample Rate = TICLK/2/(20+dacloop), if dacloop = 52 then WS Samp Rate = 319,989.1Hz
WD XCLKIN = 46,078,431.3Hz
WD LFADC CLK = (46,078,431.3/1.92e06 = 23.999); 46,078,431.3/24 = 1,919,934.6Hz
WD LFADC Sample = (46,078,431.3/32000) = 1439.95; 46,078,431.3/1440 = 31,998.91Hz
For this example the WS is sending output at 10 times the rate that the WD is sampling.
10-48
AC Instruments
Figure 10.13: DSP Clocking
10-49
Figure 10.14: Waveform Source DSP Block Diagram
10-50
AC Instruments
Figure 10.15: WS DSP – DAC Program
DDS (Direct Digital Synthesis)
In the past Waveform Generator instruments have typically been represented by a clock source,
controlling logic, waveform memory, and D/A converters. The result was the ability to source a stored
arbitrary waveform from memory. If the device required different test frequencies (Ft), the test engineer
was required to recalculate the correct signal and load the digital representation of this signal into a
different memory block. The more tones required, the larger the memory requirements and housekeeping
task became.
The KVD Waveform Source approaches single-tone sinewave generation differently. With the addition of
an on-board DSP processor, a single stored sinewave can be used to generate signals of varying
amplitude and frequency. This approach is called Direct Digital Synthesis (DDS). With this technique, not
only will the waveform amplitude be corrected at run time, but the frequency can be modified as well.
Memory requirements and housekeeping tasks are greatly reduced. The next several pages illustrate how
DDS works with the Waveform Source.
10-51
Figure 10.16: Sampled Sine Wave
10-52
AC Instruments
Figure 10.17: Direct Digital Synthesis
10-53
DDS Example
As always Ft/Fs=M/N;
if Fs=319.989Ks/S
N=5120
if indexreg=1:
Ft=Fs*1/N = 62.49Hz
if indexreg=2:
Ft=Fs*2/N = 124.99Hz
etc.
Note: DDS only applies to single-tone sinewaves. Multi-tone signals must be stored individually.
PLL Setup
As discussed in previous sections, each DSP Module (WS, WD, DSPIO) contains an on-board PLL clock
circuit that is capable of supplying clocks both internally and externally. Each PLL circuit is basically the
same. The test engineer must provide information to setup the PLL circuit to produce the desired DSP
system clocks. Since there are constraints on the PLL circuit, it may be necessary to use a utility that
assists in the PLL setup. Functions to do this are available in KVD demonstration programs - please
contact your local apps engineer for samples.
10-54
Chapter 11: Non-Instrument Software
Command Summary
LOG Object
TLOG
The TLOG class is implemented through the object LOG. This class contains an enormous number of
functions that are useful to the test engineer. Theses functions range from loading run time conditions (bin
files, limits files) to tracking the state of the test flow.
class TLOG : public TKVDNonResource;
LOG >CurTestNum
Always contains the current test number. Auto incremented after call to KVD->Test command.
unsigned CurTestNum;
LOG >DataToEventLog
Setting this to true redirects datalog strings from the Engineering screen to the CBuilder IDS's Event Log
bool DataToEventLog;
LOG >DisableAlarms
default = false. When set to true, allows the KVD->Test command to determine failures that include source
alarms.
bool DisableAlarms;
LOG >EngineeringMode
Parameter set by reading the Customer Preferences.
bool EngineeringMode;
Description:
When true, this causes the datalogs to show profiling test times.
LOG >plottestnum
Variable to set to activate the automatic plotting of the last measvm statement.
int plottestnum;
LOG >SystemMsgToEventLog
Setting this to true redirects system message strings from the status portion of the main screen to the
CBuilder IDS's Event Log.
bool SystemMsgToEventLog;
11-1
LOG >ActiveWaferTesting
Read only property.
__property bool ActiveWaferTesting;
Description:
True when a wafer is testing.
LOG >ApplicationName
Read only property.
__property AnsiString ApplicationName;
Description:
Returns the Application name, excluding the path and extension.
LOG >BadDieCount
Read only property.
__property unsigned long BadDieCount;
Description:
Returns the current total number of failed devices for this test run.
LOG >BinFileName
Read only property.
__property AnsiString BinFileName;
Description:
Returns the filename of the last bin file read.
LOG >Comment
Read/Write property.
__property AnsiString Comment;
Description:
Sets or Returns the Comment field that appears in the various data files.
LOG >ComputerName
Read only property.
__property AnsiString ComputerName;
Description:
Returns the TesterID (ComputerName) used for all data files.
11-2
Non-Instrument Software Command Summary
LOG >DatalogFileName
__property AnsiString DatalogFileName;
Description:
Sets or Returns the filename that datalogs will go to.
LOG >DataPath
__property AnsiString DataPath;
Description:
Sets or Returns the file path used for all data files.
LOG >Default_LOT_DataFileName
__property AnsiString Default_LOT_DataFileName;
Description:
Sets or Returns the BASE name applied to all lot data files (HIST, TDA, SUM, and LOG).
LOG >Default_SUBLOT_DataFileName
__property AnsiString Default_SUBLOT_DataFileName;
Description:
Sets or Returns the BASE name applied to all sublot data files (HIST, TDA, SUM, and LOG).
LOG >DUTSN
__property int DUTSN;
Description:
Sets or Returns the current serial number for the Device Under Test.
LOG >EnablePrintDatalogFile
__property bool EnablePrintDatalogFile;
Description:
Enables (true) and disables (false) the automatic printing of DatalogFile files.
11-3
Example:
//this example enables automatic printing of DatalogFile files
LOG->DatalogFile=true;
LOG >EnablePrintHistogramFile
__property bool EnablePrintHistogramFile;
Description:
Enables (true) and disables (false) the automatic printing of Histogram files.
Example:
//this example enables automatic printing of Histogram files
LOG->EnablePrintHistogramFiles=true;
LOG >EnablePrintSummaryFile
__property bool EnablePrintSummaryFile;
Description:
Enables (true) and disables (false) the automatic printing of Summary files.
Example:
//this example enables automatic printing of Summary files
LOG->EnablePrintSummaryFile=true;
LOG >EnablePrintTDAFile
__property bool EnablePrintTDAFile;
Description:
Enables (true) and disables (false) the automatic printing of TDA files.
Example:
//this example enables automatic printing of TDA files
LOG->EnablePrintTDAFiles=true;
LOG >FileDatalogAll
Read/Wite property.
__property bool FileDatalogAll;
Description:
Changes the file datalogging mode to log ALL tests.
11-4
LOG >FileDatalogFails
Read/Wite property.
__property bool FileDatalogFails;
Description:
Changes the file datalogging mode to log FAILS only.
LOG >FileDatalogOff
Read/Wite property.
__property bool FileDatalogOff;
Description:
Changes the file datalogging mode to OFF.
LOG >FileSampleNum
Read only property.
__property unsigned FileSampleNum;
Description:
When this number is equal to the File Sample Size, a datalog is generated.
LOG >FileSampleSize
Read/Wite property.
__property unsigned FileSampleSize;
Description:
Use this field to set the sample size rate for device data being logged to the file.
LOG >FirstTestNum
Read only property.
__property unsigned FirstTestNum;
Description:
Returns the first test number used in the limits array.
LOG >FixtureID
__property AnsiString FixtureID;
Description:
Sets or Returns the FixtureID that appears in the various data files.
11-5
LOG >GoodDieCount
Read only property.
__property unsigned long GoodDieCount;
Description:
Returns the current total number of good devices for this test run.
LOG >HandTestModeActive
Read only property.
__property bool HandTestModeActive;
Description:
Returns true if the operator has activated the hand test form.
LOG >Job
__property AnsiString Job;
Description:
Sets or Returns the Job Name that appears in the various data files.
LOG >LastDatalogString
Read only property.
__property AnsiString LastDatalogString;
Description:
If in NoDataCollection mode, returns the last datalog string produced by the KVD->Test command.
LOG >LastTestNum
Read only property.
__property unsigned LastTestNum;
Description:
Returns the last test number used in the limits array.
LOG >LibraryVersion
Read only property.
__property AnsiString LibraryVersion;
Description:
Returns the currently loaded library designation string.
11-6
LOG >LotNumber
__property AnsiString LotNumber;
Description:
Sets or Returns the Lot Number path used for all data files.
LOG >LotNumber
LOG->LotNumber="12345678";
AnsiString lotnum=LOG->LotNumber;
LOG >NoDataCollection
__property bool NoDataCollection;
Description:
Allows the user to perform tests, but does no record any of the data collected.
LOG >OperatorID
__property AnsiString OperatorID;
Description:
Sets or Returns the OperatorID that appears in the various data files.
LOG >ParameterFileName
Read only property.
__property AnsiString ParameterFileName;
Description:
Returns the filename of the last parameters file read.
LOG >RuntimeLevel
Read only property.
__property short RuntimeLevel;
Description:
Returns flags that indicate the run time level of the program.
11-7
LOG >SavedDatalogFileName
Read only property.
__property AnsiString SavedDatalogFileName;
Description:
Returns the Datalog file name that is being used.
LOG >ScreenDatalogAll
Read/Wite property.
__property bool ScreenDatalogAll;
Description:
Changes the screen datalogging mode to log ALL tests.
LOG >ScreenDatalogFails
Read/Wite property.
__property bool ScreenDatalogFails;
Description:
Changes the screen datalogging mode to log FAILS only.
LOG >ScreenDatalogOff
Read/Wite property.
__property bool ScreenDatalogOff;
Description:
Changes the screen datalogging mode to OFF.
LOG >ScreenSampleNum
Read only property.
__property unsigned ScreenSampleNum;
Description:
When this number is equal to the Screen Sample Size, a datalog is generated.
LOG >ScreenSampleSize
Read/Wite property.
__property unsigned ScreenSampleSize;
Description:
Use this field to set the sample size rate for device data being logged to the screen.
11-8
LOG >StartedByKVDLauncher
Indicates true when the application was started by a KVD Launcher app.
__property bool StartedByKVDLauncher;
LOG >StartLotTime
Read only property.
__property TDateTime StartLotTime;
Description:
Returns the date and time that the lot was started.
LOG >StopFF
__property bool StopFF;
Description:
Also known as Fast Binning. Set to true to enable fast binning. Set to false to disable fast binning. Read
this property to determine the fast binning mode.
LOG >TesterID
__property AnsiString TesterID;
Description:
Sets or Returns the TesterID (ComputerName) that appears in the various data files.
LOG >UploadDataPath
__property AnsiString UploadDataPath;
Description:
Sets or Returns the path that all data files will be uploaded to.
LOG >UsingCustomDataDLL
Read only property.
__property bool UsingCustomDataDLL;
Description:
Flag that indicates whether a custom data DLL is being used or not. This field is set only by enabling the
option in the customer preferences tool.
11-9
LOG >UsingDeviceHandler
Read only property.
__property bool UsingDeviceHandler;
Description:
Flag that indicates whether a device handler/prober DLL is being used or not.
LOG >WaferDescFileName
__property AnsiString WaferDescFileName;
Description:
Sets or returns the currently wafer description file name.
LOG >WafermapColorsFileName
Read only property.
__property AnsiString WafermapColorsFileName;
Description:
Returns the filename of the last WCF file read.
LOG >WafermapDescFileName
Read only property.
__property AnsiString WafermapDescFileName;
Description:
Returns the filename of the last WDF file read.
LOG >WaferMapX
__property int WaferMapX;
Description:
For Wafer testing only. Returns the last wafer X position reported by the prober.
LOG >WaferMapY
Read only property.
__property int WaferMapY;
Description:
For Wafer testing only. Returns the last wafer Y position reported by the prober.
11-10
LOG >WaferNumber
__property AnsiString WaferNumber;
Description:
Sets or Returns the Lot Number path used for all data files.
Example:
LOG->WaferNumber="12";
AnsiString wafnum=LOG->WaferNumber;
LOG >WaferTestFlow
Indicates true when the application is testing wafers, false for package test see options in Customer
Preferences Tool.
__property bool WaferTestFlow;
LOG >AddLimitUnit
Adds a new unit to the units array.
short AddLimitUnit(AnsiString name, double value);
Parameters:
AnsiString name
The name of the unit. This is the same name that will be used in the limits file.
double value
The value that is applied when the unit is used.
Returns:
0 - indicates that the unit could not be added to the list. a value greater than 0 indicates success.
Description:
The user can add their own units (an essentially unlimited number) if they so desire.
The only requirement is that the call to AddLimitUnit occur before you load the limits file, otherwise the load
will fail. KVD suggests that you put the call for AddLimitUnit in your TUser::SystemInit section.
11-11
LOG >AddUserComment
Allows the user to add comments that will show up on the data file headers
void AddUserComment(AnsiString name, AnsiString desc);
Parameters:
AnsiString name
The name will be the portion that shows on the left side of the header.
AnsiString desc
The value of the commented name.
For example LOG->AddUserComment("LASER POWER","5.00uj"); would show up as LASER POWER :

5.00uJ on the header.
Description:
This field allows the engr to add there own comments to the data file headers. It is the responsibility of the
programmer to clear the list. That is, comments added during one wafer will carry to the next wafer unless
cleared.
LOG >ClearUserComments
Clears all previously added comments
void ClearUserComments();
LOG >CurrentBin
Returns the Current bin of the device under test.
int CurrentBin(short sitenum = 0);
Parameters:
short sitenum = 0
An integer between 0 and 7 (default = 0)
Returns:
Returns the current bin for the DUT for the sitenum passed in. Value will be 0 - 63 A value of 0 indicates an
error occurred in a binning process somewhere during the test flow.
Description:
If no sitenum is passed into the function, it defaults to site 0 which is valid for all single site testing.
11-12
LOG >DatalogComment
Allows user to send strings to datalog reports.
void DatalogComment(AnsiString s);
Parameters:
AnsiString s
Your comment string.
Description:
Use this function to enter your own strings/comments into the datalog report. The string is entered at
position when it is called.
LOG >DeleteWaferData
Deletes a previously saved binary wafer map file.
bool DeleteWaferData();
Returns:
True if the file existed and was deleted, otherwise false.
Description:
Uses the wafer number, lot number as the filename. The extension is .rtl
LOG >DownGrade
Used to downgrade a device from its current PASSING bin to the next PASSING bin. Description:
short DownGrade(short sitenum);
Parameters:
short sitenum
LOG >ExecuteProgram
Executes an external program specified by the cmd parameter.
HANDLE ExecuteProgram(HWND hwnd, String cmd);
Parameters:
HWND hwnd
The handle to the windows application calling the function.

String cmd
The PATH, FILENAME, EXTENSION, and command line.
11-13
LOG >FindWaferData
Locates a previously saved binary wafer map file.
bool FindWaferData();
Returns:
True if the file exists, otherwise false.
Description:
Uses the wafer number, lot number as the filename. The extension is .bwm
LOG >GetLimitsEntry
Returns a LIMITS_STRUCT containing all the limits info for this test number.
LIMITS_STRUCT GetLimitsEntry(unsigned tn);
LOG >GetPassBinSite
Used to retrieve the passbin for one site.
short GetPassBinSite(short sitenum = 0);
Parameters:
short sitenum = 0
LOG >IsFailing
Used to determine if the DUT is currently failing.
bool IsFailing(short sitenum = 0);
Parameters:
short sitenum = 0
Returns:
Returns true if the device is considered a FAIL, false otherwise.
LOG >IsPassing
Used to determine if the DUT is currently passing.
bool IsPassing(short sitenum = 0);
Parameters:
short sitenum = 0
11-14
Returns:
Returns true if the device is still considered a PASS, false otherwise.
LOG->test_fail[tn]
Changes made so that the field LOG->test_fail[tn] works as before. Billk is believed to be the only one who
uses it. The problem he was having was that this field was buffered, and yet he reads it/needs it in real
time.
LOG >IsValidBin
Used to determine if the DUT's current bin is valid.
bool IsValidBin(short sitenum = 0);
Parameters:
short sitenum = 0
Returns:
Returns true if the DUT has a current bin that was listed in the BIN description file
LOG >load_bin_data
Loads a bin description file.
short load_bin_data(AnsiString filename);
Description:
Bin description files specify the bin numbers, whether they are pass or fail bins and maximum allowed
consecutive fails, or overall fails. Please read the HOW TO file "How to Setup a BIN File" for more
information.
LOG >load_extlimits_data
Function that loads a limits file created with the Extended Limits Editor. Description: This function differs
from the load_limits_data in the sense that it supports files created with the Extended Limits Editor, that is,
it supports multiple limits per test.
short load_extlimits_data(AnsiString filename);
Parameters:
AnsiString filename
The PATH and FILENAME of the limits file.
11-15
LOG >load_limits_data
Function that loads a limits file NOT created with the Extended Limits Editor Description: This function
loads limits data created in the older style format. That format was supported by the original Limits Editor,
not the Extended Limits Editor.
short load_limits_data(AnsiString filename);
Parameters:
AnsiString filename
The PATH and FILENAME of the limits file.
LOG >load_waferdesc_file
Loads a wafer description file.
short load_waferdesc_file(AnsiString filename);
Parameters:
AnsiString filename
The PATH and FILENAME of the wafer description file.
Returns:
-1 if the file does not exist
-2 if the file is empty
-3 if the file has the wrong format
otherwise 0.
Description:
Wafer description files can be generated automatically by using the M310direct tool. These files have the
min and max values for the rows and columns in the map, as well as the map layout for testable die, inked
die, skipped die, and untestable die.
LOG >load_wafermap_colors
Loads a wafer map colors file.
short load_wafermap_colors(AnsiString filename);
Description:
Wafer map colors files contain the colors used in the wafermap display. For more information on this, see
the HOW TO file, "Creating Wafer Map Description and Color Files".
11-16
LOG >LoadCustomerPrefFile
Loads a previously save Customer Preferences Config file.
short LoadCustomerPrefFile(AnsiString filename);
Parameters:
AnsiString filename
The PATH , FILENAME, and EXT of the cpc file.
Returns:
0 if the file is loaded ok.
Description:
Use the customer preferences tool to configure your options, and then save the file. Then, use this
command to load those preferences.
LOG >TestInProgress
Allows the user to display a TEST IN PROGRESS splash screen with their own message.
void TestInProgress(AnsiString message = NULL);
Description:
By sending in a string, the splash screen will be displayed with that string as the message. By sending in
an empty string (""), the splash screen is removed.
LOG >UserGenDatalog
LOG Example 1
User function to generate datalogs from program control.

void UserGenDatalog(REPORT_DESTINATION dest, AnsiString filename = 0);
Parameters:
REPORT_DESTINATION dest
Can be TOPRINTER, or TOFILE.

AnsiString filename = 0
Only valid if destination is TOFILE. Must include path, filename, and extension
Description:
Datalogs are normally generated at LOT end. This function can be called anytime during the program flow
to generate the datalog immediately.
Example:
//this line generates the datalog to a file
LOG->UserGenDatalog(TOFILE,"c:\MyDatalog.txt");
//this line generates the datalog and send directly to the printer
LOG->UserGenDatalog(TOPRINTER);
11-17
LOG >UserGenHistogram
User function to generate histograms from program control.
void UserGenHistogram(REPORT_DESTINATION dest, AnsiString filename = 0);
Parameters:

Description:
Histograms are normally generated at LOT end. This function can be called anytime during the program
flow to generate the histogram immediately.
Example:
//this line generates the histogram to a file
LOG->UserGenHistogram(TOFILE,"c:\MyHistogram.txt");
//this line generates the histogram and send directly to the printer
LOG->UserGenHistogram(TOPRINTER);
LOG >UserGenSummary
User function to generate summaries from program control.
void UserGenSummary(REPORT_DESTINATION dest, AnsiString filename = 0);
Parameters:

Description:
Summaries are normally generated at LOT end. This function can be called anytime during the program
flow to generate the summary immediately.
Example:
//this line generates the summary to a file
LOG->UserGenSummary(TOFILE,"c:\MySummary.txt");
//this line generates the summary and send directly to the printer
LOG->UserGenSummary(TOPRINTER);
11-18
LOG >UserGenTDA
User function to generate TDA report from program control.
void UserGenTDA(REPORT_DESTINATION dest, AnsiString filename = 0);
Parameters:

Only valid if destination is TOFILE. Must include path, filename, and extension.
Description:
TDA reports are normally generated at LOT end. This function can be called anytime during the program
flow to generate the TDA file immediately.
Example:
//this line generates the TDA report to a file
LOG->UserGenTDA(TOFILE,"c:\MyTDA.txt");
//this line generates the TDA report and send directly to the printer
LOG->UserGenTDA(TOPRINTER);
LOG->NoTester - is only true if the NoTester install was run.
KVD Object
KVD >UserParamFileName
Contains the filename of the Users Parameters File.
AnsiString UserParamFileName;
KVD >CalibrateAll
Runs the calibration program in automatic mode, which runs all calibrations.
void CalibrateAll();
KVD >CalibrateMenu
Runs the calibration program in normal user mode.
void CalibrateMenu();
Description:
The calibration program runs as normal. The user will need to run the various calibrations and exit the
program before it returns to the calling process.
KVD >DaysSinceLastCal
Returns the number of days since the last calibration was completed.
double DaysSinceLastCal();
11-19
KVD >HoursSinceLastCal
Returns the number of hours since the last calibration was completed
double HoursSinceLastCal();
KVD >LoadConfig
Loads a configuration file using the TCT tool.
short LoadConfig(AnsiString filename);
Parameters:
AnsiString filename
This is the name of the configuration file. You do not need to put in a path or extension.
Returns:
0 if config was loaded, -1 of the file could not be found.
Description:
Different test head configurations can be saved from the TCT. It automatically saves them in the TCT
folder, with a tct_config extension. The test engineer can make sure that his configuration is loaded by
loading it with this command.
KVD >ReadLauncherString
Returns strings sent in through the use of KVD Launcher.
AnsiString ReadLauncherString(AnsiString param);
Returns:
If no KVDLauncher.ini file exists, returns ERROR_KVDLAUNCHER_INI_NOT_FOUND.
If the KVDLauncher.ini file does not have a [LAUNCHERENTRIES] section, returns

ERROR_NO_LAUNCHENTRIES_SECTION.
If the parameter does not appear in the KVDLauncher.ini file, returns

ERROR_PARAM_DOES_NOT_EXIST.
Otherwise it returns the value associated with the parameter as an AnsiString.
Description:
This function differs from the function ReadParameterString in that it returns parameter values that were
set up in the KVD Launcher interface. Typically these parameters are the OperatorID and the LotNumber.
KVD >ReadParameterString
Returns the requested parameter from the parameter file.
AnsiString ReadParameterString(AnsiString param);
Returns:
If UserParamFileName hasn't been set, returns ERROR_FILENAME_IS_NULL.
11-20
If file does not have a [PARAMETERS] section, returns ERROR_NO_PARAMETERS_SECTION.
If file does not have the requested parameter, returns ERROR_PARAM_DOES_NOT_EXIST for file.
If file does not exist, returns ERROR_PARAMFILE_NOT_FOUND.
Otherwise, it returns the parameters value as an AnsiString.
Description:
This function opens up the parameter file specified by the UserParamFileName. If the file exists, and the
parameter exists, it returns the parameters value as a AnsiString. If the file does not exist, or the parameter
does not exist, it returns an ERROR string (see Return Values).
KVD >SelectView
Command that allows the user to select which page is the viewable page on the main form.
void SelectView(int pagenum);
Parameters:
int pagenum
An integer that corresponds to the page 0 - Chart View 1 - Engineering View 2 - Test Statistics View 3 -
Wafer Map View.
KVD >Test
Compares the last result to the current test limits.
short Test(void);
Returns:
FALSE for a PASSING device, and TRUE for a FAILING device.
Description:
This is the routine that is called to verify a pass/fail condition. The SITE->lastresult value is compared to
the limits for the current test number. After the compare, the datalog line is generated and test counters are
updated.
KVD >TestNoFail
Compares the last result to the current test limits. DOES NOT GENERATE FAIL INFORMATION.
short TestNoFail(void);
Returns:
FALSE for a PASSING device, and TRUE for a FAILING device.
Description:
This routine is identical to the Test function, except all fail information is not generated. For more
information, see the Test function, but remember that no fail information is generated.
11-21
KVD >tnum
Sets the current test number.
short tnum(unsigned number);
Parameters:
unsigned number
Must be between 1 and 6199.
Returns:
0 for a valid test number, -1 for an invalid test number.
Description:
Sets the LOG->CurTestNum variable. This then determines the limits to use for testing.
KVD >UserComment
Adds a comment line to the Engineering View.
void UserComment(AnsiString s);
Relay and Connection Commands

TRelay Constructor
Used to create new relays.
Command: $RELAY$ = new TRelay(<address>, <bit>)
Objects: $RELAY$
Description: an object
Data type: TRelay pointer
Arguments: <address>
Description: relay driver address
Data type: unsigned int.
<bit>
Description: bit associated with the relay
Data type: unsigned int.
Effect: Creates a new TRelay object.
Prototype: TRelay(unsigned address, unsigned bit);
Example: TRelay* K1 = new TRelay(0x30, 0x1);
11-22
TRelay -> close

Closes a relay.
Command: $RELAY$->close();
Objects: $RELAY$
Arguments: None
Effect: Closes the relay.
Prototype: short close(void);
Example: K1->close();
TRelay -> open

Opens a relay.
Command: $RELAY$->open();
Objects: $RELAY$
Arguments: None
Effect: Opens a relay
Prototype: short open(void);
Example: K1->open;
TConnection Constructor
Used to create new Connections.
Command: $CONNECTION$ = new TConnections(<Relays>)
Objects: $CONNECTION$
Data type: TConnection pointer
Arguments: <Relays>
Description: This can be either a list of previously defined relays (see TRelay) or a list of
address bit pairs. (see example).
Effect: Creates a new TConnection object.
11-23
Prototype: TConnection(TRelay* ra, TRelay* rb,

TRelay* rc, TRelay* rd,
TRelay* re, TRelay* rf,
TRelay* rg, TRelay* rh);
TConnection(unsigned add0, unsigned bit0,
unsigned add1, unsigned bit1,
unsigned add7, unsigned bit7);
Example: TConnection* DS1_TO_DUTPIN2;

DS1_TO_DIGPIN2 = new TConnection(0x30,0x1, 0x31,0x2);
//Or
TRelay* K1 = new TRelay(0x30, 0x1);
TRelay* K2 = new TRelay(0x31, 0x2);
DS1_TO_DIGPIN2 = new TConnection(K1, K2);
Things to Remember: At least one Relay or address/bit pair must be used in the constructor, and
not more than eight Relays or address/bit pairs can be used for one
TConnection object.
TConnection -> con

Connect resources.
Command: $CONNECTION$->con();
Data type: TConnection
Arguments: None
Effect: Connects resources by closing any relays in the list.
Prototype: short con(void);
Example: DS1_TO_DUTPIN2->con();
Alternative Forms: con_side(<side>) Close relays on one side only
Things to Remember: This command only has effect on active sites.
Relay closure time may take up to one millisecond. During this interval it is recommended not to force
voltages or currents, as this may cause source oscillation and/or shorten relay lifetime.
11-24
TConnection -> discon

Disconnect resources.
Command: $CONNECTION$->discon();
Data type: TConnection
Arguments: None
Effect: Disconnect a path by opening all relays in the list
Prototype: short discon(void);
Example: DS1_TO_DUTPIN2->discon();
Alternative Forms: discon_side( <side>) Open all the relays in the list, on one side only.
Thing to Remember: This command only has effect on active sites.
Relay opening time may take up to one millisecond. It is recommended that no current flow through the
relays at the time discon() is issued and during the relay open time, as this may cause source oscillation
and/or shorten relay lifetime.
11-25
11-26
Appendix A: Detailed Specifications
The latest specifications will be provided here in hard copies of the manual. For ease of updating, they are
not part of this document.
A-1
A-2
Appendix B: Release Notes and Updates
Please insert any new Release Notes sent you in this section of the manual for reference.
B-1
B-2
Appendix C: Custom Father Cards
Please insert Father Card documentation in this section of the manual for reference.
C-1
C-2
Index
A DDCH[i][1] >dstrb 9-45
AC power 4-1 DDCH[i][1] >enable 9-45
Administrative commands 8-21 DDCH[i][1] >getcomplev 9-45
DDCH[i][1] >getformat 9-45
B DDCH[i][1] >gethighlev 9-46
Batteries DDCH[i][1] >getkeepalive 9-46
Caution 2-2
DDCH[i][1] >getlowlev 9-46
Bin Description Editor 6-37
DDCH[i][1] >getname 9-46
Bin Setup Tool 6-40
DDCH[i][1] >getstarttime 9-46
BitCalc 10-54
DDCH[i][1] >getstate 9-46
BootTester 6-67
DDCH[i][1] >getstoptime 9-46
C DDCH[i][1] >getstrobe 9-46
Calibration activities 5-33 DDCH[i][1] >setname 9-47
Calibration files 5-28 DDDRV_TO_DDCH[NUMDDCHANNELS] 6-68
Cautions 1-3, 2-1 DDS 10-51
Chemicals 2-4 Delay Table 6-61
Clamps 8-5, 8-21 Devices 1-6
Clocking 9-29 Dflags 9-33
Comparator Strobe Time 9-38 Diagnostics 5-39
Connections and Relays 6-50 DIG0 >dcap_drv_en 9-39
Connections Table Tool 6-52 DIG0 >dcap_read 9-39
CSV Format 7-20 DIG0 >dcap_setup 9-39
Current ranges 8-20 DIG0 >dcap_wait 9-39
Custom data DLLs 7-20 DIG0 >dclr 9-39
Customer Preferences Tool 7-1 DIG0 >dconfig 9-39
DIG0 >dd_xclkinfreq 9-39
D DIG0 >dd_xclkoutfreq 9-39
Datalog Control Page 7-5 DIG0 >ddclock 9-39
Datalogs 7-38, 7-54 DIG0 >ddpllbits 9-40
DB25 Handler Interface 7-16 DIG0 >ddrv_load 9-40
DC power supply adjustment limits 5-4 DIG0 >ddrv_load_side 9-40
Dclr 9-32 DIG0 >ddrv_load_side_mask 9-40
DDBUSA_TO_DDCH[NUMDDCHANNELS] 6- DIG0 >ddrv_setup 9-40
68 DIG0 >dfail 9-40
DDCH[i][1] >dcomp 9-43
DIG0 >dfailaddr 9-40
DDCH[i][1] >dfmt 9-44
DIG0 >dflags 9-40
DDCH[i][1] >dfmt_long 9-44
DIG0 >dmclkconfig 9-40
DDCH[i][1] >disable 9-44
DIG0 >dreadfail 9-41
DDCH[i][1] >dka 9-44
DIG0 >dstatus 9-41
DDCH[i][1] >dlevel 9-45
DIG0 >dstop 9-41
DDCH[i][1] >dmatch 9-45
Index-1
DIG0 >dt0t 9-41 DMCH[x]->keepalive 9-82

DIG0 >dwait 9-41 DMCH[x]->l1abus_con 9-77
DIG0 >dwaitfail 9-41 DMCH[x]->l1abus_discon 9-77
DIG0 >dwaitnofail 9-41 DMCH[x]->ldenable 9-75
DIG0 >dxclkena 9-41 DMCH[x]->load 9-75
DIG0 >getsym 9-41 DMCH[x]->loaddisable 9-75
DIG0 >patexe 9-42 DMCH[x]->measfreq 9-82
DIG0 >patexe_sym 9-42 DMCH[x]->measvm 9-75
DIG0 >patload 9-43 DMCH[x]->pmuenable 9-73
DIG0 >patload1 9-43 DMCH[x]->seti 9-73
DIG0 >reset 9-43 DMCH[x]->SetSiteMode 9-69
DIG0 >set_DDXTALFREQ 9-43 DMCH[x]->setv 9-73
Digital Signal Processing 10-40 DMCH[x]->start 9-80
DIGMOD[x]->dcap_read 9-95 DMCH[x]->start_measfreq 9-83
DIGMOD[x]->dcap_setup 9-94 DMCH[x]->stop 9-81
DIGMOD[x]->ddrv_load 9-95 DMCH[x]->tmucon 9-82
DIGMOD[x]->ddrv_setup 9-95 DMCH[x]->trm 9-72
Direct Digital Synthesis 10-51 DMCH[x]->trmenable 9-73
DMCH[x]->abus_con 9-76 DMCH[x]->tset 9-80
DMCH[x]->abus_discon 9-77 DMCH[x]->vih 9-72
DMCH[x]->cmplevel 9-71 DMCH[x]->vil 9-71
DMCH[x]->cmpstart 9-81 DMCH[x]->vmeter 9-74
DMCH[x]->cmpstop 9-81 DMCH[x]->voh 9-72
DMCH[x]->dcmp 9-79 DMCH[x]->vol 9-72
DMCH[x]->dcomp 9-80 DMCH[x]->vrange 9-74
DMCH[x]->dfmt 9-79 Drive & Capture 9-50
DMCH[x]->dig_con 9-76 Drive and Compare Levels 9-38
DMCH[x]->dig_discon 9-76 DSP 10-40
DMCH[x]->disable 9-70 DSPIO Father Card Pin Assignments 9-49
DMCH[x]->dka 9-82 Dstop 9-32
DMCH[x]->dlevel 9-71 dt0t 9-33
DMCH[x]->dtiming 9-77 Dwait 9-32
DMCH[x]->dtiming_combine 9-79
E
DMCH[x]->enable 9-69
Electrostatic discharge 2-3
DMCH[x]->enastart 9-81
Enable or Disable the Driver 9-38
DMCH[x]->enastop 9-81
Engineering view 7-44
DMCH[x]->fmt 9-80
Ergonomics 2-4
DMCH[x]->force 9-70
Exception Handler 6-44
DMCH[x]->forceenable 9-70
DMCH[x]->forcemode 9-70 F
DMCH[x]->format 9-80 Failure Results 9-32
DMCH[x]->imeter 9-74 FC Relay Setup Tool 6-50
DMCH[x]->irange 9-74 FLAG 9-57
Index-2
Index
Force current 8-19 KVD >tnum 11-22

Force voltage 8-19 KVD >UserComment 11-22
Format and Timing 9-38 KVD >UserParamFileName 11-19
FPGA booting 5-30
L
G Launcher 7-35
Glossary 1-3 Lithium batteries 2-2
Grounding 2-3 LOG >ActiveWaferTesting 11-2
LOG >AddLimitUnit 11-11
H
LOG >AddUserComment 11-12
Handler Bin Table Tool 7-17
LOG >ApplicationName 11-2
Handler Options 7-6
LOG >BadDieCount 11-2
Handler/prober port 7-13
LOG >BinFileName 11-2
Hazards 1-3
LOG >ClearUserComments 11-12
HCIF 7-13
LOG >Comment 11-2
Help 1-1
LOG >ComputerName 11-2
Histograms 7-41, 7-54
LOG >CurrentBin 11-12
HPDCMOD I/O pinout 8-24
LOG >CurTestNum 11-1
HPDS[i] >actual_sample_rate 8-23
LOG >DatalogComment 11-13
HPDS[i] >Exists 8-23
LOG >DatalogFileName 11-3
HPDS[i] >getname 8-24
LOG >DataPath 11-3
HPDS[i] >hpdsirange 8-23
LOG >DataToEventLog 11-1
HPDS[i] >hpdsloopcomp 8-23
LOG >Default_LOT_DataFileName 11-3
HPDS[i] >hpdsmode 8-23
LOG >Default_SUBLOT_DataFileName 11-3
HPDS[i] >hpdsval 8-23
LOG >DeleteWaferData 11-13
HPDS[i] >hpdsvrange 8-23
LOG >DisableAlarms 11-1
I LOG >DownGrade 11-13
Installing new releases 5-5 LOG >DUTSN 11-3
Installing software 5-6 LOG >EnablePrintDatalogFile 11-3
Instrument replacement instructions 5-1 LOG >EnablePrintHistogramFile 11-4
LOG >EnablePrintSummaryFile 11-4
K LOG >EnablePrintTDAFile 11-4
K[0 thru 80] 6-68 LOG >EngineeringMode 11-1
Kelvin connections 8-5, 8-21 LOG >ExecuteProgram 11-13
KVD >CalibrateAll 11-19 LOG >FileDatalogAll 11-4
KVD >CalibrateMenu 11-19 LOG >FileDatalogFails 11-5
KVD >DaysSinceLastCal 11-19 LOG >FileDatalogOff 11-5
KVD >HoursSinceLastCal 11-20 LOG >FileSampleNum 11-5
KVD >LoadConfig 11-20 LOG >FileSampleSize 11-5
KVD >ReadLauncherString 11-20 LOG >FindWaferData 11-14
KVD >ReadParameterString 11-20 LOG >FirstTestNum 11-5
KVD >SelectView 11-21 LOG >FixtureID 11-5
KVD >Test 11-21 LOG >GetLimitsEntry 11-14
KVD >TestNoFail 11-21
Index-3
LOG >GetPassBinSite 11-14 LOG >WafermapDescFileName 11-10

LOG >GoodDieCount 11-6 LOG >WaferMapX 11-10
LOG >HandTestModeActive 11-6 LOG >WaferMapY 11-10
LOG >IsFailing 11-14 LOG >WaferNumber 11-11
LOG >IsPassing 11-14 LOG >WaferTestFlow 11-11
LOG >IsValidBin 11-15
M
LOG >Job 11-6
Maintenance personnel safety 2-2
LOG >LastDatalogString 11-6
Master Clock Selection 9-33
LOG >LastTestNum 11-6
Measure 8-7, 8-22
LOG >LibraryVersion 11-6
MP administrative commands 8-6
LOG >load_bin_data 11-15
MP current ranges 8-4
LOG >load_extlimits_data 11-15
MP force current 8-3
LOG >load_limits_data 11-16
MP force voltage 8-3
LOG >load_waferdesc_file 11-16
MPDCMOD 8-1
LOG >load_wafermap_colors 11-16
MPDCMOD block diagram 8-2
LOG >LoadCustomerPrefFile 11-17
MPDCMOD calibration 5-34
LOG >LotNumber 11-7
MPDCMOD I/O pinout 8-16
LOG >NoDataCollection 11-7
MPDS[i] >actual_sample_rate 8-10
LOG >OperatorID 11-7
MPDS[i] >Exists 8-10
LOG >ParameterFileName 11-7
MPDS[i] >get_board_local_groundsense 8-
LOG >plottestnum 11-1
11
LOG >RuntimeLevel 11-7
MPDS[i] >getname 8-11
LOG >SavedDatalogFileName 11-8
MPDS[i] >mpdsirange 8-10
LOG >ScreenDatalogAll 11-8
MPDS[i] >mpdsloopcomp 8-10
LOG >ScreenDatalogFails 11-8
MPDS[i] >mpdsmode 8-10
LOG >ScreenDatalogOff 11-8
MPDS[i] >mpdsval 8-10
LOG >ScreenSampleNum 11-8
MPDS[i] >mpdsvrange 8-10
LOG >ScreenSampleSize 11-8
MPDS[i] >read_temperature 8-11
LOG >StartedByKVDLauncher 11-9
MPDS[i] >ResourceSide 8-11
LOG >StartLotTime 11-9
MPDS[i] >ResourceSlot 8-11
LOG >StopFF 11-9
MPDS[i] >result 8-11
LOG >SystemMsgToEventLog 11-1
MPDS[i] >vmmode 8-11
LOG >TesterID 11-9
MPUVM[i] >getname 8-15
LOG >TestInProgress 11-17
Multisite Development 6-62
LOG >UploadDataPath 11-9
LOG >UserGenDatalog 11-17 N
LOG >UserGenHistogram 11-18 Nomenclature 1-3
LOG >UserGenSummary 11-18
LOG >UserGenTDA 11-19 O
LOG >UsingCustomDataDLL 11-9 Octal 8-1
LOG >UsingDeviceHandler 11-10 offset DAC 8-12
LOG >WaferDescFileName 11-10 Opcodes 9-16
LOG >WafermapColorsFileName 11-10 Operator safety 2-1
Index-4
Index
P PWSx -> clock_reset 10-18

Parallel Handler cabling 7-13 PWSx -> con 10-16
Parallel Handler driver 7-6 PWSx -> con_to_agnd 10-17
Patexe 9-31 PWSx -> con_to_cal_bus 10-16
Patload 9-31 PWSx -> con_to_ic 10-16
Pattern Control 9-13 PWSx -> con_to_l1 10-16
Patterns 9-58 PWSx -> con_to_switch_bus 10-16
Plot Tool 6-30 PWSx -> dds_reset 10-18
Power PWSx -> dds_setup 10-18
AC 4-1 PWSx -> discon 10-17
Precision Waveform Digitizer 10-28 PWSx -> discon_from_agnd 10-18
Precision Waveform Source 10-13 PWSx -> discon_from_cal_bus 10-17
Preventive maintenance 5-3 PWSx -> discon_from_ic 10-17
Production view 7-43 PWSx -> discon_from_l1 10-17
PWDx -> clock 10-33 PWSx -> discon_from_switch_bus 10-17
PWDx -> clock_div 10-33 PWSx -> filter 10-20
PWDx -> clock_reset 10-33 PWSx -> init 10-21
PWDx -> clockselect 10-34 PWSx -> offset 10-20
PWDx -> dds_reset 10-32 PWSx -> reset 10-21
PWDx -> dds_setup 10-32 PWSx -> setv 10-21
PWDx -> fft 10-36 PWSx -> xclockinfreq 10-19
PWDx -> fft_exec 10-36 PWSx -> xclockoutfreq 10-19
PWDx -> filter 10-39
PWDx -> gain 10-39 R
PWDx -> input_con 10-31 Radiation 2-4
PWDx -> input_discon 10-32 Recalibrating the Keithley 2000 5-38
PWDx -> instr_con 10-31 Relay Matrix Board 8-28
PWDx -> instr_discon 10-31 Reset 9-30
PWDx -> offset 10-38 RMX 8-28
PWDx -> read_wd2000_dc 10-39 RMX commands 8-30
PWDx -> reset 10-34 RMX I/O pinout 8-35
PWDx -> setup_fft 10-35 RMX0 >Clear 8-30
PWDx -> sinad 10-37 RMX0 >CreateNamedConnection 8-31
PWDx -> sinad_filter 10-38 RMX0 >GetLineStatus 8-32
PWDx -> snr 10-36 RMX0 >GetLineToLineStatus 8-32
PWDx -> snr_filter 10-37 RMX0 >GetPinStatus 8-32
PWDx -> start 10-34 RMX0 >NClear 8-33
PWDx -> stop 10-35 RMX0 >NSet 8-33
PWDx -> thd 10-36 RMX0 >resetall 8-33
PWDx -> thd_filter 10-37 RMX0 >resetline 8-33
PWDx -> wait 10-35 RMX0 >ResetNamedList 8-33
PWSx -> atten 10-20 RMX0 >Set 8-33
PWSx -> clock 10-19 RTI Support 9-38
Index-5
S Software backups 5-5

Safety 2-1 Subassembly replacement 5-2
Maintenance personnel 2-2 Summaries 7-40, 7-54
Operator 2-1 Synchronization 9-29
Send/Capture Memory Setup 9-34
send_value 6-61 T
SEQ0->createpatmap 9-91 TConnection -> con 11-24
SEQ0->cycle_count 9-89 TConnection -> discon 11-25
SEQ0->dcap_setup 9-94 TConnection Constructor 11-23
SEQ0->dfail 9-88 TDA 7-54
SEQ0->dflags 9-88 Test Configuration tool 5-19
SEQ0->dt0div 9-87 Test head power 5-18
SEQ0->dt0t 9-87 Test Statistics view 7-45
SEQ0->dwait 9-88 Testing 1-6
SEQ0->get_wait_timeout 9-90 TH 6-68
SEQ0->getsym 9-94 Time Measurement Unit 9-119
SEQ0->keepalive_timeset 9-87 Timing diagrams 9-35
SEQ0->MasterSlave 9-86 TLOG 11-1
SEQ0->mclk_sel 9-86 TMU 9-119
SEQ0->patexe 9-92 TMU >ddchan 9-123
SEQ0->patexe_array 9-93 TMU >enable 9-123
SEQ0->patexe_parallel 9-93 TMU >freq 9-124
SEQ0->patload 9-91 TMU >input 9-124
SEQ0->patload_parallel 9-92 TMU >interval 9-124
SEQ0->patload_pformat 9-92 TMU >level 9-125
SEQ0->patloadmap 9-90 TMU >meas 9-125
SEQ0->running 9-88 TMU >meas_array 9-125
SEQ0->set_wait_timeout 9-90 TMU >meas_neg 9-125
SEQ0->SetMode 9-85 TMU >reset 9-125
SEQ0->SetSiteMode 9-85 TMU Commands 9-123
SEQ0->SetupMCLK 9-87 TMU I/O Pinout 9-121
SEQ0->status 9-89 LOG->test_fail 11-15
Sequencer 9-57 Trace Tool 6-47
Setsites 6-62 TRelay -> close 11-23
Setup File Tool 7-31 TRelay -> open 11-23
SITE >disable 6-65 TRelay Constructor 11-22
SITE >enable 6-65
U
SITE >IsActive 6-65
User Voltmeter 8-12
SITE >lastresult 6-64
UVM 8-12
SITE >resetall 6-65
SITE >set_default_sites 6-65 V
SITE >setsites 6-65 Vector 9-14
SITE >sitemask 6-66 VirtualHandlerClass 6-58
Index-6
Index
void TlogicAnalyzer::Run() 9-104 WD->reset 10-25

Voltage ranges 8-4, 8-19 WD->start 10-24
WD->xclkinfreq 10-26
W
WD->xclkoutfreq 10-26
Wafer Mapping 6-59
WS 10-6
Warnings 1-3, 2-1
WS -> xclkinfreq () 10-10
Waveform Digitizer 10-22
WS I/O Pinout 10-8
Waveform Digitizer Hypertronics Pinout 10-
WS->atten 10-12
24
WS->clock 10-9
Waveform Source 10-6
WS->filter 10-11
Waveform Source Connections 10-7
WS->init 10-9
Waveforms
defining 10-40 WS->offset 10-11
WD 10-22 WS->pllbits 10-10
WD -> pllbits 10-25 WS->reset 10-10
WD->clock 10-24 WS->start 10-9
WD->filter 10-27 WS->store_ramp20bit 10-13
WD->gain 10-27 WS->store_sine16bit_hs 10-13
WD->hfadc 10-28 WS->store_sine20bit 10-12
WD->init 10-25 WS->store_wave20bit 10-12
WD->lfadc 10-27 WS->xclkoutfreq 10-11
WD->offset 10-26 WS2000 10-6
Index-7

M2 Test System

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

M2 Test System

Uploaded by

Copyright:

Available Formats

M2 Test System

Programming and Operations Manual

Please visit our website at: http://www.kvdco.com

M2 Windows Test System Programming and Operations Manual - Revision 4.0

Chapter 2: Safety and Regulatory Summary

Chapter 3: Unpacking and Installation Guide

Chapter 4: System Hardware

PCIDIS ..................................................................................................................... 4-11

Test Head ...................................................................................................................... 4-46

Chapter 5: Calibration and Maintenance

Notester Emulation Mode........................................................................................... 5-17

Chapter 6: Development Environment

Borland C++ Builder ......................................................................................................... 6-1

Sample Disqualify Datalog Display .............................................................................. 6-39

Chapter 7: Operations Environment

Parallel Handler Driver Instructions............................................................................... 7-6

Speed-up Techniques ................................................................................................ 7-46

MPDS[i] >ResourceSide ....................................................................................... 8-11

RMX Block Diagram ................................................................................................... 8-29

Chapter 9: Digital Instruments

Fail Disabling ............................................................................................................ 9-18

DIG0 >dclr .......................................................................................................... 9-39

Test Program Examples ............................................................................................. 9-47

DMCH[x]->force .................................................................................................. 9-70

Single Board Sequencer ....................................................................................... 9-84

Mapping Names to Pins ............................................................................................. 9-98

Chapter 10: AC Instruments

PWS Clock Setup ................................................................................................. 10-3

PWSx -> clock_reset .......................................................................................... 10-18

PWDx -> clock_div ............................................................................................ 10-33

Chapter 11: Non-Instrument Software Command Summary

LOG >DisableAlarms ............................................................................................ 11-1

LOG >UsingDeviceHandler ................................................................................. 11-10

TRelay Constructor ............................................................................................ 11-22

Appendix A: Detailed Specifications ............................................................A-1

Appendix B: Release Notes and Updates .....................................................B-1

Appendix C: Custom Father Cards ................................................................C-1

Chapter 2: Safety and Regulatory Summary

Chapter 3: Unpacking and Installation Guide

Chapter 4: System Hardware

Thermostat Control Wiring ............................................................................................................ 4-21

Motherboard Analog Bus ............................................................................................................... 4-54

Chapter 5: Calibration and Maintenance

Chapter 6: Development Environment

Main Borland IDE Display ................................................................................................................ 6-7

Chapter 7: Operations Environment

Selecting the GenHCIF.dll................................................................................................................ 7-9

Test Statistics View....................................................................................................................... 7-53

Chapter 9: Digital Instruments

Master Clock Setup Tool................................................................................................................ 9-26

Chapter 10: AC Instruments

Waveform Source Pictorial ............................................................................................................ 10-6

Chapter 11: Non-Instrument Software Command Summary

Recent Major Changes to the Manual

Where to Look for Online Help

Figure 1.1: Help Menus

Figure 1.2: Help Window

Warnings and Cautions

Figure 1.3: M2 System

Figure 1.4: M2m Cabinet and Manipulator

Figure 1.5: Dimensions of the M2m

Device Families Tested on the KVD M2

CMOS - CIF to > 16 MPixels Op Amps

Smart Cards Analog Switches