COMPUTER ARCHITECTURE

Lab 1 and 2 Somanshu Mishra

2015A8PS0427G
Ans 1.1.

Ans 1.2.1
Ans 1.2.2
The sign ”^” means EXOR(Exclusive OR) logical operation.
Ans.1.2.3
Nets are declared using the keyword “wire”. Nets represent connection
between hardware elements. Nets get output value of their drivers.
Ans.1.2.4
X0,X1,X2 and X3 are the name of the instances of adder_1_bit module.
Ans.1.2.5
In gate level modelling we implement a module in terms of logic gates and
interconnections between them. On the other hand in case of data flow
modelling the module is implemented by specifying the data flow.

Ans.1.3.1
B A Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

Ans.1.3.2
Ans.1.3.3
Ans.1.3.4 I got a syntax error while simulating . I did not name the “and” and
“not” gates while simulating. So, then I named the not gates as (n1,n2) and the
and gates (a1,a2,a3,a4).
Ans.1.3.5 I encountered an error because I forgot to instantiate the module
itself in the test bench. Then I instantiated it and got my waveforms.
Ans.1.3.6 We’ll get the error as “Illegal reference to net ‘XX’ “.

Ans1.4
Ans.1.5.1

Ans.1.5.2
Ans.1.5.3
Concepts learned
1)Gate level modelling
2)Dataflow modelling
3)Behavioral Modelling
4)Writing test benches to test our module