8TH SEM PRO Content

RFID BASED ATTENDENCE SYSTEM
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Table of Contents
RFID (Radio Frequency Identification)....................................................................................................................4
HISTORY & TECHNOLOGY BACKGROUNG..............................................................................................................5
BACKGROUNG
STANDARDS...........................................................................................................................................................7
STANDARDS
ISO STANDARDS...........................................................................................................................................10
STANDARDS
RFID HAS MAINLY TWO PARTS:...........................................................................................................................11
PARTS:
TAGS & READER:.........................................................................................................................................11
READER:
BACKSCATTER COMMUNICATION:..........................................................................................................11
COMMUNICATION:
ARCHITECTURE....................................................................................................................................................12
ARCHITECTURE
MINIATURIZATION...............................................................................................................................................16
MINIATURIZATION
HARDWARE.........................................................................................................................................................17
EEPROM INTERFACING........................................................................................................................................17
INTERFACING
FEATURES.....................................................................................................................................................17
FEATURES
DESCRIPTION...............................................................................................................................................18
DESCRIPTION
PIN DESCRIPTION........................................................................................................................................18
DESCRIPTION
MEMORY ORGANIZATION..........................................................................................................................19
ORGANIZATION
DEVICE OPERATION...................................................................................................................................19
OPERATION
DEVICE ADDRESSING.................................................................................................................................20
ADDRESSING
WRITE OPERATIONS....................................................................................................................................21
OPERATIONS
READ OPERATIONS.....................................................................................................................................22
OPERATIONS
RTC INTERFACING................................................................................................................................................24
INTERFACING
FEATURES.....................................................................................................................................................24
FEATURES
DESCRIPTION...............................................................................................................................................25
DESCRIPTION
OPERATION..................................................................................................................................................25
OPERATION
SIGNAL DESCRIPTIONS..............................................................................................................................26
DESCRIPTIONS
RTC AND RAM ADDRESS MAP....................................................................................................................27
MAP
CLOCK AND CALENDAR.............................................................................................................................28
CALENDAR
CONTROL REGISTER...................................................................................................................................29
REGISTER
2-WIRE SERIAL DATA BUS..........................................................................................................................30
BUS
NXP P89C669 MICROCONTROLLER......................................................................................................................32
MICROCONTROLLER
FEATURES.....................................................................................................................................................32
FEATURES
MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)
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BENEFITS......................................................................................................................................................33
BENEFITS
COMPLETE FEATURES...............................................................................................................................33
FEATURES
PROGRAMMING (IAP) CAPABILITY...........................................................................................................33
CAPABILITY
CAPTURE/COMPARE MODULES................................................................................................................34
MODULES
TRF7960 - RFID READER IC...................................................................................................................................41
IC
FEATURES.....................................................................................................................................................41
FEATURES
APPLICATIONS.............................................................................................................................................42
APPLICATIONS
DESCRIPTION...............................................................................................................................................42
DESCRIPTION
PHYSICAL CHARACTERISTICS...................................................................................................................44
CHARACTERISTICS
TERMINAL FUNCTIONS...............................................................................................................................44
FUNCTIONS
SYSTEM DESCRIPTION.........................................................................................................................................47
DESCRIPTION
POWER SUPPLIES........................................................................................................................................47
SUPPLIES
NEGATIVE SUPPLY CONNECTIONS..........................................................................................................48
CONNECTIONS
DIGITAL I/O INTERFACE.............................................................................................................................48
INTERFACE
SUPPLY REGULATOR CONFIGURATION..................................................................................................48
CONFIGURATION
POWER MODES............................................................................................................................................50
MODES
RECEIVER – ANALOG SECTION.................................................................................................................52
SECTION
RECEIVED SIGNAL STRENGTH INDICATOR (RSSI).................................................................................53
(RSSI)
RECEIVER – DIGITAL SECTION..............................................................................................................................54
SECTION
TRANSMITTER......................................................................................................................................................57
TRANSMITTER
TRANSMITTER – ANALOG...........................................................................................................................57
ANALOG
READER COMMUNICATION INTERFACE..............................................................................................................60
INTERFACE
SERIAL INTERFACE COMMUNICATION................................................................................................................62
COMMUNICATION
SPI INTERFACE WITHOUT SS* (SLAVE SELECT) PIN.............................................................................63
PIN
SPI INTERFACE WITH SS* (SLAVE SELECT) PIN.....................................................................................64
PIN
SPI INTERFACE WITH TRF7960 RFID READER IC..................................................................................................67
IC
TRF7960 - SPI WITH SS* MODE ERRATA...................................................................................................67
ERRATA
SCLK POLARITY SWITCH............................................................................................................................68
SWITCH
IRQ STATUS REGISTER READ.....................................................................................................................69
READ
DIRECT COMMAND PROCESSING.............................................................................................................70
PROCESSING
INITIALIZATION OF DERIVATIVE REGISTERS.........................................................................................71
REGISTERS
TRANSMITTING ONE BYTE THROUGH THE FIFO...................................................................................71
FIFO

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ISO 15693 PROTOCOL..........................................................................................................................................72

PROTOCOL
READ MULTIPLE BLOCKS..........................................................................................................................75
BLOCKS
PSEUDO-CODE (FOR READ MULTIPLE BLOCKS COMMAND WITH NO UID):...................................76
UID):
PSEUDO-CODE (FOR READ MULTIPLE BLOCKS COMMAND WITH UID):.........................................77
UID):
WRITE MULTIPLE BLOCKS.........................................................................................................................79
BLOCKS
PSEUDO-CODE (FOR WRITE MULTIPLE BLOCKS COMMAND WITH UID):........................................82
UID):
INTERRUPT HANDLER ROUTINE...............................................................................................................82
ROUTINE
ALL CIRCUTI DIAGRAMS..................................................................................................................................87
MAX232 INTERFACING........................................................................................................................................90
INTERFACING
KEYBOARD & LATCH INTERFACING......................................................................................................................91
INTERFACING
READER CIRCUTI PCB & COMPONENT LAYOUT...................................................................................................93
LAYOUT
INTRODUCTION TO KEIL SOFTWARE....................................................................................................................94
SOFTWARE
WHAT IS ΜVISION3?............................................................................................................................................94
ΜVISION3?
STEPS FOLLOWED IN CREATING AN APPLICATION IN ΜVISION3:........................................................................94
ΜVISION3:
DEVICE DATABASE.............................................................................................................................................100
DATABASE
PERIPHERAL SIMULATION..................................................................................................................................100
SIMULATION
PROGRAMMER..................................................................................................................................................100
PROGRAMMER
PROLOAD PROGRAMMING SOFTWARE.............................................................................................................101
SOFTWARE
ADVANTAGES & DISADVANTAGES.............................................................................................................103
ADVANTAGE OF RFID:........................................................................................................................................103
RFID:
DISADVANTAGE OF RFID:...................................................................................................................................103
RFID:
ADVANTAGES OF USING UHF GEN 2 RFID TAGS:...............................................................................................104
TAGS:
CONCLUSION.....................................................................................................................................................105
TROUBLE SHOOTING.......................................................................................................................................105

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RFID (Radio Frequency Identification)
Radio-frequency identification (RFID) is the use of an object (typically referred to as an

RFID tag) applied to or incorporated into a product, animal, or person for the purpose of
identification and tracking using radio waves. Some tags can be read from several meters
away and beyond the line of sight of the reader.
Radio-frequency identification comprises
interrogators (also known as readers), and tags (also
known as labels). Most RFID tags contain at least
two parts. One is an integrated circuit for storing and
processing information, modulating and
demodulating a radio-frequency (RF) signal, and
other specialized functions. The second is an antenna
for receiving and transmitting the signal. There are
generally three types of RFID tags: active RFID tags, which contain a battery and can
transmit signals autonomously, passive RFID tags, which have no battery and require an
external source to provoke signal transmission, and battery assisted passive (BAP) RFID
tags, which require an external source to wake up but have significant higher forward
link capability providing greater range. There are a variety of groups defining standards
and regulating the use of RFID, including: International Organization for Standardization
(ISO), International Electrotechnical Commission (IEC), ASTM International, DASH7
Alliance, EPCglobal. RFID has many applications; for example, it is used in enterprise
supply chain management to improve the efficiency of inventory tracking and
management. The techniques employed in home automation include those in building
automation as well as the control of home entertainment systems, houseplant watering,
pet feeding, changing the ambiance "scenes" for different events (such as dinners or
parties), and the use of domestic robots.

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HISTORY & TECHNOLOGY BACKGROUNG

In 1945 Léon Theremin invented an espionage tool for the Soviet Union which
retransmitted incident radio waves with audio information. Sound waves vibrated a
diaphragm which slightly altered the shape of the resonator, which modulated the
reflected radio frequency. Even though this device was a covert listening device, not an
identification tag, it is considered to be a predecessor of RFID technology, because it
was likewise passive, being energized and activated by electromagnetic waves from an
outside source.
Similar technology, such as the IFF

transponder invented in the United
Kingdom in 1915, was routinely used by
the allies in World War II to identify
aircraft as friend or foe. Transponders are
still used by most powered aircraft to this
day. Another early work exploring RFID
is the landmark 1948 paper by Harry
Stockman, titled "Communication by
Means of Reflected Power" (Proceedings of the IRE, pp 1196–1204, October 1948).
Stockman predicted that "... considerable research and development work has to be done
before the remaining basic problems in reflected-power communication are solved, and
before the field of useful applications is explored."
Mario Cardullo's U.S. Patent 3,713,148 in 1973 was the first true ancestor of modern
RFID; a passive radio transponder with memory. The initial device was passive, powered
by the interrogating signal, and was demonstrated in 1971 to the New York Port
Authority and other potential users and consisted of a transponder with 16 bit memory
for use as a toll device. The basic Cardullo patent covers the use of RF, sound and light
as transmission media. The original business plan presented to investors in 1969 showed
uses in transportation (automotive vehicle identification, automatic toll system,
electronic license plate, electronic manifest, vehicle routing, vehicle performance
monitoring), banking (electronic check book, electronic credit card), security (personnel
identification, automatic gates, surveillance) and medical (identification, patient history).
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An early demonstration of reflected power (modulated backscatter) RFID tags, both

passive and semi-passive, was performed by Steven Depp, Alfred Koelle, and Robert
Freyman at the Los Alamos National Laboratory in 1973. The portable system operated
at 915 MHz and used 12-bit tags. This technique is used by the majority of today's
UHFID and microwave RFID tags.
The first patent to be associated with the abbreviation RFID was granted to Charles
Walton in 1983 U.S. Patent 4,384,288.
The largest deployment of active RFID is the US Department of Defense use of Savi
active tags on every one of its more than a million shipping containers that travel outside
of the continental United States (CONUS).
The largest passive RFID deployment is the Defense Logistics Agency (DLA)
deployment across 72 facilities implemented by ODIN who also performed the global
roll-out for Airbus consisting of 13 projects across the globe.

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STANDARDS
It's commonly said that there are no standards in RFID. In fact, there are many well-
established standards and a few emerging standards. Here's a guide to the most important
ones.
Standards are critical for many RFID applications, such as payment systems and tracking
goods or reusable containers in open supply chains. A great deal of work has been going
on over the past decade to develop standards for different RFID frequencies and
applications. There are existing and proposed RFID standards that deal with the air
interface protocol (the way tags and readers communicate), data content (the way data is
organized or formatted), conformance (ways to test that products meet the standard) and
applications (how standards are used on shipping labels, for example).
The International Organization for Standardization (ISO) has created standards for
tracking cattle with RFID. ISO 11784 defines how data is structured on the tag. ISO
11785 defines the air interface protocol. ISO has created a standard for the air interface
protocol for RFID tags used in payment systems and contactless smart cards (ISO
14443) and in vicinity cards (ISO 15693). It also has established standards for testing the
conformance of RFID tags and readers to a standard (ISO 18047), and for testing the
performance of RFID tags and readers (ISO 18046).
Using RFID to track goods in open supply chains is relatively new and fewer standards
have been finalized. ISO has proposed standards for tracking 40-foot shipping
containers, pallets, transport units, cases and unique items. These are at various stages in
the approval process. The standard situation was complicated by the fact that the Auto-
ID Center, which developed Electronic Product Code technologies, chose to create its
own air interface protocol for tracking goods through the international supply chain. This
article explains the evolution of the Electronic Product Code and the importance of
various ISO standards.
The Auto-ID Center was set up in 1999 to develop the Electronic Product Code and
related technologies that could be used to identify products and track them through the
global supply chain. Its mission was to develop a low-cost RFID system, because the
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tags needed to be disposable (a manufacturer putting tags on products shipped to a

retailer was never going to get those tags back to reuse them). It had to operate in the
ultra-high frequency band, because only UHF delivered the read range needed for supply
chain applications, such as reading pallets coming through a dock door. The Auto-ID
Center also wanted its RFID system to be global and to be based on open standards. It
needed to be global because the aim was to use it to track goods as they flowed from a
manufacturer in one country or region to companies in other regions and eventually to
store shelves. For Company A to read a tag put on a product by Company B, the tag had
to use a standardized air interface protocol. The Auto-ID Center developed its own
protocol and licensed it to EPCglobal on the condition that it would be made available
royalty-free to manufacturers and end users.
The center also was charged with developing a network architecture—a layer integrated
with the Internet—that would enable anyone to look up information associated with a
serial number stored on a tag. The network, too, needed to be based on open standards
used on the Internet, so companies could share information easily and at low cost. One
option the Auto-ID Center had was to develop the numbering system and network
infrastructure and use ISO protocols as the standard for the air interface. Earlier, EAN
International and the Uniform Code Council had merged their efforts to create the Global
Tag (GTAG), with ISO's UHF protocol. But the Auto-ID Center rejected this, because
the ISO UHF protocol was too complex and would increase the cost of the tag
unnecessarily. The Auto-ID Center developed its own UHF protocol. Originally, the
center planned to have one protocol that could be used to communicate with different
classes of tags. Each successive class of tags would be more sophisticated than the one
below it. The classes changed over time, but here is what was originally proposed.
o Class 1: a simple, passive, read-only backscatter tag with one-time, field-
programmable non-volatile memory.
o Class 2: a passive backscatter tag with up to 65 KB of read-write memory.
o Class 3: a semi-passive backscatter tag, with up to 65 KB read-write
memory; essentially, a Class 2 tag with a built-in battery to support
increased read range.
o Class 4: an active tag that uses a built-in battery to run the microchip's
circuitry and to power a transmitter that broadcasts a signal to a reader.
o Class 5: an active RFID tag that can communicate with other Class 5 tags
and/or other devices.
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Eventually, the Auto-ID Center adopted a Class 0 tag, which was a read-only tag that
was programmed at the time the microchip was made. The Class 0 tag used a different
protocol from the Class 1 tag, which meant that end users had to buy multiprotocol
readers to read both Class 1 and Class 0 tags. In 2003, the Auto-ID Center transitioned
into two separate organizations. Auto-ID Labs at MIT and other universities around the
world continued primary research on EPC technologies. EPC technology was licensed to
the Uniform Code Council, which set up EPCglobal as a joint venture with EAN
International, to commercialize EPC technology. In September 2003, the Auto-ID Center
handed off the Class 0 and Class 1 protocols to EPCglobal, and EPCglobal's board
subsequently approved Class 0 and Class 1 as EPC standards.
Class 1 and Class 0 have a couple of shortcomings, in addition to the fact that they are
not interoperable. One issue is that they are incompatible with ISO standards. EPCglobal
could submit them to ISO for approval as an international standard, but it is likely that
ISO would want to revise them to bring them into line with ISO RFID standards.
Another issue is that they cannot be used globally. Class 0, for instance, sends out a
signal at one frequency and receives a signal back at a different frequency within the
UHF band; this is prohibited in Europe, according to some experts (European Union
regulations are open to interpretation). In 2004, EPCglobal began developing a second-
generation protocol (Gen 2), which would not be backward compatible with either Class
1 or Class 0. The aim was to create a single, global standard that would be more closely
aligned with ISO standards. Gen 2 was approved in December 2004. RFID vendors that
had worked on the ISO UHF standard also worked on Gen 2.
Gen 2 was designed to be fast-tracked within ISO, but a last minute disagreement over
something called an Application Family Identifier (AFI) is likely to slow ISO approval.
All ISO RFID standards have an AFI, an 8-bit code that identifies the origin of the data
on the tag. Gen 2 has an 8-bit block of code that can be used for an AFI, but it is not
required under the standard. (Requiring the eight bits to be used for an ISO AFI would
have limited EPCglobal's control over EPCs.) But vendors are making product based on
the new Gen 2 standard, which paves the way for global adoption of EPC technology in
the supply chain.

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ISO STANDARDS
ISO has developed RFID standards for automatic identification and item management.
This standard, known as the ISO 18000 series, covers the air interface protocol for
systems likely to be used to track goods in the supply chain. They cover the major
frequencies used in RFID systems around the world. The seven parts are:
o 18000–1: Generic parameters for air interfaces for globally accepted

frequencies
o 18000–2: Air interface for 135 KHz
o 18000–3: Air interface for 13.56 MHz
o 18000–4: Air interface for 2.45 GHz
o 18000–5: Air interface for 5.8 GHz
o 18000–6: Air interface for 860 MHz to 930 MHz
o 18000–7: Air interface at 433.92 MHz
EPCglobal's Gen 2 standard could be submitted to ISO under 18000-6, but it's not clear
when that will happen or how quickly it will be approved. ISO slowed approval of
18000-6 to see if it could be aligned with Gen 2. EPCglobal has set up a committee to try
to resolve the issue. Requiring an AFI would require going through a formal process of
amending the EPC standard. End users would like there to be one international standard
for tracking goods through the open supply chain using UHF RFID tags. But it could
take another year before that finally happens.

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RFID HAS MAINLY TWO PARTS:

TAGS & READER:
TAGS Type: Passive, Active & Semi-Passive
Passive: Cheapest, used for item tracking, least capabilities, must harvest energy to
operate transmitted by the reader
Active: Active power supply, active receiver, active transmitter, most costly, largest
capabilities
Semi-Passive: Costly compared to passive,cheaper compared to active,used for

monitoring purpose (monitoring the sensors) it has on board power source &
sensors,data is taken from the sensors & stored in with the power of bettry (on board)
when tag is not monitor by the reader
BACKSCATTER COMMUNICATION:
Passive tag contain antenna for two purpose: harvest energy from the reader signal,
command & carrier wave to communicate with the reader matching & deliberate
mismatching are used for backscatter comuunication.the tag can alter the matching by
adding or removing an impedence(capacitance).when capacitance is connectd the
matching is not optimal & the reflected energy is B. When capacitor is not connected
then the matching is optimal & the reflected energy is A. Now A & B is not same.thus
the differance in the energy is used for modulatiing the data on the reflected wave.
The orientation issue in rfid is normally addressed by providing circularity polarized

antenna at reader & dipole antenna at tag.thus the dipole antenna will receive energy
sufficently with any orientation.
In short circularly polarized antenna reduced the number of unfavorable tag/reader
orientation.
Linearly polarized antenna is used when maximum distance is to be covered reader/tag is

fixed.
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ARCHITECTURE
RFID technology allows an object to be automatically recognized by attaching a radio
transmitter to the product. RFID Infrastructure can detect the presence of these radio tags
and can take appropriate actions. The RFID Infrastructure can be broken down into
distinct domains. A domain is a grouping of related hardware and software components.
The following figure provides a graphical representation of the domains contained in the
RFID Architecture Framework.
The Tagged Object Domain contains the tagged products in a supply chain; or any
other assets or locations that are intended to be tracked or monitored, including the use
of sensors on tags. Since object and tag are physically attached they are considered as
components of the same domain. In contrast to other domains, most of the artefacts in
the Tagged Object Domain are mobile, i.e. can move across different RFID
Infrastructures. This imposes strict interoperability requirements on those artefacts which
would ideally be addressed through open standards.
The Antenna & Reader Domain is the interface between the world of physics (objects,
tags, radio frequencies, etc.) and the world of IT. The Domain may include various
technologies and frequencies, such as UHF, 13.56, Barcode, Gate or Pallet Readers. This
Domain can also include writers, printers, sensors on readers, stand-alone sensors and
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actuators. The Antenna & Reader Domain includes mobile devices that are connected
over a wireless network. Those mobile devices always connect to the same Edge
Domain, and thus to the same RFID Infrastructure, but security and discovery aspects
need to be addressed.
The Edge Domain includes the functionality of filtering and aggregating volumes of
data provided by the readers, supporting the analysis of data and applying local decision
making and intelligence. This activity is at the edge of the network prior to forwarding
data to the Premises Domain. The Edge Domain is typically a low cost appliance just
upstream of the readers and uses pervasive technology to establish a software stack on
the outer edge of the RFID Infrastructure. One appliance controls multiple readers. It is
organized hierarchically and provides assured message delivery into the Premises
Domain, as well as automatic reader discovery and authentication.
The Premises Domain is the intermediary between enterprise applications and the Edge
Domain. It compiles business sense of RFID read information and enables automatic
decision making. It further filters and aggregates, monitors and escalates RFID events to
detect critical business operations, or tracks the location of physical objects. It also logs
all important information on products and locations and manages ‘downstream’
components in other domains, such as readers or RFID controllers. Premises are most
typically hierarchical, in a sense that a head office coordinates subordinate premises.
Business logic can be specific for a premise. As an example, a distribution centre for
food could have different business logic from a distribution centre for hardware,
although they belong to the same retail chain and are part of the same hierarchy.
The Business Process Integration Domain is a means to connect between enterprise

applications and the RFID Infrastructure. While other domains provide a reasonable
level of functionality 'out-of-the-box', Business Process Integration will typically require
some customization to match a given enterprise environment to fulfill its function. It can
therefore be described as a toolbox for business integration.
Another key feature of the Business Process Integration Domain is the ability to act as a
business to business hub for transactions between trading partners.

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The Enterprise & Business Application Domain contains the existing ‘back end’
(sometimes called ‘legacy’) components that require information about product
movement that will be captured by the RFID Infrastructure. Such capabilities correspond
to an organization’s unique mixture of supply chain management and business support
systems. The Domain includes systems that help ordering, managing or supplying goods
and that will be interested in the product movement information. Examples are ERP,
Warehouse Management Systems, Inventory Management, Data Warehouse,
Merchandise Management, Store Systems, and so on. The Object Directory Domain
contains components that provide information about the physical object using the ID as
the lookup key. It can retrieve information about a product and allows companies to
securely share product level information. Information can be on three levels of precision:
o · on product / stock keeping unit (SKU) level
o · on instance level, as known at time of manufacturing
o · on instance level with track and trace history
The Object Directory Domain is a dynamic area, with various standards (i.e. EPC) and
products evolving. A simple, and therefore initially a frequent, instantiation of the Object
Directory Domain is a database lookup in an existing internal database of an enterprise.
A more sophisticated implementation will be required to enable secure, distributed track
and trace across multiple trading partners.
The Systems Management Domain allows customers to remotely monitor, configure,

and update software and firmware
of deployed assets such as
antennas, readers, and servers. It
includes the capability to manage
and deploy applications remotely in
a distributed environment. It also
includes a central ‘dashboard’
through which it is possible to
receive alerts when reader,
antennas, and servers break down
which will increase reliability and
reduce operations costs. Security &
Privacy Management allows customers to extend the existing security infrastructure of
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an enterprise all the way down to readers. For the core security functionality, the
infrastructure must protect both stored data and data that are in transit. The infrastructure
will ensure that stored data is only accessed and modified by authenticated and
authorized components and people, and that transmitted data will be sent with integrity
and confidentiality controls to allow for detection of tampering, and to prevent
eavesdropping.

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MINIATURIZATION
RFIDs are easy to conceal or incorporate in other items. For example, in 2009
researchers at Bristol University successfully glued RFID microtransponders to live ants
in order to study their behavior.This trend towards increasingly miniaturized RFIDs is
likely to continue as technology advances. However, the ability to read at distance is
limited by the inverse-square law.
Hitachi holds the record for the smallest RFID chip, at 0.05mm x 0.05mm. The Mu chip
tags are 64 times smaller than the new RFID tags.
Manufacture is enabled by using the Silicon-on-Insulator (SOI) process. These "dust"
sized chips can store 38-digit numbers using 128-bit Read Only Memory (ROM).A
major challenge is the attachment of the antennas, thus limiting read range to only
millimeters.
Potential alternatives to the radio frequencies (0.125–0.1342, 0.140–0.1485, 13.56, and

840–960 MHz) used are seen in optical RFID (or OPID) at 333 THz (900 nm), 380 THz
(788 nm), 750 THz (400 nm).The awkward antennas of RFID can be replaced with
photovoltaic components and IR-LEDs on the ICs.

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HARDWARE
EEPROM INTERFACING
FEATURES
o Low-voltage Operation
 2.7 (VCC = 2.7V to 5.5V)
o Internally Organized 131,072 x 8
o Two-wire Serial Interface
o Schmitt Triggers, Filtered Inputs for Noise Suppression
o Bidirectional Data Transfer Protocol
o 400 kHz (2.7V) and 1 MHz (5V) Clock Rate
o Write Protect Pin for Hardware and Software Data Protection
o 256-byte Page Write Mode (Partial Page Writes Allowed)
o Random and Sequential Read Modes
o Self-timed Write Cycle (5 ms Typical)
o High Reliability
 Endurance: 100,000 Write Cycles/Page
 Data Retention: 40 Years
o 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead LAP and 8-lead SAP Packages
o Die Sales: Wafer Form, Waffle Pack and Bumped Die

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DESCRIPTION
The AT24C1024 provides 1,048,576 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 131,072 words of 8 bits each.
Thedevice’s cascadable feature Allows up to two devices to share a common two-
wirebus. The device is optimized for use in many industrial and commercial
applicationswhere low-power and low-voltage operation are essential. The devices are
availablein space-saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead Leadless Array (LAP)
and 8-lead SAP packages. In addition, the entire family is available in 2.7V (2.7V to
5.5V) versions.
PIN DESCRIPTION
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin
is open drain driven and may be wire-ORed with any number of other open-drain or
open-collector devices.
DEVICE/ADDRESSES (A1): The A1 pin is a device address input that can be

hardwired or left not connected for hardware compatibility with other AT24Cxx devices.
When the A1 pin is hardwired, as many as two 1024K devices may be addressed on a
single bus system (device addressing is discussed in detail under the Device Addressing
section). If the A1 pin is left floating, the A1 pin will be internally pulled down to GND
if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is >3 pF,
Atmel recommends connecting the A1 pin to GND.

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WRITE PROTECT (WP): The write protect input, when connected to GND, allows
normal write operations. When WP is connected high to VCC, all write operations to the
memory are inhibited. If the pin is left floating, the WP pin will be internally pulled
down to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If
coupling is >3 pF, Atmel recommends connecting the pin to GND. Switching WP to
VCC prior to a write operation creates a software write-protect function.
MEMORY ORGANIZATION
AT24C1024, 1024K SERIAL EEPROM: The 1024K is internally organized as 512
pages of 256 bytes each. Random word addressing requires a 17-bit data word address.
DEVICE OPERATION
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an
external device. Data on the SDA pin may change only during SCL low time periods.
Data changes during SCL high periods will indicate a start or stop condition as defined
below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start

condition which must precede any other command.
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop

condition. After a read sequence, the Stop command will place the EEPROM in a
standby power mode.
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C1024 features a low-power standby mode which is

enabled:
upon power-up and b) after the receipt of the stop bit and the completion of any internal
operations.
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MEMORY RESET: After an interruption in protocol, power loss or system reset, any
two-wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
DEVICE ADDRESSING
The 1024K EEPROM requires an 8-bit device address word following a start condition
to enable the chip for a read or write operation (see Figure 7 on page 11). The device
address word consists of a mandatory one, zero sequence for the first five most
significant bits as shown. This is common to all two-wire EEPROM devices.
The 1024K uses the one device address bit, A1, to allow up to two devices on the same
bus. The A1 bit must compare to the corresponding hardwired input pin. The A1 pin uses
an internal proprietary circuit that biases it to a logic low condition if the pin is allowed
to float.
The seventh bit (P0) of the device address is a memory page address bit. This memory
page address bit is the most significant bit of the data word address that follows. The
eighth bit of the device address is the read/write operation select bit. A read operation is
initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the device will return to a standby state.
DATA SECURITY: The AT24C1024 has a hardware data protection scheme that
allows the user to write-protect the entire memory when the WP pin is at VCC.

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WRITE OPERATIONS
BYTE WRITE: To select a data word in the 1024K memory requires a 17-bit word
address. The word address field consists of the P0 bit of the device address, then the
most significant word address followed by the least significant word address.
A write operation requires the P0 bit and two 8-bit data word addresses following the
deviceaddress word and acknowledgment. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8-bit data word. Following
receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device,
such as a microcontroller, then must terminate the write sequence with a stop condition.
At this time the EEPROM enters an internally timed write cycle, TWR, to the
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM
will not respond until the write is.
PAGE WRITE: The 1024K EEPROM is capable of 256-byte page writes.

A page write is initiated the same way as a byte write, but the microcontroller does not
send a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to 255
more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller
must terminate the page write sequence with a stop. The data word address lower 8 bits
are internally incremented following the receipt of each data word. The higher data word
address bits are not incremented, retaining the memory page row location. When the
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word address, internally generated, reaches the page boundary, the following byte is
placed at the beginning of the same page. If more than 256 data words are transmitted to
the EEPROM, the data word address will “roll over” and previous data will be
overwritten. The address “rollover” during write is from the last byte of the current page
to the first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and
the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves
sending a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero, allowing the read or write sequence to continue.
READ OPERATIONS
Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “rollover” during read is from the last byte of the last memory page, to the first
byte of the first page.
Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but does generate a following
stop condition.
th
L D R P I n s ti t u t e o f T e c h n o l o g y & R e s e a r c h ,8
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RANDOM READ: A random read requires a “dummy” byte write sequence to load in
the data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition.
The microcontroller now initiates a current address read by sending a device address
with the read/write select bit high. The EEPROM acknowledges the device address and
serially clocks out the data word. The microcontroller does not respond with a zero but
does generate a following stop condition.
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the
sequential read will continue.
The sequential read operation is terminated when the microcontroller does not respond
with a zero, but does generate a following stop.

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RTC INTERFACING
FEATURES
o Real time clock counts seconds, minutes, hours, date of the month, month,
day of the week, and year with leap year compensation valid up to 2100
o 56 byte nonvolatile RAM for data storage
o 2-wire serial interface
o Programmable squarewave output signal
o Automatic power-fail detect and switch circuitry
o Consumes less than 500 nA in battery backup mode with oscillator running
o Optional industrial temperature range
o 40°C to +85°C
o Available in 8-pin DIP or SOIC
o Recognized by Underwriters Laboratory

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DESCRIPTION
The DS1307 Serial Real Time Clock is a low power, full BCD clock/calendar plus 56
bytes of nonvolatile SRAM. Address and data are transferred serially via a 2-wire bi-
directional bus. The clock/calendar provides seconds, minutes, hours, day, date, month,
and year information. The end of the month date is automatically adjusted for months
with less than 31 days, including corrections for leap year. The clock operates in either
the 24-hour or 12-hour format with AM/PM indicator. The DS1307 has a built-in power
sense circuit which detects power failures and automatically switches to the battery
supply.
OPERATION
The DS1307 operates as a slave device on the serial bus. Access is obtained by
implementing a START condition and providing a device identification code followed
by a register address. Subsequent registers can be accessed sequentially until a STOP
condition is executed. When VCC falls below 1.25 x VBAT the device terminates an
access in progress and resets the device address counter. Inputs to the device will not be
recognized at this time to prevent erroneous data from being written to the device from
an out of tolerance system. When VCC falls below VBAT the device switches into a low
current battery backup mode. Upon power up, the device switches from battery to VCC
when VCC is greater than VBAT +0.2V and recognizes inputs when VCC is greater than
1.25 x VBAT. The block diagram in Figure 1 shows the main elements of the Serial Real
Time Clock.

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SIGNAL DESCRIPTIONS
VCC, GND - DC power is provided to the device on these pins. VCC is the +5 volt
input. When 5 volts is applied within normal limits, the device is fully accessible and
data can be written and read. When a 3-volt battery is connected to the device and VCC
is below 1.25 x VBAT, reads and writes are inhibited.
However, the Timekeeping function continues unaffected by the lower input voltage. As
VCC falls below VBAT the RAM and timekeeper are switched over to the external
power supply (nominal 3.0V DC) at VBAT.
VBAT - Battery input for any standard 3-volt lithium cell or other energy source. Battery
voltage must be held between 2.0 and 3.5 volts for proper operation. The nominal write
protect trip point voltage at which access to the real time clock and user RAM is denied
is set by the internal circuitry as 1.25 x VBAT nominal. A lithium battery with 48 mAhr
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or greater will back up the DS1307 for more than 10 years in the absence of power at 25
degrees C.
SCL (Serial Clock Input) - SCL is used to synchronize data movement on the serial
interface.
SDA (Serial Data Input/Output) - SDA is the input/output pin for the 2-wire serial
interface. The SDA pin is open drain which requires an external pullup resistor.
SQW/OUT (Square Wave/ Output Driver) - When enabled, the SQWE bit set to 1, the
SQW/OUT pin outputs one of four square wave frequencies (1 Hz, 4 kHz, 8 kHz, 32
kHz). The SQW/OUT pin is open drain which requires an external pullup resistor.
SQW/OUT will operate with either Vcc or Vbat applied.
X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator
circuitry is designed for operation with a crystal having a specified load capacitance
(CL) of 12.5 pF
RTC AND RAM ADDRESS MAP
The address map for the RTC and RAM registers of the DS1307
is shown in Figure 2. The real timeclock registers are located in
address locations 00h to 07h. The RAM registers are located in
addresslocations 08h to 3Fh. During a multi-byte access, when
the address pointer reaches 3Fh, the end of RAM space, it wraps
around to location 00h, the beginning of the clock space.

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CLOCK AND CALENDAR

The time and calendar information is obtained by reading the appropriate register bytes.
The real timeclock registers are illustrated in Figure 3. The time and calendar are set or
initialized by writing the appropriate register bytes. The contents of the time and
calendar registers are in the Binary-Coded Decimal (BCD) format. Bit 7 of Register 0 is
the Clock Halt (CH) bit. When this bit is set to a 1, the oscillator is disabled. When
cleared to a 0, the oscillator is enabled.
The DS1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is
defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected.
In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour
mode, bit 5 is the second 10 hour bit (20-23 hours).
On a 2-wire START, the current time is transferred to a second set of registers. The time
information is read from these secondary registers, while the clock may continue to run.
This eliminates the need to rereadthe registers in case of an update of the main registers
during a read.

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CONTROL REGISTER
The DS1307 Control Register is used to control the operation of the SQW/OUT pin.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OUT X X SQWE X X RS1 RS0
OUT (Output control): This bit controls the output level of the SQW/OUT pin when the
square wave output is disabled. If SQWE=0, the logic level on the SQW/OUT pin is 1 if
OUT=1 and is 0 if OUT=0.
SQWE (Square Wave Enable): This bit, when set to a logic 1, will enable the oscillator
output. The frequency of the square wave output depends upon the value of the RS0 and
RS1 bits.
RS (Rate Select): These bits control the frequency of the square wave output when the
square wave output has been enabled. Table 1 lists the square wave frequencies that can
be selected with the RS bits.

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2-WIRE SERIAL DATA BUS

The DS1307 supports a bi-directional 2-wire bus and data transmission protocol. A
device that sends data onto the bus is defined as a transmitter and a device receiving data
as a receiver. The device that controls the message is called a master. The devices that
are controlled by the master are referred to as slaves. The bus must be controlled by a
master device which generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The DS1307 operates as a slave on the 2-
wire bus. A typical bus configuration using this 2-wire protocol is show in Figure
The DS1307 may operate in the following two modes:
1. Slave receiver mode (DS1307 write mode): Serial data and clock are received
through SDA and SCL. After each byte is received an acknowledge bit is
transmitted. START and STOP conditions are recognized as the beginning and
end of a serial transfer. Address recognition is performed by hardware after
reception of the slave address and *direction bit (See Figure 6). The address byte
is the first byte received after the start condition is generated by the master. The
address byte contains the 7 bit DS1307 address, which is 1101000, followed by
the *direction bit (R/W ) which, for a write, is a 0. After receiving and decoding
the address byte the device outputs an acknowledge on the SDA line. After the
DS1307 acknowledges the slave address + write bit, the master transmits a register
address to the DS1307 This will set the register pointer on the DS1307. The
master will then begin transmitting each byte of data with the DS1307
acknowledging each byte received. The master will generate a stop condition to
terminate the data write.

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2. Slave transmitter mode (DS1307 read mode): The first byte is received and
handled as in the slave receiver mode. However, in this mode, the *direction bit
will indicate that the transfer direction is reversed. Serial data is transmitted on
SDA by the DS1307 while the serial clock is input on SCL.
START and STOP conditions are recognized as the beginning and end of a serial transfer.
The address byte is the first byte received after the start condition is generated by the
master. The address byte contains the 7-bit DS1307 address, which is 1101000,
followed by the direction bit (R/W ) which, for a read, is a 1. After receiving and
decoding the address byte the device inputs an acknowledge on the SDA line. The
DS1307 then begins to transmit data starting with the register address pointed to by
the register pointer. If the register pointer is not written to before the initiation of a
read mode the first address that is read is the last one stored in the register pointer.
The DS1307 must receive a Not Acknowledge to end a read.

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NXP P89C669 MICROCONTROLLER
FEATURES
Extended features of the 51MX Core:
23-bit program memory space and 23-bit data memory space
Linear program and data address range expanded to support up to 8 Mbytes each
Program counter expanded to 23 bits
Stack pointer extended to 16 bits enabling stack space beyond the 80C51 limitation
New 23-bit extended data pointer and two 24-bit universal pointers greatly improve C
compiler code efficiency in using pointers to access variables in different spaces
100% binary compatibility with the classic 80C51 so that existing code is completely
reusable
Up to 24 MHz CPU clock with 6 clock cycles per machine cycle
96 kbytes of on-chip program Flash
2 kbytes of on-chip data RAM
Programmable Counter Array (PCA)
Two full-duplex enhanced UARTs
Byte based Fast I2C serial interface (400 kbits/s)

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BENEFITS
Increases program/data address range to 8 Mbytes each
Enhances performance and efficiency for C programs
Fully 80C51-compatible microcontroller
Provides seamless and compelling upgrade path from classic 80C51
Preserves 80C51 code base, investment/knowledge, and peripherals and ASICs
Supported by wide range of 80C51 development systems and programming tools

vendors
The P89C669 makes it possible to develop applications at lower cost and with a reduced
time-to-market
COMPLETE FEATURES
Fully static
Up to 24 MHz CPU clock with 6 clock cycles per machine cycle
96 kbytes of on-chip Flash with In-System Programming (ISP) and In-Application
PROGRAMMING (IAP) CAPABILITY

2 kbytes of on-chip RAM
23-bit program memory space and 23-bit data memory space
Four-level interrupt priority
32 I/O lines (4 ports)
Three Timers: Timer0, Timer1 and Timer2
Two full-duplex enhanced UARTs with baud rate generator
Byte based Fast I2C-bus serial interface (400 kbits/s)

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Framing error detection
Automatic address recognition
Power control modes
Clock can be stopped and resumed
Idle mode
Power-down mode
Second DPTR register
Asynchronous port reset
Programmable Counter Array (PCA) (compatible with 8xC51Rx+) with five
CAPTURE/COMPARE MODULES
Low EMI (inhibit ALE)
Watchdog timer with programmable prescaler for different time ranges (compatible with
8xC66x with added prescaler)

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P0.0 - P0.7 43 - 36 30 - 37 I/O Port 0: Port 0 is an open drain, bidirectional I/O port.
Port 0 pins that have 1s written to them float and can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to external
program and data memory. In this application, it uses strong internal pull-ups when
emitting 1s.
P1.0 - P1.7 2 - 9 1 - 3, 40 - 44
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins.
Port 1 pins that have 1s written to them are pulled HIGH by the internal pull-ups and can
be used as inputs. As inputs, Port 1 pins that are externally pulled LOW will source
current because of the internal pull-ups.

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2 40 I/O • P1.0, T2
– Timer/Counter 2 external count input/Clock out
3 41 I • P1.1, T2EX
– Timer/Counter 2 Reload/Capture/Direction Control
4 42 I • P1.2, ECI
– External Clock Input to the PCA
5 43 I/O • P1.3, CEX0
– Capture/Compare External I/O for PCA module 0
6 44 I/O • P1.4, CEX1
– Capture/Compare External I/O for PCA module 1 (with pull-up on pin)
7 1 I/O • P1.5, CEX2
– Capture/Compare External I/O for PCA module 2 (with pull-up on pin)
8 2 I/O • P1.6, SCL
– I2C serial clock (when I2C is used, this pin is open-drain and requires external pull-up
due to I2C-bus specification)
9 3 I/O • P1.7, SDA
– I2C serial data (when I2C is used, this pin is open-drain and requires external pull-up
due to I2C-bus specification)
P2.0 - P2.7 24 - 31 18 - 25 I/O Port 2: Port 2 is a 8-bit bidirectional I/O port with
internal pull-ups. Port 2 pins that have 1s written to them are pulled HIGH by the
internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally
being pulled LOW will source current because of the internal pull-ups. (See Section 9
“Static characteristics”, IIL). Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to external data memory that use 16-
bit addresses (MOVX @ DPTR) or 23-bit addresses (MOVX @EPTR, EMOV). In this
application, it uses strong internal pull-ups when emitting 1s.

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During accesses to external data memory that use 8-bit addresses (MOV @ Ri), port 2
emits the contents of the P2 Special Function Register. Note that when 23-bit address is
used, address bits A16-A22 will be outputted to P2.0-P2.6 when ALE is HIGH, and
address bits A8-A14 are outputted to P2.0-P2.6 when ALE is LOW. Address bit A15 is
outputted on P2.7 regardless of ALE.
P3.0 - P3.7 11, 13 – 19 5, 7 - 13
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled HIGH by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally pulled LOW will source current because
of the internal pull-ups.
11 5 I • P3.0, RXD0
– Serial input port 0
13 7 O • P3.1, TXD0
– Serial output port 0
14 8 I • P3.2, INT0
– External interrupt 0
15 9 I • P3.3, INT1
– External interrupt 1
16 10 I • P3.4, T0/CEX3
– Timer0 external input/capture/compare external I/O for PCA module 3
17 11 I • P3.5, T1/CEX4
– Timer1 external input/capture/compare external I/O for PCA module 3
18 12 O • P3.6, WR
– External data memory write strobe
19 13 O • P3.7, RD
– External data memory read strobe

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RXD1 12 6 I • RXD1
– Serial input port 1 (with pull-up on pin)
TXD1 34 28 O • TXD1
– Serial output port 1 (with pull-up on pin)
RST 10 4 I Reset: A HIGH on this pin for two machine cycles, while the oscillator is
running, resets the device. An internal diffused resistor to VSS permits a power-on reset
using only an external capacitor to VDD.
ALE 33 27 O Address Latch Enable: Output pulse for latching the LOW byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1¤6 the oscillator frequency, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each access to external data
memory. ALE can be disabled by setting SFR AUXR.0. With this bit is set, ALE will be
active only during a MOVX instruction.
PSEN 32 26 O Program Store Enable: The read strobe to external program memory.
When executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
EA/VPP 35 29 I External Access Enable/Programming Supply Voltage: EA must be

externally held LOW to enable the device to fetch code from external program memory
locations. If EA is held HIGH, the device executes from internal program memory. The
value on the EA pin is latched when RST is released and any subsequent changes have
no effect. XTAL1 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input
to the internal clock generator circuits.

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XTAL2 20 14 O Crystal 2: Output from the inverting oscillator amplifier.
VSS 22 16 I Ground: 0 V reference.
VDD 44 38 I Power Supply: This is the power supply voltage for normal operation as
well as Idle and Power-down modes. (NC/VSS) 1 39 I No Connect/Ground: This pin is
internally connected to VSS on the P89C669. If connected externally, this pin must only
be connected to the same VSS as at pin 22. (Note: Connecting the second pair of VSS
and VDD pins is not required. However, they may be connected in addition to the
primary VSS and VDD pins to improve power distribution, reduce noise in output
signals, and improve system-level EMI characteristics.)
(NC/VDD) 23 17 I No Connect/Power Supply: This pin is internally connected to

VDD on the P89C669. If connected externally, this pin must only be connected to the
same VDD as at pin 44. (Note: Connecting the second pair of VSS and VDD pins is not
required. However, they may be connected in addition to the primary VSS and VDD pins
to improve power distribution, reduce noise in output signals, and improve system-level
EMI characteristics.)

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TRF7960 - RFID READER IC
FEATURES
Completely Integrated Protocol Handling
Separate Internal High-PSRR Power Supplies for Analog, Digital, and PA Sections
Provide Noise Isolation for Superior Read Range and Reliability
Dual Receiver Inputs With AM and PM Demodulation to Minimize Communication

Holes
Receiver AM and PM RSSI
Reader-to-Reader Anti-Collision
High Integration Reduces Total BOM and Board Area
– Single External 13.56-MHz Crystal Oscillator
– MCU-Selectable Clock-Frequency Output of RF, RF/2, or RF/4
– Adjustable 20-mA, High-PSRR LDO for Powering External MCU
Easy to Use with High Flexibility
– Auto-Configured Default Modes for Each Supported ISO Protocol
– 12 User-Programmable Registers
– Selectable Receiver Gain and AGC
– Programmable Output Power (100 mW or 200 mW)
– Adjustable ASK Modulation Range (8% to 30%)
– Built-In Receiver Band-Pass Filter with User-Selectable Corner Frequencies
Wide Operating Voltage Range of 2.7 V to 5.5 V

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Ultralow-Power Modes
– Power Down < 1 mA
– Standby 120 mA
– Active (Rx only) 10 mA
Parallel 8-Bit or Serial 4-Pin SPI Interface With MCU Using 12-Byte FIFO
Ultrasmall 32-Pin QFN Package (5 mm ´ 5 mm)
Available Tools
– Reference Design/EVM With Development Software
APPLICATIONS
Secure Access Control
Product Authentication
– Printer Ink Cartridges
– Blood Glucose Monitors
Contactless Payment Systems
Medical Systems
DESCRIPTION
The TRF7960/61 is an integrated analog front end and data-framing system for a 13.56-
MHz RFID reader system. Built-in programming options make it suitable for a wide
range of applications for proximity and vicinity RFID systems.
The reader is configured by selecting the desired protocol in the control registers. Direct
access to all control registers allows fine tuning of various reader parameters as needed.
A parallel or serial interface can be used for communication between the MCU and
reader. When hardware encoders and decoders are used (accelerators for different
standards), transmit and receive functions use a 12-byte FIFO register. For direct
th
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transmit or receive functions, the encoders/decoders can be bypassed so the MCU can
process the data in real time. The transmitter has selectable output-power levels of 100
mW (20 dBm) or 200 mW (23 dBm) into a 50-W load (at 5 -V supply) and is capable of
ASK or OOK modulation. Integrated voltage regulators ensure power-supply noise
rejection for the complete reader system.
Data transmission comprises low-level encoding for ISO15693, modified Miller for
ISO14443-A, high-bit-rate systems and Tag-it coding systems. Included with the data
encoding is automatic generation of SOF, EOF, CRC, and/or parity bits. The receiver
system enables AM and PM demodulation using a dual-input architecture. The receiver
also includes an automatic gain control option and selectable gain. Also included is a
selectable bandwidth to cover a broad range of input subcarrier signal options. The
received signal strength for AM and PM modulation is accessible via the RSSI register.
The receiver output is selectable among a digitized subcarrier signal and any of ten
integrated subcarrier decoders (two for ISO15693 low bit rate, two for ISO15693 high
bit rate, two for ISO14443, three for ISO14443 high bit rates and one for Tag-it
systems).
Selected decoders also deliver bit stream and a data clock as outputs. The receiver
system also includes a framing system. This system performs the CRC and/or parity
check, removes the EOF and SOF settings, and organizes the data in bytes. Framed data
is then accessible to the MCU via a 12-byte FIFO register and MCU interface. The
framing supports ISO14443 and ISO15693 protocols. The TRF7960/61 supports data
communication levels from 1.8 V to 5.5 V for the MCU I/O interface while also
providing a data synchronization clock. An auxiliary 20-mA regulator (pin 32) is
available for additional system circuits.

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PHYSICAL CHARACTERISTICS
TERMINAL FUNCTIONS

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Application Schematic for the TRF7961 EVM (SPI Mode)

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SYSTEM DESCRIPTION
POWER SUPPLIES
The positive supply pin, VIN (pin 2) has an input voltage range of 2.7 V to 5.5 V. The
positive supply input sources three internal regulators with output voltages VDD_RF,
VDD_A and VDD_X that use external bypass capacitors for supply noise filtering.
These regulators provide enhanced PSRR for the RFID reader system.
The regulators are not independent and have common control bits for output voltage
setting. The regulators can be configured to operate in either automatic or manual mode.
The automatic regulator setting mode ensures an optimal compromise between PSRR
and the highest possible supply voltage for RF output (to ensure maximum RF power
output). Whereas, the manual mode allows the user to manually configure the regulator
settings.
VDD_RF The regulator VDD_RF (pin 3) is used to source the RF output stage. The
voltage regulator can be set for either 5-V or 3-V operation. When configured for the 5-
V operation range, the output voltage can be set from 4.3 V to 5 V in 100-mV steps. The
current sourcing capability for 5-V operation is 150 mA maximum over the adjusted
output voltage range.
When configured for 3-V operation, the output can be set from 2.7 V to 3.4 V, also in
100-mV steps.
The current sourcing capability for 3-V operation is 100 mA maximum over the adjusted
output voltage range.
VDD_A Regulator VDD_A (pin 1) supplies voltage to analog circuits within the reader
chip. The voltage setting is divided in two ranges. When configured for 5-V operation,
the output voltage is fixed at 3.5 V.
When configured for 3-V operation, the output can be set from 2.7 V to 3.4 V in 100-mV
steps. Note that when configured, both VDD_A and VDD_X regulators are configured
together (their settings are not independent).

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VDD_X Regulator VDD_X (pin 32) can be used to source the digital I/O of the reader
chip together with other external system components. When configured for 5-V
operation, the output voltage is fixed at 3.4 V.
When configured for 3-V operation, the output voltage can be set from 2.7 to 3.4 V in
100-mV steps.
The total current sourcing capability of the VDD_X regulator is 20 mA maximum over
the adjusted output range. Note that when configured, both VDD_A and VDD_X
regulators are configured together (their settings are not independent).
VDD_PA The VDD_PA pin (pin 4) is the positive supply pin for the RF output stage
and is externally connected to the regulator output VDD_RF (pin 3).
NEGATIVE SUPPLY CONNECTIONS

The negative supply connections are all externally connected together (to GND). The
substrate connection is VSS (pin 10), the analog negative supply is VSS_A (pin 15), the
logic negative supply is VSS_D (pin 29), the RF output stage negative supply is
VSS_TX (pin 6), and the negative supply for the RF receiver input is VSS_RX (pin 7).
DIGITAL I/O INTERFACE

To allow compatible I/O signal levels, the TRF7960/61 has a separate supply input
VDD_I/O (pin 16), with an input voltage range of 1.8 V to 5.5 V. This pin is used to
supply the I/O interface pins (I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of
the reader. In typical applications, VDD_I/O is connected directly to VDD_X to ensure
that the I/O signal levels of the MCU are the same as the internal logic levels of the
reader.
SUPPLY REGULATOR CONFIGURATION

The supply regulators can be automatically or manually configured by the control bits.
The available options are shown in Table 5-1 through Table 5-4. Table 5-1 shows a 5-V
system and the manual-mode regulator settings. Table 5-2 shows manual mode for
selection of a 3-V system. The automatic mode is the default configuration. In automatic
mode, the regulators are automatically set every time the system is activated by asserting

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the EN input HIGH. The internal regulators are also automatically reconfigured every
time the automatic regulator selection bit is set HIGH (on the rising edge).
The user can re-run the automatic mode setting from a state in which the automatic
setting bit is already high by changing the automatic setting bit from high to low to high.
The regulator-configuration algorithm adjusts the regulator outputs 250 mV below the
VIN level, but not higher than 5 V for VDD_RF , 3.5 V for VDD_A , and 3.4 V for
VDD_X. This ensures the highest possible supply voltage for the RF output stage while
maintaining an adequate PSRR (power supply rejection ratio). As an example, the user
can improve the PSRR if there is a noisy supply voltage from VDD_X by increasing the
target voltage difference across the VDD_X regulator as shown for automatic regulator
settings in Table 5-3 and Table 5-4.

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POWER MODES
The chip has seven power states, which are controlled by two input pins (EN and EN2)
and three bits in the chip status control register (00h).
The main reader enable input is EN (which has a threshold level of 1 V minimum). Any
input signal level from 1.8 V to VIN can be used. When EN is set high, all of the reader
regulators are enabled, together with the 13.56-MHz oscillator, while the SYS_CLK
(output clock for external micro controller) is made available.
The auxiliary-enable input EN2 has two functions. A direct connection from EN2 to VIN
ensures availability of the regulated supply (VDD_X) and an auxiliary clock signal (60
kHz) on the SYS_CLK output (same for the case EN = 0). This mode is intended for
systems in which the MCU controlling the reader is also being supplied by the reader
supply regulator (VDD_X) and the MCU clock is supplied by the SYS_CLK output of
the reader. This allows the MCU supply and clock to be available during power-down.
A second function of the EN2 input is to enable start-up of the reader system from
complete power down (EN = 0, EN2 = 0). In this case the EN input is being controlled
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by the MCU or other system device that is without supply voltage during complete
power down (thus unable to control the EN input). A rising edge applied to the EN2
input (which has a 1-V threshold level) starts the reader supply system and 13.56-MHz
oscillator (identical to condition EN = 1). This start-up mode lasts until all of the
regulators have settled and the 13.56-MHz oscillator has stabilized. If the EN input is set
high by the MCU (or other system device), the reader stays active. If the EN input is not
set high within 100 ms after the SYS_CLK output is switched from auxiliary clock (60
kHz) to high-frequency clock (derived from the crystal oscillator), the reader system
returns to complete power-down mode. This option can be used to wake the reader
system from complete power down by using a pushbutton switch or by sending a single
pulse.
During reader inactivity, the TRF7960/61 can be placed in power down-mode (EN = 0).
The power down can be complete (EN = 0, EN2 = 0) with no function running, or partial
(EN = 0, EN = 1) where the regulated supply (VDD_X) and auxiliary clock 60 kHz
(SYS_CLK) are available to the MCU or other system device.
When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1), the
supply regulators are activated and the 13.56-MHz oscillator started. When the supplies
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are settled and the oscillator frequency is stable, the SYS_CLK output is switched from
the auxiliary frequency of 60 kHz to the selected frequency derived from the crystal
oscillator. At this point, the reader is ready to communicate and perform the required
tasks. The control system (MCU) can then write appropriate bits to the chip status
control register (address 00) and select the operation mode.
The STANDBY mode (bit 7 = 1 of register 00) is the active mode with the lowest
current consumption. The reader is capable of recovering from this mode to full
operation in 100 ms.
The active mode with RF section disabled (bit 5 = 0 and bit 1 = 0 of register 00) is the
next active mode with low power consumption. The reader is capable of recovering from
this mode to full operation in 25 ms.
The active mode with only the RF receiver section active (bit 1 = 1 of register 00) can be
used to measure the external RF field (as described in RSSI measurements paragraph) if
reader-to-reader anticollision is implemented.
The active mode with the entire RF section active (bit 5 = 1 of register 00) is the normal
mode used for transmit and receive operations.
RECEIVER – ANALOG SECTION

The TRF7960/61 has two receiver inputs, RX1_IN1 (pin 8) and RX2_IN2 (pin 9). The
two inputs are connected to an external filter to ensure that AM modulation from the tag
is available on at least one of the two inputs. The external filter converts the PM-
modulated signal (if it appears) from the reader antenna to an AM-modulated signal.
This architecture eliminates any possible communication holes that may occur from the
tag to the reader. The two RX inputs are multiplexed to two receiver channels: the main
receiver and the auxiliary receiver. Receiver input multiplexing is controlled by control
bit B3 (pm-on) in the chip status control register (address 00). The main receiver is
composed of an RF-detection stage, gain, filtering with AGC, and a digitizing stage
whose output is connected to the digital processing block. The main receiver also has an
RSSI measuring stage, which measures the strength of the demodulated signal.
The primary function of the auxiliary receiver is to measure the RSSI of the modulation
signal. It also has similar RF-detection, gain, filtering with AGC, and RSSI blocks.

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The default setting is RX1_IN1 connected to the main receiver and RX2_IN2 connected
to the auxiliary receiver (bit pm_on = 0). When a response from the tag is detected by
the RSSI, values on both inputs are measured and stored in the RSSI level register
(address 0F). The control system reads the RSSI values and switches to the stronger
receiver input (RX1_IN1 or RX2_IN2 by setting pm_on = 1).
The receiver input stage is an RF level detector. The RF amplitude level on RX1_IN1
and RX2_IN2 inputs should be approximately 3 VPP for a VIN supply level greater than
3.3 V. If the VIN level is lower, the RF input peak-to-peak voltage level should not
exceed the VIN level. Note: VIN is the main supply voltage to the device at pin 2.
The first gain and filtering stage following the RF-envelope detector has a nominal gain
of 15 dB with an adjustable bandpass filter. The bandpass filter has adjustable 3-dB
frequency steps (100 kHz to 400 kHz for high pass and 600 kHz to 1500 kHz for low
pass). Following the bandpass filter is another gain-and-filtering stage with a nominal
gain of 8 dB and with frequency characteristics identical to the first stage.
The internal filters are configured automatically, with internal presets for each new
selection of a communication standard in the ISO control register (address 01). If
required, additional fine tuning can be accomplished by writing directly to the RX
special setting registers (address 0A).
The second receiver gain stage and digitizer stage are included in the AGC loop. The
AGC loop is activated by setting the bit B2 = 1 (agc-on) in the chip status control
register (address 00). When activated, the AGC continuously monitors the input signal
level. If the signal level is significantly higher than an internal threshold level, gain
reduction is activated. AGC activation is by default five times the internal threshold
level. It can be reduced to three times the internal level by setting bit B1 = 1 (agcr) in the
RX special setting register (address 0A). The AGC action is fast, typically finishing after
four subcarrier pulses. By default, the AGC action is blocked after the first few pulses of
the subcarrier signal. This prevents the AGC from interfering with the reception of the
remaining data packet. In certain situations, this type of blocking is not optimal, so it can
be removed by setting B0 = 1 (no_lim) in the RX special setting register (address 0A).
The bits of the RX special settings register (address 0A), which control the receiver
analog section.

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RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)

The RSSI measurement block measures the demodulated signal (except in the case of a
direct command for RF-amplitude measurement described in the Direct Commands
section). The measuring system latches the peak value, so the RSSI level can be read
after the end of the receive packet. The RSSI register values reset with every
transmission by the reader. This allows an updated RSSI measurement for each new tag
response.
Correlation between the RF input level and RSSI designation levels on the RX1_IN1 and
RX2_IN2 are shown in Table 5-6 and Table 5-7.
Table 5-6 shows the RSSI level versus RSSI bit value. The RSSI has seven levels (3 bits
each) with 4-dB increments. The input level is the peak-to-peak modulation level of the
RF signal as measured on one side envelope (positive or negative).
As an example, from Table 5-7, let B2 = 1, B1 = 1, B0 = 0; this yields an RSSI value of

6. From Table 5-6 a Bit value of 6 would yield an RSSI level of 20 mVpp.
RECEIVER – DIGITAL SECTION
The received subcarrier is digitized to form a digital representation of the modulated RF

envelope. This digitized signal is applied to digital decoders and framing circuits for
further processing.

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The digital part of the receiver consists of two sections, which partly overlap. The first
section is the bit decoders for the various protocols, whereas the second section consists
of framing logic. The bit decoders convert the subcarrier coded signal to a bit stream and
also to the data clock. Thus, the subcarrier-coded signal is transformed to serial data and
the data clock is extracted. The decoder logic is designed for maximum error tolerance.
This enables the decoders to successfully decode even partly corrupted (due to noise or
interference) subcarrier signals.
In the framing section, the serial bit-stream data is formatted in bytes. In this process,
special signals like the start of frame (SOF), end of frame (EOF), start of
communication, and end of communication are automatically removed. The parity bits
and CRC bytes are checked and also removed. The end result is clean or raw data, which
is sent to the 12-byte FIFO register where it can be read by the external microcontroller
system.
The start of the receive operation (successfully received SOF) sets the flags in the IRQ
and status register. The end of the receive operation is indicated to the external system
(MCU) by sending an interrupt request (pin 13 IRQ). If the receive data packet is longer
than 8 bytes, an interrupt is sent to the MCU when the received data occupies 75% of the
FIFO capacity to signal that the data should be removed from the FIFO.
Any error in data format, parity, or CRC is detected, and the external system is notified
of the error by an interrupt-request pulse. The source condition of the interrupt-request
pulse is available in the IRQ and status register (address 0C). The bit-coding description
of this register is given The main register controlling the digital part of the receiver is the
ISO control register (address 01). By writing to this register, the user selects the protocol
to be used. With each new write in this register, the default presets are loaded in all
related registers, so no further adjustments in other registers are needed for proper
operation.
Table 5-10 shows the coding of the ISO control register. Note that the TRF7961 does not
include the ISO14443 functionality; its features/commands in this area are non-
functional.
The framing section also supports the bit-collision detection as specified in ISO14443A.
When a bit collision is detected, an interrupt request is sent and flag set in the IRQ and
status register. The position of the bit collision is written in two registers. Register
collision position, with address 0E, and in register collision position and interrupt mask
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(address 0D), in which only the bits B7 and B6 are used for collision position. The
collision position is presented as a sequential bit number, where the count starts
immediately after the start bit. For example, the collision in the first bit of the UID
would give the value 00 0001 0000 in the collision-position registers. The count starts
with 0, and the first 16 bits are the command code and the NVB byte. Note: the NVB
byte is the number of valid bits.
The receive section also has two timers. The RX-wait-time timer is controlled by the
value in the RX wait time register (address 08). This timer defines the time after the end
of the transmit operation in which the receive decoders are not active (held in reset
state). This prevents incorrect detections resulting from transients following the transmit
operation. The value of the RX wait time register defines this time in increments of 9.44
ms. This register is preset at every write to ISO control register (address 01) according to
the minimum tag-response time defined by each standard.
The RX no-response timer is controlled by the RX no response wait time register

(address 07). This timer measures the time from the start of slot in the anti-collision
sequence until the start of tag response. If there is no tag response in the defined time, an
interrupt request is sent and a flag is set in IRQ status control register. This enables the
external controller to be relieved of the task of detecting empty slots. The wait time is
stored in the register in increments of 37.76 ms. This register is also preset,
automatically, for every new protocol selection.

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TRANSMITTER
The transmitter section consists of the 13.56-MHz oscillator, digital protocol processing,
and RF output stage.
TRANSMITTER – ANALOG
The 13.56-MHz crystal oscillator (connected to pins 31 and 32) directly generates the RF
frequency for the RF output stage. Additionally, it also generates the clock signal for the
digital section and clock signal displayed for the SYS_CLK (pin 27) which can be used
by an external MCU system.
During partial power-down mode (EN = 0, EN2 = 1), the frequency of SYS_CLK is 60
kHz. During normal reader operation, SYS_CLK can be programmed by bits B4 and B5
in the modulator and SYS_CLK control register (address 09); available clock
frequencies are 13.56 MHz, 6.78 MHz, or 3.39 MHz.
The reference crystal (HC49U) should have the following characteristics:
Parameter Specification
Frequency 13.560000 MHz
Mode of operation Fundamental
Type of resonance Parallel
Frequency tolerance ±20 ppm
Aging < 5 ppm/year
Operation temperature range –40°C to 85°C
Equivalent series resistance 50 W, minimum
The transmit power level is selectable between half power of 100 mW (20 dBm) or full
power of 200 mW (23 dBm) when configured for 5-V automatic operation. The transmit
output impedance is 8 W when configured for half power and 4 W when configured for
full power. Selection of the transmit power level is set by bit B4 (rf_pwr) in the chip
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status control register (Table 5-9). When configured for 3-V automatic operation, the
transmit power level is typically selectable between 33 mW (15 dBm) in half-power
mode and 70 mW (18 dBm) in full-power mode (Vdd_RF at 3.3 V). Note that lower
operating voltages result in reduced transmit power levels.
In normal operation, the transmit modulation is configured by the selected ISO control
register (address 01). External control of the transmit modulation is possible by setting
the ISO control register (address 01) to direct mode. While in direct mode, the transmit
modulation is made possible by selecting the modulation type ASK or OOK at pin 12.
External control of the modulation type is made possible only if enabled by setting B6 =
1 (en_ook_p) in the modulator and SYS_CLK control register (address 09). ASK
modulation depth is controlled by bits B0, B1 and B2 in the Modulator and SYS_CLK
Control register (address 09).
The range of the ASK modulation is 7%–30%, or 100% (OOK).
The coding of the modulator and SYS_CLK control register is shown in Table 5-19.
The length of the modulation pulse is defined by the protocol selected in the ISO control
register. With a high-Q antenna, the modulation pulse is typically prolonged, and the tag
detects a longer pulse than intended. For such cases, the modulation pulse length can be
corrected by using the TX pulse length register. If the register contains all zeros, then the
pulse length is governed by the protocol selection. If the register contains a value other
than 00h, the pulse length is equal to the value of the register in 73.7-ns increments. This
means the range of adjustment can be between 73.7 ns and 18.8 ms.
Transmitter – Digital
The digital portion of the transmitter is very similar to that of the receiver. Before
beginning data transmission, the FIFO should be cleared with a Reset command (0F).
Data transmission is initiated with a selected command (described in the Direct
Commands section, Table 5-29). The MCU then commands the reader to do a continuous
Write command (3Dh, see Table 5-31) starting from register 1Dh. Data written into
register 1Dh is the TX length byte1 (upper and middle nibbles), while the following byte
in register 1Eh is the TX length byte2 (lower nibble and broken byte length). The TX
byte length determines when the reader sends the EOF byte. After the TX length bytes,
FIFO data is loaded in register 1Fh with byte storage locations 0 to 11. Data transmission
begins automatically after the first byte is written into the FIFO. The TX length bytes
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and FIFO can be loaded with a continuous-write command because the addresses are
sequential. If the data length is longer than the allowable size of the FIFO, the external
system (MCU) is warned when the majority of data from the FIFO has already been
transmitted by sending an interrupt request with a flag in the IRQ register signaling FIFO
low/high status. The external system should respond by loading the next data packet into
the FIFO. At the end of the transmit operation, the external system is notified by another
interrupt request with a flag in the IRQ register that signals the end of TX.
The TX length register also supports incomplete bytes transmitted. The high two nibbles
in register 1D and the nibble composed of bits B4–B7 in register 1E store the number of
complete bytes to be transmitted.
Bit 0 (in register 1E) is a flag that signals the presence of additional bits to be transmitted
that do not form a complete byte. The number of bits are stored in bits B1–B3 of the
same register (1E).
The protocol is selected by the ISO control register (address 01), which also selects the
receiver protocol.
As defined by the selected protocol, the reader automatically adds all the special signals,
like start of communication, end of communication, SOF, EOF, parity bits, and CRC
bytes. The data is then coded to the modulation pulse level and sent to the modulation
control of the RF output stage. This means that the external system is only required to
load the FIFO with data, and all the low-level coding is done automatically. Also, all
registers used in transmission are automatically preset to the optimum value when a new
selection is entered into the ISO control register.
Some protocols have options; two registers are provided to select the TX-protocol
options. The first such register is ISO14443B TX options (address 02). It controls the
SOF and EOF selection and EGT (extra guard time) selection for the ISO14443B
protocol. The bit definitions of this register are given in Table 5-12.
The second register controls the ISO14443 high bit-rate options. This register enables the
use of different bit rates for RX and TX operations in the ISO14443 high bit-rate
protocol. Additionally, it also selects the parity system for the ISO14443A high bit-rate
selection. The bit definitions of this register are given in Table 5-13.
The transmit section also has a timer that can be used to start the transmit operation at a
precise time interval from a selected event. This is necessary if the tag requires a reply in
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an exact window of time following the tag response. The TX timer uses two registers
(addresses 04 and 05). In first register (address 04); two bits (B7 and B6) are used to
define the trigger conditions. The remaining 6 bits are the upper bits and the 8 bits in
register address 05 are lower bits, which are preset to the counter. The increment is 590
ns and the range of this counter is from 590 ns to 9.7 ms. The bit definitions (trigger
conditions) are shown in Table 5-14.
READER COMMUNICATION INTERFACE
The communication interface to the reader can be configured in two ways: a parallel 8-
pin interface and a Data_Clk or a serial peripheral interface (SPI).
These modes are mutually exclusive; only one mode can be used at a time in the
application.
When the SPI interface is selected, the unused I/O_2, I/O_1, and I/O_0 pins must be
hard-wired according to Table 5-30. At power up, the reader samples the status of these
three pins. If they are not the same (all High or all Low) it enters one of the possible SPI
modes.
The reader always behaves as the slave while the microcontroller (MCU) behaves as the
master device.
The MCU initiates all communications with the reader and is also used to communicate
with the higher levels (application layer). The reader has an IRQ pin to prompt the MCU
for attention if the reader detects a response from the proximity/vicinity integrated circuit
card (PICC/VICC). Communication is initialized by a start condition, which is expected
to be followed by an Address/Command word (Adr/Cmd).
The Adr/Cmd word is 8 bits long, and its format is shown

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The MSB (bit 7) determines if the word is to be used as a command or as an address. The
last twocolumns of Table 5-31 show the function of the separate bits if either address or
command is written. Data is expected once the address word is sent. In continuous-
address mode (Cont. mode = 1), the first data that follows the address is written (or read)
to (from) the given address. For each additional data, the address is incremented by one.
Continuous mode can be used to write to a block of control registers in a single stream
without changing the address; for example, setup of the predefined standard control
registers from the MCU’s non-volatile memory to the reader. In non-continuous address
mode (simple addressed mode), only one data word is expected after the address.
Address mode is used to write or read the configuration registers or the FIFO. When
writing more than 12 bytes to the FIFO, the continuous address mode should be set to 1.

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The command mode is used to enter a command resulting in reader action (initialize
transmission, enable reader, and turn reader On/Off...)
An example of expected communication between MCU and reader is shown below.
SERIAL INTERFACE COMMUNICATION
When an SPI interface is required, parallel I/O pins, I/O_2, I/O_1, and I/O_0, must be
hard wired according to Table 5-31. On power up, the reader looks for the status of these
pins; if they are not the same (not all high, or not all low), the reader enters into one of
two possible SPI modes.
The serial communications work in the same manner as the parallel communications
with respect to the FIFO, except for the following condition. On receiving an IRQ from
the reader, the MCU reads the reader's IRQ register to determine how to service the
reader. After this, the MCU must to do a dummy read to clear the reader's IRQ status
register. The dummy read is required in SPI mode because the reader's IRQ status
register needs an additional clock cycle to clear the register. This is not required in
parallel mode because the additional clock cycle is included in the Stop condition.
A procedure for a dummy read is as follows:
1. Starting the dummy read:
a. When using slave select (SS): set SS bit low.
b. When not using SS: start condition is when SCLK is high (See Table 5-30).
2. Send address word to IRQ status register (0Ch) with read and continuous address
mode bits set to 1 (See Table 5-31).
3. Read 1 byte (8 bits) from IRQ status register (0Ch).

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4. Dummy-read 1 byte from register 0Dh (collision position and interrupt mask).
5. Stopping the dummy read:
a. When using slave select (SS): set SS bit high.
b. When not using SS: stop condition when SCLK is high
SPI INTERFACE WITHOUT SS* (SLAVE SELECT) PIN

The serial interface without the slave select pin must use delimiters for the start and stop
conditions.
Between these delimiters, the address, data, and command words can be transferred. All
words must be 8 bits long with MSB transmitted first.
In this mode, a rising edge on data-in (I/O_7, pin 24) while SCLK is high resets the
serial interface and prepares it to receive data. Data-in can change only when SCLK is
low and is taken by the reader on the SCLK rising edge. Communication is terminated
by the stop condition when the data-in falling edge occurs during a high SCLK period.

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SPI INTERFACE WITH SS* (SLAVE SELECT) PIN

The serial interface is in reset while the SS* signal is high. Serial data-in (MOSI)
changes on the falling edge, and is validated in the reader on the rising edge, as shown in
Figure 5-9. Communication is terminated when the SS* signal goes high. All words must
be 8 bits long with the MSB transmitted first.

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The read command is sent out on the MOSI pin, MSB first, in the first eight clock cycles.
MOSI data changes on the falling edge, and is validated in the reader on the rising edge,
as shown in Figure 5-10.
During the write cycle, the serial data out (MISO) is not valid. After the last read
command bit (B0) is validated at the eighth rising edge of SCLK, after half a clock cycle,
valid data can be read on the MISO pin at the falling edge of SCLK. It takes eight clock
edges to read out the full byte (MSB first).

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Special steps are needed to read the TRF796x IRQ status register (register address 0x0C)
in SPI mode.
The status of the bits in this register is cleared after a dummy read. The following steps
must be followed when reading the “IRQ status register”.
1. Write in command 0x6C: read 'IRQ status' register in continuous mode (eight clocks).
2. Read out the data in register 0x0C (eight clocks).
3. Generate another eight clocks (as if reading the data in register 0x0D) but ignore the
MISO data line. This is shown in Figure 5-12.
Special Case – IRQ Status Register Read

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SPI INTERFACE WITH TRF7960 RFID READER IC
TRF7960 - SPI WITH SS* MODE ERRATA

It is important to note that there are some non-standard conditions when the TRF7960 is
operated in the SPI mode. These are listed below and are fixed by software patches to
work around them.
The serial interface is in reset while the SS* signal is high. Serial Data-In (MOSI)
changes on the falling edge, and are validated in the reader on the rising edge, as shown
in Figure 1. Communication is terminated when SS* signal goes inactive (high). All
words must be 8-bits long with the MSB transmitted first.

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SCLK POLARITY SWITCH

The SPI read operation is shown in Figure 2 below.
The read command is sent out on the MOSI pin, MSB first in the first 8 clock cycles.
MOSI data changes on the falling edge, and is validated in the reader on the rising edge,
as shown in Figure 2. During the write cycle the serial data out (MISO) is not valid.
After the last read command bit (B0) is validated at the 8th rising edge of SCLK, after
half a clock cycle, valid data can be read on the MISO pin at the falling edge of SCLK. It
takes 8 clock edges to read out the full byte (MSB first).

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The MOSI (serial data out) should not have any transitions (all high or all low) during
the read cycle. Also, the SS* should be low during the whole write and read operation.
The clock polarity switch is illustrated by the following pseudo code. This code refers
specifically to the MSP430 platform. Please refer to the datasheet of the relevant
microcontroller for your design.
IRQ STATUS REGISTER READ

Note: Special steps are needed when you read the TRF796x IRQ status register (register
address 0x0C) in SPI mode. The status of the bits in this register are cleared after a
“dummy read”.
The following steps need to be followed when reading the IRQ status register.
1. Write in command 0x6C: read 'IRQ status' register in continuous mode (8 clocks).
2. Read out the data in register 0x0C (8 clocks).
3. Generate another 8 clocks (as you were reading the data in register 0x0D) but ignore
the MISO data line.
This is shown in Figure 4.

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DIRECT COMMAND PROCESSING

The following are the direct commands supported by the TRF7960/61.
Of these the following are the direct commands that needs to have the software fix when
using SPI with SS* mode. These are the direct commands that are executed stand-alone
(direct commands with just one byte).
It is recommended to have this software fix written as part of a direct command function.
An example of a direct command is the slot markers (EOF) for ISO 15693. This will not
work in SPI mode. This is solved by a software fix by implementing the direct command
(for example transmit next slot” ) in one of two ways:
1. Have an additional SCLK cycle (low/high) before SS* goes high. or
2. Send a dummy TX write (8 SCLK cycles) before SS* goes high.
This is shown in the diagram below.

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INITIALIZATION OF DERIVATIVE REGISTERS

Some of the registers (RX wait time, RX no response wait time) do not take default
values when the Tag-it™ protocol is chosen in the ISO control register. This is solved by
manually programming the timing related registers in the Initialization routine as shown
in the pseudo code of the TIInventoryRequest function below.
It is also recommended that the modulator and system clock register (register 0x09) be
re-initialized when the inventory request (15693) or REQB (14443B) or REQA
(14443A) is issued.
TRANSMITTING ONE BYTE THROUGH THE FIFO

When transmitting one byte to the TRF7960 using SPI with SS* mode, a special
firmware fix is needed.
This method involves splitting the writes into two operations as shown in the pseudo
code below.
buf[0] = 0x8f;
buf[1] = 0x91;
buf[2] = 0x3d;
buf[3] = 0x00;
buf[4] = 0x10;
RAWwrite(&buf[0], 5);
buf[5] = 0x3F;
buf[6] = "one byte data to be transmitted";
buf[7] = 0x00;
RAWwrite(&buf[5], 3);
Each RAW Write function takes the SS low and high.

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ISO 15693 PROTOCOL
Procedure to Initiate Transmission (Send Inventory Request Command)
Note: The general procedure to start transmission is described below. This is applicable
to all commands that need to be transmitted to the tag. The data/command that is to be
transmitted is written in to the FIFO, a 12 byte buffer. Transmission starts when the first
data byte is written into FIFO. The reader adds SOF, EOF and CRC to the request packet
before transmitting.
1. Start condition
2. Send reset command 0x0F (command mode – 0x8F)
3. Send transmission command (0x90 - without CRC or 0x91 – with CRC)
4. Continuous write to register 0x1D (0x3D)
5. Data for register 0x1D (upper and middle nibble of the number of bytes to be
transmitted)
6. Data for register 0x1E (lower nibble of the number of bytes to be transmitted)
7. Data byte(s) for FIFO
8. Stop condition
The FIFO can be written to (and read from) in continuous mode only. For details on the
Start and Stop conditions, refer to the timing diagrams for SPI/Parallel mode. The
inventory request format (according to the ISO 15693-3 spec) is as follows:
As mentioned earlier, the SOF, CRC and EOF will be added automatically by the reader.
Only the flags, inventory command, mask length and value have to written to the FIFO
for transmission.
th
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Pseudo-code:
buf is an array that holds all the command/data bytes that are to be sent to the reader.
size is the number of bytes to be transmitted.
flags is the ISO15693 flag byte in the Inventory Request command format.
length is the mask length.
mask is the mask value.
buf[0] = 0x8f; /* Reset FIFO command */
buf[1] = 0x91; /* Send with CRC */
buf[2] = 0x3d; /* Write continuous from register 1D */
buf[3] = (char) (size >> 8); /* Data for register 1D */
buf[4] = (char) (size << 4); /* Data for register 1E */
buf[5] = 0x05; /* ISO15693 flag with 16 slots bit set*/
buf[6] = 0x01; /* ISO15693 anti collision command code */
buf[7] = length; /* Mask length */
If (length > 0)
{ xxxxxfor (i = 0; i < masksize; i++)
xxxxxbuf[i + 8] = *(mask + i); /* Mask value */ }
Write buf[0] to buf[i + 8] to TRF796x via SPI or Parallel mode (refer to the Parallel/SPI
timing diagrams in the TRF7960-61 data sheet,

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READ MULTIPLE BLOCKS

The physical memory of an ISO15693 VICC is organized in the form of blocks or pages
of fixed size. Up to 256 blocks can be addressed and a block size can be up to 32 bytes.
According the ISO15693-3 spec, the format for the read multiple blocks command is as
follows:

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Note: UID is optional. If the UID is not included, the command can be executed by any
VICC in the vicinity of the reader. While if UID field is included, only that VICC whose
UID matches the UID specified in the command will respond.
The Number of Blocks field is one less than the number of blocks that the VICC shall
return its response.
For more details on the Flags field, please refer to the ISO15693-3 spec.
Except for the SOF, CRC and EOF, all the command fields (2 to 7) have to be placed in
the FIFO for transmission.
PSEUDO-CODE (FOR READ MULTIPLE BLOCKS

COMMAND WITH NO UID):
In this case, size = 4 (flags + command code + first block number + number of blocks)
flags is the ISO15693 flags byte.
buf[5] = 0x00; /* ISO15693 flag with option flag not set*/
buf[6] = 0x23; /* Read multiple blocks command code */
buf[7] = First block number

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buf[8] = Number of blocks
1. Write buf[0] to buf[8] to TRF796x in a continuous write mode via SPI or Parallel
mode (refer to the Parallel/SPI timing diagrams in the TRF7960-61 data sheet,
SLOU186).
2. Wait for a End of TX interrupt (use a timer for timeout).
3. Wait for next interrupt (use a timer for timeout). This can be due to any of the
following:
a. End of RX
b. Collision
Check the IRQ status register to determine the cause of the interrupt (for more details,
refer to Section 2 on interrupts).
If interrupt is due to End of RX, this means that the response is received in the FIFO
without any error/collision. Read the FIFO to obtain the block data.
If interrupt is due to collision, the user can choose what to do next – try again (repeat
from step 1) or ignore.
PSEUDO-CODE (FOR READ MULTIPLE BLOCKS

COMMAND WITH UID):
In this case, size = 12 (flags + command code + UID + first block number + number of
blocks)

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buf[7] to buf[14] contains UID
According to the ISO 15693 protocol, a multiple-byte field (here, the UID field) is
transmitted least significant byte first. For example, consider a tag with UID =
E0007000006D6AC1C, then:
buf[7] = 1C;
buf[8] = AC;
buf[9] = D6;
buf[10] = 06;
buf[11] = 00;
buf[12] = 00;
buf[13] = 07;
buf[15] = E0;
1. Write buf[0] to buf[16] to TRF796x in a continuous write mode via SPI or Parallel
mode (Refer to the Parallel/SPI timing diagrams in the TRF7960-61 data sheet,
SLOU186).
2. Wait for a End of TX interrupt (yse a timer for timeout).
following:
a. End of RX
b. Collision
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without any error/collision. Read the FIFO to obtain the data received from the tag.
Check for the Error_flag in the
Flags field. If set, the error code gives information about the type of error that occurred.
Otherwise, data has been received without any error.
If interrupt is due to collision, the user can choose how to act – try again (repeat from
step 1) or ignore.
WRITE MULTIPLE BLOCKS

Note: Most tags do not support the write multiple blocks command. Hence the user
should know beforehand if the tag supports this command. If not, the ‘write single block
command can be used multiple times to write to many blocks.
The procedure to write multiple blocks is described below.
The write multiple blocks request format is as shown:
Note: UID is optional. If the UID is not included, the command can be executed by any
VICC in the vicinity of the reader. While if UID field is included, only that VICC whose
UID matches the
UID specified in the command will respond.
The Number of Blocks field is one less than the number of blocks that the VICC shall
return its response.
For more details on the Flags field, please refer to the ISO15693-3 spec.

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Except for the SOF, CRC and EOF, all the command fields (2 to 7) have to be placed in
the FIFO for transmission.
Pseudo-code (for write multiple blocks command with no UID):
datalength is the number of the data bytes to be written to the tag.
buf[9] to buf[8 + datalength] = Data
1. Write buf[0] to buf[8 + datalength] to TRF796x via SPI or Parallel mode (Refer to the
Parallel/SPI timing diagrams in the TRF7960-61 data sheet, SLOU186).
The FIFO buffer in the TRF796x is only 12 bytes long. Hence if the total number of
bytes to be transmitted is greater than 12, then:
1. Transmit the first 12 bytes.
2. Wait for TX active and 3 bytes left in FIFO interrupt (refer to Section 2 on interrupts
for more details).
3. Transmit next 9 bytes or less.

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Repeat from step 2 until all the bytes have been transmitted.
To transmit first 12 bytes:
buf[3] = (char) (total number of bytes to be TX >> 8); /* Data for register 1D */
buf[4] = (char) (total number of bytes to be TX << 4); /* Data for register 1E */
buf[9] to buf[16] = Data
Write buf[0] to buf[16] to TRF796x via SPI or Parallel mode.
To transmit next 9 bytes:
buf[0] = 0x3F; /* Continuous write to FIFO 0x1F */
buf[1] to buf[9] = Data; /* 9 data bytes for transmission */
1. Write buf[0] to buf[9] to TRF796x via SPI or Parallel mode.
2. Wait for a End of TX interrupt (use a timer for timeout).
3. If the Option_flag (in the Flags field in the request packet) is set, the VICC waits for
the reception of an
EOF and upon such reception shall return its response.
a. Send reset command (0x0F) to FIFO (command byte - 0x8F)
b. Send transmit next slot (EOF) command (0x14) (command byte – 0x94)
If the Option_flag is not set, proceed to step 4.

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following:
a. End of RX
b. Collision
without any error/collision. Read the FIFO to obtain the data received from the tag.
Check for the Error_flag bit in the Flags field of the response. The VICC reports the
success of the operation in this bit.
If interrupt is due to collision, the user can choose what to do next – try again (repeat
from step 1) or ignore.
PSEUDO-CODE (FOR WRITE MULTIPLE BLOCKS

COMMAND WITH UID):
The procedure to write multiple blocks with UID is the similar to that of write multiple
blocks except that the 8 bytes of the UID is sent along with the request packet. Please
note that the UID being a multiple-byte field, has to be sent with its least significant byte
first. Please refer to Section 1.5 on Pseudo-code for read multiple blocks command with
UID for details.
INTERRUPT HANDLER ROUTINE

The reader which is a slave device has an IRQ pin to prompt/flag the MCU for attention
in cases when the reader detects a response from the PICC/VICC. The interrupt handler
routine described below determines how the IRQ should be handled.
The TRF796x IRQ status register (Table 2) is read to determine the cause of the IRQ.
The following conditions (Table 1) are checked and appropriate actions taken:

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ALL CIRCUTI DIAGRAMS
UNIVERSAL CPU MOTHERBOARD

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NXP 9C669 ΜCONTROLLER

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POWER SUPPLY

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MAX232 INTERFACING

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KEYBOARD & LATCH INTERFACING

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READER IC INTERFACING

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READER CIRCUTI PCB & COMPONENT LAYOUT

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SOFTWARE
INTRODUCTION TO KEIL SOFTWARE
Keil Micro Vision is an integrated development environment used to create software to

be run on embedded systems (like a microcontroller). It allows for such software to be
written either in assembly or C programming languages and for that software to be
simulated on a computer before being loaded onto the microcontroller.
WHAT IS ΜVISION3?
µVision3 is an IDE (Integrated Development Environment) that helps write, compile,

and debug embedded programs. It encapsulates the following components:
A project manager.
A make facility.
Tool configuration.
Editor.
A powerful debugger.
STEPS FOLLOWED IN CREATING AN APPLICATION

IN ΜVISION3:
To create a new project in uVision3:
Select Project - New Project.
Select a directory and enter the name of the project file.
Select Project –Select Device and select a device from Device Database.
Create source files to add to the project

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Select Project - Targets, Groups, and Files. Add/Files, select Source Group1, and add the
source files to the project.
Select Project - Options and set the tool options. Note that when the target device is
selected from the Device Database™ all-special options are set automatically. Default
memory model settings are optimal for most applications.
Select Project - Rebuild all target files or Build target
To create a new project, simply start Micro Vision and select “Project”=>”New
Project” from the pull–down menus. In the file dialog that appears, choose a name and
base directory for the project. It is recommended that a new directory be created for each
project, as several files will be generated. Once the project has been named, the dialog
shown in the figure below will appear, prompting the user to select a target device. In
this lab, the chip being used is the “AT89S52,” which is listed under the heading “Atmel
Window for choosing the Target Device
Next, Micro Vision must be instructed to generate a HEX file upon program
compilation. A HEX file is a standard file format for storing executable code that is to be
loaded onto the microcontroller. In the “Project Workspace” pane at the left, right–click
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on “Target 1” and select “Options for ‘Target 1’ ”.Under the “Output” tab of the
resulting options dialog, ensure that both the “Create Executable” and “Create HEX
File” options are checked. Then click “OK” as shown in the two figures below.
Project Workspace Pane Project Options Dialog
Next, a file must be added to the project that will contain the project code. To do this,
expand the “Target 1” heading, right–click on the “Source Group 1” folder, and select
“Add files…” Create a new blank file (the file name should end in “.asm”), select it, and
click “Add.” The new file should now appear in the “Project Workspace” pane under the
“Source Group 1” folder. Double-click on the newly created file to open it in the editor.
All code for this lab will go in this file. To compile the program, first save all source
files by clicking on the “Save All” button, and then click on the “Rebuild All Target
Files” to compile the program as shown in the figure below. If any errors or warnings
occur during compilation, they will be displayed in the output window at the bottom of
the screen. All errors and warnings will reference the line and column number in
which they occur along with a description of the problem so that they can be easily
located. Note that only errors indicate that the compilation failed, warnings do not
(though it is generally a good idea to look into them anyway).

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“Save All” and “Build All Target Files” Buttons
When the program has been successfully compiled, it can be simulated using the
integrated debugger in Keil Micro Vision. To start the debugger, select
“Debug”=>”Start/Stop Debug Session” from the pull–down menus.
At the left side of the debugger window, a table is displayed containing several key
parameters about the simulated microcontroller, most notably the elapsed time (circled in
the figure below). Just above that, there are several buttons that control code execution.
The “Run” button will cause the program to run continuously until a breakpoint is
reached, whereas the “Step Into” button will execute the next line of code and then pause
(the current position in the program is indicated by a yellow arrow to the left of the
code).

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µVision3 Debugger window
Breakpoints can be set by double–clicking on the grey bar on the left edge of the window
containing the program code. A breakpoint is indicated by a red box next to the line of
code.

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‘Reset’, ‘Run’ and ‘Step into’ options
The current state of the pins on each I/O port on the simulated microcontroller can also
be displayed. To view the state of a port, select “Peripherals”=>”I/O Ports”=>”Port n”
from the pull–down menus, where n is the port number. A checked box in the port
window indicates a high (1) pin, and an empty box indicates a low (0) pin. Both the I/O
port data and the data at the left side of the screen are updated whenever the program is
paused.
The debugger will help eliminate many programming errors, however the simulation is
not perfect and code that executes properly in simulation may not always work on the
actual microcontroller.

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DEVICE DATABASE
A unique feature of the Keil µVision3 IDE is the Device Database, which contains
information about more than 400 supported microcontrollers. When you create a new
µVision3 project and select the target chip from the database, µVision3 sets all
assembler, compiler, linker, and debugger options for you. The only option you must
configure is the memory map.
PERIPHERAL SIMULATION
The µVision3 Debugger provides complete simulation for the CPU and on-chip
peripherals of most embedded devices. To discover which peripherals of a device are
supported, in µVision3 select the Simulated Peripherals item from the Help menu. You
may also use the web-based Device Database. We are constantly adding new devices
and simulation support for on-chip peripherals so be sure to check Device Database
often.
PROGRAMMER
The programmer used is a powerful programmer for the Atmel 89 series of

microcontrollers that includes 89C51/52/55, 89S51/52/55 and many more.
It is simple to use & low cost, yet powerful flash microcontroller programmer for the
Atmel 89 series. It will Program, Read and Verify Code Data, Write Lock Bits, Erase
and Blank Check. All fuse and lock bits are programmable. This programmer has
intelligent onboard firmware and connects to the serial port. It can be used with any type
of computer and requires no special hardware. All that is needed is a serial
communication port which all computers have.
All devices also have a number of lock bits to provide various levels of software and
programming protection. These lock bits are fully programmable using this programmer.
Lock bits are useful to protect the program to be read back from microcontroller
only allowing erase to reprogram the microcontroller.
Major parts of this programmer are Serial Port, Power Supply and Firmware
microcontroller. Serial data is sent and received from 9 pin connector and converted

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to/from TTL logic/RS232 signal levels by MAX232 chip. A Male to Female serial port
cable, connects to the 9 pin connector of hardware and another side connects to back of
computer.
All the programming ‘intelligence’ is built into the programmer so you do not need any
special hardware to run it. Programmer comes with window based software for easy
programming of the devices.
PROLOAD PROGRAMMING SOFTWARE
‘Proload’ is a software working as a user friendly interface for programmer boards from
Sunrom Technologies. Proload gets its name from “Program Loader” term, because that
is what it is supposed to do. It takes in compiled HEX file and loads it to the hardware.
Any compiler can be used with it, Assembly or C, as all of them generate compiled HEX
files. Proload accepts the Intel HEX format file generated from compiler to be sent to
target microcontroller. It auto detects the hardware connected to the serial port. It also
auto detects the chip inserted and bytes used. The software is developed in Delphi and
requires no overhead of any external DLL.
The programmer connects to the computer’s serial port (Comm 1, 2, 3 or 4) with a

standard DB9 Male to DB9 Female cable. Baud Rate - 57600, COMx Automatically
selected by window software. No PC Card Required. After making the necessary
selections, the ‘Auto Program’ button is clicked as shown in the figure below which
burns the selected hex file onto the microcontroller.

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Programming window

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ADVANTAGES & DISADVANTAGES
ADVANTAGE OF RFID:
Inventory efficiency - Because line-of-sight is not required to read RFID tags, inventory
can be performed in a highly efficient method. For example, pallets in a warehouse can
be read, inventoried, and their location can be determined no matter where the tag is
placed on the pallet. This is because the radio waves from the reader are strong enough
for the tag to respond regardless of location.
Return on investment (ROI) - Though the cost may be high at first, the total cost of
ownership should go down over the years and provide a good ROI, if the implementation
provides a significant method to improve business processes.
Vulnerability to damage minimized - Barcodes can be damaged in many ways.

Although, 2D barcode types such as Data Matrix can be read even when up to 40% of
the barcode is damaged.
DISADVANTAGE OF RFID:
Dead areas and orientation problems - RFID works similar to the way a cell phone or
wireless network does. Like these technologies, there may be certain areas that have
weaker signals or interference. In addition, poor read rates are sometimes a problem
when the tag is rotated into an orientation that does not align well with the reader. These
issues are usually minimized by proper implementation of multiple readers and use of
tags with multiple axis antennas.
Security concerns - Because RFID is not a line-of-sight technology like barcoding, new
security issues could develop. For example, a competitor could set up a high-gain
directional antenna to scan tags in trucks going to a warehouse. From the data received,
this competitor could determine flow rates of various products. Additionally, when RFID

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is used for high-security operations such as payment methods, fraud is always a

possibility.
Ghost tags - In rare cases, if multiple tags are read at the same time the reader will
sometimes read a tag that does not exist. Therefore, some type of read verification, such
as a CRC, should be implemented in either the tag, the reader or the data read from the
tag.
Proximity issues - RFID tags cannot be read well when placed on metal or liquid objects
or when these objects are between the reader and the tag. Nearly any object that is
between the reader and the tag reduces the distance the tag can be read from.
High cost - Because this technology is still new, the components and tags are expensive
compared to barcodes. In addition, software and support personnel needed to install and
operate the RFID reading systems (in a warehouse for example) may be more costly to
employ.
Unread tags - When reading multiple tags at the same time, it is possible that some tags
will not be read and there is no sure method of determining this when the objects are not
in sight. This problem does not occur with barcodes, because when the barcode is
scanned, it is instantly verified when read by a beep from the scanner and the data can
then be entered manually if it does not scan.
Vulnerable to damage - Water, static discharge or high-powered magnetic surges (such

as lightning strike) may damage the tags.
ADVANTAGES OF USING UHF GEN 2 RFID TAGS:
UHF GEN 2 tags greatly reduce (if not eliminate) the ghost tag problem, using a
mandatory hardware based CRC. The CRC is created when the tag is encoded, and the
reader verifies the CRC when the tag is read. If the CRC does not match, the data read is
considered invalid. In addition, more tags can be read simultaneously when using GEN2.
Encoding and Writing RFID Tags one of the readermodule is Sonmicro SM130
read/write module(28 pin IC). The SM130 has a TTL serial interface that you can
connect to a micocontroller, or to a personal computer through a USB-to-serial interface.

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CONCLUSION
The PIC MCU is well-suited to X-10 applications. With its plethora of on-chip
peripherals and a few external components, a PIC MCU can be used to implement an
X-10 system that can transmit and receive messages over the AC power line wiring. The
small code size of the X-10 library leaves ample space for the user to create application
specific code. PIC MCUs, such as the PIC16F877A, have plenty of additional resources
for creating more complex X-10 applications, while smaller PIC MCUs can be selected
for economical use in simpler X-10 applications.
TROUBLE SHOOTING
In case of a system hang-up condition, the reset button in the vicinity of the
Microcontroller can be used to revive the system.

Gandhinagar
SEM

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RFID BASED ATTENDENCE SYSTEM

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

ISO 15693 PROTOCOL..........................................................................................................................................72

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

RFID (Radio Frequency Identification)

Radio-frequency identification (RFID) is the use of an object (typically referred to as an

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

HISTORY & TECHNOLOGY BACKGROUNG

Similar technology, such as the IFF

An early demonstration of reflected power (modulated backscatter) RFID tags, both

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

tags needed to be disposable (a manufacturer putting tags on products shipped to a

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

o 18000–1: Generic parameters for air interfaces for globally accepted

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

RFID HAS MAINLY TWO PARTS:

Semi-Passive: Costly compared to passive,cheaper compared to active,used for

The orientation issue in rfid is normally addressed by providing circularity polarized

Linearly polarized antenna is used when maximum distance is to be covered reader/tag is

The Business Process Integration Domain is a means to connect between enterprise

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

The Systems Management Domain allows customers to remotely monitor, configure,

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

Potential alternatives to the radio frequencies (0.125–0.1342, 0.140–0.1485, 13.56, and

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

DEVICE/ADDRESSES (A1): The A1 pin is a device address input that can be

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

START CONDITION: A high-to-low transition of SDA with SCL high is a start

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop

STANDBY MODE: The AT24C1024 features a low-power standby mode which is

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

PAGE WRITE: The 1024K EEPROM is capable of 256-byte page writes.

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

CLOCK AND CALENDAR

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

2-WIRE SERIAL DATA BUS

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

NXP P89C669 MICROCONTROLLER

23-bit program memory space and 23-bit data memory space

Program counter expanded to 23 bits

Up to 24 MHz CPU clock with 6 clock cycles per machine cycle

96 kbytes of on-chip program Flash

2 kbytes of on-chip data RAM

Programmable Counter Array (PCA)

Two full-duplex enhanced UARTs

Byte based Fast I2C serial interface (400 kbits/s)

MANI PRINCE SUBROTO SWAPAN KUMAR (06EC019)

Enhances performance and efficiency for C programs

Fully 80C51-compatible microcontroller

Provides seamless and compelling upgrade path from classic 80C51

Preserves 80C51 code base, investment/knowledge, and peripherals and ASICs

Supported by wide range of 80C51 development systems and programming tools

Up to 24 MHz CPU clock with 6 clock cycles per machine cycle

96 kbytes of on-chip Flash with In-System Programming (ISP) and In-Application

PROGRAMMING (IAP) CAPABILITY

23-bit program memory space and 23-bit data memory space

Four-level interrupt priority