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S= A.X2 + B.X + C
A parte operativa tem carater acumulativo,
ou seja, multiplica ou soma e acumula no
Entrada X
registrador da saida do operador lógico.
LX
clk
Modificamos a equação
A B C
00 01 10 11 0 1
M1 M2
S= X (A.X + B) + C
Multiplicador
H=0 soma
H=1 multiplica Somador
Start=1
S= X (A.X + B) + C IDLE
Entrada X
LX S0 S1 S2
clk
S4 S3
LS
S5
clk
LX=0 LX=0
LX=0 M1=00
S M1=X M1=11
M2=1 M2=1
M2=X H=1
H=X H=0
LS=1 LS=1
LS=0 P=0
P=1 P=0
Start=1
S= X (A.X + B) + C IDLE
Entrada X
RESET
LX
0 S0 S1 S2
clk
S4 S3
LS 0 S5
clk
LX=0 LX=0
LX=0 M1=00
S M1=X M1=11
M2=1 M2=1
M2=X H=1
H=X H=0
LS=1 LS=1
LS=0 P=0
P=1 P=0
Start=1
S= X (A.X + B) + C
Entrada X
LX valor S0 S1 S2
clk
S4 S3
LS
S5
clk
LX=0 LX=0
LX=0 M1=00
S M1=X M1=11
M2=1 M2=1
M2=X H=1
H=X H=0
LS=1 LS=1
LS=0 P=0
P=1 P=0
Start=1
S= X (A.X + B) + C
Entrada X
LX valor S0 S1 S2
clk
S4 S3
LS
S5
clk A.valor
LX=0 LX=0
LX=0 M1=00
S M1=X M1=11
M2=1 M2=1
M2=X H=1
H=X H=0
LS=1 LS=1
LS=0 P=0
P=1 P=0
Start=1
S= X (A.X + B) + C
Entrada X
LX valor S0 S1 S2
clk
S4 S3
LS
S5
clk A.valor+B
LX=0 LX=0
LX=0 M1=00
S M1=X M1=11
M2=1 M2=1
M2=X H=1
H=X H=0
LS=1 LS=1
LS=0 P=0
P=1 P=0
Start=1
S= X (A.X + B) + C
Entrada X
LX valor S0 S1 S2
clk
S4 S3
LS
S5
clk (A.valor+B).X
LX=0 LX=0
LX=0 M1=00
S M1=X M1=11
M2=1 M2=1
M2=X H=1
H=X H=0
LS=1 LS=1
LS=0 P=0
P=1 P=0
Start=1
S= X (A.X + B) + C
Entrada X
LX valor S0 S1 S2
clk
S4 S3
LS
S5
clk (A.valor+B).X+C
LX=0 LX=0
LX=0 M1=00
S M1=X M1=11
M2=1 M2=1
M2=X H=1
H=X H=0
LS=1 LS=1
LS=0 P=0
P=1 P=0
Start=1
S= X (A.X + B) + C
Entrada X
LX valor S0 S1 S2
clk
S4 S3
LS
S5
clk (A.valor+B).X+C
LX=0 LX=0
LX=0 M1=00
S M1=X M1=11
M2=1 M2=1
M2=X H=1
H=X H=0
P=1 (FIM) LS=0 LS=1 LS=1
P=0 P=0
P=1
Start=1
architecture Behavioral of pc_funcao1 is
type tstate is (idle, S0, S1, S2, S3, S4, S5);
IDLE
signal estado, prox_estado : tstate;
begin
process(reset, clk)
begin S0 S1 S2
if (reset='1') then
estado <= idle;
elsif (clk'event and clk='1') then LX=1 LX=0 LX=0
estado <= prox_estado; M1=X M1=01 M1=10
end if; M2=1
end process; M2=X M2=0
process(estado, start) H=X H=1 H=0
begin LS=X LS=1 LS=1
CASE estado IS P=0
WHEN idle => if start='1' then prox_estado <= S0; else prox_estado <= idle; end if; P=0 P=0
LX<= 'X'; M1<="XX"; M2 <= 'X'; H <= 'X'; LS <= 'X'; P<='0';
WHEN S0 => prox_estado <= S1;
LX<= '1'; M1<="XX"; M2 <= 'X'; H <= 'X'; LS <= 'X'; P<='0';
WHEN S1 => prox_estado <= S2;
S5 S4 S3
LX<= '0'; M1<="01"; M2 <= '0'; H <= '1'; LS <= '1'; P<='0';
WHEN S2 => prox_estado <= S3;
LX<= '0'; M1<="10"; M2 <= '1'; H <= '0'; LS <= '1'; P<='0';
LX=0 LX=0
WHEN S3 => prox_estado <= S4; LX=0
M1=11 M1=00
LX<= '0'; M1<="00"; M2 <= '1'; H <= '1'; LS <= '1'; P<='0'; M1=X
WHEN S4 => prox_estado <= S5; M2=1 M2=1
M2=X
LX<= '0'; M1<="11"; M2 <= '1'; H <= '0'; LS <= '1'; P<='0';
H=0 H=1
WHEN S5 => prox_estado <= idle; H=X
LS=1 LS=1
LX<= '0'; M1<="XX"; M2 <= 'X'; H <= 'X'; LS <= '0'; P<='1'; LS=0
WHEN others => prox_estado <= idle; P=0 P=0
LX<= '0'; M1<="XX"; M2 <= 'X'; H <= 'X'; LS <= '0'; P<='0';
P=1
END CASE;
end process;
Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
process(A_16, B_16, C_16, regx, M1)
entity PO_funcao1 is begin
Port ( reset : in STD_LOGIC; CASE M1 IS Aula
VHDL clk : in STD_LOGIC;
LX : in STD_LOGIC;
WHEN "00" => mux1 <= regx;
WHEN "01" => mux1 <= A_16;
M1 : in STD_LOGIC_VECTOR(1 downto 0);
M2 : in STD_LOGIC;
WHEN "10" => mux1 <= B_16;
WHEN others => mux1 <= C_16;
9
RTL LS : in STD_LOGIC;
H : in STD_LOGIC;
END CASE;
end process;
dado : in STD_LOGIC_VECTOR (7 downto 0);
A : in STD_LOGIC_VECTOR (7 downto 0); process(regx, regs, M2)
B : in STD_LOGIC_VECTOR (7 downto 0); begin
C : in STD_LOGIC_VECTOR (7 downto 0); if M2 = '1' then mux2 <= regs;
Saida_funcao : out STD_LOGIC_VECTOR (15 downto 0)); else mux2 <= regx;
end PO_funcao1; end if;
end process;
um multiplicador
multiplexador e de
Atraso = atraso de
process(clk, reset) M1 00 01 10 11 0 1 M2
begin
if reset='1' then
regs <= "0000000000000000";
elsif (clk'event and clk='1') then
if LS ='1' then regs <= ula; Multiplicador
H=0 soma
else regs <= regs; Somador
H=1 multiplica
end if; end if;
end process;
process(mux1, mux2, H)
begin LS
if H='0' then ula <= mux1 + mux2;
else ula <= mux1 * mux2; Implementação SERIAL clk
end if;
end process;
Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt S
Aula
Parte Operativa
9
XC2v80 (VirtexII)
Alocação de recursos:
Processamento serial
Somador/subtrator
Multiplicador
Codificação One-hot
7 flip-flops para 7 estados
S= A.X2 + B.X + C
A X C
X B
A X B
C
+
X +
dois somadores
X
um somador
2 multiplicadores
+ 2 somadores
3 multiplicadores +
2 somadores
S S
Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
entity funcao1_comb is
Port ( dado : in STD_LOGIC_VECTOR(7 downto 0);
clk : in STD_LOGIC; Aula
reset : in STD_LOGIC;
start : in STD_LOGIC; VHDL
a : in STD_LOGIC_VECTOR(7 downto 0);
b : in STD_LOGIC_VECTOR(7 downto 0);
9
c : in STD_LOGIC_VECTOR(7 downto 0);
saida_funcao : out STD_LOGIC_VECTOR(15 downto 0));
end funcao1_comb;
S= X.(A.X + B) + C
• Paralelismo máximo
architecture Behavioral of funcao1_comb is
signal dado_16, A_16, B_16, C_16, regx, regs : std_logic_vector(15 downto 0);
begin
A X C
saida_funcao <= regs;
X B
A_16 <= "00000000"&A;
B_16 <= "00000000"&B;
process(clk, reset)
begin
X
if reset='1' then
regx <= "0000000000000000";
elsif (clk'event and clk='1') then
if start ='1' then
regx <= dado_16;
else regx<=regx;
end if; end if; +
end process;
dois somadores
process(clk, reset)
begin
if reset='1' then
X
regs <= "0000000000000000";
elsif (clk'event and clk='1') then 2 multiplicadores
if start='0' then
regs <= (((A_16 * regx) + B_16)* regx ) + C_16; 2 somadores
else
regs <= regs; +
end if;
end if;
end process;
end Behavioral;
S
Disciplina: Sistemas Digitais – Profa. Dra. Fernanda Gusmão de Lima Kastensmidt
Aula
Descrição em VHDL: Exemplo 1
9
RTL – versão 2
entity funcao1_altonivel is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC; process(reset, clk)
start : in std_logic; begin
dado : in STD_LOGIC_VECTOR(7 downto 0); if (reset='1' or start='1') then
A, B, C : in STD_LOGIC_VECTOR(7 downto 0); cont <= "00";
saida_funcao : out STD_LOGIC_VECTOR(15 downto 0)); elsif clk'event and clk='1' then
end funcao1_altonivel; if start='0' then
cont <= cont +1;
architecture Behavioral of funcao1_altonivel is end if;
end if;
signal dado_16, A_16, B_16, C_16, regx, regs : std_logic_vector(15 downto 0); end process;
signal cont : std_logic_vector(1 downto 0);
begin process(clk, reset)
begin
if reset='1' then
saida_funcao <= regs; regs <= "0000000000000000";
A_16 <= "00000000"&A; elsif (clk'event and clk='1') then
B_16 <= "00000000"&B; if start='0' then
C_16 <= "00000000"&C; CASE CONT IS
dado_16 <= "00000000"&dado; WHEN "01" => regs <= A_16 * regx;
WHEN "10" => regs <= regs + B_16;
process(clk, reset) WHEN "11" => regs <= regs * regx;
begin WHEN others => regs <= regs + C_16;
if reset='1' then END CASE;
regx <= "0000000000000000"; else
elsif (clk'event and clk='1') then regs <= regs;
if start ='1' then end if;
regx <= dado_16; end if;
else end process;
regx<=regx;
end if; end Behavioral;
end if;
end process;
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