Embedded System Note by

Md. Hassanul Karim Roni

Features
8051 8254 8255

Features: Features: Features:

1. 8-bit CPU 1. It includes three 16-bit counter 1. Intel 8255A is a general purpose
2. 4KB of internal program that can work independently in parallel I/O interface.
memory (ROM) 6 different modes. 2. The peripheral devices are
3. 128 bytes of internal data 2. It is packaged in a 24 DIP with slower than the microprocessor.
memory (RAM) 5V power supply PPI makes an inter-relation
4. 32 bi-directional IO lines 3. It can count either in between microprocessor and
5. 64 KB of external program binary/BCD peripheral devices.
memory address space 4. Its counter can operate at a 3. It provides three I/O port (Port
6. 64 KB of external data memory maximum frequency of 10 MHz. A, Port B and Port C)
address space
7. Two 16-bit timer/ counter
8. 8-bit program status word
(PSW)
9. 8-bit stack pointer
10. 4 register bank with 8 register in
each bank

8237

1. A DMA controller interfaces with several peripherals that may request

DMA.
2. The controller decides the priority of simultaneous DMA requests
communicates with the peripheral and the CPU, and provides memory
addresses for data transfer.
3. DMA controller commonly used with 8086 is the 8237- programmable
device.
4. The 8237 is in fact a special-purpose microprocessor. Normally it appears
as part of the system controller chip-sets.
5. The 8237 is a 4-channel device. Each channel is dedicated to a specific
peripheral device and capable of addressing 64 K bytes section of
memory.

Block diagrams:
1. 8051

Micro-controller: A small computer usually implemented on a

single IC that contains a central processing unit (CPU),
some memory, and peripheral devices such as
counter/timers, analog-to-digital converters, serial
communication hardware, etc.

8254
 Embedded System Note by
Md. Hassanul Karim Roni
❖The Intel 8254 is a counter/timer device designed to solve the common timing control problems in microcomputer system design.

❖It provides three independent 16-bit counters, each capable of handling clock inputs up to 10 MHz.

❖ All modes are software programmable.

❖The 8254 is a superset of the 8253

8254 Read and write operation

8255A Programmable Peripheral

Interface (PPI)

❖ Intel 8255A is a general purpose

parallel I/O interface.

❖ The peripheral devices are slower than

the microprocessor. PPI makes an inter-
relation between microprocessor and
peripheral devices.

❖ It provides three I/O port (Port A, Port

B and Port C)

8237 Direct Memory Access Controller:

 Embedded System Note by
Md. Hassanul Karim Roni
DMA is for high-speed data transfer from/to mass storage peripherals, e.g. harddisk drive, magnetic tape, CD-ROM, and sometimes video
controllers.

For example, a hard disk may boasts a transfer rate of 5 M bytes per second, i.e. 1 byte transmission every 200 ns. To make such data
transfer via the CPU is both undesirable and unnecessary.

The basic idea of DMA is to transfer blocks of data directly between memory and peripherals. The data don’t go through

the microprocessor but the data bus is occupied.

“Normal” transfer of one data byte takes up to 29 clock cycles. The DMA transfer requires only 5 clock cycles. Nowadays, DMA can transfer
data as fast as 60 M byte per second. The transfer rate is limited by the speed of memory and peripheral devices.

PLC: A PROGRAMMABLE LOGIC CONTROLLER is a solid-state control system that continuously monitors the status of devices connected
as inputs. Based upon a user written program, stored in memory, it controls the status of devices connected as outputs.

The three types of programming languages used in PLCs are:

• Ladder • Boolean • Grafcet

IEEE defines two graphical languages and two text-

based languages for use in PLC programming.

The graphical languages use symbols to program

control instructions, while the text based languages use
character strings to program instructions.

Graphical languages

• ladder diagrams (LD) • function block diagram

(FBD)

Text-based languages

• instruction list (IL) • structured text (ST) •Sequential

functional chart (SFC)

CPLD: Instead of relying on a programming unit to configure a chip, it is

advantageous to be able to perform the programming while the chip is
still attached to its circuit board. This method of programming is known
as “In-System programming (ISP). It is not usually provided for PLAs (or)
PALs, but it is available for the more sophisticated chips known as
“Complex programmable logic device”.

A Complex programmable logic device is a device that contain multiple

combination of PLAs and PALs”. A simple architecture of CPLD is shown
below
 Embedded System Note by
Md. Hassanul Karim Roni
Modern architecture of FPGA:

A Field Programmable Gate Array (FPGA) is a Programmable Logic Device(PLD)

with higher densities and capable of implementing different functions in a short
period of time.

The basic elements of an Field Programmable Gate Array are:

• Configurable logic blocks(CLBs):

• Configurable input output blocks(IOBs)
• Two-layer metal network of vertical and horizontal lines for
interconnecting the CLBS and FPGAs (programmable interconnect)

Architecture of CLB

The configurable logic block which is RAM based or PLD based is the
basic logic cell. It consists of registers (memory), muxes and
combinatorial functional unit. An array of CLBS are embedded within a
set of vertical and horizontal channels that contain routing which can be
personalized to interconnect CLBs. The following figure represents the
architecture of a
single CLB

ADC converter (See the slide)

MC vs MP based system
 Embedded System Note by
Md. Hassanul Karim Roni
Functional block diagram of MC

Fig. 10.3 shows the functional block diagram of the microcontroller.

The core of the microcontroller consists of the central processing unit
(CPU) and memory controller. The CPU contains the register file and
the register arithmetic-logic unit (RALU). A 16-bit internal bus
connects the CPU to both the memory controller and the interrupt
controller. An extension of this bus connects the CPU to the internal
peripheral modules. An 8-bit internal bus transfers instruction byte
from the memory controller to the instruction register in the RALU-

PTS: The interrupt-handling system has two main components: the

programmable interrupt controller and the peripheral transaction
server (PTS). The programmable interrupt controller has a hardware
priority scheme that can be modified by the software. Interrupts that go
through the interrupt controller are serviced by interrupt service
routines those are provided by you. The peripheral transaction server (PTS) which is a micro-coded hardware interrupt-processor
provides efficient interrupt handling.

Pulse-width Modulator (PWM) The output waveform from each PWM channel is a variable duty-cycle pulse. Several types of electric
motor control applications require a PWM waveform for most efficient operation. When filtered, the PWM waveform produces a DC level
that can change in 256 steps by varying the duty cycle. The number of steps per PWM period is also programmable (8 bits).

Frequency Generator(FG) Some microcontrollers of this class has this frequency generator. This peripheral produces a waveform with a
fixed duty cycle (50%) and a programmable frequency (ranging from 4 kHz to 1 MHz with a 16 MHz input clock).

Waveform Generator A waveform generator simplifies the task of generating synchronized, pulse-width modulated (PWM) outputs. This
waveform generator is optimized for motion control applications such as driving 3-phase AC induction motors, 3-phase DC brushless
motors, or 4-phase stepping motors. The waveform generator can produce three independent pairs of complementary PWM outputs,
which share a common carrier period, dead time, and operating mode. Once it is initialized, the waveform generator operates without CPU
intervention unless you need to change a duty cycle.

EPA: The event processor array (EPA) performs high-speed input and output functions associated with its timer/counters. In the input
mode, the EPA monitors an input for signal transitions. When an event occurs, the EPA records the timer value associated with it. This is
called a capture event. In the output mode, the EPA monitors a timer until its value matches that of a stored time value. When a match
occurs, the EPA triggers an output event, which can set, clear, or toggle an output pin.

This is called a compare event. Both capture and compare events can initiate interrupts, which can be serviced by either the interrupt
controller or the PTS. Timer 1 and timer 2 are both 16-bit up/down timer/counters that can be clocked internally or externally. Each
timer/counter is called a timer if it is clocked internally and a counter if it is clocked externally

Watchdog Timer The watchdog timer is a 16-bit internal timer that resets the microcontroller if the software fails to operate properly.
A watchdog timer (WDT) is a device or electronic card that performs a specific operation after a certain period of time if something goes
wrong with an electronic system and the system does not recover on its own.

RALU: Register Arithmetic-logic Unit. The RALU contains the microcode engine, the 16-bit arithmetic logic unit (ALU), the master
program counter (PC), the processor status word (PSW), and several registers.

Memory hierarchy:

The memory at the basic level can be classified as

1. Processor Memory (Register Array)
2. Internal on-chip Memory
3. Primary Memory
4. Cache Memory
5. Secondary Memory

Processor Memory (Register Array)

Most processors have some registers associated with the arithmetic

logic units. They store the operands and the result of an instruction.
The data transfer rates are much faster without needing any additional
 Embedded System Note by
Md. Hassanul Karim Roni
clock cycles. The number of registers varies from processor to processor. The more is the number the faster is the instruction execution.
But the complexity of the architecture puts a limit on the amount of the processor memory.

Internal on-chip Memory

In some processors there may be a block of memory location. They are treated as the same way as the external memory. However, it is
very fast.
Primary Memory

This is the one which sits just outside the CPU. It can also stay in the same chip as of CPU. These memories can be static or dynamic.
Cache Memory

This is situated in between the processor and the primary memory. This serves as a buffer to the immediate instructions or data which
the processor anticipates. There can be more than one levels of cache memory.
Secondary Memory

These are generally treated as Input/Output devices. They are much cheaper mass storage and slower devices connected through some
input/output interface circuits. They are generally magnetic or optical memories such as Hard Disk and CDROM devices. The memory
can also be divided into Volatile and Non-volatile memory.
Volatile Memory

The contents are erased when the power is switched off. Semiconductor Random Access Memories fall into this category.
Non-volatile Memory

The contents are intact even of the power is switched off. Magnetic Memories (Hard Disks), Optical Disks (CDROMs), Read Only
Memories (ROM) fall under this category.

Extra:

OTP ROM: One-time programmable ROM

The Connections “programmed” after manufacture by user. The user provides file of desired contents of ROM. The file input to machine
called ROM programmer. Each programmable connection is a fuse. The ROM programmer blows fuses where connections should not
exist.
• Very low write ability: typically written only once and requires ROM programmer device
• Very high storage permanence: bits don’t change unless reconnected to programmer and more fuses blown
• Commonly used in final products: cheaper, harder to inadvertently modify

EPROM: Erasable programmable ROM

This is known as erasable programmable read only memory. The programmable component is a
MOS transistor. The EPROM has
• Better write ability
– can be erased and reprogrammed thousands of times
• Reduced storage permanence
– program lasts about 10 years but is susceptible to radiation and electric noise
• Typically used during design development

Flash Memory
It is an extension of EEPROM. It has the same floating gate principle and same write ability and storage permanence. It can be erased at a faster
rate i.e. large blocks of memory erased at once, rather than one word at a time. The blocks are typically several thousand bytes large
• Writes to single words may be slower
– Entire block must be read, word updated, then entire block written back
• Used with embedded systems storing large data items in nonvolatile memory
– e.g., digital cameras, TV set-top boxes, cell phones

EEPROM
EEPROM is otherwise known as Electrically Erasable and Programmable Read Only Memory. It is erased typically by using higher than normal
voltage. It can program and erase individual words unlike the EPROMs where exposure to the UV light erases everything.
 Embedded System Note by
Md. Hassanul Karim Roni
Memroy Interface:

In a memory read operation the CPU loads the address onto the address bus.
Most cases these lines are fed to a decoder which selects the proper memory
location. The CPU then sends a read control signal. The data is stored in that
location is transferred to the processor via the data lines.

In the memory write operation after the address is loaded the CPU sends the
write control signal followed by the data to the requested memory location.

DA and AD conversion process:

Two main steps of process of ADC conversion

process
1. Quantizing
2. Encoding

Various errors are in

ADC
i. Sampling error
ii. Quantization
iii. Coding
Algorithm
iv. in accurate modeling
v. Finite word length
vi. Round of errors
vii. Delay due to finite execution time of the processor
DAC
viii. Decoding
ix. Transients in sampling time

Types of AD & DA
ADC DAC
AD Converter Types: DA types
1. Flash ADC 1. Binary wieghted resistor
2. Delta Sigma ADC 2. R-2R ladder
3. Dual slope ADC 3. Multiplier DAC
4. Successive ADC 4. Non-multiplier DAC
 Embedded System Note by
Md. Hassanul Karim Roni
 Embedded System Note by
Md. Hassanul Karim Roni
Differences:

Micro-controller vs micro-processor

Microprocessor Microcontroller

Microprocessor contains ALU, General purpose Microcontroller contains the circuitry of

registers, stack pointer, program counter, clock microprocessor, and in addition it has built in
timing circuit, interrupt circuit ROM, RAM, I/O Devices, Timers/Counters etc.

It has many instructions to move data between It has few instructions to move data between
memory and CPU memory and CPU

Few bit handling instruction It has many bit handling instructions

Less number of pins are multifunctional More number of pins are multifunctional

Single memory map for data and code Separate memory map for data and code
(program) (program)

Access time for memory and IO are more Less access time for built in memory and IO.

Microprocessor based system requires It requires less additional hardwares

additional hardware

More flexible in the design point of view Less flexible since the additional circuits which is
residing inside the microcontroller is fixed for a
particular microcontroller

Large number of instructions with flexible Limited number of instructions with few
addressing modes addressing modes
 Embedded System Note by
Md. Hassanul Karim Roni

RISC vs CISC

RISC CISC

Instruction takes one or two cycles Instruction takes multiple cycles

Only load/store instructions are used to access In additions to load and store instructions,
memory memory access is possible with other
instructions also.

Instructions executed by hardware Instructions executed by the micro program

Fixed format instruction Variable format instructions

Few addressing modes Many addressing modes

Few instructions Complex instruction set

Most of the have multiple register banks Single register bank

Highly pipelined Less pipelined

Complexity is in the compiler Complexity in the microprogram

 Embedded System Note by
Md. Hassanul Karim Roni

Harvard vs Von-neuman

Von-Neumann (Princeton architecture) Harvard architecture

It uses single memory space for both It has separate program memory and data
instructions and data. memory

It is not possible to fetch instruction code and Instruction code and data can be fetched
data simultaneously

Execution of instruction takes more machine Execution of instruction takes less machine
cycle cycle

Uses CISC architecture Uses RISC architecture

Instruction pre-fetching is a main feature Instruction parallelism is a main feature

Also known as control flow or control driven Also known as data flow or data driven
computers computers

Simplifies the chip design because of single Chip design is complex due to separate memory
memory space space

Eg. 8085, 8086, MC6800 Eg. General purpose microcontrollers, special

DSP chips etc.

Hardwired vs PLC system

Micro-controller vs PLC

MC PLC

It is used in embedded system It is mainly used in Industrial control system

It runs on low power, typically 5VDC It run on 230V AC, 24VDC

It is a non-robust controller It is a robust controller. Means it can undergo noise, vibration

or harsh environment
 Embedded System Note by
Md. Hassanul Karim Roni
C, C++, python programming language are widely used for Ladder programming, FBD are popularly used for
programming MC programming PLC

It is a low-cost controller It is much expensive device than MC

MC input/output pin is fixed. PLC input/ output can be extended using additional I/O card.

Wiring and hardware setup is difficult It’s wiring or setup is quite simple

RAM ROM

Definition Random Access Memory or RAM is a form of
data storage that can be accessed randomly at
any time, in any order and from any physical
location., allowing quick access and
manipulation.
Read-only memory or ROM is also a form of data storage that
can not be easily altered or reprogrammed.Stores instuctions
that are not nescesary for re-booting up to make the
computer operate when it is switched off.They are hardwired.

Stands Random Access Memory Read-only memory

for

Use RAM allows the computer to readdata quickly to ROM stores the program required to initially boot the
run applications. It allows reading and writing. computer. It only allows reading.

Volatility RAM is volatile i.e. its contents are lost when the It is non-volatile i.e. its contents are retained even when the
device is powered off. device is powered off.

Types The two main types of RAM are static RAM and The types of ROM include PROM, EPROM and EEPROM.
dynamic RAM.

Static vs Dynamic Memory:

Static Memory: Static Memory devices are semiconductor memories in which the stored data will remain permanently stored as long
as power is applied without the need of periodically rewriting or refreshing the data into the memory. The basic element of this
storage is a flip flop or a gate. SRAM, Punched Card and Tape are examples of Static Memory.

Dynamic Memory: Dynamic Memory devices are semiconductor memories in which the stored data will not remain permanently
stored, even with power applied unless the data is periodically rewritten into the memory. Data is stored as charge on capacitors. The
charge on capacitor has to be periodically refeshed in order to prevent it from leaking away. DRAM & Charge Coupled Device (CCD)
are example of Dynamic Memory.

Static VS Dynamic RAM

Basic types of RAM DRAM: Dynamic RAM

SRAM: Static RAM – Memory cell uses MOS transistor and capacitor to store bit
– Memory cell uses flip-flop to store bit – More compact than SRAM
– Requires 6 transistors – “Refresh” required due to capacitor leak
– Holds data as long as power supplied • word’s cells refreshed when read
– Typical refresh rate 15.625 microsec.
– Slower to access than SRAM
 Embedded System Note by
Md. Hassanul Karim Roni
ADC Comparision:

Programming:
PLC program

Boolean Mnemonics
 Embedded System Note by
Md. Hassanul Karim Roni

Grafset symbols

Grafcet (Graphe Fonctionnel de Commande Étape Transition) is a symbolic,

graphic language, which originated in France, that represents the control
program as steps or stages in the machine or process.

•In fact, the English translation of Grafcet means “step transition function
charts.”

8255

8254:
 Embedded System Note by
Md. Hassanul Karim Roni

8051 Timer programming register –

In order to program 8051 timers, it is important to

know the calculation of initial count value to be stored
in the timer register. The calculations are as follows.

In any mode, Timer Clock period = 1/Timer Clock

Frequency= 1/(Master Clock Frequency/12)

a. Mode 1 (16 bit timer/counter): Value to be loaded in

decimal = 65536 – (Delay Required/Timer clock period)
Convert the answer into hexadecimal and load onto THx
and TLx register. (65536D = FFFFH+1)
b. Mode 0 (13 bit timer/counter): Value to be loaded in
decimal = 8192 – (Delay Required/Timer clock period)
Convert the answer into hexadecimal and load onto THx
and TLx register. (8192D = 1FFFH+1)
c. Mode 2 (8 bit auto reload): Value to be loaded in
decimal = 256 – (Delay Required/Timer clock period)
Convert the answer into hexadecimal and load onto THx
register. Upon starting the timer this value from THx
will be reloaded to TLx register. (256D = FFH+1)
 Embedded System Note by
Md. Hassanul Karim Roni
Some important definitions:
Introduction:
System: A system is a way of working, organizing or doing one or many tasks according to a
fixed plan, program or set of rules. A system is also an arrangement in which all its units
assemble and work together according to the plan or program.
Embedded system:
• Any device that includes a computer but is not itself a general-purpose computer.
• It is an electronic/ electro-mechanical system designed to perform a specific function
and is a combination of hardware and firmware (Software). An example of an
embedded system is a microprocessor that controls an automobile engine.
• An embedded system is designed to run on its own without human intervention, and
may be required to respond to events in real time.

An embedded system is a computer system with a dedicated function within a larger

mechanical or electrical system, often with real-time computing constraints. It is embedded as
part of a complete device often including hardware and mechanical parts.Embedded
systems control many devices in common use today

A typical embedded system consists of the following units housed on a single board or chip.
1. Processor
2. Memory
3. Input/output interface chips
4. I/O Devices including Sensors and Actuators
5. A-D and D-A converters
6. Software as operating system
7. Application Software

Each ES is designed to serve the purpose of any one or combination of the following
task
• Data collection/Storage/Representation
• Data Communication
• Data(Signal) Processing
• Monitoring
• Control
• Application specific user interface

Parts of ES:
* It has Hardware Processor, Timers, Interrupt controller, I/O Devices, Memories,
Ports, etc.
* It has main Application Software Which may perform concurrently the series of tasks or multiple tasks.
* It has Real Time Operating System (RTOS) RTOS defines the way the system work which supervise the application software. It sets the
rules during the execution of the application program. A small scale embedded system may not need an RTOS

NPTEL Lecture:
Instruction Register: A register inside the CPU which holds the instruction code temporarily before sending it to the decoding unit.
Program Counter: It is a register inside the CPU which holds the address of the next instruction code in a program. It gets updated
automatically by the address generation unit.
Instruction Queue: A set of memory locations inside the CPU to hold the instructions in a pipeline before rending them to the next
instruction decoding unit.
Control Unit: This is responsible in generating timing and control signals for various operations inside the CPU. It is very closely
associated with the instruction decoding unit.

General Purpose Processor Architecture has the following characteristics

• Multiple Stages of Pipeline
• More than one Level of Cache Memory
• Branch Prediction Mechanism at the early stage of Pipe Line
• Separate and Independent Processing Units (Integer Floating Point, MMX, 3D etc)
• Because of the uncertainties associated with Branching the overall instruction execution time is not fixed (therefore it is not suitable for
some of the real time applications which need accurate execution speed)
• It handles a very complex instruction set
• The over all power consumption because of the complexity of the processor is higher

8051:
 Embedded System Note by
Md. Hassanul Karim Roni
Baud rate: The rate at which data is transmitted is called baud rate or transfer rate.
Communication link:
1. Simplex: The line is dedicated for transmission or reception only.
2. Half Duplex: The communication link can be used either for reception or transmission. Data is transmitted only one direction at a time.
3. Full Duplex: If the data is transmitted in both direction at the same time, it is called a full duplex system.

8254: Some of the other counter/timer functions common to microcomputers which can be implemented with the 8254 are:
✓Real time clock ✓Event-counter ✓Digital one-shot ✓Programmable rate generator ✓Square wave generator ✓Binary rate multiplier
✓Complex waveform generator ✓Complex motor controller
ADC & DAC:
Quantizing:: A process in which the continuous range of values of an analog signal is sampled and divided into nonoverlapping (but not
necessarily equal) subranges, and a discrete, unique value is assigned to each subrange.

Resolution in ADC: The resolution of a n-bit analog-to-digital Converter (ADC) is a function of how many parts the maximum signal can be
divided into. The formula to calculate resolution is 2^n. For example, a 12 bit ADC has a resolution of 2^12 = 4,096. Therefore, our best
resolution is 1 part out of 4,096, or 0.0244% of the full scale.

Aliasing: Occurs when the input signal is changing much faster than the sample rate. For example, a 2 kHz sine wave being sampled at 1.5
kHz would be reconstructed as a 500 Hz (the aliased signal) sine wave.
Sampling Rate: Frequency at which ADC evaluates analog signal.
Nyquist Rule: Use a sampling frequency at least twice as high as the maximum frequency in the signal to avoid aliasing.
8051:
Micro-controller: A small computer usually implemented on a single IC that contains a central processing unit (CPU),
some memory, and peripheral devices such as counter/timers, analog-to-digital converters, serial communication hardware, etc.

Features of 8051:
i. It Includes Boolean Processing Engine. Thus internal registers and RAM can
carry Boolean logic operations directly and efficiently.
ii. It gives us many functions in a single chip. (For example: CPU,RAM,ROM,I/O,
Interrupt, Timer etc)
iii. It have 8 bit Data bus.
iv. It have 8 bit Stack Pointer.
v. It have 16 bit Program Counter.
vi. It have 16 bit address bus which can access almost 65,536 memory locations.
vii. Data memory or RAM of 128 bytes.(On-Chip).
viii. Program Memory or ROM of 4 KB.(On Chip).
ix. Bi-Directional I/O port of 4 bytes.
x. It has 4 separate Register Sets.
xi. Serial Port or UART.
xii. It features Power Saving Mode which saves power.
xiii. Two Timers/Counters each of 16 bit.
xiv. Internal and External Interrupt Sources.
xv. 2 level interrupt priority.

Addressing Modes in 8051:

• Register
• Direct
• Register Indirect
• Immediate
• Relative
• Absolute
• Long
• Indexed

Instruction Timing: The 8051 internal operations and external read/write operations are controlled by the oscillator clock. T-state,
Machine cycle and Instruction cycle are terms used in instruction timings.
T-state is defined as one subdivision of the operation performed in one clock period. The terms 'T-state' and 'clock period' are often used
synonymously.
Machine cycle is defined as 12 oscillator periods. A machine cycle consists of six states and each state lasts for two oscillator periods. An
instruction takes one to four machine cycles to execute an instruction.
Instruction cycle is defined as the time required for completing the execution of an instruction. The 8051 instruction cycle consists of one
to four machine cycles.
 Embedded System Note by
Md. Hassanul Karim Roni
The instructions of 8051 can be broadly classified under the following headings.
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Branch instructions
5. Subroutine instructions
6. Bit manipulation instructions

Assembler directives: Assembler directives tell the assembler to do something other than creating the machine code for
an instruction. In assembly language programming, the assembler directives instruct the
assembler to
1. Process subsequent assembly language instructions
2. Define program constants
3. Reserve space for variables

The following are the widely used 8051 assembler directives.

ORG (origin) The ORG directive is used to indicate the starting address. It can be used only when the program counter needs to be
changed. The number that comes after ORG can be either in hex or in decimal. Eg: ORG 0000H ;Set PC to 0000.

EQU and SET EQU and SET directives assign numerical value or register name to the specified symbol
name.
EQU is used to define a constant without storing information in the memory. The symbol defined with EQU should not be redefined.
SET directive allows redefinition of symbols at a later stage.

DB (DEFINE BYTE) The DB directive is used to define an 8 bit data. DB directive initializes memory with 8 bit
values. The numbers can be in decimal, binary, hex or in ASCII formats. For decimal, the 'D' after the decimal number is optional, but for
binary and hexadecimal, 'B' and ‘H’ are required. For ASCII, the number is written in quotation marks (‘LIKE This).

DATA1: DB 40H ; hex

DATA2: DB 01011100B ; b i n a r y
DATA3: DB 48 ; decimal
DATA4: D B 'HELLOW’ ; ASCII
END

The END directive signals the end of the assembly module. It indicates the end of the program to the assembler. Any text in the assembly
file that appears after the END directive is ignored. If the END statement is missing, the assembler will generate an error message.

BASICS OF INTERRUPTS.
During program execution if peripheral devices needs service from microcontroller, device will generate interrupt and gets the service
from microcontroller. When peripheral device activate the interrupt signal, the processor branches to a program called interrupt service
routine. After executing the interrupt service routine the processor returns to the main program.

Steps taken by processor while processing an interrupt:

1. It completes the execution of the current instruction.
2. PSW is pushed to stack.
3. PC content is pushed to stack.
4. Interrupt flag is reset.
5. PC is loaded with ISR address.

ISR will always ends with RETI instruction. The execution of RETI instruction results in the following.
1. POP the current stack top to the PC.
2. POP the current stack top to PSW.

Classification of interrupts.
1. External and internal interrupts: External interrupts are those initiated by peripheral devices through the external pins of the
microcontroller. Internal interrupts are those activated by the internal peripherals of the microcontroller like timers, serial controller etc.)

2. Maskable and non-maskable interrupts.

The category of interrupts which can be disabled by the processor using program is called maskable interrupts.
Non-maskable interrupts are those category by which the programmer cannot disable it using program.

3. Vectored and non-vectored interrupt.

Starting address of the ISR is called interrupt vector. In vectored interrupts the starting address is predefined. In non-vectored interrupts,
the starting address is provided by the peripheral as follows-
• Microcontroller receives an interrupt request from external device.
 Embedded System Note by
Md. Hassanul Karim Roni
• Controller sends an acknowledgement (INTA) after completing the execution of current instruction.
• The peripheral device sends the interrupt vector to the microcontroller.

TIMERS AND COUNTERS

Timers/Counters are used generally for
• Time reference • Creating delay • Wave form properties measurement • Periodic interrupt generation • Waveform generation

8051 has two timers, Timer 0 and Timer 1. Timer in 8051 is used as timer, counter and baud rate generator. Timer always counts up
irrespective of whether it is used as timer, counter, or baud rate generator: Timer is always incremented by the microcontroller. The time
taken to count one digit up is based on master clock
frequency.

Some important Problems:

Ramp generator:

• Design an O/P port with the address FFh to interface the 1408 D/A converter that is calibrated for 0 to 10V range.
• Write a program to generate a ramp.