Third International Symposium on Intelligent Information Technology and Security Informatics
A General Method of Constructing the Reversible Full-adder
Lihui Ni Zhijin Guan
College of Electronics and College of Computer Science and
Information Technology
Nantong University Nantong University
Nantong,China Nantong,China
nilihuiandpzl@126.com guan_zj@nuaa.edu.cn
Abstract—The reversible gates, attracting people’s attention
increasingly, have been widely used in low-power CMOS
design, optical computing and quantum computing. In many
existing literatures, only the methods of constructing certain
specific reversible full-adders were presented, while we
proposed a general approach to construct the reversible full-
adder. According to the approach, we can realize a variety of
reversible full-adders flexibly with only two reversible gates
and two garbage outputs, which have improvements in the gate
count and garbage count and can reduce the cost of network.
Keywords- reversible full-adder; reversible gates; gate count;
garbage outputs
I. INTRODUCTION
Landauer[1] has proved that the circuits built by the
traditional irreversible logic gates such as AND gate or XOR
gate will inevitably lead to energy dissipation in the running
process. For every bit of information loss, there will generate
kT ∗ ln 2 joules, where k is the Boltzmann’s constant and
T is the absolute temperature. Comparing with the other
forms of energy dissipation kT ∗ ln 2 is negligible.
However, the amount of energy consumed is proportional to
the numbers of bits erased. That is to say, the more numbers
of bits lose, the more energy will dissipate.
In order to avoid energy dissipation in the circuit, it must
be built circuits using reversible logic gates[2]. Reversible
logic circuits are information lossless. Hence, reversible
logic circuits have theoretically zero internal power
dissipation. Design of reversible logic circuits is quite
different from that of traditional irreversible circuits. It’s
necessary to add constant signals to ensure the reversibility
of the circuits. It’s necessary to add constant signals to
ensure the reversibility of the circuits. A reversible circuit
should have the following features[3]: 1) Use minimum
number of reversible logic gates; 2) Use minimum number of
garbage outputs; 3) Use minimum constant inputs.
In many computational units, adders are the basic
building blocks. There are various ways to implement
reversible full-adder based on the cascading of reversible
gates. In [4], the proposed reversible full-adder needs one 3
input/output Toffoli gate and one 2 input/output Feynman
gate and one 3 input/output New gate. Another reversible
full-adder uses two 3 input/output Toffoli gate and two 2
input/output Feynman gate in [5]. The third reversible full-
978-0-7695-4020-7/10 $26.00 © 2010 IEEE 109
DOI 10.1109/IITSI.2010.25
Wenying Zhu
College of Electronics and
Information
Nantong University
Nantong,China
zwy.fjf@gmail.com
adder using two 3 input/output New gate and one 2
input/output Feynman gate is presented in [6]. By examining
the previous three design methods, we propose a general
approach to construct the reversible full-adder. According to
the approach, we can realize a variety of reversible full-
adders flexibly with only two reversible gates and two
garbage outputs.
II. PRELIMINARIES
A. Definition
In this section, some basic definitions of reversible logic
are given.
Definition 1: For an input/output function F , if there is a
one-to-one correspondence between its inputs and outputs,
then this function is reversible. Therefore, the input vector
can be uniquely reconstructed by the output vector, and vice
verse.
Definition 2: An n input/output reversible logic gate can
be represented as:
I V = ( I1 , I 2 ," , I n ) (1)
OV = (O1 , O2 ," , On ) (2)
Where IV is the input vector, and OV is the output
vector. That is to say, a reversible gate has the same number
of inputs and outputs.
Definition 3: Given two bit strings p and q , the
Hamming distance can be defined as the number of the
positions for which p and q differ[7].
Definition 4: Given the function f ( x) , the
complexity C ( f ) is defined as the sum of the individual
Hamming distances over the 2 n input/output patterns[7].
For example, the value of C ( f ) for the function in
Table 4 is 4.
B. The Reversible Gate
Here, we just give two reversible gates which will be
used later in this paper.
Fig.1 shows a 3 input/output New gate[8]. When C = 0 ,
then Q = AB and R = A ⊕ B which are the carry and sum
outputs of a half adder[9]. Fig.2 shows a 3 input/output New
Toffoli gate[8]. New Toffoli gate can be used as a gate that
generates an AND gate and an XOR gate when C = 0 .
 A P= A A P= A reversible gates and Cin be the third input. According to (3)
B Q = AB ⊕ C B Q = A⊕ B and (4), the output expressions of the second category
reversible gates should be S = M ⊕ Cin , Cout = N ⊕ MCin
C R = AC ⊕B C R = AB⊕C
and with another garbage output G2 (the sequence of the
Figure 1. New gate Figure 2. New Toffoli gate
outputs is arbitrary).
Table 1. The truth table of the traditional full-adder So, the proposed approach of constructing the reversible
Input Output full-adder only needs two 3 input/output reversible gates and
A B Cin S Cout each of which is accompanied by one garbage output.
0 0 0 0 0
0 0 1 1 0 A. Realization of the First Category Reversible Gate
0 1 0 1 0
0 1 1 0 1 In order to achieve the first category of 3 input/output
1 0 0 1 0 reversible gates, it should meet the following conditions:
1 0 1 0 1 When C = 0 , the output expressions should be M = A ⊕ B ,
1 1 0 0 1
1 1 1 1 1 N = AB .
Let
III. APPROACH M = ABC + ABC + XC+YC (5)
In order to fully present the general approach of Where X and Y are the different combinations of
constructing the reversible full-adder, we firstly analyze the AB , AB , A B and A B . So there are C 42 = 6 cases which
truth table of the traditional irreversible full-adder (Table 1) satisfy (5). Let’s discuss these cases separately.
and its corresponding logical expressions.
According to the truth table, we can get the logical (a) X = AB and Y = A B , then
expressions of the outputs. M = AB C + A BC + ABC + A BC (6)
S = A ⊕ B ⊕ Cin (3) The corresponding Karnaugh map is shown in Fig.3.a,
and we can get M = AC ⊕ B after simplification.
Cout = AB ⊕ ( A ⊕ B )Cin (4)
The following cases from (b) to (f) can be analyzed in the
Where S is sum, and Cout is carry. same way.
In the reversible gate, there is a one-to-one mapping (b) X = AB and Y = AB , then
between the inputs and the outputs. From the truth table M = AB C + A BC + ABC + AB C (7)
(Table 1) we get that there are three inputs and two outputs The corresponding Karnaugh map is shown in Fig.3.b,
for the traditional full-adder and the output vectors can be
and we can get M = A ⊕ BC after simplification.
derived from the input vectors, while the input vectors can
not be uniquely reconstructed from the output vectors. In (c) X = AB and Y = A B , then
order to make the traditional full-adder reversible, garbage M = AB C + A BC + ABC + A B C (8)
outputs must be added. In the input combinations, three input The corresponding Karnaugh map is shown in Fig.3.c,
vectors-(0,0,1), (0,1,0) and (1,0,0) all corresponds to the and we can get M = A ⊕ B ⊕ C after simplification.
output vector (1,0). So, the output combinations are not (d) X = A B and Y = A B , then
unique at all. To make the output combinations unique, we M = AB C + A BC + A BC + A B C (9)
should add two garbage outputs at least, which is the The corresponding Karnaugh map is shown in Fig.3.d,
foundation of constructing the reversible full-adder. and we can get M = A ⊕ B ⊕ C after simplification.
In this paper, the reversible full-adders can be created by
cascading two 3 input/output reversible gates with only two
garbage outputs. So the approach we presented is optimal in
regard to the garbage count. The main steps are as follows:
Step 1: Let M = A ⊕ B , then (3) can be expressed as
S = M ⊕ Cin .
(a) (b)
Step 2: Let N = AB , then (4) can be expressed as
Cout = N ⊕ MCin .
Step 3: Let A , B and C be the inputs of the first
category reversible gates. In order to realize the reversible
full-adder, we should guarantee one constant signal among (c) (d)
A , B and C (Set C = 0 ). When C = 0 , the output
expressions should be M = A ⊕ B , N = AB and with one
garbage output G1 (the sequence of the outputs is arbitrary).
Step 4: Let the outputs M and N of the first category
reversible gates be the two inputs of the second category (e) (f)
Figure 3. Karnaugh maps of M

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 (e) X = A B and Y = AB , then Example 1: Discuss the combination of (a) and ① and its
M = AB C + A BC + A BC + AB C (10) truth table is given in Table 2 (Let the order of the outputs be
The corresponding Karnaugh map is shown in Fig.3.e, G1 , M and N , and the 0, 1 permutation of G1 will be
and we can get M = A ⊕ B after simplification. discussed below.).
(f) X = A B and Y = AB , then Know from Table 2, we can get that the combination of
M = AB C + A BC + A B C + AB C (11) (a) and ① meets the above requirements, so go to Step 2; or
The corresponding Karnaugh map is shown in Fig.3.f, discuss the next combination.
and we can get M = B ⊕ ( A + C ) after simplification. Step 2: Consider the 0, 1 permutation of G1 . In order to
The satisfied expressions of M can be seen above, and realize reversibility, there must be four 0 and four 1 in the
there exits 6 cases. line of G1 . The number of 0, 1 permutation is 2 4 = 16 ,
Let which means there exists 16 different truth tables when we
N = AB C + X C + Y C + Z C (12) choose the combination of (a) and ①. Different truth tables
Where X , Y and Z are the different combinations of correspond to different reversible gates. For these 16
AB , AB , A B and A B . So there are C 43 = 4 cases which reversible gates, when C = 0 , we can all get M = A ⊕ B ,
can satisfy (6). Let’s discuss these cases separately. N = AB and the only difference among them is the different
expression of G1 because of its different 0, 1 permutation.
① X = AB , Y = A B and Z = A B , then
Analyze all the other combinations in the same way, and
N = AB C + ABC + A BC + A B C (13)
we can get the result which is showed in Table 3.
The corresponding Karnaugh map is shown in Fig.4.a, In Table 3, “√” means that its corresponding combination
and we can get N = AB + A C after simplification. meets the conditions of realizing a reversible gate, while “×”
② X = AB , Y = AB and Z = A B , then means that its corresponding combination does not meet the
N = AB C + ABC + A B C + A B C (14) requirements of realizing a reversible gate. We can get from
The corresponding Karnaugh map is shown in Fig.4.b, Table 3 that there are 12 combinations which can be used to
structure the first category of 3 input/output reversible gates.
and we can get N = AB + B C after simplification.
Example 2: Based on the complexity, which can be seen
③ X = AB , Y = A B and Z = AB , then as one of the criteria measuring the performance of the
N = ABC + ABC + A BC + AB C (15) reversible gates, we can find out the first category of 3
The corresponding Karnaugh map is shown in Fig.4.c, input/output reversible gates with the least complexity. There
and we can get N = AB + AC + BC after simplification. are two such reversible gates called RG1 _ 1 and
④ X = A B , Y = AB and Z = A B , then RG1 _ 2 both with the least complexity of 4. See Fig.5 and
N = AB C + A BC + A B C + A B C (16) Fig.6 respectively, and their corresponding truth tables are in
The corresponding Karnaugh map is shown in Fig.4.d, Table 4 and Table 5.
and we can get N = AB ⊕ C after simplification. Table 2. The combination of (a) and ①
We have got the satisfied expressions of M and N ,
A B C G1 M N
respectively. M has 6 cases from (a) to (f) and N has 4 0 0 0 - 0 0
cases from ① to ④. Theoretically, there are 4×6=24 cases 0 0 1 - 0 1
0 1 0 - 1 0
which can realize the first category reversible gates. 0 1 1 - 1 1
However, not each case meets the requirements of building a 1 0 0 - 1 0
reversible gate, and we should verify each combination 1 0 1 - 0 0
through the truth table. Steps are as follows: 1 1 0 - 0 1
1 1 1 - 1 1
Step 1: Given the truth table of each combination and
make sure that there are two pairs of (0,0), (0,1), (1,0) and Table 3. Results of all the combinations
(1,1) respectively for the combination of M and N .
combinations a b c d e f
① √ × √ √ × ×
② × √ √ × × √
③ √ √ × × √ ×
④ × × × √ √ √

(a) (b)
A G1 = A A M = A⊕ BC
B M = AC ⊕ B B G1 = B
C N = AB+ AC C N = AB+ BC

(c) (d) Figure 5. RG1_1 Gate Figure 6. RG1_2 Gate

Figure 4. Karnaugh maps of N

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 Table 4. The truth table of RG1_1 Table 6. The combination of S and Cout
A B C G1 M N A B Cin G2 S Cout
0 0 0 0 0 0 0 0 0 - 0 0
0 0 1 0 0 1 0 0 1 - 0 1
0 1 0 0 1 0 0 1 0 - 1 0
0 1 1 0 1 1 0 1 1 - 1 1
1 0 0 1 1 0 1 0 0 - 1 0
1 0 1 1 0 0 1 0 1 - 0 0
1 1 0 1 0 1 1 1 0 - 0 1
1 1 1 1 1 1 1 1 1 - 1 1
Table 5. The truth table of RG1_2 Then consider the 0, 1 permutation of G2 . Make sure
A B C M G1 N that there are four 0 and four 1 in the line of G2 . The number
0 0 0 0 0 0
0 0 1 0 0 1 of 0, 1 permutation which meet the above requirements is
0 1 0 1 1 0 2 4 = 16 .
0 1 1 0 1 0
1 0 0 1 0 0 Example 3: Based on the complexity, we can also find
1 0 1 1 0 1 out the second category reversible gates with the least
1 1 0 0 1 1 complexity of 6. There is only one such gate called RG 2.1 .
1 1 1 1 1 1
Let’s see Fig.8 and its corresponding truth table is presented
B. Realization of the Second Category Reversible Gate in Table 7.
When structuring the reversible full-adder, the two inputs C. Cascading the Two Categories of the Reversible
of the second category reversible gates are the two outputs of Gates
the first category reversible gates, that is, the inputs of the
When creating the reversible full-adder, it’s assumed that
second category reversible gates are M , N and Cin . We
the third input be 0 for the first category reversible gates, and
can set the first two inputs be A and B which correspond to the third input be Cin for the second category reversible
M and N when designing the second category reversible
gates. Let the outputs M and N of the first category
gates, and the third input be Cin , then the outputs of the
reversible gates connect the inputs A and B of the second
second category reversible gates should meet: S = A ⊕ Cin , category reversible gates, respectively. Then the reversible
Cout = B ⊕ ACin and with one garbage output G 2 . In fact, full-adder is done.
Example 4: Cascading the reversible gate RG1 _ 1
the position of Cin is not fixed, which can be used as either
(Fig.5) with the reversible gate RG 2 _ 1 (Fig.8), we can get
the first input or the second input. Regardless of its position,
the reversible full-adder presented in Fig.9.
the analysis is the same. The same condition is to A and B .
It is known that: IV. COMPARISON
S = A ⊕ Cin In the existing literatures[4][5][6], only the methods of
= AC + A C (17) constructing certain specific reversible full-adders were
in in
presented, while we proposed a general approach to create
= ABCin + AB Cin + A BCin + A B Cin the reversible full-adder. According to the approach, we can
Its corresponding Karnaugh map is shown in Fig.7.a. realize a variety of reversible full-adders flexibly with only
It is known that: two reversible gates and two garbage outputs. The results of
Cout = B ⊕ ACin the comparison among different reversible full-adders are
(18)
= ABCin + AB Cin + A BCin + A BCin given in Table 8.
Its corresponding Karnaugh map is shown in Fig.7.b. A G2 = A
It’s clearly that the expressions of S and Cout are both
B Cout = B ⊕ ACin
unique. Further, there are two pairs of (0,0), (0,1), (1,0) and
(1,1) respectively for their combination in Table 6 (Let the Cin S = A ⊕ Cin
sequence of the inputs be A , B and Cout , and the sequence
Figure 8. RG2_1 Gate
of the outputs be G2 , S and Cout . The 0, 1 permutation of
Table 7. The truth table of the reversible gate RG2_1
G2 will be discussed below.).
A B Cin G2 Cout S
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 1
1 0 1 1 1 0
(a) (b) 1 1 0 1 1 1
Figure 7. Karnaugh maps of S and Cout 1 1 1 1 0 0

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 A G1 = A
A⊕ B
B G2 = A ⊕ B
0 AB Cout = AB⊕( A⊕ B)Cin
Cin S um = A ⊕ B ⊕ C in
Figure 9. The reversible full-adder proposed in this paper
Table 8. The results of the comparison among different reversible
full-adders
adder gate count garbage count
Our adders 2 2
Existed adder[4] 3 3
Existed adder[5] 4 2
Existed adder[6] 3 3
In [8], a reversible full-adder (Fig.10) was presented,
which is quite similar to the proposed reversible full-adders
in our paper (Fig.9). The former is cascaded by two 3
input/output reversible gates (one 3 input/output New gate
and one 3 input/output New Toffoli gate) and contains a
constant signal and two garbage outputs.
Let’s compare Fig.9 with Fig.10. It’s clearly that the
expressions of the two garbage outputs are the same. There
are two differences between them. First, the position of
connection is not the same. Second, the sequence of the
outputs S and Cout is different.
In fact, New gate is included in the first category
reversible gates. When chosen the combination of (f) and ④,
and set the 0, 1 permutation of G1 be (0,0,0,0,1,1,1,1), we
can get one truth table which is the same to the New gate’s.
The diagram of New gate is showed in Fig.1.
Likely, New Toffoli gate is included in the second
category reversible gates. Let the second input be C in , that
is, the sequence of the inputs is A , Cin and B . The
Karnaugh maps of the sum S and the carry Cout are
presented in Fig.11.a and Fig.11.b, respectively. When the
sequence of the outputs is G2 , S and Cout , and the 0, 1
permutation of G2 is (0,0,0,0,1,1,1,1), we can get one truth
table which is the same to that of New Toffoli gate. The
diagram of New Toffoli gate is showed in Fig.2.
A G1 = A
AB
B [7]
A⊕ B
0 G2 = A⊕ B
Cin Sum = A ⊕ B ⊕Cin
Cout = AB⊕( A⊕ B)Cin
Figure 10. The reversible full-adder cascaded by NG and NTG[8]
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(a) (b)
Figure 11. The Karnaugh maps of S and Cout
V. CONCLUSION
In this paper, we proposed a general approach to
construct the reversible full-adder. According to the
approach, we can realize a variety of reversible full-adders
flexibly with only two reversible gates and two garbage
outputs. The reversible full-adder, as reversible modules, can
be used to construct the large-scale reversible systems and
can reduce the cost of the circuits.
Our future work will focus on how to convert the
irreversible function to the reversible ones and try to find out
a general approach which can be applied to any irreversible
function.
ACKNOWLEDGMENT
This work is supported by the National Natural Science
Foundation of China under grant No. 60873069, and Science
and Technology Innovation Program of Nantong University
under grant No. YKC09048.
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