Evaluation Board For PulSAR 48 Lead ADCs

Preliminary Technical Data EVAL-AD76XXEDZ

FEATURES www.Analog.com/PulSAR and should be consulted when
Converter and Evaluation Development (EVAL-CED1Z) utilizing this evaluation board.
compatibility The evaluation board is ideal for use with Analog Devices USB
Versatile analog signal conditioning circuitry based Converter and Evaluation Development EVAL-CED1Z,
On-board reference, clock oscillator and buffers
(CED) or as a stand-alone system. These boards are also
Buffered 14, 16 (or 18) bit parallel outputs
compatible for use with the EVAL-CONTROL BRDxZ capture
Buffered serial port interface
board and software for using this board is available on the
Ideal for DSP and data acquisition card interfaces
Analog and digital prototyping area website. Since many newer PC’s do not offer a parallel port
PC software for control and data analysis along with overcomplicated BIOS port settings, the CED board
GENERAL DESCRIPTION is strongly recommended.

The EVAL-AD76XXEDZ is an evaluation board for the 48 lead
AD761X, AD762X, AD763X, AD764X, AD765X, AD766X,
AD767X and AD795X 14-bit, 16-bit and 18- bit PulSAR®
analog to digital converter (ADC) family. These low power,
successive approximation register (SAR) architecture ADCs (see
ordering guide for product list ) offer very high performance
with 100kSPS to 3MSPS throughput rate range with a flexible
parallel or serial interface. The evaluation board is designed to
demonstrate the ADC's performance and to provide an easy to
understand interface for a variety of system applications. A full
description of the ADCs for this board are available at
The design offers the flexibility of applying external control
signals and is capable of generating conversion results on
parallel 14-bit, 16-bit or 18-bit wide buffered outputs. On-board
components include a high precision band gap reference,
(AD780, ADR431, or ADR435), reference buffers, a signal
conditioning circuit with two op-amps and digital logic.
The EVAL-AD76XXEDZ interfaces to the CED capture board
with a 96-pin DIN connector. A 40-pin IDC connector is used
for parallel output, and test points are provided for the serial
port. SMB connectors are provided for the low noise analog
signal source, and for an externally generated CNVST (convert
start input.
External CNVST

Reference/Buffer
96-Pin CED/ECB
Interface
PulSAR ADC

Analog Inputs

Supplies

Figure 1. Evaluation Board

Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
EVAL-AD76XXCB Preliminary Technical Data

TABLE OF CONTENTS
FEATURES ........................................................................................ 1 Evaluation Board Setting for Bipolar ADC Input
Configurations...............................................................................4
GENERAL DESCRIPTION ............................................................ 1
Hardware Setup .............................................................................4
Overview........................................................................................ 3
Software Installation .....................................................................5
Conversion Control/Master Clock............................................. 3
Running the Evaluation Software ..............................................6
Analog Inputs................................................................................ 3
Setup Screen...................................................................................6
Power Supplies and Grounding .................................................. 3
DC Testing - Histogram ...............................................................6
Using the Eval-AD762X/AD765X/AD766X/ AD767XCBZ as
Stand-Alone................................................................................... 3 AC Testing ......................................................................................6

Schematics/PCB Layout............................................................... 4 Evaluation Board Schematics and Artwork............................ 16

Supplying Power for Stand-Alone use ....................................... 4 Ordering Guide .......................................................................... 22

LIST OF FIGURES
Figure 1. Evaluation Board .............................................................. 1 Figure 9. Schematic, Digital........................................................... 17

Figure 2. Setup Screen .................................................................... 10 Figure 10. Schematic, Power.......................................................... 18

Figure 3. Context Help ................................................................... 11 Figure 11. Top Side Silk-Screen .................................................... 19

Figure 4. Histogram Screen ........................................................... 12 Figure 12. Top Layer....................................................................... 19

Figure 5. Summary.......................................................................... 13 Figure 13. Ground Layer................................................................ 20

Figure 6. FFT Spectrum ................................................................. 14 Figure 14. Shield Layer................................................................... 20

Figure 7. Oscilloscope .................................................................... 15 Figure 15. Bottom Side Layer ........................................................ 21

Figure 8. Schematic, Analog .......................................................... 16 Figure 16. Bottom Side Silk-Screen.............................................. 21

LIST OF TABLES
Table 1. CNVST Generation, Analog Input Range....................... 7 Table 5.Test Points .............................................................................9
Table 6. Bill of Materials for the Connectors .............................. 22
Table 2. Jumper Description............................................................ 8
Table 3. S16 - Configuration Select Switch Description.............. 8
Table 4. S35 - Configuration Select Switch Description.............. 8

Rev. PrB | Page 2 of 23

Preliminary Technical Data
OVERVIEW
Figure 1 shows the EVAL-AD76XXEDZ evaluation board.
When used in stand-alone mode or in conjunction with the
EVAL-CED1Z, the gate array, U10, provides the necessary
control signals for conversion and buffers the ADC data. The
evaluation board is a flexible design that enables the user to
choose among many different board configurations, analog
signal conditioning, reference, and different modes of
conversion data.
CONVERSION CONTROL/MASTER CLOCK
Conversion start (CNVST) controls the sample rate of the ADC
and is the only input needed for conversion; all SAR timing is
generated internally. CNVST is generated either by the gate
array or externally via J3 (SMB) and setting JP22 in the external
(EXT) position. The evaluation board is factory configured for
the CNVST range shown in Table 1. Externally generated
CNVST should have very low jitter and sharp edges for the
maximum dynamic performance of the part. Since CNVST
jitter usually results in poor SNR performance, it is
recommended to use the on-board CNVST generation
whenever possible.
The master clock (MCLK) source for the gate array is generated
from the CED capture board or from U12, the 40MHz local
oscillator selectable when using the accompanying software.
The range for CNVST in
Table 1is a ratio generated from this master clock. In stand-
alone mode, other clock frequencies can be used to change the
gate array generated CNVST by this ratio. However, other
timings will be affected – namely the slave serial clock (SCLK)
interface. In serial slave mode, SCLK = MCLK.
While the ADC is converting, activity on the BUSY pin turns on
the LED, D2. Additionally, the BUSY signal can be monitored
test point TP1. Buffered conversion data (BD) is available at
U10 on the output bus BD[0:15] on the 40-pin IDC connector
P2, and on the 96-pin connector P3. When operating with the
CED, data is transferred using a 16 bit bus and corresponding
word and byte modes selectable with the software. For the 18 bit
converters two consecutive 16 bit words are read, however, the
ADC data is still read into the gate array as 18 bits. Additionally,
BD is updated on the falling edge of BBUSY on P3-C17, and on
the rising edge of DBUSY on P2-33. When either parallel or
serial reading mode of the ADC is used, data is available on this
parallel bus.
When using Serial Mode, serial data is available at T3, T4, T5,
and T6 (SDOUT, SCLK, SYNC and RDERROR) and buffered
serial data is output on TP17, TP18, and TP19 (SCLK, SYNC,
and SDOUT). When using Slave Serial Mode, the external serial
clock SCLK applied to the ADC is the MCLK, U12, frequency
(40MHz). Refer to the device specific datasheet for full details
of the interface modes.
Rev. PrB | Page 3 of 23
EVAL-AD76XXEDZ
ANALOG INPUTS
The analog inputs amplifier circuitry (U6, U7 and discretes)
allows configuration changes such as positive or negative gain,
input range scaling, filtering, addition of a DC component, use
of different op-amp and supplies depending on the ADC. The
analog input amplifiers are set as unity gain buffers at the
factory. The supplies are selectable with solder pads and are set
for the ±12V range.
Table 1 shows the analog input range for the available
evaluation boards.
The default configuration for the single ended (SE) unipolar
ADCs sets U6 at mid-scale from the voltage divider (VCM *
R6/(R6+R7)) and U7 at mid-scale from the voltage divider (VCM
* R29(R29+R60)) for the differential unipolar ADCs.
For the bipolar devices (AD7663, AD665, AD7671), the buffer
output is centered at 0V (mid-scale) as these boards are
configured for the +/-5V input range. Note the input impedance
is 1k ohm (R6, R29 =1k ohm to GND). To use another input
range, the solder pads S[7:1] need to be reconfigured.
These input configurations allows a transition noise test
(histogram) without any other equipment. In some applications,
it is desired to use a bipolar or wider analog input range, for
instance, ± 10V, ± 5V, ± 2.5V, or 0 to -5V. For ADCs which do
not use these input ranges directly, simple modifications of the
input driver circuitry can be made without any performance
degradation. Refer to the datasheet under the Application Hints
section for component values or to application note AN594 on
the product web page for other input ranges.
Note that the AD7663, AD7665, and AD7671 evaluation boards
are factory configured for the +/-5V range. For different ranges,
the board needs appropriate solder pad configurations.
For dynamic performance, an FFT test can be done by applying
a very low distortion AC source.
POWER SUPPLIES AND GROUNDING
The evaluation board ground plane is separated into two
sections: a plane for the digital interface circuitry and an analog
plane for the analog input and external reference circuitry. To
attain high resolution performance, the board was designed to
ensure that all digital ground return paths do not cross the
analog ground return paths by connecting the planes together
directly under the converter. Power is supplied to the board
through P3 when using with the EVAL-CED1Z
USING THE EVAL-AD762X/AD765X/AD766X/
AD767XEDZ AS STAND-ALONE
Using the evaluation board as stand-alone does not require the
CED nor does it require use of the accompanied software.
When the CONTROL input to the gate array is LOW, which is
pulled down by default, the gate array provides the necessary
signals for conversion and buffers the conversion data.
EVAL-AD76XXEDZ
In stand-alone mode, the gate arrays flexible logic buffers the
ADC data according to the read data mode configuration (word
or byte). In parallel reading mode the board is configured for
continuous reading since CS and RD are always driven LOW by
the gate array. Thus, the digital bus is not tri-stated in this mode
of operation and BD[0:15] will continuously be updated after a
new conversion. BD[0:15] is available on P2 after BUSY goes
HIGH. Note that with the 18 bit devices the full 18 bits of data
BD[-2:15] are output directly on P2 since the evaluation board
is not limited to 16 bit wide transfers in stand-alone operation.
When either parallel or serial reading mode, the data is available
on this parallel bus. Refer to Figure 9 to obtain the data output
pins on P2.
Configuration Switches
The evaluation board is configurable for the different operating
modes with 16 positions on the configuration select switches,
S16 and S35. A description of each switch setting and jumper
position is listed in Figure 9 and the available test points are
listed in Table 5. Note that the switches in the ON position
define a logic HIGH level (pulled up with 10kΩ,) and that the
switches are active only in stand-alone mode.
For all interface modes, S16 and S35 allows the selection of:
Warp, Normal or Impulse mode conversions (where applicable)
Binary or 2s complement data output
Reading during or after conversion
Resetting the ADC
ADC power-down
Internal Reference and Buffer power-down (where applicable)
In parallel reading mode, s16 allows the selection of:
Byte swapping for 8 bit interfacing (LSByte with MSByte)
18-bit, 16-bit and 8-bit interfacing (for 18-bit converters)
In serial reading mode, the default settings are Master Read
during Conversion Mode using the internal ADC serial clock.
Serial data is available at T3, T4, T5 and T6 for SDOUT, SCLK,
SYNC and RDERROR respectively. Buffered serial data is
output on the three test points TP17, TP18 and TP19 for SCLK,
SYNC, and SDOUT respectively.
For serial reading mode, S16 allows the selection of:
Choice of inverting SCLK and SYNC
Choice of using internal or external (slave mode) SCLK
SCHEMATICS/PCB LAYOUT
The EVAL-AD76XXEDZ is a 4-layer board carefully laid out
and tested to demonstrate the specific high accuracy
performance of the PulSAR ADC. Figure 8 to Figure 10 show
the schematics of the evaluation board. The printed circuit
layouts of the board are given in Figure 11 - Figure 16. Note
these layouts are not to scale.
Top side silk-screen - Figure 11
Top side layer - Figure 12
Ground layer - Figure 13
Shield layer - Figure 14
Rev. PrB | Page 4 of 23
Preliminary Technical Data
Bottom side layer - Figure 15
Bottom side silk-screen - Figure 16
SUPPLYING POWER FOR STAND-ALONE USE
Power needs to be supplied through the two power supply
blocks SJ1 and SJ2. Linear supplies are recommended. SJ1 is the
analog supply for the ADC (AVDD), front end op amps and
reference circuitry. SJ2 is the digital supply for the ADC
(DVDD, OVDD) and gate array. The supplies to the device are
configurable through the power supply jumpers shown in . In
most applications four supplies are required; ±12V and +5V for
analog, and +5V for digital. On board regulators, where
applicable, are used to reduce the operating voltages to the
correct levels. The analog and digital supplies can be from the
same source however, R27 (typically 20Ω) is required from
AVDD to DVDD. In this configuration, JP9, DVDD selection,
should be left open. Furthermore, the OVDD (ADC digital
output supply) may need to be brought up after the analog +5V
supply. See datasheet for details.
EVALUATION BOARD SETTING FOR BIPOLAR ADC
INPUT CONFIGURATIONS
The AD7610, AD7612, AD7631, AD7634, AD7663, AD7665,
AD7671, AD7951 and AD7952 can use both unipolar and
bipolar ranges. The available options are +/-10V, +/-5V, +/-2.5V,
0 to 10V, 0 to 5V and 0 to 2.5V (depending on the ADC).
For the AD7663, AD7665 and AD7671 the evaluation board is
set for the ±5V bipolar input range since these ADCs input
ranges are hardware pin strapped. Simple modifications to these
evaluation boards can be made to accommodate the different
input ranges by changing the INA-IND inputs with the available
solder pads.
iCMOS ADCs
For the AD7610, AD7612, AD7631 AD7634 and AD7951, the
evaluation board can use all input ranges since the input range
is controlled by software (or S16 DIP switches in stand-alone
mode).
For operating in unipolar mode for any of the bipolar
evaluation boards it is recommended to use the voltage divider
consisting of (VCM * R6/(R6+R7)) and (VCM * R29/(R29+R60)).
This allows a transition noise test without any additional
equipment.
HARDWARE SETUP
Using EVAL-CED1Z Capture Board
• EVAL-AD76XXEDZ PulSAR ADC evaluation board
• EVAL-CED1Z
• Enclosed World compatible 7V DC supply
• Enclosed USB to mini USB cable
• DC source (low noise for checking different input ranges)
• AC source (low distortion)
• Band pass filter suitable for 16 or 18 bit testing (value based
on signal frequency)
Preliminary Technical Data EVAL-AD76XXEDZ
• PC operating Windows XP.
Proceed to the Software Installation section to install the
software. Note: The EVAL-CED1Z board must not be
connected to the PC’s USB port until the Software is
installed. The 7V DC supply can be connected however to
check the board has power (green LED lit).
SOFTWARE INSTALLATION
It is recommended to close all Windows’ applications prior to
installing the software.
System Requirements
• PC operating Windows XP.
• USB 2.0 (for CED board)
• Administrator privileges
CD-ROM –Navigate to Software\CED Version x.x, double click
on setup.exe and follow the instructions on the screen. If
another version of Analog Devices PulSAR Evaluation Software
is present, it may be necessary to remove this. To remove, click
on the Windows “Start” button, select “Control Panel” and “Add When installed properly, Windows displays the following.
or Remove Programs”. When the list populates, navigate to
Analog Devices High Resolution sampling ADC’s Evaluation
Software or PulSAR Evaluation Software and select Remove.
Website Download
The software versions are also available from the Analog
Devices PulSAR Analog to Digital Converter Evaluation Kit
page. After downloading the software, it is recommended to use
the WinZip “Extract” function to extract all of the necessary
components as opposed to just clicking on setup.exe in the
zipped file. After extracting, click on seteup.exe in the folder
created during the extraction and follow the instructions on the
screen. If another version exists, it may be necessary to remove
as detailed in the above CD-ROM section.
USB Drivers
The software will also install the necessary USB drivers. After
installing the software, power up the CED board and connect to
the PC USB 2.0 port. The Windows “Found New Hardware” On some PCs, the Found New hardware Wizard may show up
Wizard will display. Click on Next to install the drivers again and if so follow the same procedure to install it properly.
automatically.
The “Device Manager” can be used to verify that the driver was
installed successfully.

Troubleshooting the Install

If the driver was not installed successfully the device manager
will display a question mark for “Other devices” as Windows
does not recognize the CED1Z board.

Rev. PrB | Page 5 of 23

EVAL-AD76XXEDZ
The “USB Device” can be opened to view it’s uninstalled
properties.
This is usually the case if the software and drivers were installed
by a user without administrator privileges. If so, log on as an
administrator with full privileges and reinstall the software.
RUNNING THE EVALUATION SOFTWARE
The evaluation board includes software for analyzing the
AD7682, AD7689, AD7699 and AD7949. The EVAL-CED1Z is
required when using the software. The software is used to
perform the following tests:
Rev. PrB | Page 6 of 23
Preliminary Technical Data
• Histogram for determining code transition noise (DC)
• Fast Fourier transforms (FFT) for signal to noise ratio
(SNR), SNR and distortion (SINAD), total harmonic
distortion (THD) and spurious free dynamic range (SFDR)
The software is located at C:\Program Files\Analog Devices\
PulSAR ADC Evaluation Software\Eval PulSAR CED.exe.
A shortcut is also added to the Windows “Start” menu under
“Analog Devices PulSAR ADC Evaluation Software”, “Eval
PulSAR CED”. To run the software, select the program from
either location.
SETUP SCREEN
Figure 2 is the setup screen where ADC device selection, test
type, input voltage range, sample rate and number of samples
are selected.
DC TESTING - HISTOGRAM
Figure 4 shows a screen shot for the histogram screen. This tests
the ADC for the code distribution for DC input and computes
the mean and standard deviation, or transition noise of the
converter and displays the results. Raw data is captured and
passed to the PC for statistical computations. To perform a
histogram test, select “Histogram” from the test selection
window and click on the “Start” radio button. Note: a histogram
test can be performed without an external source since the
evaluation board has a buffered VREF/2 source at the ADC input
for unipolar parts and at 0V for bipolar devices. To test other
DC values, apply a source to the J1/J2 inputs. It is advised to
filter the signal to make the DC source noise compatible with
that of the ADC. C26/C41 provide this filtering.
AC TESTING
Figure 6 is a screen shot of the fast Fourier transform, FFT. This
tests the traditional AC characteristics of the converter and
displays an FFT of the result. As in the histogram test, raw data
is captured and passed to the PC where the FFT is performed
thus displaying SNR, SINAD, THD and SFDR. The data can also
be displayed in the time domain. To perform an AC test, apply a
sinusoidal signal to the evaluation board at the SMB inputs J1
for IN+ and J2 for IN-. Low distortion, better than 100dB, is
required to allow true evaluation of the part. One possibility is
to filter the input signal from the AC source. There is no
suggested bandpass filter but consideration should be taken in
the choice. Furthermore, if using a low frequency bandpass
filter when the full-scale input range is more than a few Vpp, it
is recommended to use the on board amplifiers to amplify the
signal, thus preventing the filter from distorting the input
signal.
Preliminary Technical Data EVAL-AD76XXEDZ
Table 1. CNVST Generation, Analog Input Range
Part Resolution Sample Rate Analog Input Range Analog Input Type
(bits)
AD7621 16 3 MSPS 0 to 2.5V Diff, Unipolar
AD7622 16 2 MSPS 0 to 2.5V Diff, Unipolar
AD7623 16 1.33 MSPS 0 to 2.5V Diff, Unipolar
AD7641 18 2 MSPS 0 to 2.5V Diff, Unipolar
AD7643 18 1.25 MSPS 0 to 2.5V Diff, Unipolar
AD7650 16 100 kSPS 0 to 2.5V Single Ended, Unipolar
AD7651 16 100 kSPS 0 to 2.5V Single Ended, Unipolar
AD7652 16 500 kSPS 0 to 2.5V Single Ended, Unipolar
AD7653 16 1 MSPS 0 to 2.5V Single Ended, Unipolar
AD7660 16 100 kSPS 0 to 2.5V Single Ended, Unipolar
AD7661 16 100 kSPS 0 to 2.5V Single Ended, Unipolar
AD7663 16 250 kSPS -5V to +5V1 Single Ended, Bipolar
AD7664 16 570 kSPS 0 to 2.5V Single Ended, Unipolar
AD7665 16 570 kSPS -5V to +5V Single Ended, Bipolar
AD7666 16 500 kSPS 0 to 2.5V Single Ended, Unipolar
AD7667 16 1 MSPS 0 to 2.5V Single Ended, Unipolar
AD7671 16 1 MSPS -5V to +5V Single Ended, Bipolar
AD7674 18 800KSPS 0 to 5V Diff, Unipolar
AD7675 16 100 kSpS 0 to 2.5V Single Ended, Unipolar
AD7676 16 500 kSPS 0 to 2.5V Single Ended, Unipolar
AD7677 16 1 MSPS 0 to 2.5V Single Ended, Unipolar
AD7678 18 100KSPS 0 to 5V Diff, Unipolar
AD7679 18 571KSPS 0 to 5V Diff, Unipolar
1
Available Input Ranges are 0 to 2.5V, 0 to 5V, 0 to 10V, +/- 2.5V, +/-5V, and +/- 10V. however the board is factory configured for the +/-5V input range. Modify S1 to S7
accordingly (see schematics and datasheets) for different input range configuration.

Rev. PrB | Page 7 of 23

EVAL-AD76XXEDZ Preliminary Technical Data
Table 2. Jumper Description
Jumper Name Default Function
Position
JP1, JP2 BUFF BUFF Buffer amplifier: BUFF = use op amps to buffer analog input. NO BUFF = direct input from J1,
J2 (SMB).
JP3 VDRV- -12V Buffer amplifier negative supply: Selection of -12V, -5V or GND when using EVAL-CED1Z or
voltages on SJ1 in stand alone mode.
JP4 REFS REF Reference selection: REF = use on board reference output for ADC reference. VDD = use
analog supply (AVDD) for ADC reference.
JP6 OVDD 3.3V ADC digital output supply voltage: Selection of 2.5V, 3.3V and VDIG. VDIG = +5V when using
EVAL-CED1Z or voltage on SJ2 in stand-alone mode.
JP7 VREF+ +12V Reference circuit positive supply: Selection of +12V, +5V or AVDD when using EVAL-CED1Z or
voltages on SJ1 in stand alone mode.
JP8 VDRV+ +12V Buffer amplifier positive supply: Selection of +12V, +5V or AVDD when using EVAL-CED1Z or
voltages on SJ1 in stand alone mode.
JP9 DVDD VDIG/2.51 ADC digital supply voltage: Selection of +2.5V or VDIG (+5V) when using EVAL-CED1Z or
voltage on SJ2 in stand-alone mode.
JP19 AVDD +5V/2.51 ADC analog supply voltage: Selection of +2.5V, +5V or EXT when using EVAL-CED1Z
JP20 REFB BUF Reference buffer: BUFF = use U2 to buffer or amplify reference source. NO BUFF = use
reference directly into ADC.
JP21 VIO 3.3V Gate array I/O voltage: Selection of 3.3V or OVDD. Note: gate array will be damaged if >3.3V
(ie. when using OVDD = VDIG).
JP22 CNVST INT CNVST source: INT = use gate array to generate CNVST. EXT = use external source into J3, SMB
for CNVST.
1
For AD7621/22/23//25/41/43 these are set to +2.5V. Note that setting these to +5V will permanently destruct the ADC.
Table 3. S16 - Configuration Select Switch Description
Note: (OFF = LOW, ON = HIGH)
Position Name Default Function
Position
1 WARP LOW Conversion mode selection: Used in conjunction with IMPULSE. When HIGH with IMPULSE=
LOW, the fastest (Warp) mode is used for maximum throughput. When LOW and IMPULSE =
LOW, Normal mode is used.
2 IMPULSE LOW Conversion mode selection: Used in conjunction with WARP. When HIGH with WARP = LOW, a
reduced power mode is used in which the power consumption is proportional to the
throughput rate.
3 BIP LOW For future use.
4 TEN LOW For future use.
5 A0/M0 LOW A0, input Mux selection: Used for AD7654/AD7655 (refer to datasheet).
M0, data output interface selection: Used along with M1 for 18-bit ADCs.
6 BYTE/M1 LOW BYTESWAP, used for 8-bit interface mode on 16-bit ADCs: MSByte is swapped with LSByte on 8
data lines.
M1, data output interface selection: Used along with M0 for 18-bit ADCs.
7 OB/2C HIGH Data output select: LOW = Use 2’s complement output. HIGH = Straight binary output.
8 SER/PAR LOW Data output interface select: LOW = Parallel interface. HIGH = Serial interface.
9 EXT/INT LOW Serial clock source select: LOW = Use ADC internal serial clock, SCLK is an output. HIGH= Use
external clock, which is MCLK (40 MHz) and SCLK is an input. Not used in parallel reading mode.
10 INVSYNC LOW Serial sync (SYNC) active state: LOW = SYNC is active HIGH. HIGH = SYNC is active LOW. Used
only for Master mode (internal SCLK). Not used in parallel reading mode.
11 INVSCLK LOW Serial clock (SCLK) active edge: LOW = Use SCLK falling edge. HIGH = Use SCLK rising edge.
Active in all serial modes. Not used in parallel reading mode.
12 RDC LOW Read during convert: LOW = Read data after conversion (BUSY = LOW). HIGH = Read data
during conversions (BUSY = HIGH). Used in both parallel and serial interface modes.

Table 4. S35 - Configuration Select Switch Description

Note: (OFF = LOW, ON = HIGH)

Rev. PrB | Page 8 of 23

Preliminary Technical Data EVAL-AD76XXEDZ
Position Name Default Function
Position
1 RESET LOW Reset ADC: LOW = Enables the converter. HIGH = Abort conversion (if any).
2 PD LOW Power down: LOW = Enables the converter . HIGH = Powers down the converter. Power
consumption is reduced to a minimum after the current conversion.
3 PDBUF LOW Internal reference buffer power down: LOW = Enable on chip buffer. HIGH = Power down
internal buffer.
4 PDREF LOW Internal reference power down: LOW = Enable on chip reference. HIGH = Power down internal
reference. Note that when using the on chip reference, the buffer also needs to be enabled
(PDREF = PDBUF = HIGH).

Table 5.Test Points

Test Available Type Description
Point Signal
TP1 BUSY Output BUSY signal.
TP2 A0/M0 Input Same as S16, position 5
TP3 SIG+ Input Analog +input.
TP4 AGND GND Analog ground close to SIG+.
TP5 REF Input/Output Reference input. Output for devices with on-chip reference.
TP7 DGND GND Digital ground near SJ2.
TP8 CNVST Input CNVST signal.
TP9 AGND GND Analog ground close to REF.
TP10 CS Input CS, chip select signal.
TP11 RD Input RD, read signal.
TP12 OVDD Power Digital output supply.
TP13 DVDD Power Digital core supply.
TP14 AVDD Power Analog supply.
TP15 AGND GND Analog ground close to SIG-.
TP16 SIG- Input Analog –input for differential parts.
TP17 SCLK Input/Output Buffered serial clock.
TP18 SYNC Output Buffered serial sync.
TP19 SDOUT Output Buffered serial data.
TP20 TEMP Output TEMP, for ADC with internal reference. Outputs temperature dependant voltage (approx.
300mV with TA = 25°C).
TP22 REFIN Input/Output For ADCs with internal reference, REFBUFIN can be used to connect external reference into
the reference buffer input when PDBUF = LOW and PDREF = HIGH. With the internal
reference (and buffer) enabled, this pin will produce the internal bandgap reference voltage.
TP23 BVDD Output Internal reference bandgap supply. Connected to AVDD via s19.
T3 SDOUT Output Direct ADC serial data.
T4 SCLK Input/Output Direct ADC serial clock.
T5 SYNC Output Direct ADC serial SYNC.
T6 RDERROR Output Direct ADC serial read error.

Rev. PrB | Page 9 of 23

EVAL-AD76XXEDZ
Figure 2. Setup Screen
1. The arrow is used to start the software. When running
is displayed.
2. The part to be evaluated is selected here.
3. The controls are used to set:
Sample Frequency – Enter in kHz Units can be used such as 3k
(case sensitive) for 3,000,000 Hz or 3MSPS.
Clock Source - Selections between control (capture) board or
evaluation board.
Mode – This selects the conversion mode of operation. Some
ADCs have different modes Warp, Normal, and Impulse.
Cnv Mode – Conversion mode; this selects between continuous
(Cont.) or Burst conversion modes. In continuous mode, the
ADC is continuously converting. In Burst mode, the ADC is not
converting (sample clock held in inactive state) and the
conversions begin once the “Single Capture” or “Continuous
Capture” buttons have been selected.
Interface mode – This selects the digital interface to the on-
board FPGA.
Byteswap – A subset of the digital interface mode, this is used
to demonstrate byte-wide transfers to the FPGA.
Rev. PrB | Page 10 of 23
Preliminary Technical Data
1
Coding – Another subset to the digital interface mode, this can
be used to select straight binary or 2’s complement output. Note
the time domain chart and data output (F5) plots and saves data
in straight binary.
Reset – Resets the ADC.
PD, PDREF, PDBUF – These can be used to power down the
ADC, internal reference and internal reference buffer.
4. These controls are used for saving, printing, help, etc. and are
also accessed in the File menu.
Save (F5): type – LabView config, allows the current
configuration to be saved to a filename.dat file. Useful when
changing many of the default controls. To load the saved
configuration, use the Load Previous Configuration.
Type – Html, saves the current screen shot to an Html file.
Type – Spreadsheet, saves the current data displayed in the chart
in a tab delimited spreadsheet. Raw ADC Data is time domain
in Codes, FFT or Decimated is in dB.
5. Stop (F10) is used to stops the software. The can also be
used to stop the software. RESET is used to reset the CED or
ECB capture boards.
Preliminary Technical Data EVAL-AD76XXEDZ

Figure 3. Context Help

2

1. To use the on-screen help. Select Help, Show Context Help or

click the Help (F1). An example of the Context Help is shown , are used to set axes properties such as format,
above for the Sample Frequency. Placing the curser on most precision, color, etc. Right mouse click to change to
screen items displays useful help for the particular control or Hexadecimal, number of digits, etc.
displayed unit.
Displays the cursor.
2. These controls are used for axes and zooming panning.
Is used For zooming in and out.
Locks the graph axis to automatically fit the data.
Is used for panning.
Uses last axis set by user. , rescale the axes to the
automatic values.
Is used to set various graph properties such as graph
type, colors, lines, etc.

Rev. PrB | Page 11 of 23

EVAL-AD76XXEDZ Preliminary Technical Data
1

Figure 4. Histogram Screen

3 2

1. These radio buttons are used to perform a Single Capture or

Continuous Capture of data set in the # of Samples field. The
results are displayed in the chart. Note that the results can be
displayed as:

Or an (time domain)
2., 3.These display the statistics for the X and Y-axes,
respectively.

Rev. PrB | Page 12 of 23

Preliminary Technical Data EVAL-AD76XXEDZ

Figure 5. Summary

The charts can be displayed together when the tab is selected.

Rev. PrB | Page 13 of 23

EVAL-AD76XXEDZ Preliminary Technical Data
1

Figure 6. FFT Spectrum

1 3 2

1. Displays the FFT when the Spectrum chart is selected

2., 3. Display the data for the X and Y-axes, respectively.
.

Rev. PrB | Page 14 of 23

Preliminary Technical Data EVAL-AD76XXEDZ

Figure 7. Oscilloscope

1. Time domain data can be viewed with the oscilloscope also.

Rev. PrB | Page 15 of 23

 1 2 3 4 5 6

TP14
AVDD
AVDD
EVAL-AD76XXEDZ

NOTE:
U5B
EITHER U5A OR U5B AVDD
VREF+
IS USED AT A TIME AD158X
3 1 C9B C9T
D IN OUT TP13 TP12 D
.1uF .1uF
C27

GND
DVDD OVDD
.1uF
GND

2
DVDD OVDD
C60

2
GND DVDD OVDD
GND C5B C5T C7B C7T
REFOUT BUF JP20
6 R10 R37 REFB .1uF .1uF .1uF .1uF

+VIN
VOUT
AVDD 10K VREF+ 6 VCM
A BUF
GND REF 7 GND GND
U2B

8
VREF+ U5A JP4
VREF+ ADR43X 2 5
VDD A REFS
GND 1 C25
GND U2A C8
3 5 R4 3 .1uF
TEMP TRIM NOBUF 10uF OVDD DVDD AVDD

GND
2.5/3v
4
-VS C28 10K AD8032AR
C6
GND

4
8
C29 1uF C59
-VS .1uF .1uF REF
+VA C9

18
19
2
1
20
17

GND U1
C64 R9 1uF
+VA TP9 GND

AGND
TP5

OVDD
DVDD
AVDD
AGND
DGND
DGND

D[0..15]
REF D[0..15]
9 D0
GND GND D0
10 D1
D1
REF 37 11 D2
REF D2/DIVSCLK(0)
12 D3
S31 D3/DIVSCLK(1)
13 D4
C D4/EXT/INT C
DAC+ NOTE: 14 D5
DAC+ D5/INVSYNC
C32B 15 D6
ANY PASSIVE COMPONENTS WITHOUT VALUE C31B D6/INVSCLK
S32 C31T 16 D7
ARE NOT POPULATED 1uF D7/RDC/SDIN
47uF 21 D8
D8/SDOUT
AIN+ VCM 38 22 D9
AIN+ REFGND D9/SCLK
23 D10
TP3 GND S30 D10/SYNC
24 D11
C19 SIG+ D11/RDERROR
25 D12
EVALUATION BOARD SCHEMATICS AND ARTWORK

D12
S12 S13 26 D13
D13
R2 VDRV+ TP22 27 D14
R3 AD76XX D14
C20 VBG 28 D15
D15
0 VDRV+ R96 REFOUT
GND .1uF
GND 0.0 S11 35 CNVST

7
J1 R1 2 R46 R48 CNVST CNVST
TP4 AIN+ R90 NOBUF SIG+ IN_D 43 29 BUSY
6 IN_D/IN+ BUSY BUSY
GND R5 R31 U6A IN_C 42
3 BUF 0.0 15 IN_C
0.0 JP1 AVDD IN_B 41 3 A0

4
5 SIG+ S1 S2 S4 S6 S15 IN_B/INB2 A0 A0
0.0 49.9 S14 S18 IN_A 40 31 RD
VCM C34 IN_A/INBN RD RD
R7 AD8021 S19 INGND 39 32 CS
VCMT INGND/IN-/INB1 CS CS
VCMT 47
PDREF/T0 PDRT0
C53 590 10pF-NPO C40 36
GND

Rev. PrB | Page 16 of 23

S34 T0/PDREF T0PDR
.1uF R6 C22 46 30
C26 TP23 REFIN/INA1 T1/EOC T1/EOC
590 44 48

Figure 8. Schematic, Analog

INA2 PDBUF/T1 PDBT1
45
BVDD INAN/TEMP
VDRV- .1uF GND
B B
PD
BYTESWAP
RESET
SER/PAR
IMPULSE
WARP
OB/2C A/B

GND
S17
4
8
7
6
5

34
33

R35 R44 TEMP

S21
C13
TEMP
S3 S5 S7 S20 S8
-VS +VS GND
TP20 OB/2C
C38 TEMP
DAC- WARP
DAC- S10 IMPULSE
IMPULSE
SER/PAR
S33 SER/PAR
RESET
AIN- GND RESET
AIN-
BYTE/M1
C56 PD
C36 S9 C55 PD

VDRV+ C37
C39
R43 R42 .1uF
GND
49.9 GND SIG-

7
J2 GND R59 2 NOBUF R45 R47
AIN- R91 SIG-
6
TP15 R61 R34 U7A
3 BUF 0.0 15
AGND 0.0 R97

4
0.0 49.9 5 JP2
0.0
A VCM C35 A
R60 AD8021
EVAL-AD76XXCB
C52 590
GND C42 10pF-NPO
.1uF R29 TP16
C41
590 VDRV- SIG-
VDRV- .1uF GND ANALOG

GND 8-Feb-2005 Rev. : J M.M

1 2 3 4 5 6
Preliminary Technical Data
 1 2 3 4 5 6

3.3V 3.3V
8 6
3.3V CASC 3.3V
7
3.3V C16
3.3V D[0..15] U10A 4 R38 R39 R40
D[0..15] CS 1K 1K .1uF
D0 26 125 DATA 1 1K
TP8 D0 DATA DATA U11
CNVOUT D1 25 3
R36 CNVST D1 OE
D2 T1 24 EPC1441
JP22 INT 1M D2
JP11 D3 T2 23 128 DCLK 2 5
CNV SEL D3 DCLK DCLK GND
D4 22
D CNVST D4 D
CNVST D5 21 105 CONF_D
D5 CONF_D GND
D6 16 56 STATUS
A EXT R83 D6 STATUS
J3 D7 15 53 CONFIG
D7 CONFIG
CNVSTIN D8 T3 14 4
R28 R30 D8 CE
TP21 D9 T4 12 33
100 100 GND D9 MSEL
D10 T5 11 GND P3A
TP10 TP11 TP1 D10
D11 T6 10 107 BD-1 BD15 C19
CS RD BUSY D11 BD-1
D12 144 108 BD-2 BD15 BD14 C18
GND D12 BD-2 1 2
D13 143 129 BD0 BD14 BD13 B18
GND D13 BD0 3 4
D14 142 124 BD1 BD13 BD12 A18
D14 BD1 5 6
3.3V D15 141 123 BD2 BD12 BD11 B17
D15 BD2 7 8
D9 13 120 BD3 BD11 BD10 B15
SCLKIN BD3 9 10
140 117 BD4 BD10 BD9 B14
R85 BUSY BUSY BD4 11 12
Preliminary Technical Data

P3B 139 115 BD5 BD9 BD8 B13

10K RD RD BD5 13 14
A32 +VA 138 112 BD6 BD8 BD7 B11
CS CS BD6 15 16
B32 137 110 BD7 BD7 BD6 B10
+VA CNVST BD7 17 18
C32 CNVOUT R68 134 109 BD8 BD6 BD5 B9
R86 CNVSTOUTB BD8 19 20
A31 -VA 49.9 2 94 BD9 BD5 BD4 B7
CNVSTOUT BD9 21 22
B31 49.9 BYTE/M1 39 87 BD10 BD4 BD3 B6
-VA BYTE/M1 BYTE BD10 23 24
C31 +12V RESET 136 84 BD11 BD3 BD2 B5
RESET RESET BD11 25 26
C30 WARP 37 72 BD12 BD2 BD1 B3
+12V C57 WARP WARP BD12 27 28
A8 VDIG OB/2C 38 81 BD13 BD1 BD0 B2
OB/2C OB/2C BD13 29 30
B8 TP2 SER/PAR 35 82 BD14 BD0 AD2 C14
VDIG A0 SER/PAR SER/PAR BD14 31 32
C8 -12V IMPULSE 36 73 BD15 DBUSY AD1 A14
C GND IMPULSE IMPULSE BD15 33 34 C
A30 PD 135 BD-1 AD0 C15
-12V PD PD 35 36
A4 A0 A0/M0 57 85 BBUSY D2 BD-2 BCS C10
A0 A0 BBUSY 37 38
A12 40 DBUSY BCS BBUSY C17
S24 S26 DBUSY 100 TP6 39 40
A16 PDRT0 PDREF 58 49 ADCOK BRD A9
PDRT0 PDREF ADCOK GND
A20 VIO R80 P2 BWR C9
S22
B4 R41 1K RESETD A17
B12 S16A 131 FSYNC CONTROL B1
S25 FSYNC SYNC-FFT
B16 WARP R15 1 24 BIP 59 R67 10K SDIN A5
WARP T0PDR TEST0
B20 10K TFS0 A6
S23 10K
C4 R33 111 BCS R51 DSPCLK A19
BCS R53
C12 1K S16B 10K SDOUT C5
R19 10K
C16 IMPULSE 2 23 60 130 CONTROLR52 SCLK C7
IMPULSE EOC CONTROL
C20 10K R82 SYNC C6
R69 10K GND
B26 43 RESETS R56 DAC+ A27
10k RESETS DAC+
B27 1K S16C DAC- C27
S28 GND DAC-
B28 BIP R20 3 22 R32 TEN 61 86 RESETD R57 10K
BIPOLAR T1/EOC TEST1_OUT RESETD
B29 10K 100
S27
B30 R70 T1 113 BRD R58 10K GND
PDBT1 BRD
C21 1K S16D VIO 3.3V
S29 R66 10K
R21

Rev. PrB | Page 17 of 23

C22 TEN 4 21 TEN PDBUF 62 114 BWR VIO 3.3V
VIO PDBUF BWR
C23 10K S16G
10K

Figure 9. Schematic, Digital

C24 R71 18 7 R11 OB/2C 44 M3 R62 3.3V
OB/ 2C MODE3
C25 1K S16E 10K R54 R55
7
19
32
55
78
91
104
127
6
31
77
103

R22 R72 10K 10K 10K R63

B C26 A0/M0 5 20 VIO 45 M2 B
A0/M0 MODE2 C21 C23 C24 C3
C29 10K S16H 1K
10K .1uF .1uF .1uF .1uF
R76
VIO
VIO
VIO
VIO
VIO
VIO
VIO
VIO

R12 R64
3.3V
3.3V
3.3V
3.3V

A21 17 8 SER/PAR 46 M1
SER/PAR JP14 GND MODE1
A22 1K S16F 10K
R65 EPF6010ATC144
BYTE/M1 R81 6 19 R73 47 M0 10K GND
BYTE/M1 MODE0
10K S16I 1K 95 AD2
R77 R13 AD2 GND
P3C 16 9 D4 TEMP 41 96 AD1 U10B
EXT/ INT TEMP TEMP AD1
B25 1K 10K 93 AD0
AD0
GND
GND
GND
GND
GND
GND
GND
GND

B24 R74 VIO

S35A S16J
5

B23 1K 116 SCLK TP17

18
30
54
76
90

SCLK0
126
102

B22 RESET R88 1 8 RESET 15 10 R17 D5 118 TFS0 SCLK

INVSYNC TFS0 C17 C18 C5 C7 C4 C10 C11 C12
B21 10K 10K 119 SYNC TP18
R92 R75 RFS0 SYNC .1uF .1uF .1uF .1uF .1uF .1uF .1uF .1uF
A29 121 SDIN
DT0 GND
A26 1K S35B S16K 1K 122 SDOUT
DR0 TP19
A25 PD R89 2 7 14 11 R16 D6 SDOUT GND
PD INVSCLK
A24 10K 10K 71 DSPCLK U12 3.3V
R93 DSPCLK R49
A23 R78 69 3 4
MCLK OUT VDIG
1K S35C S16L 1K 0 TP7
R100 R14 C47 GND
PDBUF 3 6 RDC 13 12 D7 EPF6010ATC144-3 C30
GND PDBUF
10K 10K 3.3V .1uF
R98 R79 1 2
GND VDIG GND
1K S35D 1K GND
PDREF R101 4 5 GND GND
PDREF
10K
A R99 A
1K
GND EVAL-AD76XXCB

DIGITAL

8-Feb-2005 Rev. : J M.M

1 2 3 4 5 6
EVAL-AD76XXEDZ
 1 2 3 4 5 6

-VS
-VS
+VA
+VA
EVAL-AD76XXEDZ

-12V
D -12V D
OVDD -VA
-VA
+VA
R84
0 +VA
+12V
+12V
VDIG 3.3V JP21 VIO
JP6 3.3V
2.5V VIO
1
2 4 VREF+
VREF+
3 C14 3.3V
D1 10uF 3.3V
C48
10uF

VIO
GND VIO
OVDD
AVDD OVDD
GND DVDD
DVDD
VDIG AVDD
AVDD
R27 GND
GND
JP9 DVDD
1 VDIG
3 VDIG
2
C49
C 10uF C

GND SJ1 JP3

1 -12V 1 VDRV-
U5 -12V
2 4
VDIG ADP3334ARM VDRV-
2 -VA 3
8 1 -5V C50
IN OUT 10uF
3 +VA
7 2 R8 +5V
IN OUT C33 106.1k GND
1uF 4 +12V
4 3 +12V JP8
C32 NC

GND
SD
FB
VDIG 1uF VDRV+
5 EXT

5
6
EXT
VDRV+
R24 6 C54
VDIG GND 10uF
SJ2 94.5k
GND JP7
VREF+
GND
GND
GND C51

Rev. PrB | Page 18 of 23

U4
VDIG ADP3334ARM 3.3V 10uF

Figure 10. Schematic, Power

GND 8 1 U8 JP19
IN OUT ADP3334ARM
+VA 3 AVDD GND
B 7 2 R23 8 1 2 4 B
IN OUT C46 IN OUT
140K 1
1uF C2
4 3 7 2 R18
C1 C45 NC

GND
SD
FB IN OUT C44 10uF
10uF 1uF 106.1k
1uF

5
6
4 3
C43 NC FB
GND
R26 SD GND
1uF
78.7K
5
6
-VA -12V
GND
R25
94.5k JP5
GND 3 -VS
GND 2 4
1
GND C15
10uF
GND
+12V GND

JP10
+VS
2
3
EXT 1
C31
10uF

GND
A A

EVAL-AD76XXCB

POWER

8-Feb-2005 Rev. : J M.M

1 2 3 4 5 6
Preliminary Technical Data
Preliminary Technical Data EVAL-AD76XXEDZ

Figure 11. Top Side Silk-Screen

Figure 12. Top Layer

Rev. PrB | Page 19 of 23

EVAL-AD76XXEDZ Preliminary Technical Data

Figure 13. Ground Layer

Figure 14. Shield Layer

Rev. PrB | Page 20 of 23

Preliminary Technical Data EVAL-AD76XXEDZ

Figure 15. Bottom Side Layer

a
Figure 16. Bottom Side Silk-Screen

Rev. PrB | Page 21 of 23

EVAL-AD76XXEDZ Preliminary Technical Data

Table 6. Bill of Materials for the Connectors

Ref Des Connector Type Manf. Part No.
J1 – J3 RT Angle SMB Male Pasternack PE4177
P2 0.100 X 0.100 straight IDC header 2X20 3M 2540-6002UB
P3 32X3 RT PC MOUNT CONNECTOR ERNI 533402

ORDERING GUIDE
These evaluation boards are compatible with both EVAL-CED1Z and EVAL-CONTROL BRDxZ. For simplicity, this document was made
especially for EVAL-CED1Z usage. Refer to Analog Devices PulSAR Evaluation Kit product page for the user’s guide specific to EVAL-
CONTROL BRDxZ usage.
Evaluation Board Model Product
EVAL-AD7621CBZ AD7621ASTZ/ACPZ
EVAL-AD7622CBZ AD7622BSTZ/BCPZ
EVAL-AD7623CBZ AD7623ASTZ/ACPZ
EVAL-AD7641CBZ AD7641BSTZ/BCPZ
EVAL-AD7643CBZ AD7643BSTZ/BCPZ
EVAL-AD7650CBZ AD7650ASTZ/ACPZ
EVAL-AD7651CBZ AD7651ASTZ/ACPZ
EVAL-AD7652CBZ AD7652ASTZ/ACPZ
EVAL-AD7653CBZ AD7653ASTZ/ACPZ
EVAL-AD7660CBZ AD7660ASTZ/ACPZ
EVAL-AD7661CBZ AD7661ASTZ/ACPZ
EVAL-AD7663CBZ AD7663ASTZ/ACPZ
EVAL-AD7664CBZ AD7664ASTZ/ACPZ
EVAL-AD7665CBZ AD7665ASTZ/ACPZ
EVAL-AD7666CBZ AD7666ASTZ/ACPZ
EVAL-AD7667CBZ AD7667ASTZ/ACPZ
EVAL-AD7671CBZ AD7671ASTZ/ACPZ
EVAL-AD7674CBZ AD7674ASTZ/ACPZ
EVAL-AD7675CBZ AD7675ASTZ/ACPZ
EVAL-AD7676CBZ AD7676ASTZ/ACPZ
EVAL-AD7677CBZ AD7677ASTZ/ACPZ
EVAL-AD7678CBZ AD7678ASTZ/ACPZ
EVAL-AD7679CBZ AD7679ASTZ/ACPZ
EVAL-CED1Z USB Capture Board

Rev. PrB | Page 22 of 23

Preliminary Technical Data EVAL-AD76XXEDZ

NOTES

©2009 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
PR07201-0-3/09(PrB)

Rev. PrB | Page 23 of 23