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With accurate
XII
readings Electronics
(C-2)
Practical Experiments Paper-II
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N O T ES S P AC E
Experiment 1–(Set-II)
Circuit diagrams –
r g
o
A B Y = A.B A B Y = A+B A Y= A
.
0 0 0 0 0 0 0 1
r
0 1 0 0 1 1 1 0
1 0 0 1 0 1
a
1 1 1 1 1 1
g
Truth tables of AND gate, OR gate & NOT gate
s a
v Pin configurations of AND gate, OR gate & NOT gate ICs
Specifications of components –
Note – write observed truth tables on left page of practical record book with pencil only.
g
signal at output, it is also called as inverter.
. o r
a r
a g
v s
Experiment 2–(Set-II)
r g
o
A B LHS = A.B A B LHS = A B RHS = A . B
.
RHS = A B
0 0 1 1 0 0 1 1
r
0 1 1 1 0 1 0 0
1 0 1 1 1 0 0 0
a
1 1 0 0 1 1 0 0
g
Truth tables for both the theorems
a
Pin configurations of the ICs –
Specifications of components –
Conclusion – in this way, we have studied the De Morgan’s both theorems and found that –
A.B A B and A B A . B
r g
r . o
g a
s a
v
Experiment 3–(Set-II)
Name– study of universal building blocks – NAND gate and NOR gate.
Aim – to study the construction of basic gates using NAND gates and NOR gates.
Apparatus – IC 7400, IC 7402, circuit board, power supply +5V DC, LED, connecting wires, soldering
iron, cutter etc.
Circuit diagrams –
r g
r . o
a
Circuit diagrams of AND gate, OR gate & NOT gate using NAND gates & NOR gates
g
Pin configurations of the ICs –
s a
v Pin configurations of NAND gate & NOR gate ICs
Specifications of components –
A B Y = A.B A B Y = A+B A Y= A
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
g
1 1 1 1 1 1
r
Theoretical truth tables of AND gate, OR gate & NOT gate
o
Brief theory –
.
1) NOT gate using NAND/NOR gates –here both input terminals of NAND/NOR gate are shorted
r
together. So input signal at terminal A will be equally distributed to both inputs of the gate. Hence, the
output will be the same as NOT gate with a single input. Thus, we have –
a
Y = A
2) AND gate using NAND/NOR gates –when two NAND gates are cascaded we get one AND gate, as
g
shown in the above left figure. Similarly when three NOR gates are connected as shown in the above
right figure, we can obtain an AND gate.
a
Y = A.B
s
3) OR gate using NAND/NOR gates –when two NOR gates are cascaded we get one OR gate, as shown
in the above right figure. Similarly when three NAND gates are connected as shown in the above left
v
figure, we can obtain an OR gate.
Y = A + B
All the ICs used in this experiment, are TTL (Transistor Transistor Logic) ICs. When the
code number printed on the body of IC, starts with 74XX series, it is called TTL IC. The
circuits of these ICs strictly run on +5V DC power supply.
Draw observed truth tables also on left page of practical record book.
Experiment 4–(Set-II)
Circuit diagram –
r g
o
Pin configurations of the ICs –
r .
g a
s a
v Pin configurations of AND gate, OR gate, NOT gate& Ex-OR gate ICs
Specifications of components –
Type of component
IC 7404
Specifications
Hex inverter, NOT gate
IC 7408 Quad 2–input AND gate
IC 7432 Quad 2–input OR gate
IC 7486 Quad 2–input Ex-OR gate
Resistors 330, ¼W, carbon composition, 5% tolerance
LED Color: RED, VF = 1.65V
Diodes 1N4001 rectifier diode
Capacitor 1000F/25V electrolytic capacitor
Transformer 6V–0V–6V, 500mA secondary transformer
IC 7805 +5V, 3–terminal regulator IC
g
0 1 1 1 0 1 0 0
r
1 0 1 1 1 0 0 0
1 1 0 0 1 1 1 0
. o
Brief theory – to construct the Ex-OR gate using basic gates above circuit is used. Here one of each inputs
of both AND gates are bubbled and other inputs are direct. Its output equation with step-by-step
r
mathematical treatment is given as follows. Let outputs (Y1) and (Y2) are the outputs of NOT gates, given
by –
g aY1 A and Y2 B
Similarly, outputs of both AND gates are given by –
Y3 Y1.B and Y4 Y2 .A
a
i.e.
Y3 A.B and Y4 A.B
s
These outputs of AND gates are inputs of OR gate. Thus, we get –
v
Y Y3 Y4
Conclusion –
1) Ex-OR gate can be constructed using 2–NOT gates, 2–AND gates and 1–OR gate.
2) When one more NOT gate is connected at the output of Ex-OR gate, the circuit can be converted
into Ex-NOR gate. Its output equation is given by Y A .B A.B
3) The IC 7486 was tested and found that it is Quad 2–input Ex-OR gate TTL IC.
Experiment 5–(Set-II)
Name– study of Ex-OR logic using NAND gates as universal building blocks.
Aim – to study the working of Ex-OR gate using derived gates i.e. NAND gates.
Apparatus – IC 7400 and IC 7486, circuit board, power supply +5V DC, LED, connecting wires, soldering
iron, cutter etc.
Circuit diagram –
r g
r . o
g a
Pin configurations of NAND gate& Ex-OR gate ICs
a
Theoretical & observed truth tables –
s
A B Y=AB A B Y=AB
0 0 0
v
0
0 1 1 1
1 0 1 1
1 1 0 0
Specifications of components –
Exclusive-OR gate – it is a very special type of gate in digital electronics. It is a logic circuit whose output
becomes high only when its both inputs are UNEQUAL. Its logic equation is –
g
b) When A = 0, B = 1, Y = A.B A.B = 1
c) When A = 1, B = 0, Y = A.B A.B = 1 A B Y=AB
r
d) When A = B = 1, Y = A.B A.B = 0 0 0 0
0 1 1
o
1 0 1
.
1 1 0
r
Symbol & truth table of Ex–OR gate
a
Ex-OR gate using NAND gates –
The output of left NAND gate, Y1 is given by –
g
Y1 A.B
a
Now outputs of middle NAND gates, Y2 and Y3 are given by –
Y2 A.Y1 A. A.B and Y3 B.Y1 B. A.B
s
Finally, the last output Y is given by –
v
Y Y2 .Y3 A.( A.B) . B.(A.B)
To make the calculations simple, suppose –
C A.( A.B) and D B.(A.B)
From above equation, we get –
Y A.( A.B) B.( A.B)
Y A.( A.B) B.( A.B)
Now applying the De Morgan's theorem to the inner brackets, we get –
Y A.( A B) B.(A B)
Y A.A A.B B.A B.B
Y A.B A.B
Conclusion –
1) We constructed an Ex-OR gate using four NAND gates. Thus, we found that the NAND gate acts as
universal building block.
2) The IC 7486 was tested and found that it is Quad 2–input Ex-OR gate TTL IC.
Experiment 6–(Set-II)
Circuit diagram –
r g
Pin configurations of the IC –
r . o
g a
a
Pin configurations of Ex-OR gate IC
s
Observation table –
Control Data input Data output
v
Specifications of components –
input
0
0
1
1
P Q R S A B C D
1 1 0 0 1 1 0 0
1 0 1 1 1 0 1 1
1 1 0 1 0 0 1 0
1 1 1 1 0 0 0 0
Brief theory –
becomes high only when its both inputs are UNEQUAL. Its logic equation is –
r g
Exclusive-OR gate – it is a very special type of gate in digital electronics. It is a logic circuit whose output
o
Y=AB or Y A.B A.B
.
The Ex–OR addition rules for all possible combinations of inputs are –
a) When A = B = 0, Y = A.B A.B = 0
b) When A = 0, B = 1, Y = A.B A.B = 1
c) When A = 1, B = 0, Y = A.B A.B = 1
d) When A = B = 1, Y = A.B A.B = 0
a rA B Y=AB
0
0
0
1
0
1
g
1 0 1
1 1 0
Controlled inverter – the Ex-OR gate can be used as controlled inverter circuit. When input of single Ex-
v
OR gate is permanently connected to logic–1 level & other input–A is variable (either 1 or 0) then by the
basic property of Ex-OR gate, if A = 0 then Y = 1 & if A = 1, then Y = 0. This is possible only when one
input of Ex-OR gate is high. This result is equivalent to NOT gate. Hence, Ex-OR gate can be used as
controlled inverter i.e. controlled NOT gate.
Now as shown in above figure, a group of four Ex-OR gates are used as controlled inverter circuit. It
produces following results –
When DCBA = 1010 and control input = 0 then PQRS = 1010
When DCBA = 1010and control input = 1 then PQRS = 0101, which is the 1’s complement of 1010.
Hence, the circuit produces 1’s complement of binary number.
Thus, input condition at control input terminal decides the condition of data at output terminals of the
circuit.
Conclusion –
1) When one input of Ex-OR gate is permanently kept HIGH, then the gate works as NOT gate.
2) A number of Ex-OR gates can be used as controlled inverter, to produce the 1’s complement of
input word (binary number).
Experiment 7–(Set-II)
Circuit diagrams –
Truth tables –
RS flip-flop using NAND gates
r g
o
R S Q Q R S Q Q
.
0 0 N/C 0 0 Forbidden
r
0 1 1 0 0 1 1 0
1 0 0 1 1 0 0 1
a
1 1 Forbidden 1 1 N/C
Pin configurations –
a g
v s Pin configurations of NAND gate & NOR gate ICs
Specifications of components –
Brief theory –
RS Flip-flop using NOR gate – consider the above left-side circuit. Here two NOR gates are used such that
the output of one is the input of other. Also, one input of each gate is taken out as SET and RESET. The two
g
outputs are Q and Q .
r
As per truth table, we have four possible conditions –
1) When R = S = 0, the flip-flop does NOT change its output state. It remains in last state. Hence, it is
o
called no change (N/C) condition.
.
2) When R = 0 and S = 1, gate–1 is enabled and gate–2 is disabled. Therefore, Q = 1 and Q = 0. The
r
flip-flop is now SET.
3) When R = 1 and S = 0, gate–1 is disabled and gate–2 is enabled. Therefore, Q = 0 and Q = 1. The
a
flip-flop is now RESET.
4) When R = S = 1, both NOR gates are disabled. But practically there is race between two NOR gates.
g
Now we cannot determine output conditions. Hence, it is called FORBIDDEN state. It is also called
as the RACE condition.
s a
RS Flip-flop using NAND gates – consider the above right-side circuit. Here two NAND gates are
connected such that the output of one is the input of other. And one input of each gate is taken out as SET
and RESET input. The two outputs are Q and Q .Using the truth table, we have four conditions, as follows –
v
1) When R = S = 0, one input of each gate is HIGH. So Q = Q = 1. This is contradictory. Hence, this
state is called forbidden state of flip-flop.
2) When R = 0, and S = 1, gate–1 is enabled and gate–2 is disabled. Hence, at output we get Q = 1 and
Q = 0. The flip-flop is now SET.
3) When R = 1, and S = 0, gate–2 is enabled and gate–1 is disabled. Hence, at output we get Q = 0 and
Q = 1. The flip-flop is now RESET.
4) When S = R = 1, the flip-flop will NOT change its state and will remain in LAST STATE. Hence, it
is called no change (N/C) condition.
Conclusion –
1) In above flip-flops, the first and last states of outputs are interchanged.
2) In RS flip-flop using NOR gates, the initial state of the circuit is called LAST STATE.
3) In RS flip-flop using NAND gates, the initial state of the circuit is called FORBIDDEN STATE.
4) In both types of flip-flops, the output Q follows the state of input S.
Experiment 8–(Set-II)
Circuit diagram –
r g
. o
Circuit diagram of BCD to 7–seg decoder/driver
r
BCD
inputs
0000
a
0
g
b
0
a 7–segment coded outputs
c
0
d
0
e
0
f
0
g
1
Display
output
0
a
0001 1 0 0 1 1 1 1 1
0010 0 0 1 0 0 1 0 2
s
0011 0 0 0 0 1 1 0 3
0100 1 0 0 1 1 0 0 4
v
0101 0 1 0 0 1 0 0 5
0110 1 1 0 0 0 0 0 6
0111 0 0 0 1 1 1 1 7
1000 0 0 0 0 0 0 0 8
1001 0 0 0 1 1 0 0 9
Specifications of components –
Procedure –
1) You are given IC 7447/7448 and the 7–segment common anode LED display. Identify them with
their proper pin configurations.
2) Switch on the power supply of the circuit.
r g
3) Connect different BCD inputs from 0000 to 1001 and note down the corresponding output on the
o
display.
.
4) Tabulate the readings.
r
Note – the BCD inputs from 1010 to 1111 should not be applied
to the IC 7447. These are forbidden inputs.
a
g
Brief theory –to display the data, we have to convert it from BCD to 7-segment code. The IC makes this
process. It has four inputs called BCD inputs and seven outputs to drive the display.
a
For common anode LED display, the decoders used are IC 7446, IC 74246, IC 7447, IC 74247 etc.
They have active low, open collector outputs.
s
And for common cathode LED display, the ICs are IC 7448, IC 74248, IC 7449 etc. They have
active high, open collector outputs.
v
Working of the circuit –
1) When BCD inputs from 0000 to 1001 are applied at the input terminals, the IC produces equivalent
outputs at its output terminals from a–g. The 7–seg display is common anode type.
2) Suppose BCD input is DCBA = 0101. It is equivalent to decimal 5. This input is converted into
equivalent 7–seg code by the IC and its outputs abcdefg = 0100100. For the input DCBA = 1000, all
segments of the display will glow to show decimal 8 and outputs abcdefg = 0000000 and so on.
Conclusion –
1) When corresponding BCD inputs are applied from 0000 to 1001, we get decimal output on the
display from decimal 0 to decimal 9.
2) The tails of ‘6’ and ‘9’ are not displayed on the display.
3) To display the tails of ‘6’ and ‘9’ IC 74247 is required.
4) In common anode FND 507 type display, the anodes of all LEDs are connected to a common line
and connected to +5V regulated power supply. The cathode of each LED segment is used as input
from ‘a’ to ‘g’.
Experiment 9–(Set-II)
Circuit diagram –
r g
r . o
g a
Pin configurations of AND gate IC &Ex-OR gate IC
a
Observation table –
v s A
0
0
1
1
B
0
1
0
1
Carry = A.B
0
0
0
1
Sum = A. B A. B
0
1
1
0
Specifications of components –
Brief theory –half adder is logic circuit, which can add two binary digits at a time. In half adder, there are
two inputs A & B with two outputs SUM and CARRY. The SUM is the output of Ex-OR gate and CARRY
is the output of AND gate.
g
2) When A = 0 and B = 1,
r
Sum = A. B A. B = 0.1 0.1 = 1.1 + 0.0 = 1 + 0 = 1 & carry = A.B = 0.1 = 0, (addition = 01)
3) When A = 1 and B = 0,
o
Sum = A. B A. B = 1.0 1.0 = 0.0 + 1.1 = 0 + 1 = 1 & carry = A.B = 1.0 = 0, (addition = 01)
.
4) When A = B = 1,
r
Sum = A. B A. B = 1.1 1.1 = 0.1 + 1.0 = 0 + 0 = 0 & carry = A.B = 1.1 = 1, (addition = 10)
Conclusion –
a
1) The circuit can add any two binary digits.
2) The circuit follows the basic rules of Boolean algebra and produces following results –
g
a) 0 + 0 = 00
b) 0 + 1 = 01
a
c) 1 + 0 = 01
d) 1 + 1 = 10
v s
Experiment 10–(Set-II)
Circuit diagram –
Pin configurations of AND gate IC, Ex-OR gate & OR gate ICs
Observation table –
Procedure –
1) Solder the circuit of full adder, on the given board.
2) Connect respective pins of each gate to the corresponding pins of other gate.
3) Connect the outputs ‘sum’ and ‘carry’ to two LEDs.
4) Apply different combinations of inputs as per truth table and note down the corresponding change in
the outputs of the circuit.
5) Tabulate the readings.
Brief theory –
Possible input combinations –full adder can add three binary digits at a time. It is actually the extension of
half adder circuit. It has three inputs A, B, C with two outputs CARRY and SUM. Note that when two half
adders are cascaded along with an OR gate, we get full adder.
The logic equations of carry and sum outputs are given below –
a) carry A.B A B.C
b) sum A B C
For example, if A = 1, B = 0, C = 1, then –
carry 1.0 1 0.1 1
and sum 1 0 1 0 addition = 10
Conclusion –
1) The circuit can add any three binary digits.
2) It follows the basic rules of Boolean algebra and produces following outputs –
a) 0 + 0 + 0 = 00
b) 0 + 0 + 1 = 01
c) 0 + 1 + 1 = 10
d) 1 + 1 + 1 = 11
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