Name: Jacob Sy and Kaethryn Viloria

experiment number: 5
title: Optimizing Combinational Logic Path

Codes:

*Unoptimized
.protect

.MODEL mn NMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 7.8E-9
+XJ = 1E-7 NCH = 2.2E17 VTH0 = 0.4867759
+K1 = 0.5982003 K2 = 7.110775E-3 K3 = 74.853704
+K3B = -10 W0 = 5E-5 NLX = 2.522198E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 2.8489298 DVT1 = 0.8382014 DVT2 = -0.2705174
+U0 = 364.7816729 UA = -7.07762E-10 UB = 2.214939E-18
+UC = 3.217876E-11 VSAT = 1.427282E5 A0 = 1.0943978
+AGS = 0.1518849 B0 = 9.486928E-7 B1 = 5E-6
+KETA = 2.703951E-3 A1 = 1.331977E-4 A2 = 0.5082922
+RDSW = 1.03395E3 PRWG = -0.0999764 PRWB = -0.1019712
+WR = 1 WINT = 1.517735E-7 LINT = 0
+XL = -5E-8 XW = 1.5E-7 DWG = -3.822451E-9
+DWB = 3.625123E-9 VOFF = -0.0834415 NFACTOR = 1.4572053
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 1 ETAB = 0.0333683
+DSUB = 0.8054936 PCLM = 1.4582292 PDIBLC1 = 1.807793E-3
+PDIBLC2 = 1.210914E-4 PDIBLCB = 0.0219649 DROUT = 3.881351E-4
+PSCBE1 = 7.237622E8 PSCBE2 = 1E-3 PVAG = 0
+DELTA = 0.01 RSH = 78.9 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 3.4E-10 CGSO = 3.4E-10 CGBO = 1E-12
+CJ = 9.085053E-4 PB = 0.8 MJ = 0.3519913
+CJSW = 2.378884E-10 PBSW = 0.8 MJSW = 0.1980245
+CJSWG = 1.82E-10 PBSWG = 0.8 MJSWG = 0.1980245
+CF = 0 PVTH0 = -0.0232737 PRDSW = -96.6778453
+PK2 = 4.200437E-3 WKETA = -9.87476E-4 LKETA = -1.128415E-4 )

.MODEL mp PMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 7.8E-9
+XJ = 1E-7 NCH = 8.52E16 VTH0 = -0.6614536
+K1 = 0.4432406 K2 = -0.0123618 K3 = 55.5705007
+K3B = -4.9925721 W0 = 5.384636E-6 NLX = 2.456563E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.5822634 DVT1 = 0.6339255 DVT2 = -0.0307983
+U0 = 154.7137452 UA = 1.012464E-10 UB = 1.993677E-18
+UC = -1.28065E-11 VSAT = 1.541575E5 A0 = 1.1866041
+AGS = 0.3740281 B0 = 2.496159E-6 B1 = 5E-6
+KETA = -8.04538E-3 A1 = 5.431049E-4 A2 = 0.3497898
+RDSW = 4E3 PRWG = -0.1040295 PRWB = 0.2075363
+WR = 1 WINT = 1.526389E-7 LINT = 0
+XL = -5E-8 XW = 1.5E-7 DWG = -1.735873E-8
+DWB = 9.026191E-9 VOFF = -0.1325104 NFACTOR = 2
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 2.138549E-3 ETAB = 1.084482E-4
+DSUB = 7.47981E-3 PCLM = 3.3740219 PDIBLC1 = 0.0382188
+PDIBLC2 = 1.851992E-3 PDIBLCB = -1E-3 DROUT = 0.3134832
+PSCBE1 = 7.721166E10 PSCBE2 = 5E-10 PVAG = 0.3435962
+DELTA = 0.01 RSH = 2.6 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 2.24E-10 CGSO = 2.24E-10 CGBO = 1E-12
+CJ = 1.42554E-3 PB = 0.99 MJ = 0.5513383
+CJSW = 3.541201E-10 PBSW = 0.99 MJSW = 0.4557818
+CJSWG = 4.42E-11 PBSWG = 0.99 MJSWG = 0.4557818
+CF = 0 PVTH0 = 6.570075E-3 PRDSW = -27.3095793
+PK2 = 1.62036E-3 WKETA = 3.82077E-3 LKETA = 1.865988E-3)
.unprotect

.global vdd gnd

.subckt nand3 va vb vc vout wid=0

m1 vout va VDD VDD mp w='wid*2' l=1u

m2 vout vb VDD VDD mp w='wid*2' l=1u
m3 vout vc VDD VDD mp w='wid*2' l=1u
m4 vout va yy gnd mn w='wid*3' l=1u
m5 yy vb xy gnd mn w='wid*3' l=1u
m6 xy vc gnd gnd mn w='wid*3' l=1u
.ends

.subckt nand2 va vb vout wid=0 mf=0

m1 vout va VDD VDD mp w='wid*2' l=1u m='mf'

m2 vout vb VDD VDD mp w='wid*2' l=1u m='mf'
m4 vout va y gnd mn w='wid*2' l=1u m='mf'
m5 y vb gnd gnd mn w='wid*2' l=1u m='mf'
.ends

.subckt inv vin vout win=0 mb=0

m2 vout vin vdd vdd mp w='win*2' l=1u m='mb'
m1 vout vin gnd gnd mn w='win' l=1u m='mb'
.ends

x1 gnd vdd vout1 nand2 wid=1.7196u mf=1

x2 gnd Ci vout2 nand2 wid=1u mf=1
x3 vdd Ci vout3 nand2 wid=1u mf=1
x4 vout1 vout2 vout3 vout4 nand3 wid=1.7196u
x5 gnd vout4 vout5 nand2 wid=1u mf=1
x6 gnd vdd vout6 nand2 wid=1.848u mf=1
x7 vout4 vdd vout7 nand2 wid=3.178u mf=1
x8 vout5 vout6 vout7 vout8 nand3 wid=1u
x9 vout8 vout9 inv win=4.554u mb=1
x10 gnd vout10 inv win=9.889u mb=1
x11 gnd vout9 vout11 nand2 wid=1u mf=1
x12 vout8 vout10 vout12 nand2 wid=1u mf=1
x13 vout11 vout12 vout13 nand2 wid=1u mf=1
x14 vout13 vout14 inv win=1u mb=1
x15 vdd vout15 inv win=1u mb=1
x16 vdd vout14 vout16 nand2 wid=1u mf=1
x17 vout13 vout15 vout17 nand2 wid=1u mf=1
x18 vout16 vout17 S2 nand2 wid=1u mf=1

c1 S2 gnd 4.2p

vdd vdd gnd dc 3V

.op
.tran 0.1u 50u
.measure tran tphl trig v(Ci) val=1.5 rise=1 targ v(S2) val=1.5 fall=1
.measure tran tplh trig v(Ci) val=1.5 fall=1 targ v(S2) val=1.5 rise=1
Vcin Ci gnd pulse (0 3 0 0.1u 0.1u 5u 10u)
.print v(Ci) v(S2)
.end

*optimized
.MODEL mn NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 7.8E-9
+XJ = 1E-7 NCH = 2.2E17 VTH0 = 0.4867759
+K1 = 0.5982003 K2 = 7.110775E-3 K3 = 74.853704
+K3B = -10 W0 = 5E-5 NLX = 2.522198E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 2.8489298 DVT1 = 0.8382014 DVT2 = -0.2705174
+U0 = 364.7816729 UA = -7.07762E-10 UB = 2.214939E-18
+UC = 3.217876E-11 VSAT = 1.427282E5 A0 = 1.0943978
+AGS = 0.1518849 B0 = 9.486928E-7 B1 = 5E-6
+KETA = 2.703951E-3 A1 = 1.331977E-4 A2 = 0.5082922
+RDSW = 1.03395E3 PRWG = -0.0999764 PRWB = -0.1019712
+WR = 1 WINT = 1.517735E-7 LINT = 0
+XL = -5E-8 XW = 1.5E-7 DWG = -3.822451E-9
+DWB = 3.625123E-9 VOFF = -0.0834415 NFACTOR = 1.4572053
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 1 ETAB = 0.0333683
+DSUB = 0.8054936 PCLM = 1.4582292 PDIBLC1 = 1.807793E-3
+PDIBLC2 = 1.210914E-4 PDIBLCB = 0.0219649 DROUT = 3.881351E-4
+PSCBE1 = 7.237622E8 PSCBE2 = 1E-3 PVAG = 0
+DELTA = 0.01 RSH = 78.9 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 3.4E-10 CGSO = 3.4E-10 CGBO = 1E-12
+CJ = 9.085053E-4 PB = 0.8 MJ = 0.3519913
+CJSW = 2.378884E-10 PBSW = 0.8 MJSW = 0.1980245
+CJSWG = 1.82E-10 PBSWG = 0.8 MJSWG = 0.1980245
+CF = 0 PVTH0 = -0.0232737 PRDSW = -96.6778453
+PK2 = 4.200437E-3 WKETA = -9.87476E-4 LKETA = -1.128415E-4 )

.MODEL mp PMOS ( LEVEL = 49

+VERSION = 3.1 TNOM = 27 TOX = 7.8E-9
+XJ = 1E-7 NCH = 8.52E16 VTH0 = -0.6614536
+K1 = 0.4432406 K2 = -0.0123618 K3 = 55.5705007
+K3B = -4.9925721 W0 = 5.384636E-6 NLX = 2.456563E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.5822634 DVT1 = 0.6339255 DVT2 = -0.0307983
+U0 = 154.7137452 UA = 1.012464E-10 UB = 1.993677E-18
+UC = -1.28065E-11 VSAT = 1.541575E5 A0 = 1.1866041
+AGS = 0.3740281 B0 = 2.496159E-6 B1 = 5E-6
+KETA = -8.04538E-3 A1 = 5.431049E-4 A2 = 0.3497898
+RDSW = 4E3 PRWG = -0.1040295 PRWB = 0.2075363
+WR = 1 WINT = 1.526389E-7 LINT = 0
+XL = -5E-8 XW = 1.5E-7 DWG = -1.735873E-8
+DWB = 9.026191E-9 VOFF = -0.1325104 NFACTOR = 2
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 2.138549E-3 ETAB = 1.084482E-4
+DSUB = 7.47981E-3 PCLM = 3.3740219 PDIBLC1 = 0.0382188
+PDIBLC2 = 1.851992E-3 PDIBLCB = -1E-3 DROUT = 0.3134832
+PSCBE1 = 7.721166E10 PSCBE2 = 5E-10 PVAG = 0.3435962
+DELTA = 0.01 RSH = 2.6 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 2.24E-10 CGSO = 2.24E-10 CGBO = 1E-12
+CJ = 1.42554E-3 PB = 0.99 MJ = 0.5513383
+CJSW = 3.541201E-10 PBSW = 0.99 MJSW = 0.4557818
+CJSWG = 4.42E-11 PBSWG = 0.99 MJSWG = 0.4557818
+CF = 0 PVTH0 = 6.570075E-3 PRDSW = -27.3095793
+PK2 = 1.62036E-3 WKETA = 3.82077E-3 LKETA = 1.865988E-3)

.global vdd gnd

*inverter subcircuit
.subckt inv vout vin
m1 vout vin gnd gnd mn w=2u l=2u
m2 vout vin vdd vdd mp w=4u l=2u
.ends

*3 NOR subcircuit
.subckt nor1 vout2 vin1 vin2 vin3
m3 n1 vin1 vdd vdd mp w=6.219u l=2u m=4
m4 n2 vin2 n1 n1 mp w=6.219u l=2u m=4
m5 vout2 vin3 n2 n2 mp w=6.219u l=2u m=4
m6 vout2 vin1 gnd gnd mn w=4.146u l=2u
m7 vout2 vin2 gnd gnd mn w=4.146u l=2u
m8 vout3 vin3 gnd gnd mn w=4.146u l=2u
.ends

*3 NAND subcircuit
.subckt nand vout3 vin4 vin5 vin6
m9 vout3 vin4 vdd vdd mp w=6.015u l=2u m=4
m10 vout3 vin5 vdd vdd mp w=6.015u l=2u m=4
m11 vout3 vin6 vdd vdd mp w=6.015u l=2u m=4
m12 vout3 vin4 n4 n4 mn w=9.0225u l=2u m=4
m13 n4 vin5 n5 n5 mn w=9.0225u l=2u m=4
m14 n5 vin6 gnd gnd mn w=9.0225u l=2u m=4
.ends

*2 NOR subcircuit
.subckt nor2 vout4 vin7 vin8
m15 n6 vin7 vdd vdd mp w=9.3098u l=2u m=15
m16 vout4 vin8 n6 n6 mp w=9.3098u l=2u m=15
m17 vout4 vin7 gnd gnd mn w=8.548u l=2u m=4
m18 vout4 vin8 gnd gnd mn w=8.548u l=2u m=4
.ends

*inverter subcircuit
.subckt inv1 vout5 vin9
m19 vout5 vin9 gnd gnd mn w=8.4427u l=2u m=20
m20 vout5 vin9 vdd vdd mp w=9.6488u l=2u m=35
.ends

c1 voutf gnd 4.2p

x1 vouta vin inv

x2 voutb gnd vouta gnd nor1
x3 voutc vdd voutb vdd nand
x4 voutd voutc gnd nor2
x5 voutf voutd inv1

vdd vdd gnd dc 3V

.op
vpulse vin gnd pulse (0 3 0 10n 10n 400n 800n)
.tran 0.1n 3200n
.print v(voutf) v(vin)

.measure tran tphl trig v(vin) val=1.5 fall=1 targ v(voutf) val=1.5 rise=1
.measure tran tplh trig v(vin) val=1.5 rise=1 targ v(voutf) val=1.5 fall=1
.end

Graphs/Figures

Figure 1. Solving for the optimal size per gate.

For the first part of the experiment we are to select a path from input to the output. Since all
path are identical you just have to be consistent in choosing the gate as long as it passes through the
same path. In computing for the optimal size per gate it is dependent on the type of gate, number of
inputs and the number of branches (branch out). Furthermore you need to know the raito of the
output capacitance and the input capacitance. For selecting the ratio of width and length it is
common practice to set the length to 1 when given the ratio of W/L for easy usage. But the
limitation is that the width must not exceed 20 thus making corresponding adjustmnets
 Figure 2. Propagation Delay of Optimized Path

Figure 3. Waveform of Unoptimized InverterCircuit (Blue = Input, Green = Output)

 Figure 4. Waveform of Optimized Circuit

Conclusion

An instantaneous change of state is desired in digital circuits. A figure of merit for

determining the time for the change of state is called the propagation delay. For logic gates they
are designed using PMOS and NMOS. PMOS and NMOS have internal and external capacitance
that causes delay in the change of state. As small as micro seconds design engineers or those in
the industry try to make it as small as possible Figure 4 shows significant improvement in
contrast to Figure 3. In personal computers the processors are categorized by it’s speed and a
faster clock frequency is desired. The need for every software applications to run fast and
smoothly. Digital Circuits ideal characteristics is that it only should be logic high and logic low
only. Figure 3 shows that it is somewhat an analog signal because of the slow propagation delay.
Resizing of the gates is the only solution for reducing the capacitance because the dimensions of
the PMOS and NMOS varies the capacitance and resistance. Furthermore an IC should be as
small as possible that is why we have set the w should never exceed 20 micrometer.