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The 8085 Microprocessor is an 8-Bit general-purpose microprocessor having 40 pins which is capable
of Addressing 64 kb of Memory.
It works on +5v of single power-supply & can operate at the maximum frequency of 6 Megahertz’s.
Thus, it provides 8-Bit Data-Bus & 16-Bit Address-Bus, it generates 8-Bit I/O Address, so 28=256 i.e
only 256-Input Ports & 256-Output Ports can be accessed.
Similarly, it provides 74-Instructions with 5-Different Addressing-Modes.
These all 40 Logic Pin-Out Structure of 8085 Microprocessor are divided into 14 Various Groups which
are involved into the process of transferring Data & executing Instructions in the microprocessor.
These 14 Different Groups in the 8085 Microprocessor can be classified as following:
Here, each group helps these entire 40 Logic Pin-Out Structure of 8085 Microprocessor to perform the
operations assigned by the 8085 Microprocessor, which are as follows:
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d) Here to set the frequency of internal clock generator, X1 can also be an external clock Input
instead of the First-Input Frequency Signal.
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c) The Input of this pin is always By-Defaultly Edge as well as Level-Sensitive Triggered, so it makes a
Transition from Low (i.e 0) to High (i.e 1) State & it remains High until & unless it is indirectly
acknowledged by INTR (sending an Interrupt ng-ac no e gement s gna ) in order to
Interrupt the 8085 Microprocessor till the end of the execution of an Instruction received by an
Externally Interrupting Signal from the Externally-Connected Peripheral Devices, & Thus due to
this it avoids False-Triggering caused by some Noise-Susceptibility & Transients.
d) So, whenever this Interrupt gets activated in the DI/SI State, the 8085 Microprocessor gets an
Externally Interrupting Signal from the Externally-Connected Peripheral Devices, which is
recognised by its High-to-Low State transition, & it automatically sets to low & accepts it.
e) Thus after accepting the Interrupts, the 8085 Microprocessor sends the active low signal within
INTA pin to the Externally-Connected Peripheral Devices which automatically branches to the new
ISR where the Vectored-Address of the TRAP Interrupt is stored in the location 0024H of the
Program-Counter, & so the 8085 Microprocessor executes ISR Addressed in Program-Counter.
f) Thus, after the end of the execution of an Instruction received by an Externally Interrupting Signal
from the Externally-Connected Peripheral Devices, the Input of this TRAP pin is De-Activated in the
middle of the ISR by an I/O Port only after the port is provided the service by the 8085
Microprocessor to the Externally-Connected Peripheral Devices.
g) Therefore, it is a Non-Maskable Interrupt, A Condition may rise to mask it, So it can only be
masked by Resetting the Whole 8085 Microprocessor , else there is no other way to mask it even
if gets activated in the DI/SI State.
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b) According to the Priority, it is the Fourth Highest Priority Interrupt after TRAP pin, which can be
enabled by EI Instruction & Disabled/Resetted by DI Instruction, SYSTEM or Processor RESET or
after Re-Organization of Interrupts.
c) Thus it is a Positive Edge-Sensitive Triggered Interrupt, it must go to Low-Sate & back to High-State
& so it does not need to be maintained high unless and until before a new Interrupt or itself is
been recognized to initiate it.
d) Thus, it consists an In-Built Internal Restart Function; it automatically transfers the Program-
Control by saving the contents of the Program-Counter Register into the stack & by jumping to the
Specific Memory Vectored Address Location 002CH respectively when it is received.
9) INTR: ( Pin.No.10 )
a) It is an Active-High, Maskable, Vectored-Hardware General Purpose Interrupt which is
implemented for the use of Externally Connected I/O Device to Interrupt the operation performed
by the 8085 Microprocessor in the system for transferring Data to and fro from Memory to itself or
Vice-Versa.
b) According to the Priority, it is the Fifth Highest Priority Interrupt after TRAP pin & Among all these
Interrupts it has the Lowest Priority which is Enabled by EI Instruction (when an Interrupt is
received to the 8085 Microprocessor) & is Disabled Immediately after an Interrupt has been
received by the 8085 Microprocessor or by SYSTEM or Processor RESET or after Re-Organization
of Interrupts.
c) Thus, when an Interrupt is received to the 8085 Microprocessor, the INTR gets activated & it
suspends the Normal Sequence of the Instruction where the Program-Counter is inhibited from
incrementing & then the 8085 Microprocessor Immediately Disables the INTR by sending an
Interrupt-Acknowledgement Signal to the Externally Connected I/O Device for transferring
Data to and fro from Memory to itself or Vice-Versa.
d) Thus, when an Interrupt is Acknowledged by the 8085 Microprocessor through the Interrupt-
Acknowledgement Signal , the branching Address depends upon the instruction provided to
the 8085 Microprocessor, where during this cycle, a RESTART or CALL Instruction is been inserted
to jump to the ISR.
10) : ( Pin.No.11 )
a) It is an Active-Low, General-Purpose Interrupt-Acknowledgement Signal which indicates that the
processor has acknowledged the Externally Connected Peripheral Devices that it has recognized
the Interrupt-Signal by an INTR pin & needs the Operation-Code to proceed further.
b) However, this Interrupt-Acknowledgement Signal has the same timing as RD Signal; it is used
instead of RD-Instruction during the Instruction Cycle after an INTR pin is accepted.
c) Thus whenever any Interrupt has been recognized through the INTR pin during the Interrupt
acknowledge cycle, the 8085 Microprocessor generated this Interrupt-Acknowledgement Signal
by making it High & sends this signal (instead of RD Signal) where the Operation-code
provided by the Externally Connected Peripheral-Devices is loaded into the Instruction-Register.
d) Therefore, if the Operation-Code sent by the device implies a Multi-Byte Instruction ona
gna s are sent out y the 8085 Microprocessor to complete the Machine-Cycle.
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Bit Data of the 8-Bit Data-Bus, where these multiplexed-Bits of the Address & Data lines present in
the AD0-AD7 pin are bi-directionally served as A0-A7 & D0-D7 at the same time, so that it can be
used to carry both, the 16-Bit Address of the 16-Bit Address-Bus & 8-Bit Data of the 8-Bit Data-
Bus.
c) Hence, these Address & Data lines both consists of a set of maximum 32 lines which are parallel-
connected to each other, these lines are de-multiplexed i.e separated using a latch through the ale
pin during any op-code fetch operation/execution of any Instruction to save value before the
function of the Bits changes & then it is passed to the M pin which decides wheather the
obtained op-code Address is for Memory or the I/O Devices.
d) Therefore, during any opcode-fetch / execution of any Instruction, in the first clock-cycle of every
machine-cycle, these lines carries the first lower-order of 8-Bit Address-Bits from the 16-Bit
Address-Bits to the Memory or I/O Device from the location to be readed or written & during the
second as well as third clock-cycle of every machine cycle, it subsequently transfers the 8-Bit Data
from the cpu to the Memory or I/O Device or vice-versa where the cpu may read or write out the
Data throughout this tri-stated lines which also connects the I/O ports & the microprocessor.
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S0 S1 Operation
0 0 HALT
0 1 READ
1 0 WRITE
1 1 OP-CODE FETCH
16) R: ( Pin.No.31 )
a) It is an Active-Low, Tri-Stated Output-Control-Signal used to control the writing operations of 8085
Microprocessor.
b) This pin writes the Data to the Memory-Location or an I/O Device generated by the 8085
Microprocessor.
c) Here, to write a Data into a Memory-Location or an I/O Device, microprocessor selects a device
(depending upon the status of pin & the 2 Status Pins S0 & S1 which decides wheather the
Data is for either Memory-Location or an I/O Device) & then it transfers the Data with Data-lines
by genera ng s gna .
d) Thus, when the status of M & S1 is 0 & the status of S0 is 1, then the Data is writtened to the
Memory & when the status of M & S0 is 1 & the status of S1 is 0, then the Data is writtened to
the I/O Device.
17) : ( Pin.No.32 )
a) It is an Active-Low, Tri-Stated Output-Control-Signal used to control the reading operations of 8085
Microprocessor.
b) This pin reads the Data from the Memory-Location or an I/O Device generated by the 8085
Microprocessor.
c) Here, to read a Data from the Memory-Location or an I/O Device, microprocessor selects a device
(depending upon the status of pin & the 2 Status Pins S0 & S1 which decides wheather the
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Data is either in the Memory-Location or an I/O Device) & makes Data-Bus available & then it
generates the signal to read the Data from the selected device.
d) Thus, when the status of M & S0 is 0 & the status of S1 is 1, then the Data is readed from the
Memory & when the status of M & S1 is 1 & the status of S0 is 0, then the Data is readed from
the I/O Device.
18) : (Pin.No.34)
a) M i.e Input-Output or Memory is a Output Status-Signal Line by which the 8085 Microprocessor
comes to know wheather the operation is to be performed is related to Memory or I/O Device.
b) Here, if M=0 (i.e Low) then the microprocessor is acknowledged to perform the operation
related to the Memory & if if M=1 (i.e High) then the microprocessor is acknowledged to
perform the operation related to the I/O Device.
c) Therefore , the operation being performed on the Memory or I/O Device is indicated by the 2
Status-Signal Lines i.e S0 & S1 , if S0=0 and S1=1 then the Status Signals indicates the READ Operation
& if S0=1 and S1=0 then the Status Signals indicates the WRITE Operation.
d) Thus, in case of HALT, HOLD & RESET operation, the M pin is set to High-Impedance (Z), but only
in HOLD & RESET operation, the Status is Not-Defined (X), while in HALT Operation the Status is 0.
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high & after completing the present job, the processor Enables & sets the READY Signal to access
the Data.
e) Here, if READY Signal from READY pin is high during a READ/WRITE Cycle, it show that the memory
or peripheral is ready to send or receiving the Data & then the microprocessor completes the
operation & proceeds for next operation
f) But if READY Signal from READY pin is low during a READ/WRITE Cycle, then the microprocessor
WAITs until the Input at this READY pin goes high before completing the READ/WRITE Cycle.
20) - : (Pin.No.36)
a) It is an Active-Low Input Reset-Signal used to pass an acknowledgement to RESET OUT Signal Line
which indicates that the Whole Internal Structure present in the 8085 Microprocessor along with
the Connected-Devices is Resetted to its Original Initial State.
b) Thus, when an Acknowledgement-Signal sended by the RESET OUT is received to the Reset-Signal
- , the Reset-Signal - resets the HLDA Flip-Flops, the Interrupts Enabled & the
Program-Counter to its Original Initial State (i.e 0) & sets the Address & Data Bus along with the
Control-Lines Tri-Stated by clearing the entire operands/op-code present temporary in the Memory
of Flag-Register & Temporary-Register.
c) After this Process is completed, the program-counter starts executing from its initial Memory-
location 0000H onwards & this - sends an Acknowledgement-Signal to the RESET-OUT to
indicate that the complete 8085 Microprocessor along with the Connected-Devices has been
Resetted to its Original Initial State.
d) Hence the 8085 Microprocessor is held in the Reset-Condition as long as this signal is been applied
to Low-Sate, but after System-Reset Status, the Internal- eg ster an F ag’s are Un-Predictable.
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b) Whenever an Externally Connected Peripheral I/O Device wants to transmit/receive any Data from
the Internal-Memory through the 8085 Microprocessor & at that time if the 8085 Microprocessor
is using the Address & Data Bus for the Operation related to the Internal Memory, it requests the
2-DMA Controller i.e INTEL 8257 & INTEL 8237 to indicate the request sended by the Externally
Connected Peripheral I/O Device to the 8085 Microprocessor is been recognized by the 8085
Microprocessor, So in response to it the DMA Controller ask for the Buses to the 8085
Microprocessor by making the Output of the HOLD-Pin High which is connected to the Input of
HOLD of Microprocessor.
c) Thus, the Internal Processing of the 8085 Microprocessor using the Address & Data Bus for the
Operation related to the Internal Memory can be continued, the 8085 Microprocessor receives this
High-Output gna from the H L ’s Input, it relinquishes the control of Buses and transfers the
control to the Externally Connected Peripheral I/O Device as soon as the current machine cycle is
completed & then it sends this High-Output Signal to HLDA to hold the Acknowledgement, that the
HOLD-Request has been received by the DMA Controller, by indicating that it has turned the
control over Buses for other master in the system & making the Address & Data Lines Tri-Sated
followed by the RD, WR, and IO/M Lines.
d) Thus, after when the process of transferring the Data to and fro from the Externally Connected
Peripheral I/O Device to the Internal Memory or vice-versa is completed, the Externally Connected
Peripheral I/O Device returns the control of Buses back to the 8085 Microprocessor by sending
back a Low HOLD Signal.
e) Therefore, the 8085 Microprocessor regain the control of Buses after when the HOLD pin gets De-
Activated & continues to the Internal Processing of the 8085 Microprocessor where the Operation
related to the Internal Memory was been Halted.