Tugas Material Elektronik

Caesaria Ayu Ramadhani

1506717323

Fakultas Teknik

Universitas Indonesia

2017
 1. What is FINFET? Explain the difference between FINFET and MOSFET.

FINFET is a fin like structure, possibly enabling performance to create faster and more
compact circuits and computer chips. The term “FINFET” describes a non-planar, double gate
transistor built on an SOI substrate, based on the single gate transistor design. The important
characteristics of FINFET is that the conducting channel is wrapped by a thin Si “fin”, as shown
in fig 1 which forms the body of the device. The fin thickness, which determines the effective
channel length of the device.

The FinFET model structure consists of following regions :

• With very low doping silicon fin region.

• Poly-silicon region, source and drain contact region, highly doped.

• Gate region- oxide (SiO2) The advantages of FinFET are as follows

• Excellent control of short channel effects in submicron regime and making transistors still
scalable. Due to this reason, the small- length transistor can have a larger intrinsic gain and
much Lower off-state current compared to bulk counterpart.

• Promising matching behaviour.

• Low cost

• Higher technological maturity than planar DG.

• Suppressed Short Channel Effect(SCE)

FinFET technology takes its name from the fact that the FET structure used looks like
a set of fins when viewed. The main characteristic of the FinFET is that it has a conducting
channel wrapped by a thin silicon "fin" from which it gains its name. The thickness of the fin
determines the effective channel length of the device.

In terms of its structure, it typically has a vertical fin on a substrate which runs between
a larger drain and source area. This protrudes vertically above the substrate as a fin. The gate
orientation is at right angles to the vertical fin. And to traverse from one side of the fin to the
other it wraps over the fin, enabling it to interface with three side of the fin or channel. This
form of gate structure provides improved electrical control over the channel conduction and it
helps reduce leakage current levels and overcomes some other short-channel effects. The term
FinFET is used somewhat generically. Sometimes it is used to describe any fin-based, multigate
transistor architecture regardless of number of gates.

A Fin Field-effect transistor(FinFET) is a MOSFET double-gate transistor built on

an substrate where the gate is placed on two, three, or four sides of the channel or wrapped
around the channel, forming a double gate structure. These devices have been given the generic
name "finfets" because the source/drain region forms fins on the silicon surface. The FinFET
devices have significantly faster switching times and higher current density than the
mainstream CMOS technology.

The FinFET transistors can have gate thickness of 5 nanometres and gate width under
50 nm, are supposed to find application in sub-28 nanometer chips. FinFET technology is being
pursued by AMD, IBM, and Motorola and in academia. The industry's first 25 nanometre
transistor operating on just 0.7 Volt was demonstrated in December 2002 by TSMC. The
"Omega FinFET" design, named after the similarity between the Greek letter "Omega" and the
shape in which the gate wraps around the source/drain structure, has a gate delay of just
0.39 picosecond (ps) for the N-type transistor and 0.88 ps for the P-type. Intel's tri-gate
transistors, where the gate surrounds the channel on three sides, is claimed to be technically
superior.

The first finfet transistor type was known under the name of fully Depleted Lean-
channel TrAnsistor or DELTA transistor. Articles covering the DELTA transistor were first
published in the beginning of the 1990s. The gate of the transistor can cover and electrically
contact the semiconductor channel fin on both the top and the sides or only on the sides. The
former is called a tri-gate transistor and the latter a double-gate transistor. A double-gate
transistor optionally can have each side connected to two different terminal or contacts. This
variant is called split transistor. This enables more refined control of the operation of the
transistor.

FinFET is one of the promising and better technologies for its applications and the
circuit design for better performance and reliability.
 Fig 1 : 3D view of FinFET and SOI FinFET

FINFET ADVANTAGES

PARAMETER DETAILS

Power Much lower power consumption allows high

integration levels. Early adopters reported 150%
improvements.

Operating voltage FinFETs operate at a lower voltage as a result of

their lower threshold voltage.

Feature sizes Possible to pass through the 20nm barrier

previously thought as an end point.

Static leakage current Typically reduced by up to 90%

Operating speed Often in excess of 30% faster than the non-FinFET

versions

Table 1 : Advatages of FINFET.

The FinFET is a technology that is used within ICs. FinFETs are not available as
discrete devices. However FinFET technology is becoming more widespread as feature sizes
within integrated circuits fall and there is a growing need to provide very much higher levels
of integration with less power consumption within integrated circuits.

FinFETs possess the following key advantages over bulk MOSFETs: reduced
leakage,excellent subthreshold slope, and better voltage gain without degradation of noise or
linearity. This makes them attractive for digital and low-frequency RF applications around 5
GHz, wherethe performance-power tradeoff is important. On the other hand,in high-frequency
applications, planar bulk MOSFETs are seento hold the advantage over FinFETs due to their
higher peak transconductance. However, this comes at a cost of a reducedvoltage gain of bulk
MOSFETs.

Metal Oxide Semiconductor FET is very different from that of the Junction FET. Both
the Depletion and Enhancement type MOSFETs use an electrical field produced by a gate
voltage to alter the flow of charge carriers, through the semi conductive drain-source channel.

Fig 2 : 2D view of MOSFET

In fig 1, shows that the gate electrode is placed on the top of a very thin insulating layer
and there are a pair of small regions of n-types just under the drain and source electrodes. Fig
1: 2D view of MOSFET authors have concluded that reducing the gate dielectric thickness
raises the MOSFET drain current or allows the supply voltage to be reduced while maintaining
an acceptable drain current and facilitates the reduction of gate length by the suppression of
short-channel effects. Aggressive scaling of CMOS technology in recent years has reduced the
silicon dioxide (SiO2) gate dielectric thickness. Major causes for concern in further reduction
of the SiO2 thickness include increased poly-silicon (poly-Si) gate depletion, gate dopant
penetration into the channel region, and high direct-tunneling gate-leakage current, which leads
to questions regarding dielectric integrity, reliability, and stand-by power consumption. As well
recognized in increased gate leakage current in MOSFET is a challenge to continue in the
scaling. In [18] authors reveal that scale down the MOSFETs to the nanometer regime leads to
short channel effects, which degrades the system performance and reliability.

The field-effect transistor (FET), a voltage-amplifying device, is more compact and

power efficient than BJT devices. A thin gate oxide located between the other two electrodes
of the transistor insulates the gate on the MOSFET. There are two categories of MOSFETs,
nMOS (n-channel) and pMOS (p-channel), each which is defined by its majority current
carriers. There is a biasing scheme for operating each type of MOSFET in conduction mode.

Fig 3 : MOSFETs

• Metal-poly-Oxide-Semiconductor structures built onto substrate - Diffusion: Inject dopants

into substrate - Oxidation: Form layer of SiO2 (glass) - Deposition and etching: Add
aluminum/copper wires.

2. Explain the “Fin effect” metioned in the paper.

Fin effect is one of the performance elements and parameter to know whether or not the
gaining of material’s performances enhances. It provides improved drive current/it can
increases drive cureent for a given capacitive load. The fin effect makes the researchers know
that the FinFET architecture has successfully delivered improved MOSFET electrostatic, that
fatherly it enables gate-length to scale down until 48nm Contacted Gate Pitch (CPP) at the 7nm
node. With combination to plateau in the LGate,it will result on extreme pressure on the vertical
conduction path from contacts to source and drain. Fin effect can be boosted by aggressive
scaling of fin-pitch.

3. The paper explained about scaling challenge for FINFET architecture. What is
“scaling” and why do the researcher encounter a problem on scaling the FINFET?

Scaling is a process to reduce scales of semiconductor device fabrication. It is the ability

of a technology to scale to a smaller process. In the paper, the problem on scaling the FINFET
arises because with the electrostatic below CPP of ~50nm, it will tend to halt the LGate scaling.
Because a practical minimum power-supply-voltage of ~3×Vth-eff, makes SS and DIBL small,
and LGate scaling will opposes device performance. Other than that, the current values of contact
resistivity for metal-to-degenerately-doped silicon of ~2×10-9 FinFET performance will
significantly deteriorate below CPP of ~40nm. While the theoretical stated that ~1×10-10 Ω-
cm2 could push the CPP limit to below 30nm. Because those facts, it becomes a problem on
scaling in the 30-40nm CPP region to achieve the power/performance benefits of CMOS
scaling. Other than that, the problem is scaling is needed because if it is being limited to further
scaling, it will result in accelerated reduction in source/drain sizes vs. CPP.

4. From the paper, do the researcher finally able to overcome the challenge? If yes,
how do they handle the problem? If not, why?

From the paper, the researcher is able to overcome the challenge but with some
conditions required to make the challenges work. The scalling of FinFET below CPP of
40nm can be done and can extend its performance gains if ρC of ~8×10-10 Ω-cm2 is used,
The use of ρC of ~8×10-10 Ω-cm2 to scal the FinFET below CPP of 40nm is required to
make the challenge succesfully overcome. While the FinFETs below CPP of 30nm can be
done and can extend its performance to if attainment of ρC at fully ohmic limit, and/or
innovative contact structures is used. Otherwise, the challenge can not be done and a
transition to a new device architecture will be required. So, the researcher does able to
overcome the challenge with few conditions.
Referensi

Scaling Challengesof FinFET Architecture below 40nm Contacted Gate Pitch, A. Razavieh1,
P. Zeitzoff1, D.E. Brown1, G. Karve2,and E.J. Nowak1 1GLOBALFOUNDRIES, 257 Fuller
Rd.,Albany,NY 12203,USA 2IBM, 257 Fuller Rd., Albany, NY 12203, USA

Field Effect Transistor, Radio electronics http://www.radio-

electronics.com/info/data/semicond/fet-field-effect-transistor/finfet-technology-basics.php
diakses pada 20 Desember 2017 13:45 WIB

Hisamoto, D.; Kaga, T.; Takeda, E. (June 1991). "Impact of the vertical SOI 'DELTA' structure
on planar device technology" (PDF). IEEE Transactions on Electron Devices. 38 (6): 1419–
1424. doi:10.1109/16.81634. Archived from the original (PDF) on 2016-12-01.

Hisamoto, D. et al. (1991) "Impact of the vertical SOI 'Delta' Structure on Planar Device
Technology" IEEE Trans. Electron. Dev. 41 p. 745.

Difference between FINFET and Trigate MOSFET ,

https://www.researchgate.net/post/What_is_difference_between_FinFET_and_Trigate_MOS
FET diakses pada 21 Desember 2017 20:35 WIB

Chenming Hu; Bokor, J.; et al. (December 2000). "FinFET-a self-aligned double-gate
MOSFET scalable to 20 nm". IEEE Transactions on Electron Devices. 47 (12): 2320–
2325. doi:10.1109/16.887014