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Microelectronics Reliability 54 (2014) 2410–2416

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Electrical Overstress of Integrated Circuits
K.T. Kaschani a,⇑, R. Gärtner b,1
Texas Instruments, Haggertystr. 1, 85356 Freising, Germany
Infineon Technologies AG, Am Campeon 1-12, 85579 Neubiberg, Germany

a r t i c l e i n f o a b s t r a c t

Article history: Common misconceptions regarding electrical overstress (EOS) and the failure characteristics of
Received 11 March 2013 integrated circuits (ICs) are summarized, analyzed and clarified. In order to avoid EOS fails right from
Received in revised form 7 April 2014 the beginning of the IC design process, a methodology is proposed that accounts for the special
Accepted 9 April 2014
characteristics of ICs and their applications in order to deal with EOS in the design, handling and
Available online 10 May 2014
application of ICs.
Ó 2014 Elsevier Ltd. All rights reserved.
Electrical overstress
Integrated circuit

1. Introduction electrical stress requirements though needed are often neglected
and are therefore shaded in grey in Fig. 1. Hence, IC manufacturers
There is a trend driven by system manufacturers to integrate have to get by with the knowledge that they have learned from
more and more ‘‘EOS protection’’ on-chip due to cost, overall form previous designs and analyses of competitor ICs (2) in order to
factor and performance reasons [1]. Unfortunately, many users of design ‘‘robust’’ ICs (3). Since on the other hand system manufac-
ICs often do not distinguish between the different causes of EOS turers are not aware of the failure characteristics of ICs and of
[2,3]. E.g. users expect the integrated component-level ESD (CL- the electrical stress they are exposed to in their manufacturing
ESD) protection of ICs not only to withstand any CL-ESD event and application environments, system manufacturers often com-
but also to protect ICs from system-level ESD (SL-ESD) and other pare compatible ICs of competitors to select the most ‘‘robust’’
kinds of electrical stress. This lack of distinction has unintention- one (4). Unfortunately, this trial-and-error process causes often
ally been encouraged over many years by IC manufacturers, who unpleasant surprises, e.g. when an IC with an excellent CL-ESD
classified field returns, which were caused by specific types of immunity fails for another kind of electrical stress. In this case, sys-
EOS, simply as ‘‘EOS/ESD’’ [3]. Moreover, despite the remarkable tem manufacturers often request failure analysis reports and
advances in ESD control, many users of ICs still cling to meanwhile detailed information on the failing IC from the IC manufacturer
out-dated ESD requirements, e.g. 2 kV human-body-model (HBM) (5). Unfortunately, they generally do not provide much informa-
[4], or misinterpreted models, e.g. the so-called ‘‘machine-model’’ tion on the conditions that caused the failure. As a result, IC man-
(MM) [5]. At the same time, IC manufacturers are required to sup- ufacturers typically run failure analyses in order to find the root
ply ‘‘EOS robust’’ ICs to their customers without knowing the final cause of the failure and try to fix it by a re-design of the IC (6). If
application and its electrical stress requirements [1]. the root cause of the failure cannot be found and ICs still fail, some
These inconsistencies cause several replacement processes and system manufacturers respond to the assumed lack of ‘‘EOS robust-
result typically in a trial-and-error development process to design ness’’ by increasing their CL-ESD and LU requirements or by asking
‘‘EOS robust’’ ICs (cf. Fig. 1). Unfortunately, only a few electrical for robustness validation of ICs (7). Finally, they rate IC manufac-
stress requirements (e.g. CL-ESD and latch-up (LU) requirements) turers based on the ‘‘EOS robustness’’ of their ICs.
are generally specified by system manufacturers (1). Other The aforementioned inconsistencies and the problems they
cause are often due to common misconceptions regarding ICs
and EOS. These misconceptions and the desire for simple EOS solu-
⇑ Corresponding author. Tel.: +49 8161 80 4348; fax: +49 8161 80 3322. tions are often encouraged by today’s tight time-to-market and
E-mail addresses: (K.T. Kaschani), reinhold.gaertner
cost requirements [6]. Therefore, it is important to understand (R. Gärtner).
Tel.: +49 89 234 23754; fax: +49 89 234 9552117.
and accept that physics does not respond to time-to-market and
0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.

it has to be concluded that ICs are gen- (b) The same part of an IC is assumed to be damaged regardless erally non-linear systems. tion devices is also confirmed by the lack of a common correlation between their HBM robustness and their SL-ESD robustness as 2. Only by taking into account the characteristics simulated [7]. annealing). this assumption is ure mechanism (immediate failure) or by accelerated aging generally wrong as will be explained in the following sections. instantaneously as soon as a certain threshold voltage is exceeded istics of ICs and their applications in order to deal with EOS in the but may be significantly delayed. Especially ESD EOS. Kaschani. snap- stress that they may experience. As As shown in [2]. it is possible to protect them from back. by taking saturation. Unfortunately.g.g. their breakdown does not necessarily occur to propose a methodology that accounts for the special character. In fact. protection to protect ICs not only from CL-ESD events but also from Irreversible failures are permanent. which The expectation of on-chip ESD protection to protect ICs not makes it very difficult (if not impossible) to predict their response only from CL-ESD events but also from other kinds of electrical to other kinds of electrical stress. K. their application systems and the different kinds of electrical become especially clear. linear mechanism) of an IC component. if these devices are operated beyond their safe operating area. The non-linear characteristics of active devices of ICs. Failure mechanisms ferent kinds of electrical stress. stress is often based on one or the other of the following Even passive devices like resistors. ible (soft) and irreversible (hard) failures. transistors and SCRs) are explained in [2. another non- As explained in [2]. to present typical causes of EOS and explained in [8]. (delayed failure). Reversible failures are caused by electrical stress electrical stress can be superimposed to give the response exceeding the trigger threshold of a functional failure mechanism of the IC to superimposed electrical stresses. R. Gärtner / Microelectronics Reliability 54 (2014) 2410–2416 2411 Fig. As failure characteristics of ICs. (c) Specific parts of an IC are assumed to respond equally to dif. The major failure mechanisms leading to irre- versible failures caused by EOS are thermal overload due to dissi- 2. The non-linearity of ESD protec- design. active and passive devices.e. 1. reset) or it can be healed by self-healing or physical treatment (f) It is assumed that the responses of an IC to single kinds of (e.g. (d) The response of an IC to electrical stress is assumed to be The failures caused by EOS can generally be divided into revers- independent of its mode of operation. it is the purpose of this paper to clarify the in order to clamp the voltage while conducting large currents. Hence. They are either caused by other kinds of electrical stress is typically based on the assumption electrical stress exceeding the trigger threshold of a physical fail- that ICs are linear systems. Typical trial-and-error development process to design ‘‘EOS robust’’ ICs.2. Taking into account that almost all ICs employ both different kinds of electrical stress. protection elements are typically driven deeply into breakdown. breakdown. i. This is the reason. 2. capacitors and inductors are assumptions: known to show non-linear characteristics. the expectation of on-chip ESD nisms causing reversible failures are non-linear. breakdown. hysteresis and memory effects into account. active devices (diodes. why their electro-thermal threshold of semiconductor devices and the stress time on the characteristics are not analytically solved but are numerically one hand and the relation between the time-to-failure and the .10]. Given these facts.T. A reversible failure can (e) The response of an IC to electrical stress is assumed to be be removed by a functional reset (e. a power restart or a logic proportional to the level of the given electrical stress. the failure mecha- tics of linear systems.12].1. the relation between the thermal overload non-linear devices. Failure characteristics of ICs reported in [1]. a non-linear mechanism) or by approaching the failure threshold (e. of the kind of electrical stress. all these assumptions refer to characteris. which may occur for (a) The current path within an IC is assumed to be the same for any EOS [9. handling and application of ICs. different ESD protection elements were found to have significantly different correlation factors. Hence. Semiconductor devices and ICs pated energy and dielectric breakdown due to an electric field or voltage stress imposed for a certain amount of time [11]. cost requirements. (The chronological sequence is indicated by the digits 1–7). (a switching operation.

This proves that the response of an IC probability distribution of an IC. Application circuit According to [2.5. it does not account for failures caused by kinds of EOS can generally not be superimposed to give the electromagnetic interference (EMI) and by misapplication. Gärtner / Microelectronics Reliability 54 (2014) 2410–2416 electrical field (or voltage) across gate oxides on the other hand is to an electrical stress is not necessarily independent of its mode always non-linear. This proves that and hence based on the dissipated energy.g. external the failure signatures of different EOS events. These non-linear characteristics have a only some fundamental characteristics of voltage and current strong impact on the design of any electrical stress protection both waveforms that caused the failure can be inferred.4. Failure signatures 2. EOS in relation to AMR for a given electrical stress type and failure turned out to be only 1 kV. Furthermore. external capacitors can be both beneficial or detrimental to the due to the dissipated energy. more complex the on-chip circuitry is that is connected to a pin. EOS is defined in this paper as characterized by failing stress levels that are framed by lower follows: and higher stress levels. many IC and system manufacturers are used to classify failures as the more different current paths may be triggered by different ‘‘EOS failures’’ based on the size of the physical failure signature stress waveforms that are imposed on that pin. The the lack of a clear and consistent definition of EOS. failure dent of its application system and that ICs have to be regarded as signatures can generally not be clearly attributed to specific volt. this lack of capacitors may lead to immediate destruction of an ESD protection correlation confirms again that ICs are non-linear systems. When unbiased. However. if snapback devices are involved. 2. Hence. of devices to be protected are not constant. stress that exceeds the absolute maximum ratings (AMR) of an IC and causes it to fail is likely to be attributed to the cause 2. While small failure the same part of an IC is not necessarily damaged regardless of signatures (small dissipated energies) are attributed to ‘‘ESD’’. age and/or current waveforms. 2. device. They prove that the response of an IC to an electrical stress is not necessarily proportional to the level of the given electrical stress. This shows that there is generally no correlation between currents.7. the effects of external capacitors (CDM) type overstress events generally cause dielectric breakdown connected to the pins of ICs are explained in [2. E.18]. which are passed. Kaschani. Traditionally. to ‘‘EOS’’. 2. non-linear systems. Given response of the IC to superimposed EOS. ing irreversible failures of ICs are non-linear. As 3. characteristics of protection elements and the breakdown voltages tures is misleading. All of the aforementioned aspects prove the non-linear failure By means of the type and the size of the different failure signatures. the kind of EOS. on-chip CL-ESD protec- 2. many different voltage and/or current waveforms can lead to the same failure signature. the quasi-static IV aphor of a ‘‘fingerprint’’ that is often used to describe failure signa. It is of electrical overstress. since the major failure mechanisms in ICs depend on the the electrical stress immunity of an IC is not necessarily indepen- time duration that voltages and/or currents are applied [2]. as soon as its trigger voltage is exceeded. As already indicated in the previous section. It is no surprise. Failure location tion cannot be expected to protect ICs from any other kind of elec- trical stress. of operation. Hence. any low-energy electrical is a characteristic of a non-linear system. If non-snapback devices are often result in large molten areas or even blown bond wires [16] employed. the failure location can vary for different ESD events that are imposed on the same pin of an IC because different One of the reasons. the exam. which in turn confirms the non-linearity of ICs.13] different kinds of EOS typically cause differ. Hence.T. while charged-device-model nity of ICs to electrical stress.6.9].3. dissipated energies and medium sized failure signatures are con- ple given in [2] also proves that the responses of an IC to single cerned. the SL-ESD immunity of the IC was found to be 7 kV. also the major failure mechanisms caus. which in turn lead to high overvol. Again. is stress waveforms can trigger different current paths in ICs. window effects are an indication for the non-linear nature of ICs. on component-level and on system-level.2412 K. Window effects ‘‘ESD’’ rather than to the cause ‘‘EOS’’. E. In contrast. EOS root causes explained in [2]. Depending on due to their large peak currents. external capacitors can mitigate the electrical stress owing to a tremendous power dissipated over a long period of imposed on ESD protection devices by buffering detrimental peak time. if the A PASS–FAIL–PASS–FAIL sequence that is obtained as the stress root causes of IC failures are only determined based on the effects imposed on an IC is increased is called window effect [2. when the IC was biased. E. . Therefore. since SL-ESD is often regarded as large failure signatures (large dissipated energies) are attributed superposition of HBM and CDM and although a successful superpo. However. Unfortunately. Furthermore. HBM-type overstress events cause melt-filaments IC. This shows that Note. the SL-ESD immunity Fig. why EOS of ICs is so difficult to address. the met. As a result. high energy EOS events electrical stress immunity of that IC. Window effects are well-known and often caused by competition between protection elements and devices to be protected. Therefore. different EOS waveforms may lead to different failure locations within ICs. this ‘‘definition’’ is not clear as medium sition has been reported in a couple of individual cases. the kind of the ESD protection devices that are integrated with an tages within ICs. Also application circuits can have a strong effect on the immu- ent types of failure signatures. characteristics of ICs. R. In fact. that cus- tomers of ICs request ever-increasing CL-ESD immunities.g.g. Mode of operation According to [17] the SL-ESD immunity of an audio amplifier IC was found to vary depending on the applied supply voltage of the IC. but have to be adjusted to each type of electrical stress. such a behavior the traditional failure classification. Failure signatures are not that unique.

immediate and electrical stress. mis- require that the recommended operating conditions are in total insertion and specification violations.T. useful life of an IC have to be taken into account when AMR are The category ESD includes both causes of charging and of uncon- specified. .g. 3. the rate of immediate failures indicated by the solid electrical stress that an IC is supposed to withstand. centrate on its effects. Therefore.9. immediate failures or accelerated aging of to withstand a violation of its own specification. that latch-up (LU) can cause EOS failures. they may results in IC failures.10]. fast may already occur when the recommended operating conditions voltage transients. Finally. Following the the tFT. AMR sepa. it is the given ICs and the electrical stress they experience. surge currents. the term ‘‘EOS robust’’ is become subject to accelerated aging and delayed failures though. Such cases are pulses (EMP). uncontrolled power supplies). EOS is a specification violation that healthy ICs are robust against immediate failures. This understanding of AMR matches quite spread they are given by a band rather than a sharp line. the category Misapplication is divided into usually indicated in the datasheets of corresponding ICs. 3. Electrical overstress (EOS) is any electrical stress that tFT are not constant but depend on the given electrical stress exceeds any of the absolute maximum ratings (AMR) of an IC and type. The stress level range that covers the increase of the failure voltages. The guard band between the AMR and the tFT accounts trolled discharges. The uncer. the power-to-failure of an integrated diode for constant causes it to fail.g. EMI and misapplication. [3]). Some of these root causes are shown in the tainty introduced by unknown electrical stress and unknown cause-effect diagram of Fig. for no product can be expected Within the tFT band. Above well the AMR definition given in IEC 60134 [14]. Hence. all EOS definition given above. Since failure thresholds are subject to process delayed failures of ICs. in some cases noticeable accelerated aging transients (e. reversibly or irreversibly. Cause–effect diagram with typical causes of EOS to ICs (cf. Note. testing. of course a contradiction in terms. EOS application conditions and the impact of accelerated aging on the causes can generally be divided into ESD. electrical stress is much lower than the power-to-failure of the same diode for a 1 ns electrical stress pulse [2. (application) system design. The category EMI is divided into slow voltage for these factors. ICs may occur depending on the individual failure thresholds of In order to develop effective measures to deal with EOS. in bold line is plotted over the stress level of a given electrical stress the EOS definition given above AMR are not restricted to constant type. although [15] suggests not exceeded for too long. noise and EMI due to RF and electromagnetic (ROC) are exceeded for more than just an instant. Note. necessary to understand its typical root causes rather than to con- rate the area of safe handling and application from EOS. R. immediately or delayed. K. In this connection. Below the tFT. Gärtner / Microelectronics Reliability 54 (2014) 2410–2416 2413 Definition. They causes due to assembly. E. Kaschani. According to this diagram. all healthy ICs will immediately fail. but comprise all constant and time-dependent physical rate from 0% to 100% is denoted as typical failure thresholds limits that are specified by IC manufacturers in order to ensure ser- (tFT) of all healthy ICs of the same type that experience the same viceability and avoid reversible and irreversible. 2. This definition and its implications are illustrated in Fig. LU is not included with Fig. In AMR cannot be constant either and have to be adjusted for the this figure.

T. Standards can help to (e. Special attention (S3) Electrical Stress Specification addresses the specification of should also be paid to peculiarities because they often introduce the electrical characteristics of inevitable and potentially special risks [3]. intuitive methods. a comparative specification.g. those related to functionality. This clearly shows the need to concentrate on EOS rather individual intuitive methods should be applied prior to joint than on ESD. by hot plug control. its components. mitigated and root cause analyzed. up’’ method and one ‘‘top-down’’ method [19]. Special requirements or features should be taken harmful electrical stress. by ESD control. Fig. EOS related to cross-coupling can EMC design techniques) as well as fail-safe design techniques be minimized e.g. Given the power of EOS minimization as EOS [3]. machines. EOS.2414 K. ‘‘top-down’’ methods (e. such a specification cannot be ruled by a standard.g. failure mode and effects analysis) start with possible failures following steps: on component-level and assess their impact on system-level and application-level. to identify their root causes. as many EOS risks as possible by means of EOS minimization EOS related to handling can be minimized e. all failures on system-level and component-level that may cause (S2) EOS Risk Assessment denotes the risk assessment of possible the given failures on application-level. because LU is not a cause but a failure define precautions in order to minimize unacceptable risks [3]. 5-steps EOS methodology. if the given risk can be specified. connec. such as the handling of ICs. how- minimize EOS sources that are related to routine tasks and proce. EOS risk assessment. systematic methods should be deployed. supplies. Quite the contrary. EOS related addressed by EOS mitigation (S4). i. .g. Measurements and com- puter simulations can help to characterize and specify inevitable electrical stress [20]. a necessary prerequisite for the mitigation of the impact of inevitable electrical stress is a complete and detailed specification of its electrical properties in terms of time-dependent current and voltage waveforms and repetition rates [3]. does not need to be risk assessed. tools. 5-Steps EOS methodology Systematic methods can be divided into failure-driven risk assessments and risk assessments of peculiarities. Specific EOS risks. cially low/high temperature. be generally minimized by best practice design techniques (e. minimization addressed by EOS minimization (S1) or if it needs to be addressed of EOS sources is the most powerful measure to avoid fails due to by EOS mitigation (S4).g. humidity. Only with such a specification. 4 is proposed [3]. different risks. risk assessments also help to avoid over. of inevitable electrical stress.1. into account (e. time-to- (S4) EOS Mitigation describes the mitigation of the impact of market or cost). Risks are also introduced by changes (e. In order to cover as many and potentially harmful electrical stress in the design. EOS risks can of course to applications can be minimized e. noise). radiation. In contrast. R. per EOS type.g. ‘‘Bottom-up’’ methods methodology shown in Fig. Often.2.g. 4. EOS minimization (S1) (misuse) should be considered [19]. materials. For any unacceptable risk that is identified in the course of the Every EOS that does not occur. brainstormings) should be applied butes only 6% of customer complaints to ESD but 94% to other first to avoid biasing other people’s mind. may trigger a LU of an IC. its application and its environmental conditions [3]. Afterwards. Given the number of typical causes systematic risk assessments should be carried out. to quantify their impact and to parts of an IC may be damaged depending on the time depen- dent waveform of an electrical stress [2].g. Hence. Electrical stress specification (S3) The purpose of risk assessments is to discover and anticipate Due to the non-linear failure characteristics of ICs. control of noise and EMI. it is recommended to address causes of EOS shown in Fig. To consider all relevant risks both intuitive and AMR. Note. Minimization can be achieved by paying attention to the explained in the previous section. Kaschani. pressure. han. espe- cause identification of fails due to unforeseen EOS. Intuitive methods (e. it has to be evaluated. Note. engineerings on the other hand. system and component designers are able to develop effective mitigation strategies. fault tree (S1) EOS Minimization covers the minimization of EOS sources in analysis) start with failures on application-level and trace back the design. handling and application wherever possible.3. 3 nicely agrees with a recent report that attri. provision of redundant systems) [19]. ever. Also. For the same reason. Hence. by noise and EMI control.g. Gärtner / Microelectronics Reliability 54 (2014) 2410–2416 the EOS cause-effect diagram. is not sufficient because it bears the risk of ignoring serious threats on the one hand and of driving unreasonable and ineffective over- Fig. Failure-driven In order to minimize IC failures due to EOS the 5-steps EOS risk assessments focus on possible failures. risks as possible. tor design and AMR compliance. It comprises the (e.g.g. it is recommended to use at least one ‘‘bottom- dling and application of ICs. (S1). which only refers to a related system or component and is often made for lack of time. techniques (S5) EOS Root Cause Analysis covers the failure analysis and root and procedures) or by special environmental conditions (e. EOS risk assessment (S2) 4. also possible and (assumed) ‘‘impossible’’ user action 4. 4. In mechanism. EOS [16]. human resources. 4. need to be carefully specified and addressed in order to be dures. the design of connectors and the effectively mitigated [3].or under-engi- paper. the specification of electrical stress requires a fundamen- tal understanding of the given system: its manufacturing condi- tions. given the EOS definition of this this way. 3.e. electrical stress that exceeds the corresponding neering of systems. Finally. reliability. Only those EOS risks that cannot be minimized should be hot plug control and optimized working procedures.

This cuitry has to be designed to partly or completely withstand a failure caused a short-circuit condition for one of the power tran- given electrical stress. As a suming troubleshooting processes with three different OEMs. Need- less to say. that were driving the ESD protection element connected to the Co-designing of IC pins implies that the interfacing IC cir. The failure analysis of the become very complex [3]. because in contrast to measurements they do not affect the signal integrity [21]. electrical current screening test into the final test of the IC in order to screen stress decoupling maximizes the freedom of system designers to for weak devices as a containment action. The electrical stress protec. in case of ESD by shielding and in case monitoring data of the affected lots and to run an ESD re-qualifica- of EMI by low pass filters. turer. an electrical stress created or the assumption of a weakness of the wafer process. same IC pin repeatedly into breakdown until it finally failed. this is often not sufficient. Taking into account the non-linearity of ICs and of Example: During the ramp-up of a new IC an increased number other components. In such manufacturer assumed a weakness of the wafer process to be the a case. it was finally decided to introduce a leakage pendent of system-level electrical stress. components. To verify this assumption. As a result.T. pins that are connected to local PCB networks in order to (4) Narrowing down of possible failure mechanisms (Which support basic IC functions are naturally decoupled and usually failure mechanisms can explain the given failure conditions. cient free-wheeling diode that was used on the PCBs of the system electrical stress decoupling and co-designing do not rule out each manufacturer as a replacement of a costly Schottky diode. which in turn could (1) Detailed specification of the failure conditions (When was distort the input signal. the process-control monitoring data and in order to be most effective. the function mentioned criteria (What is the probability of the experi- of which is likely to be impaired by co-designing. However. IC manufacturer revealed a large carbonized area (burn mark) As already mentioned. which generally will lead to a more special and hence number of field returns increased strongly. which eventually take much more time to fix the problem tive actions. As a general rule. EOS root cause analysis (S5) the likely root cause. Half a year later. there may be fails due to unforeseen EOS. OEM 2 design components into their systems. e. com- may be functionally impaired by co-designing. enced in between?) decoupling is the preferred mitigation strategy for IC pins that (2) Localization of the damaged structure (Which system. However. Kaschani. . optically and electrically characterized?) tion. it result.g. As a result. EOS mitigation (S4) than a careful root cause analysis and correction process.5. The system manufacturer and the IC trical stress represent a special risk to the given system. Basic IC functions are supported location and signature? This should be done by engineers. grounded resistors. the designed. The analysis of introduced as close as possible to the given electrical stress source the final test data-logs. decided to analyze the final test data-logs and the process-control This can be achieved e. mechanically.g. E. In addi. which in turn may impair the overtemperature detection circuit of the IC. EOS can generally be mitigated by best above one of the power transistors that are used to drive a motor practice design techniques as well as fail-safe design techniques and a smaller carbonized area above the ESD protection element [19]. this designers may be needed to reach this goal. Unfortunately. by decoupling capacitors and charge-pump capacitors for who are familiar with the damaged structure and its failure internal voltage supplies. system-level or component-level cess. it is of utmost importance to identify the root cause these requirements they need to be supported by templates of each fail in the first step before the most effective corrective that guide engineers quickly through the troubleshooting pro- action on manufacturing-level. After three time-con- less flexible design of both the component and the system.) networks and crystals for internal oscillators. problems that are delayed by such ‘‘short cuts’’ do Typically. it is beneficial to decouple as many components as possible root cause of the field returns. high speed. This imposes additional requirements sistors. if specific types of elec.g. A corresponding co-designing of a sup. the resulting system affected by EOS can of field returns was observed by OEM 1. it was in terms of the given electrical stress from the remaining system. weakness of the PCB was a priori ruled out by the system manufac- nents that are decoupled from the system can be designed inde. the damaged part last known to be fully functional? When ply pin could increase the leakage current of this pin so much was it first known to fail? Which processes has it experi- that it may become critical for battery applications. Hence. R. should be enced processes to cause the given failure? Which decoupled. given the simple truth is often ignored for ‘‘lack of time’’. high speed or RF input pins and low (3) Identification of the failure signature (How is the failure impedance. Also a co-troubleshooting by system and component can be determined in the second step [3]. EOS involves both the application system and its not vanish but get bigger. do not need to be co-designed. other parts can free-wheeling diode caused repetitive inductive voltage transients be co-designed. passive feedback mechanisms. trouble- to the complexity of the entire system and the manufacturing shootings have to be both efficient and effective [3]. A possible fed into the system will not reach this component. For lack of time. Due Given today’s tight time-to-market requirements. to fix likely root cause steps (S1) to (S4) of the 5-step EOS methodol- the unsolicited fail without loss of time often ‘‘short cuts’’ are ogy should be repeated in order to determine effective correc- taken. If a component is effectively decou. co-designing a high An effective root cause analysis requires [3]: speed input pin for SL-ESD would add a significant capacitive load and/or series resistance to this pin. To meet process. K. of the corresponding pin. which was damaged because it was turned-off too late by on the design of such circuitries. the ESD re-qualification did not give any results that could support pled from the remaining system.4. and OEM 3 completed the qualification of products based on sim- tion of the remaining system and its components has to be co. the functionality of the given IC pin. At the same time. Gärtner / Microelectronics Reliability 54 (2014) 2410–2416 2415 4. Instead. Such decoupling measures should be tion with increased sample size on all affected lots. This other. co-designing will limit the freedom of system designers to finally turned out that the field returns were caused by an insuffi- apply co-designed components to different systems. processes have the highest probability to cause the given damage? Computer simulations may help to narrow down 4. Finally. (5) Identification of likely root causes that meet all of the afore- pins connected to complex IC circuitries and pins. While parts of a system can be decoupled. ilar PCBs of the same system manufacturer. RF or high voltage output pins. These pins are ponent and structure is damaged?) typically supply pins.) Even with all the aforementioned steps (S1) to (S4) meticu- lously followed. compo.

Gärtner R. analyzed and clarified. Standards that are often called for can only help to solve fre- [13] Stadler W et al. Charvaka Duvvury and Hans Kunz from Texas Instruments. Christoph Thienel from Bosch and Jean-Luc Lefebvre from Presto Engineering for Common misconceptions concerning ICs and EOS that facilitate many inspiring and fruitful discussions on EOS. Tamminen P. ESD in silicon integrated circuits. PhD Thesis. 1961. [8] Johnsson D et al. Gärtner R. ESD physics and devices. standards cannot improve the robustness of ICs against unknown [15] JEDEC solid state technology association. 2011. typical mitigation strategies and to the measures for modeling. Symp. Systematic design technique for improvements of mobile The authors would like to thank the members of the ESD Forum phone’s immunity to electrostatic discharge soft failures. 2002. tion violations. Wiley & Sons. . ESD-Forum.. Analysis of HBM ESD testers and specifications using a 4th lems in the design. ESD-Forum. failure mechanisms and models for semiconductor devices. JEP155. Chichester: John Wiley & Sons.. Symp.T.57:2470–6. tubes and valves and analogous semiconductor devices. It was pointed out that ICs have in general non-linear failure characteris. electrical stresses and standards cannot protect ICs from specifica.. On the significance of the machine model. process. EMC. the design. IC failures have been summarized. JEP122E. 2011. Gärtner / Microelectronics Reliability 54 (2014) 2410–2416 5. 2011. (S3) the [7] Snowden CM. designing. 1993.. 12. 11. handling and application of integrated circuits.. of EOS sources. EOS/ESD Symp. 10. 2004. Measurements and simulation in product specific risk Acknowledgments analysis. EOS and (S5) the root cause analysis of EOS failures. However. on ESD was explained. EOS/ESD Symp. On-Chip ESD Protection in integrated circuits: device physics. Symp. In order to avoid EOS fails right from the beginning of the design August 2008. [16] Thienel C. In: IEEE Intl. [10] Voldman SH. Based on a recent investigation integrated with ICs and its practical implications. Chichester: John tion was paid to EOS minimization strategies. (S4) the mitigation of Trans Electron Dev 2010. Summary and conclusions Michael Mayerhofer from Infineon Technologies. Berlin: Springer. 1989. [20] Reinvuo T. 2004. Euroforum. which have a strong impact on the design of any electrical [1] Thijs S et al. Special atten. [4] JEDEC. of ICs and EOS and to collaborate in order to solve the EOS prob. the concepts of electrical stress decoupling and co. [9] Amerasekera A.V. IC Latch-up. The impact of electrical overstress on the design. [12] JEDEC solid state technology association. both system designers and component 2010. Duvvury C. 2001. Impact of the power supply on the ESD system level robustness. Test. 2010. EOS/ESD Symp. IEEE specification of inevitable electrical stress. From the ESD robustness of products to the system ESD quent problems related to regular electrical stress. efficient and effective troubleshootings. Based on the typical [6] Kaschani KT. of ESD and EOS failures the need to concentrate on EOS rather than [3] Kaschani KT. (S2) the risk assessment of possible EOS. handling and application of ICs. handling and application of ICs. 2010. In order to develop effective measures to deal with EOS. [21] Kim KH et al. [17] Giraldo S et al. Needless to say. JESD78D. A methodology to deal with electrical overstress in the causes of EOS this methodology addresses (S1) the minimization design. [18] Verhaege K et al. circuit simulation. EMC. Kaschani. [11] Mergens M. R. designers are asked to pay attention to the special characteristics EOS/ESD Symp.0. SCCF – System to Component Level Correlation Factor. EOS/ESD stress protection both on component-level and on system-level. a 5-steps methodology was introduced to deal with EOS in [5] Kaschani KT et al. Semiconductor device modelling. Electrical overstress of automotive semiconductors. e. Gärtner R. ESD-Forum. Konstanz: Hartung-Gorre. Including EMC in risk assessments. 2011. are not suitable and may be even detrimental for problems that [14] IEC International Electrotechnical Commission. [19] Armstrong K.. 2009. handling and application of integrated circuits. 2007. 2010. EOS risk assess.2416 K. EOS/ESD Symp. 2010. Therefore. March 2009. References tics. they robustness. order lumped element model. Recommended ESD target levels for HBM/MM qualification. The system theoretical significance of ESD protection causes of EOS have been presented. In: IEEE Intl. Rating systems for electronic are rare or related to irregular electrical stress. Avalanche breakdown delay in ESD protection diodes. typical [2] Kaschani KT.. ments.. IEC 60134 ed1..

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