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A. CLIPPER CIRCUIT
D2 will remain on for a short time. The output waveforms for the clippers of Fig. 5.25[(d) and (e)] circuit looks as if a portion of the output signal was cut off (clipped). Although the input voltage can have
are iden-
any waveform, we will assume that the input voltage is sinusoidal, vS ! Vm sin !t, in order to describe the
tical, as shown in Fig. 5.25(f).
output voltage. Clippers can be classified into two types: parallel clippers and series clippers. The diode
The circuits of Fig. 5.25[(a) and (d)] (with E1 reversed and renamed as E2 ) can be combined to form
can be connected either in series or in parallel with the load.
a two-level clipper, as shown in Fig. 5.25(g). The positive and negative voltages are limited to E1 and
E2, respectively, as shown in Fig. 5.25(h). One battery terminal of the clippers in Fig. 5.25 is common
to the ground. 5.5.1 Parallel Clippers
A clipper is a limiting circuit; it is basically an extension of the half- A clipper in which the diode is connected across the output terminals is known as a parallel clipper
5.5.2 Series Clippers
wave rectifier. The output of a clipper circuit looks as if a portion of the because the diode will be in parallel (or shunt) with the load. In a shunt connection, elements are connected
in parallel such that each element carries a different current. Some examples of parallel clipper circuits and
A clipper in which the diode forms a series circuit with the output terminals is known as a series clipper. their corresponding output waveforms are shown in Fig. 5.25. The resistance R limits the diode current
output
The current-limiting signal
resistance was
R can be used cut
as a load, off
as shown (clipped).
in Fig. 5.26(a). If the direction of the bat-
tery is reversed, the negative part of the sine wave is clipped as shown in Fig. 5.26(b). If the direction of
when the diode conducts. In determining the output waveform of a clipper, it is important to keep in mind
that a diode will conduct only if the anode voltage is higher than the cathode voltage.
E1 vO vO
D1 on vS
A B
+ vO Vm − E1 D1 on
+ + − D1 + D2 off
+ R + + E1
0 D2 vO
vS D1
R vO wt R
−E1 vS vO vS vO 0
E1 + +
p 2p 3p q
− − vS E1 E1 Vm
− − − − − − D1 off
D1 off
D2 on
(a)
(a) (b) (c)
E1 vO
B A D1 on vO D1 off
E1 + Vm vO
+ − + + D2 on vO
D1 Vm + R + + +
D2 E1
vS vO D1 Vm
R E1 R
0 vS + vO vS + vO 0
− wt p 2p 3p q
− E1 E1
D1 off − − − − − − D1 on
vS vS
D2 off
(b)
(f)
(d) (e)
E1 vO
vO
A B D1 off vS D1 on
+ − + D2 off vS
D1 +
+ R
0 E1 vO
vS vO wt D1 D2
R −E1
vS + − vO 0
Vm p 2p 3p q
− E1 E2 Vm
−(E1 + Vm) − − + E2
vO D1 on − D1 off
D2 on
(c)
(g) (h)
B. CLAMPER CIRCUITS
As shown in Fig. 5.29, a fixed-shift clamper shifts the output voltage by an amount !Vm with respect to
the zero level. Let us consider the clamping circuit in Fig. 5.29(a). As soon67722_05_ch05b_p264-298.qxd
as the input voltage vS is
switched on, diode D1 will conduct during the first positive quarter-cycle of the input voltage, and the
capacitor C will be charged almost instantaneously to the peak input voltage Vm. But the output voltage
2/19/10 5:04 PM Page 286
will be zero, vO ! 0. The circuit will reach a steady-state condition with a voltage of Vm across the capac-
A clamping circuit simply shifts the output waveform to a different DC
itor C, as depicted in Fig. 5.29(a). Therefore, after the first quarter-cycle, the capacitor voltage will be
vC " Vm, and the output voltage vO will become
level. Thus, it is often known as pa level shifter. The shapes of the input
v = v - v = v - V = V sin vt - V = V (sin vt - 1) for vt Ú
O S C S m m m m
2
and output waveforms are identical;
as shown in Fig. 5.29(b).
286 onlyMicroelectronic
the DC level is shifted.
Circuits: The
Analysis and Design
Let us assume that the input voltage v falls below the initial peak voltage of V (say, 20 V) to a
input
new peak voltage
value of V can
(say, 10 V). This
m1 have
situation any
is shown in
S
shape.
Fig. 5.29(c). The diode voltage is now
m
vO " vS # vC " 10 sin !t # 20, which is negative for all !t, and the diode becomes reverse biased.
vO p 3p 5p 7p D1
Vm p 2p 3p
2 2 2 2
+ − 0
+ 67722_05_ch05b_p264-298.qxd
+ + 2/19/10 5:04 qPM
= wt
Page 286+ + + +
vC D1 on
vS = Vm sin q vD D1 vO −Vm
vp +
− − − −2Vm vS = Vm sin q vC1 C1 = C Vm
−
(a) Circuit (b) Output voltage − − −
vO
Vm 286 Microelectronic Circuits: Analysis and Design
Vm + FIG
20 V
+ − + −
+ + + vC2 +
+ vC vC C2 = C V
vS = Vm sin q
−
~ vO D1 vS vO R D1
− m
− − − D1 − −
(c) Circuit for Vm1 < Vm (d) Circuit with changing
+ + input voltage + +
D2
vp +
vS = Vm sin q vC1 C1 = C Vm
-Vm vO −
−
5.7.2
FIGURE Voltage Triplers
doubler circuit and Qu
+
+ + −
2Vm
− −
vO
vC
+ 5.35 Full-wave voltage
vS = Vm sin q R D1 vO Vm
D1 on
− vC2 +
− C2 = C V
0
− m
p
2
p 3p
2
2p 5p
2
3p
−
q = wt
Two
−
half-wave voltage doublers can be cascaded to deve
(e) Circuit (f) Output voltage
D2
as shown in Fig. 5.36(a). Note that resistances, which are
FIGURE 5.29 Fixed-shift clamping circuit be connected so that the circuit can cope with a changing
5.7.2 Voltage Triplers and
cycleQuadruplers
(0 ! !t ! " ⁄ 2) of input voltage vS, capacitor C1 w
quarter-cycle (" ! !t ! 3" ⁄ 2), capacitor C2 will be cha
SUPER DIODE Integrated Analog Circuits and Applications 1081
Superdiode
+ + vD −
ii +
vd A
+
− − D1
vO1
+
vS ~ −
− vO
iL +
vO vO = vS
RL
−
0
vS
v1
D1
v2 +
D2
v3 Ao = ∞
D3 +
− FIGURE 16.2 Positive signal detector
vO
IDC
−
22_16_ch16_p1079-1176.qxd 2/19/10 6:08 PM Page 1082
+
ii
+ D1 vS, vO
+ +
vd
+ A1
vO
vS ~ −
− − vd A2
− +
C R − vS
vO
vd ≈ 0
ii ≈ 0 −
0
t
(a) Circuit diagram (b) Waveforms for voltages
peak input signal. The unity follower offers a high resistance to the capacitor and supplies the capacitor
voltage to the output without discharging any charge of the capacitor. Resistance R, when connected, will
allow the capacitor to discharge slowly so that the circuit can adjust to a lower input voltage. Otherwise,
the capacitor will maintain its previous higher voltage and will not indicate the correct peak voltage.
PRECISION HALF-WAVE
rectifiers are not suitable for rectification of low voltage. An op-amp circuit with two diodes, as shown in
Fig. 16.4(a), can rectify a very small voltage in the range of microvolts. The circuit operation can be divided
RECTIFIERS
into two intervals: interval 1 and interval 2. We will consider the circuit operation with a sinusoidal input
voltage vS ! Vm sin !t.
if RF = R1
D2 vS
Vm
R3 = R1 0
R1
wt
− − D1 R2 = R1 vO2
iS
vd A = ∞ −
o + + 0
+ + wt
+ Ao = ∞ −Vm
vS ~ +
− vO1 vO2 + vO
(R1 || R3) vO Vm
(R2 || R3) 0
p 2p wt
− − −
PRECISION FULL-WAVE
RECTIFIER
1084 Microelectronic Circuits: Analysis and Design
R4
RF R3
vS
Vm
R1 D2 0
wt
−
R2 vO2
A1 −
+ D1
+ 0
wt
+ + A2 −Vm
vS ~ +
− vO1 vO2 + vO
vO Vm
Rx = (R1 || RF)
Ry = (R2 || R3 || R4) 0
− p 2p wt
− −
(a) Circuit (b) Waveforms
vS
Vm Vref = 0
R
0
wt
C
B A vC
−
− vC + − D1
vd A1 Vm
+ + + +
vS ~ + 0
− + vO1 vO vO wt
Vref 2Vm
− − − Vm
(a) Circuit diagram 0
p 2p 3p wt
R (b) Waveforms
+ C
vO = Vm(1 + sin wt) + Vref
Ad −
− D1
_ vd A2 +
+ +
+ +
+ A3
vS ~ +
− + vO1 vO2 −
Vref vO = vO2
−
− − −
D1
vO D1
RF
RF
R1 RF R1
− − Slope = −
R1 −
is vd −
A=∞ is vd
+ 0 A = ∞v
+ + + S +
+ + −V
vS ~
vS ~ D +
− vO vO
Rx = (R1 || RF) Rx = (R1 || RF)
− −
(a) Circuit (b) Transfer characteristic (b) Tr
(a) Circuit
FIGURE 16.8 Negative voltage limiter FIGURE 16.9 Positive voltage limiter
+VA
R2
iD
Vx
ch16_p1079-1176.qxd 2/19/10 6:08 PM Page 1093
vO
+ +
(VD + VZ1)
vd A=∞
+ − +
vS − VZ2
−
vO 0 vS
R
VZ1 Slope = 1 + F
Vx R1
R1 RF
− − (VD + VZ2)
VZ1 VZ2 vO
EXAMPLE 16.5
vO vO
VH VH
vS +
Comparator
vO 0 Vref vS 0 Vref vS
Vref −
VL VL
+VCC 0
t
External
R limiter
− −
vO
D1 D2 vd A
+
+ + +Vsat
vS +
− vO
0
Rx = R RL t
−VEE
− −Vsat
Diodes D1 and D2 in Fig. 16.24(a) protect the comparator from damage due to excessive input voltage vS.
Because of these diodes, the differential input voltage vd of the comparator is clamped to approximately
0.7 V or !0.7 V. These diodes, called clamp diodes, are external to the comparator. It is up to the designer
to determine if the diodes are needed to protect the circuit. Resistance R is connected in series with input
have no effect on the state of the output voltage. The complete transfer characteristics are shown in
Fig. 16.28(b).
SCHMITT TRIGGER
16.5.3 Schmitt Trigger with Reference Voltage
A Schmitt trigger compares a regular or irregular waveform with a reference signal and
converts voltage
The switching the wave-of a form
Schmitt to trigger
a square or pulse
circuit wave.
is defined as A
theSchmitt trigger
average of is V
VLt and often
. known
For the as
circuits
Ht
a squaring
in Figs. 16.25(a) circuit. It is also
and 16.28(a), VLt !known as ahence
"VHt, and bistable multivibrator
the switching because
voltage it has
Vst, which two
is the stable
width of the
states,band,
hysteresis lowisand high.
zero; that Itis,can remain
Vst ! (VLt #inVHtone
) ⁄ 2state
! 0. indefinitely;
However, someit applications
moves to the othershifting
require stablethe
crossover
state voltage
only whenin either the positive
a triggering or the
signal negative direction
is applied. along thecan
Schmitt triggers vS-axis. This can into
be classified be accom-
plished
twobytypes
adding a referenceonvoltage
depending the typeVrefoftoop-amp
the circuit in Fig. 16.25(a),
configuration as inverting
used: shown in Fig.
or 16.29(a) for a
noninverting.
if RF
vO
R1
+ +
Vref
vd A VLt VHt
Rx +
− −
0 vS
+ vO Vst
vS
− −
v vO
C Vsat ≈ VCC
vC R
RS +VCC
+Vth
vC
v− − − 0
t iC
vd µA741 R
R1 vO −Vth
v+ + + +
+
t1 t2 −
RS −VEE Vth C vC Vsat
−Vsat ≈ −VEE +
T − −
RF
v
5 v'O v'O
v1
− Vsat
− R
C
2 3 4
vd A1 vO
v2 + Vth
+ +VCC t1
0
6 − vpp t
−
1 −Vth
Node P vd A2
RF vO
+ +
R1 −Vsat
−VEE
T
4
(a) Circuit (b) Waveforms
RF IRF RF IRF
Node P Node P
+Vsat −Vsat
IR1 IR1
R1 R1
−Vth +Vth
!Vsat, and one side of R1 will be at the negative-going ramp of A2. When the negative-going ramp exceeds
16.8 Sawtooth-Wave Generators
SAWTOOTH-WAVE GENERATOR
In a triangular waveform, the rise time is always equal to the fall time. That is, the same amount of time
is required for a triangular wave to swing from !Vth to "Vth as from "Vth to !Vth. On the other hand,
In a triangular waveform,
a sawtooth waveformthe has
rise timeriseisand
unequal always equal
fall times. totime
The rise themay fall
be time. That
faster than is,time
the fall theorsame amount
vice versa. The triangular-wave generator in Fig. 16.37(a) may be converted to a sawtooth generator by
of time is required for a triangular wave to swing from ︎Vth to ︎Vth as from ︎Vth to ︎Vth. On the
adding a variable DC voltage Vref to the noninverting terminal of the op-amp. The addition of Vref,
which acts aswaveform
other hand, a sawtooth a reference signal
hasforunequal
the integratorrise
A2, can
and be fall
accomplished
times.byThe using rise
a potentiometer,
time may as be faster
shown in Fig. 16.40(a). The voltage waveforms are shown in Fig. 16.40(b). As with the triangular-wave
than the fall time or vice
generator, versa.ofThe
the operation triangular-wave
the circuit generator
can be divided into two modes. in Fig. 16.37(a) may be converted
During mode 1, v" # 0 and the output of A1 is at positive saturation "Vsat, which is the input signal
to a sawtooth generator by adding a variable DC voltage Vref to isthe
to the integrator A2. The equivalent circuit for the operation of the integrator
non-inverting terminal of
shown in Fig. 16.40(c). At
the op-amp. The the addition of mode,
beginning of this Vrefthe, which actsisasVtha, and
output voltage reference
the voltage atsignal forterminal
the inverting is v1 ! Vref. A2, can be
the integrator
Thus, the initial voltage on the capacitor is
accomplished by using a potentiometer, as shown in Fig. 16.40(a).
v (t = 0) = v - v = V - V
C 1 O ref th
+VCC vO
− v
C
R vO
A1 Vsat
+ +VCC
−VEE vO
Vth
A2 0
RF vO t
Vref
−Vth
R1 −VEE
+VCC −VEE −Vsat
R3 Rise time
Fall time tr T
tf
(a) Circuit (b) Waveforms
R C iC R C iC
v1 v1
Vsat vO −Vsat vO
Vref Vref