1042 JOURNAL OF NETWORKS, VOL. 4, NO.

10, DECEMBER 2009

The Design of a Wireless Data Acquisition and

Transmission System
CAI Jun
Department of Electrical and Communication Engineering, Sun Yat-Sen University; School of Electronics
and Information, Guangdong Polytechnics Normal University
Guangzhou, P. R. China
e-mail:gzhcaijun@gmail.com

YU Shun-Zheng
Department of Electronic and Communication Engineering Sun Yat-Sen University, Guangzhou 510275,
P. R. China

LIU Jing-li
School of Electronic and Information, Guangdong Polytechnic Normal University
Guangzhou, P. R. China

Abstract—In the field of modern wireless communication,
there are mainly some technologies that provide solutions to
the wireless data transmission network, such as: GSM,
CDMA, 3G, Wi-Fi. These solutions make network work
with high efficiency and good quality, but still with high
cost. So it was difficulty in popularizing in with low cost
and at the circumstance of infrastureless or infrastructure
destruction. According to this situation, in this paper, the
key components of the Information Terminal and the
wireless receiving modules on the data collection and
wireless transmission network were designed with the
principle of transceiver nRF905 and 51 series of single-chip
computer as the core hardware, besides, combining with
the current technology on the Wireless Ad Hoc Networks, a
short-rang wireless data sampling and transmission
network was putting up , which provides a low-powered
and high-performance wireless data communication system,
works in the ISM (Industrial Scientific Medical )Band.
Then, an available solution to the wireless data
communications was put forward, and this solution was
good at stronger real-time response, higher reliability
requirement and smaller data amount. Through software
and hardware debugging and actual measuring, this system
based on our solution had work well, reached the expected
goal and been already successfully applied to Wireless
vehicle System.
Index Terms—Ad Hoc Network; data acquisition;
transmission network
I. INTRODUCTION
In modern wireless communication, GSM, CDMA,
3G, and Wi-Fi become the mainstream solution of
wireless data transmission network because of their high
speed and reliable quality. They also have the
shortcomings of high cost, so wider application would
cause a great waste of resources, and they cannot be
promoted in small regional, low speed data
communications. Multi-point short-range wireless data
collection and transmission network will be the best
solution. The system supports the development of
communication system of peer-to-peer,
point-to-multipoint, and multipoint-to-multipoint.
Short-range wireless communication can adopt
different network technologies, such as Bluetooth [1],
IEEE802.11 [2], HomeRF [3] and Infrared [4].
Compared with long-distance wireless communication
network, they are different in the basic structure, the
application level, service range, and business (data,
voice). The original intention of design of short-range
wireless communication network is to provide
short-distance broadband wireless access to mobile
environment or formulation of temporary network, it is
the further development of internet in mobile
environment. The main advantage of short-range
wireless communication network is lower cost and more
flexible use.
This paper presents the design proposal of hardware
and software of information terminal (a machine) and
wireless receiver module of multi-point short-range
wireless data collection and transmission network, which
provides a low-powered and high-performance wireless
data communication system, works in the ISM
（Industrial Scientific Medical ）Band. The remainder of
this paper is organized as follows. In Section Ⅱ, we
describe the general block diagram of the wireless data
acquisition and transmission system. In section Ⅲ, we
analyze the key technologies about the system hardware
design. In section Ⅳ, the system software design is
introduced. In section Ⅴ, the testing results of system is
presented. Finally, we present the conclusion and future
work in Section Ⅵ.

© 2009 ACADEMY PUBLISHER

doi:10.4304/jnw.4.10.1042-1049
JOURNAL OF NETWORKS, VOL. 4, NO. 10, DECEMBER 2009
II. SYSTEM IMPLEMENTATION MODEL
A. System Model
As a point to multi-points multi-mission wireless
communication system, it consists of one central
monitoring system (CMS) and Multiple Remote
Terminal Units (RTU) (figure 1). In fact, this remote
terminal unit is some kind of removable stations which
can communicate with other stations in the process of
motion. Furthermore, the CMS communicate with RTU
in bidirectional way.
In the next part, some pivotal segment on software and
hardware of the information terminal and control center
was designed.
Figure 1. Diagram of reticulate wireless communication system
B. Reference Model
The system in this paper is designed based on the first
layer (the physical layer) and the second layer (the data
link layer) of the architecture of OSI/RM (Open Systems
Interconnection Reference Model) that the ISO
(International Organization for Standardization)
proposed, such as figure 2. The function of the physical
layer is finished through constructing the circuit and
special chips. Otherwise, communication protocols in the
data link layer are realized by software.
Figure 2 The virtual and actual communication process between the
source and destination unit
Ⅲ.THE HARDWARE DESIGN OF THE SYSTEM
For the sake of the convenience of design,
maintenance and update, some hardware circuit cell and
node was divided into some different module according
to functional and electric characteristic. There are RF
Transceiver module [5], controlling and dealing module,
Universal Serial interface module, data buffer and
© 2009 ACADEMY PUBLISHER
1043
storage module and multifunctional power management
module in the basic structure (Figure 2).
Figure 2. Diagram of system basic structure
A. Transceiver and receiving Module
In the process of sending, the data package should
been Modulated with High frequency and sent to object
RF Transmitting module, in the process of receiving, the
high frequency signal have been demodulated to original
data package through the RF receiver module.
NRF905 [5] is the key of RF Transceiver module
whose frequency is 16MHz Crystal Oscillator. NRF905
can receive the RF signal by Printed Antenna, but this
module adopts the external antenna and Filter Circuits in
order to improve the receiver sensitivity and
anti-jamming ability.
B. Controlling and Treating modue
The controlling and treating module consists of MCU
and external circuit, it have two functions: one made all
module’s working under control and harmony; the other
function is treating and transmitting the data got from
interface, such as router processing, data packaging,
verification and repeating request.
Module’s key MCU is 51 series microprocessor, and
considering the industrial function, the WINBOND
78LE546] 7] was applied in this practical experiment
because of it’s good capability in 8-bit CMOS
microprocessor, compatibility with 2.4-5.5V wide
voltage electric supply, 256Bytes embedded RAM,
16KB Flash EPROM and 64KB addressing space, four 8
Bit standard I/O interfaces, one standard I/O dual serial
interface.
The Crystal Oscillator frequency of SCM is
22.1184MHz, and the electric power is 3.3V to adapting
to nRF905 logical level in wireless transceiver chip. The
impending PIN was protected by connecting with VCC
to keeping its stability. The specific connection between
MCU and all modules is described in TABLAE 1.
1044
TABLE 1 THE MCU DESCRIPTION MODULE INTERFACE
RF transceiver storage universal power module
module module interface
P1.0 CSN P0.0A0\D RXDRO1 VCCVCC_OUT_3
P1.1 SCK 0 TXDTin1 .3V
P1.2 MOSI | | GNDGND
P1.3 MISO P0.7A7\D
P1.4PWR_UP 7
P1.5 TRX_CE
P1.6 TX_EN P2.0A8
P3.2 AM | |
P3.3 DR P2.7A15
P3.5 CD WRWE
RDOE
ALEC
C. Multifunctional Electric Power Management Module
The most remarkable characteristic is compatibility
with 8-24V wide voltage electric supply including
CMOS power and TTL power, respectively in 5V and
3.3V, which provided all modules with the suitable and
stable power. Meanwhile, it means so much in energy
source saving because of its electronic switch. The power
supply transfer chip C851414 and AS-1117-3.3 is the
primary ingredient in this module. The C851414 made
the electric voltage transfer from 8V to 24V, then, the
AS-1117-3.3 made it from 5V to 3.3V. Furthermore,
suitable filter capacitance and inductance was introduced
to make power’s ripple characteristic perfect as
possible.
D. Universal Serial Interface Module
The main function of Universal Serial interface
module is connecting universal terminal equipment, such
as signal output equipment or analog collection
equipment with AD transfer. At the same time, it
provides entrance to the computer terminal data
exchange through universal RS232 serial interface.
E. Data Buffer and Storage Module
It has two kinds of function, one is data buffer, the
other is data storage, respectively performed by 32KByte
RAM and 16KByte EEPROM. Data buffer district
supervise buffering some temporary data, such as
transmit data, waiting data. Data storage district
supervise some fixed data memory, such as router data,
local host, local address and some renewed data for
power-off protective.
F. High Frequency Shielding Protecting Moudule
In order to prevent electromagnetic interference from
environment, circuit in our designing system is protected
with metal enclosure. At the same time, preventing the
digital circuit interfere from the radio frequency circuit
in the system, we placed the two circuits in different
isolated bin, such as figure 3. There is a small hole with
diameter less than 1/4 wavelength in the metal box side,
which is either easy to pass the line or prevent the
electromagnetic wave from getting in it.
© 2009 ACADEMY PUBLISHER
JOURNAL OF NETWORKS, VOL. 4, NO. 10, DECEMBER 2009
Digital circuit Radio frequency
circuit
Figure 3 the schematic diagram of circuit shielding
Ⅳ.SYSTEM SOFTWARE DESIGN
The realization of system performance depends on its
effective and reasonable software control. The design of
this software is on the basis of the hardware environment
to development a wireless network protocol that have
functions as data transmission, avoiding conflict, the
retransmission when error occurs, and overtime retry, in
order to achieve the design goal. The entire network is
composed of a host and many scattered terminals, each
terminal must have a wireless transceiver node (this
system adopts nRF905 single-chip RF transceiver), any
nodes of the entire wireless network has a unique
identified address which is composed of an unique
identified terminal. For convenience’s sake, each
terminal wireless transceiver node addresses of the actual
system is set by ourselves (4 bytes).
In order to improve the reliability of the system, the
protocol is designed as stop-wait mode. In data link layer,
the send process is roughly as follow. Firstly, the data
sources send a connection request to the data targets, and
it will transfer data after the data sources respond. Then
wait for response from data target after each transmission.
If the response is correct, another transmission will start.
After all the data transmission is done, the data source
will send a request to release channel resources, the
transmission is finished when the response from the
target is received. The receive process is as follow: the
data target will receive data after give a response to the
source, and will give a effective or uneffective response,
until receive a demolition request. Then, save the data
and send a response to end the entire process.
A. The Define of Address Field and Frame Format
We defined the frame format based the above
transceiver process. There are two frames:
request/response frame (TABLE 2) and data frame
(TABLE 3).
JOURNAL OF NETWORKS, VOL. 4, NO. 10, DECEMBER 2009 1045

data values are serially transferred, pumped into a shift

register and are then internally available for parallel
TABLE 2 REQUEST/RESPONSE FRAME FORMAT
processing. Here we already see an important point, that
Fra Destin Request/re Sou Fra check must be considered in the philosophy of SPI bus systems:
me ation sponse type rce me sum The length of the shift registers is not fixed, but can
head address code addres numb
s er differ from device to device. Normally the shift registers
Field explanation are 8Bit or integral multiples of it. Of course there also
mark implication exist shift registers with an odd number of bits. For
example two cascaded 9Bit EEPROMs can store 18Bit
Frame head The beginning of the frame
data. If a SPI device is not selected, its data output goes
Frame number Ensuring the sole request and response into a high-impedance state, so that it does not interfere
Destination/source The destination and source address of with the currently activated devices. When cascading
address request/response several SPI devices, they are treated as one slave and
Request/response type Denoting the function of request/response therefore connected to the same chip select [5]. In figure
code frame 4 the cascaded devices are evidently looked at as one
Checksum Detecting the correctness of the frame
larger device and receive therefore the same chip select.
The data output of the preceding device is tied to the data
The request/response type code, such as: input of the next, thus forming a wider shift register.
0x0100: request for establishing the connection； Based on the characteristics of SPI technology, we
0x0200: response for establishing the connection； proposed the solution such as figure 5 the algorithm flow
0x0300: the correct response of data frame； of writing SPI and figure 6 the algorithm flow of reading
0x0400: the error response of the data frame； SPI.
0x0500: request for connection termination；
0x0600: response for connection termination.

TABLE 3 DATA FRAME FORMAT

Fra- Identifica Destina- Sour- Fram Pac- Da- Check-
me -tion of tion ce -e ket ta sum
head data address addr- num lengt
frame ess ber -h

Field explanation
Mark implication

Frame head The same table 2 Figure 4 Cascading several SPI devices
Identification of data We fixed 0x80,denoting the frame is data
frame frame
Destination/source The same table 2
address
Frame number The same table 2
Packet length Denoting the following data length
data Data packet transmission
checksum The same table 2

B. Serial Peripheral Interface Technology

The Serial Peripheral Interface Bus or SPI bus is a
synchronous serial data link standard named by Motorola
that operates in full duplex mode. Devices communicate
in master/slave mode where the master device initiates
the data frame. Multiple slave devices are allowed with
individual slave select (chip select) lines. There is a
MASTER and a SLAVE mode. The MASTER device
provides the clock signal and determines the state of the
chip select lines, i.e. it activates the SLAVE it wants to
communicate with. CS and SCKL are therefore outputs.
The SLAVE device receives the clock and chip select Figure 5 The algorithm flow of writing SPI
from the MASTER, CS and SCKL are therefore inputs.
This means there is one master, while the number of
slaves is only limited by the number of chip selects.
A SPI device can be a simple shift register up to an
independent subsystem. The basic principle of a shift
register is always present. Command codes as well as

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1046 JOURNAL OF NETWORKS, VOL. 4, NO. 10, DECEMBER 2009

to choose the tout. If tout is too short, the sender

retransfers the data frame under normal condition.
Conversely, the sender wastes much time. Generally,
tout is slightly larger the average time between the
sender sending data frame and receiving the confirmation
frame.
Based on the above the situation, the retransmission
mechanism is applied in designing serial incept, wireless
receiving and sub unit unpacking module waiting for the
information terminal returning messages.

E. the whole realizing module

Whether the function of system can realize and stay
stable depends on the rational programming of the
software. After various considerations and assumptions,
we design the software as the module that is presented in
Figure 7, so as to make the system achieve better
Figure 6 The algorithm flow of reading SPI efficacy and adaptability. Figure 8 is demonstrating the
software flowchart of the Control Centre (host), while
C. Address code information compression and treatment Figure 9 is information terminals (terminal). We will
technology focus on some critical part of the module.
The name of communication terminal is same to the
wireless communication address in the most wireless
application system, which bring some convenience for
design and application of this system. The maximum
address length of the wireless transceiver chip nRF905 is
32 bit, that is four byte length, which only storage the
two Chinese ASCII code value. So the technology of
address code compression was proposed to solve this
problem.

D. Timer application and error retransmission

In process of communication, because of the
disturbance of link or the other factors, the receiver can
not receive the data frame from the sender, or the data
frame is not correct, at this time, the receiver will not
return any confirmation frame, if the sender does not
send the next frame until the confirmation frame from
the receiver, then it will wait forever, or the receiver can
not process the error information from the sender, which
leads to the deadlock phenomena. A timeout timer is
initiated after the sender or the receiver finishes a data
frame to solve this problem. The sender needs to
retransfer the last data frame when the sender can not
receive response message within the retransfer time tout
setting in timeout timer. Obviously, it is very important

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JOURNAL OF NETWORKS, VOL. 4, NO. 10, DECEMBER 2009 1047

Main program

system initialization module RS232 transceiver module SPI interface module wireless transceiver module packet processing module

Telex Processing module

Nrf905 initialation

Host receiving module

RS232 initialation

RS232 transmitting

Data packet module

external variable

Transmitting module

Sub-host receiving
Timer

Write SPI module

Read SPI module

RS232 receiver
initialization
initialization

module
Figure 7 Diagram of program structure

Figure 8. Software of control center (host) Figure 9. Software of Information Terminal

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1048 JOURNAL OF NETWORKS, VOL. 4, NO. 10, DECEMBER 2009

Ⅴ.SYSTEM TESTING
Because communication between any two nodes may
be tested through point to point, in this system Testing
Process, communication model between node
A and node B is a good example for testing schematic
diagram, just like figure 10.

Figure 11. Relation diagram of efficient data, address

information and synchronous clock in wireless sending
After the address was confirmed, the wireless receiver
began to pick up and send out the effective data, distilled
address information. The relationship between effective
data to be received and synchronous clock was showed
in figure 12
Figure 10. Schematic diagram of system testing
Closed-loop testing circuit is put up through PC with
double serial ports and two RS232 ports and
communication node A and B. On one terminal, data was
sent through serial port testing auxiliary tool “serial port
assistant V2.2”, on the other terminal, returning data is
monitored. Data is sent through PC’s serial port A,
RS232 port, then data buffer and finally wireless
transceiver module successively. However, the process
of data receiving was SPI serial, data buffer, then RS232
port, finally PC. In t In this paper, a low-powered and
high-performance wireless data communication system
were designed with the principle of transceiver nRF905 Figure12. Relation diagram of efficient data and
and 51 series of single-chip computer as the core synchronous clock in wireless receiving
hardware. An available solution to the wireless data In figure 13, some relationship between the data
communications was put forward, and this solution was packet to be sent and to be received is demonstrated.
good at stronger real-time response, higher reliability They distribute in well-proportioned pectinate interval,
requirement and smaller data amount, which is widely which make the frame synchronization, avoid packet to
applied various fields such as data communications, be lost and wrong as possible, which means the most
environmental monitoring and security Guard System. balanced and stable situation for the wireless data
We believe that integrated and intelligent transceiver.
Communication Protocol are realized after software
design is refined and improved further.
he testing process, digital oscilloscope was also used
to monitor the data transfer of communication node A ,
node B , RS232 port and SPI port. In the following
section, information from MOSI/SCK and MISO/SCK
was analyzed to verify the system’s Correctness.
As a waveform of wireless sending data, figure 11
demonstrate some relations among efficient data, address
information and synchronous clock in wireless sending
process. Because the receiver address must be designated
by the transmit terminal, 4 byte address require to be sent
after sending packet.
Figure 13 Comb relation diagram of wireless sending
and receiving
In the stability test, we have run the uninterrupted
random transceiver experiment on system for one week,
dead computer, packet loss and packet wrong have never
happened.

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JOURNAL OF NETWORKS, VOL. 4, NO. 10, DECEMBER 2009 1049

TDD-CDMA systems to support asymmetric services by

using directional antennas. Vehicular Technology, IEEE
TABLE 4 TEST RESULTS
Transactions on. Volume: 54, Issue: 3. 1056- 1069
[5]Nordic VLSI.Data sheets for nRF905 Multiband
Test contents Test results Transceiver.2005
[6]http://batescomponents.com/catalog/parts/78LE54-24.
transmission rate 16kbps html
[7] Popa, M.Popa, A.S., Cretu, V., Micea, M.,
Stably operating time ＞one week “Monitoring Serial Communications in Microcontroller
Based Embedded Systems Computer Engineering and
Bit error rate Not yet found bit error Systems”, The 2006 International Conference on，Nov.
In Bit error rate test, implement with the perfect 2006 Page(s):56 - 61Computational Intelligence in
verification and error retransmission rules, the result is Scheduling (SCIS 07), IEEE Press, Dec. 2007, pp. 57-64,
encouraged in the stability and reliability test for one doi:10.1109/SCIS.2007.357670.
week. [8] http://www.mct.net/faq/spi.html
Under the maximal operation loading, we can [9]Lan hui-li Zhang Ren-cheng Mao Si-wen. Design of
calculate some data sensed by oscillographs: Temperature Detection System for Grain Situation Based
rate=effective data/transmission time, the outcome of on Wireless Sensors Network ,China Science Paper
tested wireless transmission rate is 16kbps, specific Online.
conclusion as follow TABLE 4.

Ⅵ.CONCLUSION CAI Jun is presently a PHD candidate with the

communication information system at department of
In this paper, a low-powered and high-performance electrical and communication engineering, Sun Yat-Sen
wireless data communication system were designed with University. He is also an instructor at Guangdong Polytechnic
the principle of transceiver nRF905 and 51 series of Normal University. He received his master degree in
single-chip computer as the core hardware. An available communication from the Jinan University in 2006. He has
solution to the wireless data communications was put published more than 10 journal papers.
forward, and this solution was good at stronger real-time
response, higher reliability requirement and smaller data
amount, which is widely applied various fields such as
data communications, environmental monitoring and
security Guard System. We believe that integrated and
intelligent Communication Protocols are realized after
software design is refined and improved further.

ACKNOWLEDGEMENTS
We would like to thank all the members in our
research group, for the valuable discussions about the
ideas presented in this paper. Funding from Project
supported by the National High Technology Research
and from Development Program of China (Grant
No.2007AA01Z449) and the Key Program of
NSFC-Guangdong Joint Funds (Grant No.U0735002).

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