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 MAHENDRA ENGINEERING COLLEGE
(AUTONOMOUS)
MODEL EXAMINATION – SEPT. / OCT. - 2016
Third Semester
ELECTRICAL AND ELECTRONICS ENGINEERING
15EE13301 - DIGITAL LOGIC CIRCUITS
(Regulation – 2015)
Time: 3 Hours Maximum: 100 Marks
Answer all the questions
PART – A (20 x 1 = 20 Marks)
I. Choose the best Answer
1. Fan out of RTL ___________.
a)4 a)4
c)18 c)18
2. ___________ is used as data selector.
a)demultiplexer b)multiplexer
C)encoder d)decoder
3. The counter which never goes to lock out condition is called as ___________.
a) Synchronous counter b) Ripple counter
c) Self starting counter d) Modulus counter
4. PLD consists of ___________.
a) AND, OR gate b) NAND, OR gate
c) NAND, NOR gate d) AND, NAND gate
5. ___________ specifies behavior, functionality, interconnections between inputs & outputs
a)Entity b)architecture
C)package d)subprograms
II. Fill in the Blanks
6. The gray code is also called as __________.
7. ___________ converts binary information from n input lines to 2n output lines.
8. MOD-5 synchronous counter uses ___________ flip flops are required.
9. PROM consists of ___________.
10. ___________ are the modeling techniques in HDL.
III. True or False
11. DTL is used in portable instruments.
12. Decoder has n selection lines.
13. In synchronous counter all flip flops are not clocked simultaneously.
14. The merger table method is also called as implication chart method.
15. Each bit combination of the input variables is called address.
IV. Match the Following
16. SOP (a) Counter
17. Least propagation delay (b) moore model
18. Qn+1 (c) minterm
19. Present state (d) I2L
20. sequential switching (e) D flip flop
PART – B (10 x 2 = 20 Marks)
21. Give the comparison between TTL, CMOS & ECL.
22. Explain wired –And connection.
23. What are logic gates? What is parity generator and parity checker?
24. Define look ahead carry addition.
25. Define synchronous counter. What is lockout? How it is avoided?
26. Define state table & state
27. What are fundamental mode & pulse mode sequential circuit
28. What are hazards, Essential hazards & how to eliminate it?
29. What do you mean by test bench? Mention the types.
30. What is VHDL? What is packages and what is the use of these packages
PART – C (5 x 12 = 60 Marks)
31. (a) i) Explain the concept, working and characteristics of TTL logic families.
ii) Explain the operation and characteristics of MOS families and various gates with 12
its truth table.
OR
(b) i) Explain the concept, working and characteristics of ECL and RTL logic families. 12
ii) Explain briefly weighted and non-weighted codes with examples
32. a) i) Minimize the expression
12
Y=AB’CD’+A’B’CD+A’B’C’D’+ABCD+A’BC’D’+A’BCD’ and
Y(w,x,y,z) = Σm(1,2,3,5,9,12,14,15) + Σd(4,8,11)
ii) Design a Binary to Gray code converter and BCD to Excess 3.
OR
b) i) Explain the operations of adder and subtractor along with truth table and logic diagram
12
ii) Explain about MUX and DEMUX
33. a) i)Design a sequential circuit using JK flip-flop for the following state table [use state 12
diagram]

ii) Draw and explain the block diagram of Mealy circuit.

OR
b) i) Design a mod-10 synchronous counter using Jk ff. Write excitation table and state table. 12
ii) A sequential circuit has 2D ff’s A and B an input x and output y is specified by the
following next state and output equations.
a. A (t+1) = Ax + Bx b. B (t+1) = A’x c. Y= (A+B) x’
(i) Draw the logic diagram of the circuit (ii) Derive the state table
(iii) Derive the state diagram

34. a) i) Design an asynchronous sequential circuit that has 2 inputs x2 and x1, and one output z. 12
theoutput is to remain 0 as long as an X1 is 0. The first change in x2 that occurs while x1 is 1
will cause z to be 1. Z is to remain 1 until x1 returns to 0.
ii) Discuss on the concept of working and applications of following memories.
a) ROM b) EPROM c) PLA.
OR
b) i) Implement the following function using PLA.
a. A (x, y, z) = Σm (1, 2, 4, 6) b. B (x, y, z) = Σm (0, 1, 6, 7) 12
c. C (x, y, z) = Σm (2, 6)
ii) Explain with neat diagrams RAM architecture.

35. a) i)Write an HDL data flow description of a 4 bit adder subtractor of Unsigned numbers use 12
the conditional operator.
ii) Write the HDL gate level description of the priority encoder.
OR
b) i) Write a behavioral VHDL description of the 4 bit counter. 12
ii) Write a VHDL description of an S-R latch using a process.